J-5- 9-U'CtO* 92CS-19I4I FUNCTIONAL DIAGRAM 430E57

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

J-5- 9-U'CtO* 92CS-19I4I FUNCTIONAL DIAGRAM 430E57

Datasheet Thumbnail

Top Searches for this datasheet

HARRIS SEflICOND SECTOR
J-5-
9-U'CtO*
92CS-19I4I
FUNCTIONAL DIAGRAM
430E571 GG37b70 BHAS
T-Hb-CTt-d
CD4572U3 Types
CMOS Gate
Four Inverters, 2-lnput Gate, 2-lnput NAND Gate
P'S-H
Features:
input positioned adjacent easy gate inverter
NAND input positioned adjacent easy gate inverter
Standard symmetrical output characteristics
100% tested quiescent current
Maximum input current over full package-temperature range: VandiS'C
5-V, 10-V, 15-V parametric ratings
Meets requirements JEDEC Standard 13B, "Standard Specifications Description Series CMOS Devices"
CD4572UB Gate provides system designer with direct implementation inverter, NAND, functions supplements existing family CMOS gates.
CD4572UB devices meet requirements JEDEC Standard 13B, "Standard Specifications Description Series CMOS Devices,"
INPUTS PROTECTEO CMOS PROTECTION NETWORK
CD4572UB types supplied 16-lead dual-In-line ceramic packages suffixes), 16-lead dual-in-line plastic package suffix), chip form suffix).
TERMINAL ASSIGNMENT
Fig. Schematic diagram lour identical inverters.
Fig. Schematic diagram 2-input gate.
92CS-39I49
Fig. Schematic diagram 2-input NAND gate.
3-351
HARRIS SEMCON]) SECTOR M3GB271 0037b71
CD4572UB Types Ol'll
MAXIMUM RATINGS, Absolute-Maximum Values:
SUPPLY-VOLTAGE RANGE, (VDD)
Voltages referenced Terminal) -0.5Vto +20V
INPUT VOLTAGE RANGE, INPUTS .".-.'. !.,.;.,. .-0.5V +0.5V
INPUT CURRENT, INPUT
POWER DISSIPATION PACKAGE (PQ);
-550C f.:.'.".500mW
Linearity 200mW
DEVICE DISSIPATION OUTPUT TRANSISTOR
full package-temperature range (All PackageTypes). 100mw
OPERATING-TEMPERATURE RANGE fTf).
STORAGE TEMPERATURE RANGE (Tstg)
LEAD TEMPERATURE (DURING SOLDERING): distance 1/16 1/32 Inch (1.59 0.79mm) from case ._:. +2650C
RECOMMENDED OPERATING CONDITIONS
maximum reliability, nominal operating conditions should selected that operation always within following ranges:
CHARACTERISTIC LIMITS UNITS
Min. Max.
Supply-Voltage Range (ForTA=Full Package-Temperature Range)
STATIC ELECTRICAL CHARACTERISTICS
CHARACTERISTIC CONDITIONS UNITS
LIMITS INDICATED TEMPERATURES (OC)
+125 Min. Typ. Max.
Quiescent Device Current, Max. 0.25 0.25 0.01 0.25
0.01
0.01
0.02:
Output (Sink) Current' Min. 0.64 0.61 0.42 0.36 0.51
6.8.
Output High (Source) Current, Mln, -0.64 -0,61- -0.42 -0.36 -0.51
-1.8 -1.3 -1.15 -1.6 -3.2
-1.6 -1:5 -1.1 -0.9 -1.3 -2.6
13.5 -4.2 -2.8 -2.4 -3.4 -6.8
Output Voltage:" Low-Level, Max. 0.05 0.05
0.05 0.05-
0.05 0.05
Output Voltage:. High-Level, Min. 4.95 4.95
9,95 9.95
14.95 14.95
Input Voltage, Max, 0.5,
1.5, 13.5
Input High Voltage, Min, 0.5;
1.5, 13.5 12.5 12.5
Input Current, Max.
3-352
HARRIS SEMICOND SECTOR 0037fa75
CD4572UB Types
DYNAMIC ELECTRICAL CHARACTERISTICS Input tr,tf=20 Cl=50
CHARACTERISTIC SYMBOL TEST CONDITIONS LIMITS UNITS
VDD(V) Min. Typ. Max.
Propagation Delay Time tpHL. tpLH
Transition Time
Input Capacitance Input
DRAIN1-TO-SOURCE VOLTAGE
Fig, Typical output characteristics.
VDL.TAGE
Fig. Typical output characteristics.
12.5 INPUT VOLTAGE
Fig. Minimum maximum inverter voltage transfer characteristics.
DRAW-TO-SOURCE VOLTAGE CVDSJ~-V
92CS 'Z43I9RI
Fig. Minimum output (stnk) current characteristics.
Fig. Minimum output high (source) current characteristics.
12.9 17.5 WPVT VOLTAGE (ViI
Fig. Typical inverter voltage transfer characteristics function temperature.
3-353
HARRIS SEMICOM SECTOR 4302571 0037b73
-r-Hb-oi-"
CD4572UB Types
12.5 INPUT VOLTAGE (Vjl-V
Fig. Typical Inverter current voltage transfer characteristics.
LOAD CAPACITANCE
Fig. Typical transition time load capacitance.
IEN1 4PER
POWER DISSIPATION 1NVEB
LOAD CAPACITANCE FIXTURE* 39pFEXT) CL-l3pFtllpF FIXTURE* 4pFEXT.) a.Ll 8,^4
input frequency
92CS-36682
Fig. Typical dynamic power dissipation frequency.
inputsr
LOAD CAPACITANCE (CLJ-pF
92CS-29929
Fig. Typical propagation delay time function load capacitance.
SUPPLY VOLTAGE (VDD)-V
92CS-39I4S
Fig. Typical propagation delay time supply voltage.
Fig.
SUPPLY VOLTAGE (Vdo'
92CS-25II4HI
Variation normalized propagation delay time-" (fpHL fpLH) with supply voltage.
9K3-27427BI
Fig. Quiescent device current test circuit.
Fig. Noise immunity test circuit.
3-354
92CS*27429
Fig. Input leakage current test circuit,
HARRIS SEMICOND SECTOR 4302271 QG37b74
CD4572UB Types
-H6'0Tft
inverting output
'phl
I-50*
-|Q*n
VD0|
~f-90*
/-50*
'plh
Fig. Transition times propagation delay times, combination logic.
39150
Dimensions layout CD4572UBH.
Dimensions parentheses millimeters derived Irom basic inch dimensions indicated, arid graduations mils inch).
3-355

J-5- 9-U'CtO* 92CS-19I4I FUNCTIONAL DIAGRAM 430E57

Top Searches for this datasheet

Other recent searches