SEMICONDUCTOR MHMMHH^bmmbbh AN1102 Interfacing Power MOSFETs
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MOTOROLA AN1102/D
SEMICONDUCTOR MHMMHH^bmmbbh
AN1102
Interfacing Power MOSFETs Logic Devices
Prepared Berringer Motorola Discrete Applications
POWER MOSFET DRIVE CHARACTERISTICS
Power MOSFETs commonly used switching applications their fast switching speeds static losses. When driven with sufficient gate voltage, power MOSFET will turn have very on-resistance. gate voltage insufficient bias Power MOSFET fully excessive drain currents applied, power MOSFET will operate saturation (pinch-off) region. other words, certain gate voltage will support only limited amount drain current.
Most current crop fourth generation power MOSFETs require volts gate drive support their maximum continuous drain current. This means that volt logic will provide enough voltage drive standard power MOSFET. family Logic Level power MOSFETs available that support their rated drain current with gate voltage volts. With proper considerations, these power MOSFETs easily interfaced most logic families.
Design MOSFETs gate drive dependent MOSFET's input capacitance, which strongly affected size. Therefore, selecting correct device application only minimizes component cost, also optimizes switching performance. Static, losses determined power MOSFET's on-resistance RDS(on). which function junction temperature (Tj), gate voltage (Vqs), drain current (Ip). RDS(on) typically specified equal half rated drain current, volts- junction temperatures
power MOSFET's static losses easily calculated pulsed applications. First, correct rated RDS(on) your drain current estimated operating temperature with help manufacturers' data sheet curves. Then multiply this value times load current squared [P$tatic lrms2RDS(on)l -You should choose power MOSFET with current rating (Id) voltage rating (Vqss) wefl above your worst case load conditions. good rule thumb select device with twice your worst case drain current voltage rating above your worst case drain voltage.
high frequency applications switching losses often more significant than static losses. minimize switching losses must decrease switching times. When power MOSFET used switching applications, gate cannot modeled simple capacitor sizable displacement currents Crss, drain-to-gate capacitor, brought large swings drain-to-gate voltage. result, total input capacitance, CjSS, varies greatly over power MOSFET's operating range. Ciss piecewise modeled linear
Reprinted from EDN. (October 12.1989) CAHNERS PUBLISHING COMPANY Division Publishing,
MOTOROLA INC. 1990
capacitor order find first order approximations switching times.
better method calculating switching times gate charge data from manufacturers' data sheet. Although power MOSFET usually thought voltage controlled device, accurately modeled charge controlled device. charge required power MOSFET handle given current relatively constant even though drain-to-gate capacitance (Crss) varies drastically with drain-to-gate voltage. value Crss increase 1000% more over operating range.
vG(max) O-QD
Figure Driving Power MOSFET with Constant Current Source
When power MOSFET driven current source Figure gate voltage will nearly piecewise linear shown Figure three distinct regions turn delay ti), rise time (t-| t2), excess charge time t3). turn delay (t-j) power MOSFET begins conduct drain current still very small. During rise time power MOSFET actually turns drain voltage drops almost zero. resistive switching rise time tnSe actually measured time takes drain voltage drop from highest value. called rise time referring drain current rise time although voltage what's usually measured. This time corresponds time that remains plateau region Figure
TIME (us)
Figure Gate-to-Source Voltage versus Time Current Source Turning Power MOSFET
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AN1102
During excess charge time RDS(on) continues decrease. This excess charge must removed during turn delay, driving gate unnecessarily high voltage will increase total turn time.
Unlike bipolar transistors, power MOSFETs majority carrier devices. Without minority injection, power MOSFETs turned just easily they turned identical gate drive currents, rise time will equal fall time. turn waveform constant gate current will mirror image Figure Note that turn delay does equal turn delay, instead corresponds turn excess charge time.
Since gate current Figure constant equal charge unit time, horizontal axis labeled time charge. Gate charge data usually measured using current source which means will provide (nano-Coloumb) charge pis. Manufacturers' data sheets usually include gate charge chart with labeled Figure important note that value during rise time, also called plateau voltage, increases with therefore does turn delay. Also, amount charge needed rise time will vary with drain supply voltage. This usually indicated gate charge chart multiple lines excess charge region labeled with corresponding Vqs-
determine switching times using current source drive Power MOSFET, find charge required each region using gate charge chart, Figure then simple equation:
Using this information with Equation obtain equations rise fall time.
Qg/lG-
charge requi turn delay ion, Qd(on). drawing line down from first inflection point horizontal axis Figure This gate charge rated tested your actual drain current different than rated current improve accuracy linearly scaling Qd(on)- calculate turn delay using Equation Next find gate charge required rise time (Qfise)from 9ate charge chart distance between first inflection point intersection plateau with line your expected vds- typical value sometimes listed qgcj. This value used calculate both rise fall times. Next find intersection point your maximum an(*the line corresponding your VpS- This total gate charge Qg(total)- find charge required turn delay Qd(off) (and turn excess charge), subtract Qd(on) Qrisefrom Qg(total)- maximum total gate charge Qg(max) often specified facilitate worst case design, however this figure sometimes includes substantial guard-band.
When driving power MOSFET with voltage source with series resistance (Thevenin source), calculations little more complex. During rise fall times relatively constant since gate current used charge gate-to-drain capacitor. Ohm's law, therefore also constant gate charge chart used with Equation find rise fall times. During turn voltage across series resistance effective source voltage (usually supply voltage) minus gate-to-source plateau voltage, VqsP- During turn voltage across resistor plateau voltage minus effective sink voltage (usually ground). Rise fall times will therefore typicallybe different.
trise fall time:
Reff(ON)
vsource-vqsp
Reff(OFF)
vgsp-vsink
VGSPis Power MOSFET's gate-to-source plateau volt-age, VSource gate driver's effective source voltage, VSjnk,s gate driver's effective sink voltage, Reff gate driver's effective resistance (output resistance). During turn VSjnk near zero volts even negative voltage.
vDs=25
vDs=45
Amps
GATE CHARGE (nC) time current source]
Figure Gate Charge Chart MTP3055E
During turn turn delays gate current constant gate charge data cannot used determine switching speeds. series resistance gate capacitance form simple network; however, capacitance varies greatly over operating range. find switching times must determine capacitance each region from capacitance chart like Figure During turn delay near maximum value, near zero> input capacitance low. Find value Cjss capacitance curve your maximum value this capacitance, Point Figure calculate turn delay. Equation approximate turn delay time.
td(ON) Reff{ON) Cjgs(MIN)
vsource
vsource-vgsp
During turn delay will Cjss will have larger value. Find value Cjss corresponding minimum V[>s maximum Vqs. p0'nt capacitance chart. Then Equation approximate turn delay time.
td(OFF) Reff(OFF)
VG(MAX)-vSINK
vgsp-vsink
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vG(max)is initiaI 9ate voltage prior turn (usually supply voltage), Reff(off)is effective series resistance during turn off, VSjnk effective sink voltage. VSjn|< ground, then Vsjn|< terms will drop Equation
1000
cfss
cfss
Crss
vgs, gate-to-source voltage (volts)
Figure Capacitance Chart MTP3055E
vds, drain-to-source voltage (volts)
Note that gate charge chart capacitance curves related. slope line gate charge chart volts nano-Coloumb. Farad capacitance equal Coloumb volt.
(coulomb/sec) dV/dt(Farad-volts/sec).
From this equation, find that
Farad coulomb/volt.
Therefore, reciprocal slope input capacitance nano-Farads (1000 pF). However, should both charts. gate charge chart most useful when input capacitance varies gate current constant (rise fall times). capacitance curve most useful when input capacitance constant gate current varies (delay times).
DIRECT INTERFACE STANDARD POWER MOSFETs
Standard power MOSFETs interfaced directly with standard CMOS devices, such MC14000 family. This family uses complementary channel FETs output stage. Although standard outputs rated buffer outputs rated saturation currents short circuit conditions much higher. While CMOS gate should short circuited long periods time, safely operated saturation region when switching large capacitive loads. 14049UB inverter buffer typically source sink using volt supply.
output current limited, CMOS gate's output will like current source, output current limited less than saturation currents, CMOS gate's output will like voltage source with finite output resistance. MC14000 series family will operate from volts. common volt supply will drive Power MOSFETs nicely.
14049UB connected directly standard power MOSFET such MTP3055E Figure MTP3055E rugged amp, volt power MOSFET that very popular industry. gate drive current limited series resistor therefore gate drive current will equal 14049's output saturation currents +30/-120 Using gate charge data with Equation predict following switching times.
kl(ON) nC/30 nsec Vise nC/30 nsec id(OFF) nC/120 nsec tfall nC/120 nsec switching times were measured using circuit Figure actual scope waveforms shown Figure measured switching times shown Table
Table Switching Times Standard CMOS Devices Driving MTP3055E Amps gate used unless noted
Driver (Volts) td(on) <ns) trise (ns) td(off) (ns)
4049UB
4049UB
4049UB
4049UB
4049UB
4049UB
4050B
4050B
4050B
4069UB
4Q69UB
4069UB
4069UB
Figure Standard CMOS Interface Circuit
calculated values were fairly accurate first order approximations considering that speeds high enough that circuit parasitics affect performance. saturation currents '4049 vary from device device with supply voltage junction temperature. Driving directly from logic will provide quickest rise fall times, these times will vary greatly.
adding resistor between CMOS buffer's output gate power MOSFET Figure control switching times limiting gate drive current. However, increasing gate resistor also increases power MOSFETs susceptibility noise accidental dv/dt turn rapid change power MOSFETs drain voltage will cause voltage appear gate, which sufficient turn
AN1102
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turn-off
Figure Scope Waveforms MC14049 Driving MTP3055E
Keeping driver impedance will minimize eliminate this phenomenon.
find switching times using gate resistor, Equations find rise fall times. Then Equations find delay times. Here Reff(on/off) equals gate resistor, plus CMOS buffer's output resistance, approximate output resistance '4049 turn turn off. Vsource equal VSjnk equal zero. Switching times several gate resistors summarized Table
MC14049UB stands "un-buffered". This means that consists single complementary inverter. additional gate Figure used ensure power MOS-FET driver itself driven Vdd- input voltage will greatly affect saturation currents therefore switching times. MC14050B "buffered" non-inverting buffer consists cascaded inverters. therefore does invert signal, less susceptible soft drive conditions. diodes input Figure clamp input voltage ground Vdd- Excessive voltage applied CMOS input damage it's internal static protection diodes. Voltage excess supply voltage, Vdd. applied output CMOS device cause latch-up destroy itself. Remember
decouple logic device, drawing substantial currents.
Open collector gates also used drive standard power MOSFETs. However, most open collectoroutput stages were designed volt operation. power Schottky (LS) gates such 74LS05 typically have collector-emitter breakdown voltage volts. This makes them unsuitable operation using volt supply. They operated from volt supply with volt zener clamp output; however, long-term reliability logic device will suffer.
74LS26 designed interface volt logic tested breakdown greater than volts. This Quad NAND gate used drive power MOSFET with single pull-up resistor, Figure Using 1.5Ki2 pull-up with volt supply will limit steady state sink current This necessary guarantee 'LS26's rated output voltage Vq{_ volts. Using smaller pull-up resistor would increase 'LS26, consequently increase drain-to-source leakage current power MOSFET state.
During turn current supplied pull-up resistor. During turn 'LS26 must sink both gate current pull-up resistor current. pull-down transistor output will typically sink about Turn times calculated using Equations with Reff(on)=Rp VSOurce=vp' where pull-up resistor pull-up's supply voltage. Turn times calculated using Equations with Reff(off)=Rp Vsjnk=Vp-lsjnkRp (vsink negative). equations Reff(off)and vsink Thevenin equivalent ideal constant current source working against pull-up resistor. Vsin|< equation only valid when pull-down transistor approximated current source. During turn delay fall times, pull-down transistor provides nearly constant sink current, since pull-down transistor's collector-emitter voltage exceeds it's VcE(sat)and base drive current relatively constant.
'LS26 with pull-up used drive MTP3055E Figure Oscilloscope waveforms shown Figure switching times summarized Table
This configuration provides minimum rise fall times; however, fall times will vary greatly, since "LS26's sink current will vary with temperature from device device. series gate resistor used slow control turn off. Switching times again calculated using Equations through large gate resistors following approximations: Reff(on)=Rp+Rg, VSource=Vp, Reff(off)^Rg. VSjnk=0.5 volts. Switching times several gate resistors summarized Table
Table Switching Times 74LS26 Driving MTP3055E Amps Only gate used
td(on) Vise ld(off) tfall
(Volts) (ns) (ns) (ns) (ns)
1500
1800
1500 1500 2000 1300 1450
3000 3000 3900 2500 2900
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AN1102
Figure Power Schottky Interface Circuit
turn-on
TURN-OFF
Figure Scope Waveforms 74LS26
Driving MTP3055E Volts, Volts, 1.5KG
DIRECT INTERFACE LOGIC LEVEL POWER MOSFETs
Logic level Power MOSFETs designed easily interfaced volt logic devices. They have larger transconduc-tance lower threshold voltage than their conventional counterparts. More importantly, RoS(on) specified Vqs=5 volts. Unfortunately most volt logic families have volt high output (Voh) capability. Fast Schottky (FAST) power Schottky (LS) logic have minimum rated voits. This means that pull-up resistor volts required drive Logic Level Power MOSFETs. High speed CMOS (HC) rating 4.95 volts, therefore does need pull-up resistor.
Figure shows output stages logic devices. output stage Figure identical standard CMOS output stage, except that complementary MOSFETs have been optimized vott operation. Most devices buffered additional complementary stages. output stage Figure uses totem pole output. pull-down transistor biased about current gain about This means sink maximum resistor limits pull-up transistor's sink current about when output shorted.
Figure shows interface FAST logic Logic Level Power MOSFETs. Note input termination protection circuitry. This necessary drive logic devices with pulse generator. best drive Logic Level Power MOSFET driver with device from same logic family. When connecting CMOS) device board connector, diodes should used protection.
Figure shows switching waveforms three logic families driving Logic Level Power MOSFET using circuits Figure measured switching times Table
Table Switching Times Logic Devices Driving Logic Level MTP3055EL Amps unless noted. gate used unless noted.
td(on) trise td(off) tfall
Driver (fl) (ns) (ns) (ns) (ns) Comment
74HC04
74LS04
74F04
74HC04 gates
74HC04 i2A50aC
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FROM INPUT RESISTOR BUFFER
P-CHANNEL PULL-UP
vout
N-CHANNEL PULL-DOWN
VssorGND CMOS Output Stage
FROM PHASE SPLITTER
DARLINGTON PULL-UP
vout
pull-down
Output Stage
Figure Logic Output Stages
74HC04 inverter connected directly Logic Level Power MOSFET. switching times calculated same CMOS inverter buffer. 'HC04 will source sink about with volt supply.
family operating supply range volts. device will drive Logic Level Power MOSFETs gate within Vqd- However, supply falls below volts switching times RDS(on)wi" increase dramatically. reduction volts) will increase rise time about fall time roughly 15%. RDS{on)wi" increase from 100% more depending drain
current junction temperature. voltage operation real possibility should choose Logic Level Power MOSFET heatsink handle this worst case condition. Examine curves "On-region Characteristics", KRoS(on) versus Id"- "RDS(on) versus Temperature" manufacturers' data sheet. need device with current rating much larger than your expected load current attain desired RDS(on) under supply conditions. Manufactures developing volt logic level power MOSFETs with RDS(on) rated volts. These devices easily interfaced logic devices operated down
volts. However, lower threshold voltage makes them more susceptible noise increases leakage currents.
74LS04 Figure must have pull-up resistor
volts. minimum pull-up resistor will guarantee logic device output voltage, Vol. volts. During turn gate drive current supplied pull-up resistor 'LS04's internal pull-up transistor. During turn 'LS04 must sink both gate drive current pull-up resistor current. larger will increase turn time decrease turn time. smaller would increase 'LS04, increasing power MOSFETs leakage current. lower threshold voltage logic level power MOSFETs makes rating critical. threshold voltage power MOSFET decreases temperature increases. Therefore, ofthe logic device must less than logic level power MOSFETs threshold voltage VQg^h) maximum expected junction temperature. this reason volt logic level power MOSFETs incompatible with logic devices.
Switching times again estimated using Thevenin equivalents drive circuit with Equations through During turn delay, current supplied Darlington pull-up transistor 74LS04, external pull-up resistor. Darlington saturation with VcE(sat) about Volts. 74LS04's output current then limited internal resistor. calculate turn delay time, Equation with Vsource -5RpARp 110Q)] Reff(on) Rp|| During rise time nearly current supplied pull-up resistor, since Vqsp's usually above 'LS04. therefore Equation with VSource Reff(on) estimate rise time.
During turn pull-down transistor must sink both gate current pull-up resistor current, just like open collector 74LS26 Figure calculate turn times, Vsink=VCC 'sinkRp Reff(off) with Equations pull-down transistor's maximum sink current, lSjnk. typically about
74LS family's specified supply voltage (Vcc) ran9e from 4.75 5.25 volts. rise time will vary greatly with supply voltage while fall time only varies about rise time will vary from about +80% -40% equals 4.75 5.25 volts respectively. This supply voltage affecting both pull-up resistor current pull-up transistor current. Since operating supply range less than that logic, RoS(on)wili va,7 much, must considered.
FAST logic family source sink much more current than family. 74F04 source about sink about minimum pull-up resistor will guarantee logic device's output voltage
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AN1102
PULSE GENERATOR
PULSE GENERATOR
1.312 l80<D0nF
MTP3Q55EL
High Speed CMOS
JonF
1N914
74LS04
TN914
1/674F04
tr-L
TlOnF
MTP3055EL
74LS04 74F04
Schottky
Figure Logic Level Power MOSFET Interface Circuits
volts. larger will increase turn time decrease turn time. switching times calculated family. 74F04 uses internal resistor limit pull-up Darlington's output current, instead resistor. same supply voltage considerations family also apply FAST family.
series gate resistor used with circuits Figure slow control switching times. switching times large gate resistors (greater than FAST) estimated using Reff(on/off) with Equations through When switching loads even slightly inductive, inductive kick-back during turn cause drain voltage rise above load supply. Slowing down turn with gate resistor will reduce this voltage. this voltage large enough sufficient energy present destroy Power MOSFET family rugged Power MOSFETs handle considerable energy under these conditions. also want choose large value order reduce Electromagnetic Interference (EMI). When driving lamp, want very large resistor limit in-rush current. Long-term reliability logic device will also improved using gate resistor and/or larger pull-up resistor. gate resistor dissipates most gate drive power losses, instead logic device, reducing stress logic output devices. larger pull-up resistor limits steady state current pull-down transistors, thereby decreasing their power dissipation. However, using large gate resistor will also increase power MOSFETs susceptibility noise dv/dt turn
Logic gates same chip paralleled increase switching speeds. output current capability will increase proportion number gates used. gate resistor used, switching times will decrease proportion number gates used. gate resistor used safely decreased, proportion number gates, decrease switching times. Paralleling logic gates will change total logic package power dissipation, since output current increases switching times decrease. When many gates used, switching times decrease point where they limited stray inductance load lay-out. Logic gates different chips from different families should paralleled because different propagation delays cause excessive shoot-through currents which might damage logic devices.
Spare gates left over from digital circuit used drive Logic Level power MOSFET However, large currents being used driver cause targe amounts noise supply rail. This noise cause data errors other gates same Limiting current with large gate resistor carefully decoupling logic device will reduce power supply noise. Also driving logic device must grounded same point source power MOSFET avoid ground shift problems caused large drain currents. separate logic analog grounds used they should connected only source power MOSFET.
close attention power supply scheme. gate power MOSFET should never left floating with voltage
AN11Q2
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74HC04
74LS04 560n
74F04 Figure Logic Devices Driving MTP3055EL
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1102
applied drain. When this happens power MOSFET turn destroy itself current limited. separate supplies used load logic logic supply should powered first powered down last. this possible, consider what happens logic device output when power removed. pull-up resistors FAST circuits Figure will pull power MOSFETs gate down when low, turning power MOSFET off. inverter's output, however, will high impedance state when logic supply voltage low, allowing power MOSFET's gate float. large resistor logic supply voltage ground, using small signal diode clamp output below logic supply voltage, will solve this problem. logic supply voltage also cause power MOSFET failure insufficient gate drive. When power MOSFET fails drain voltage will usually appear it's gate, which take entire logic circuit. gate resistor will also limit current under this power MOSFET failure condition.
INTERFACING MICROPROCESSOR
Microprocessors easily interfaced Power MOSFET. circuits Figure used buffer between microprocessor port Logic Level power MOSFET. want standard power MOSFET, will have 'LS26 circuit Figure level shifter. MC14504B level shifter used interface FAST standard CMOS. This level shifter used drive Power MOSFET directly with buffer like MC14049UB Figure decrease switching times. MC14504B selectable TTUCMOS level inputs standard CMOS outputs. source sink maximum about using volt supply.
very careful when using drivers latches which have tri-state outputs, like 74LS240-74HC240 74LS373-74HC373, drive power MOSFET. tri-state devices require pull-up resistor drive power MOSFET volts, will therefore leave power MOSFET when outputs disabled. devices with tri-state outputs will gate float when outputs disabled, possibly damaging power MOSFET. Tri-state devices used provided output enable tied true, negative logic enable inputs. tri-state devices require pull-up resistor drive logic level power MOSFET, therefore used with pull-down resistorto ground. Note that tri-state outputs should never pulled above supply rail below ground.
When simplicity important, single chip microcomputer like 68HC11 used drive power MOSFET directly. This microcomputer used perform functions like Pulse Width Modulation, complex motor speed control, controlling multiple power MOSFETs bridge applications. When microcomputer used single chip mode, pins parallel output port used drive Logic Level power MOSFET large gate series resistor should used minimize power dissipation noise chip. This means that switching times will fairly slow. This arrangement also exposes microprocessor possible harm from power MOSFET failure. Although outputs port will reset zero Power-On Reset (POR), pull down ground should used ensure power MOSFET will during power down. some appli-
cations necessary initialize power MOSFET gate drive software before power supplied power MOSFET.
Port also used strobed mode using STRB signal from control port STRB signal will high after data port valid used latch enable logic device driving power MOSFET. This mode useful when exact synchronization desired between microprocessor controlled devices.
When used extended memory mode, ports used address data busses. 68HC24 port replacement unit will replace port software transparent fashion. Thus, system developed using 68HC11 with 68HC24 external memory, while final product will only 68HC11.
CONCLUSION
have seen that standard Power MOSFETs interfaced directly standard CMOS logic with very good performance, about rise fall times MC14049UB driving power MOSFET. Standard Power MOSFETs also interfaced volt logic using special interface device such 74LS26 open collector NAND gate MC14504B level shifter. 74LS26 driving standard Power MOSFET gives turn times about fast turn times less than Switching times easily estimated using four simple equations series resistor selected give desired rise fall times.
Logic Level Power MOSFETs driven directly with logic, logic with addition pull-up resistor. Switching speeds using device very fast, less than gate when driving power MOSFET. Using device, turn speed good, about turn speed excellent, less than Again, switching speeds easily estimated series resistor selected give desired performance.
Logic power supply variations most important aspect affecting Logic Level Power MOSFET performance. Power supply sequencing under-voltage protection necessary ensure system integrity. Circuit lay-out power supply decoupling also important high speeds.
Finally Logic Level Power MOSFET interfaced directly dedicated microprocessor output port when microprocessor control desired.
Bibliography
Motorola Power MOSFET Transistor Data, DL135
1988, 1-4, 3.711-716.
Motorola MTP3055EL Designer Data Sheet, MTP3055EUD,
1988.
Motorola CMOS Logic Data, DL131 1988, 6.125-128 6.154-155.
Motorola FAST Data, DL121 1988, 4.6-7 5.6.
Motorola High-Speed Logic Data, DL129 3,1988, 5.11-14.
Paul Grey Robert Meyer. Analysis Design Analog Integrated Circuits, Second Edition, 1984, Wiley Sons, 55-75,
Adel Sedra Kenneth Smith. Microelectronic Circuits; Holt, Rinehart Winston; 1982; 689-715.
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25178T PRINTED (1994) PWft YAAGAA
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