Products 100117 Gate Triple 1-2-2 Input OR-AND/OR-AND-I
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100117
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Triple 1-2-2 Input OR-AND/OR-AND-INVERT Gate Product Specification
100117 three 1-2-2 input NAND gates with true complementary outputs.
TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT <-"ee)
100117 0.75ns 57mA
1.40ns
ORDERING CODE
PACKAGES COMMERCIAL RANGE Vcci Vera GND; -4.2V -4.8V
Ceramic 100117F
Ceramic Flat Pack 100117Y
PINS Do-D,, Data Inputs
Enable Inputs
Qo-Q2, QO-52 Data Outputs
CONFIGURATION LOGIC SYMBOL
CERAkUC
_&SSJRRB_
THHTETHEE
VcciVcca VIEW
Figure
Veci VcC2 8(5)
<3)5
04)3 7(4)
(1)4 12(9)
tmss
(22)1
(23)2
(20)23 1-17 11(8)
(21)24 13(10)
(17)20
(12)15
(13)* 1-no
(14)17 14(11)
Plfi connactfons Flat Pack Caramto package
Figure
January 1986 7-40 853-0610 82178
This Material Copyrighted Respective Manufacturer
Signetics Products
Product Specification
Gate 100117
FUNCTION TABLE (One Gate)
INPUTS OUTPUTS
Positive Logic:
HIGH state (more positive voltage) state (less positive voltage) Don't Care
ABSOLUTE MAXIMUM RATINGS (Operation beyond limits forth this table impair useful life device. Unless
otherwise noted, these limits specified over operating ambient temperature range.)
PARAMETER 100K UNIT
Supply voltage (Veci Vcc2 ~GND) -7.0
Input voltage (V|N should never more negative than VEE) +0.5
Output source current
Storage temperature +150
Maximum junction temperature
OPERATING CONDITIONS
PARAMETER 100K UNIT
Vcci. Vcc2 Circuit ground
Supply voltage (negative) -4.2 -4.5 -4.8
Supply voltage (negative) when operating with family -5.7
HIGH level input voltage Veci Vcc2 -4.2V -1150 -880
=-4.5V -1165
=-4.8V
HIGH level input threshold voltage -4.2V -1150
=-4.5V -1165
-4.8V
level input threshold voltage -4.2V -1475
-4.5V
-4.8V -1490
level input voltage -4.2V -1810 -1475
-4.5V
-4.8V -1490
Operating ambient temperature
NOTE:
When operating other than specified voltages {-4.2V, -4.5V.-4.8V) Characteristics will vary slightly from specified values.
January 1986 7-41
This Material Copyrighted Respective Manufacturer
Signetics Products Product Specification
Gate 100117
ELECTRICAL CHARACTERISTICS Vcc, Vcc2-GND, VEE-4.2V to.oiov -4.8V
unless otherwise specified13
PARAMETER UNIT TEST CONDITIONS2
HIGH level output voltage -4.2V -1025 -870 V|Hmax ViLmin Loading with -2.0V 0.010V
-4.5V -1025 -955 -880
-4.8V -1035 -880
HIGH level output threshold voltage VEe-4.2V -1035 ViHmin V|Lmax
-4.5V -1035
-4.8V -1045
level output threshold voltage -4.2V -1590 V|Hmtn V|Lmax
-4.5V -1610
-4.8V -1610
level output voltage -4.2V -1810 -1600 V|Hmax ViLmin
-4.5V -1810 -1705 -1620
-4.8V -1830 -1620
HIGH level input current V|Hmax
Other inputs
level input current ViLmin
-Iee supply current Inputs open
HIGH level output voltage compensation -4.2V 0.025
level output voltage compensation 0.050
NOTES:
specified limits represent "worst case" value parameter. Since these "worst case" values normally occur temperature extremes, additional noise immunity guard banding achieved decreasing allowable system operating ranges.
Conditions testing shown tables necessarily worst case. worst case testing guidelines, refer Section Testing, Testing.
specified limits shown Characteristics only after thermal equilibrium been established. Thermal equilibrium established applying power least minutes white maintaining transverse flow meteis/s (500 linear feet/min) over device either mounted test socket printed circuit board. Test voltage values given Operating Conditions defined Figure
January 1986 7-42
This Material Copyrighted Respective Manufacturer
Signetics Products
Product Specification
Gate
100117
VOUI
NOTES:
ViHowx Maximum HIGH level input voltage (the most poajtive V)H)-
HIGH level input threshold voltage.
VILT level input threshold voltage.
Villain Minimum level input voltage (the most negative ViJ.
VoHmw Maximum high level output voltage (the most positive Voh) under specified input loading concfetion.
VoHmin Minimum HIGH level output vottage (the most negative Voh) under specified input loading condHion.
Voht HIGH level output threshold voltage with inputs their respective threshold levels.
Volt level output threshold voltage with inputs their respective threshold levels.
Vounax Maximum level output voltage (the most positive Vol) under specified input loacHng condttons.
volff* Minimum level output voltage (the most negative Vol) under specified input loading conditions.
Reference bias voltage (the internally generated reference voltage which used input output threshold level).
Figure Transfer Characteristics
ELECTRICAL CHARACTERISTICS
Ceramic Vcci -4.av to.otov
parameter +25"C unit test conditions
tpLH Propagation delay tpHL 0.90 0.90 2.60 2.60 0.90 0.90 2.50 2.50 0.90 0.90 2.60 2.60 Figs.
tpLH Propagation delay tpHL 0.45 0.45 1.40 1.40 0.45 0.45 1.30 1.30 0.45 0.45 1.40 1.40
tTLH Transition time tjHL 80%, 0.45 0.45 1.20 1.20 0.45 0.45 1.10 1.10 0.45 0.45 1.20 1.20
Ceramic veci vcc2 gnd, vee-5.2V
PARAMETER UNIT TEST CONDITIONS
tpi_H Propagation delay tpHL 0.90 0.90 2.60 2.60 0.90 0.90 2.50 2.50 0.90 0.90 2.60 2.60 Figs.
tpLH Propagation delay tpHL 0.45 0.45 1.40 1.40 0.45 0.45 1.30 1.30 0.45 0.45 1.40 1.40
tTLH Transition time tthi 80%, 0.45 0.45 1.20 1.20 0.45 0.45 1.10 1.10 0.45 0.45 1.20 1.20
Flat Pack Veci =Vcc2-gnd, +0.010V -4.8V 0.010V
PARAMETER +85"C UNIT TEST CONDITIONS
tpLH Propagation delay tpHL 0.90 0.90 2.40 2.40 0.90 0.90 2.30 2.30 0.90 0.90 2.40 2.40 Figs.
tpLH Propagation delay tpHL 0.45 0.45 1.20 1.20 0.45 0.45 1.10 1.10 0.45 0.45 1.20 1.20
Itlh Transition time tfHL 80%, 0.45 0.45 1.20 1.20 0.45 0.45 1.10 1.10 0.45 0.45 1.20 1.20
January 1986 7-43
This Material Copyrighted Respective Manufacturer
Signetics Products
Product Specification
Gate 100117
ELECTRICAL CHARACTERISTICS
Flat Pack Voci VCC2 GND, VEE-S.2V
PARAMETER +25"C UNIT TEST CONDITIONS
tpLH Propagation delay tpHL 0.90 0.90 2.40 2.40 0.90 0.90 2.30 2.30 0.90 0.90 2.40 2.40 Figs.
tpLH Propagation delay tpHL 0.45 0.45 1.20 1.20 0.45 0.45 1.10 1.10 0.45 0.45 1.20 1.20
tjLH Transition time tTHL 80%, 0.45 0.45 1.20 1.20 0.45 0.45 1.10 1.10 0.45 0.45 1.20 1.20
WAVEFORMS
Figure Propagation Dalay Transition Timas
January 1986 7-44
This Material Copyrighted Respective Manufacturer
Signetics Products
Product Specification
Gate
100117
TEST CIRCUITS WAVEFORMS
+2.0 0.010
NOTES:
Vcci Vcc2 2.0V 10.010V. -3-2V 0.010V.
Decoupling 25/jF from Vcc. 0.01 25(iF from VeE. (0.01 capacitors should Ceramic type). Decoupling capacitors should placed close physically possible lead length should kept less than inch (6mm).
unused inputs should connected either HIGH state consistent with LOGIC function required.
unused outputs loaded with 50ft GND.
equal length 50ft impedance lines. distance from junction cable from Pulse Generator cable Scope, should exceed inch (6mm).
50ft terminator internal Scope.
unmatched wire stub between coaxial cable pins under test must less than inch (6mm) long proper test.
Fixture stray capacitance 3pF.
unterminated stubs connected anywhere along transmission line between Pulse Generator between Scope should exceed inch (6mm) length (refer section setup procedure).
50ft resistors should have tolerance better.
connections Flat Pack parentheses Ceramic DIP.
Figure Test Circuit
NEGATIVE PULSE
POSITIVE PULSE
INPUT PULSE REQUIREMENTS
VCC1 VCC2= +2.0V 0.010V, -2.5V 0.010V, (0V)
Family Amplitude Rate Pulse Width *TLH tTHL
100K 740mVp-p 1MHz 500ns 0.1ns 0.1ns
Figure Input Pulse Definition
January 1986 7-45
This Material Copyrighted Respective Manufacturer
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