MSM60300, MSM60700, MSM61000 CMOS GATE ARRAYS GENERAL DESCRIPTION

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MSM60300, MSM60700, MSM61000 CMOS GATE ARRAYS GENERAL DESCRIPTION

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MSM60300, MSM60700, MSM61000 CMOS GATE ARRAYS GENERAL DESCRIPTION
MSM60300. MSM60700. MSM61000 gate arrays fabricated using state-of-the-art dual-layer metal silicon gate CMOS technology. unit cell consists pairs transistors where each pair made PMOS NMOS transistor. 2-input NAND gates implemented unit cell. Each interface cell used input, push/pull, tri-state bi-directional buffer, open drain driver. offers PLCC, DIP. FLAT PACK packages. number pins available these packages ranges from pins.
Series Name MSMC0300 MSM60700 MSM61000
Number Unit Cells 1,000
Equivalent 2-input Gates 1,440 2,000
Number l/O's
Supply Pins
dual-layer silicon gate CMOS technology
Typical gate delay nsec.
operating frequency
power dissipation High noise Immunity
inputs protected against damage Electro Static Discharge (ESD)
inputs/outputs CMOS compatible
Each interface cell used Input, push/pull, tri-state buffer, open drain driver
functional blocks (e.g. INV, NAND, FFs, etc.)
MACRO LOGIC BLOCKS (7400 series logic functions)
Sophisticated tools logic, timing fault simulations auto place route
->90% utilization
100% auto place routable
3-"3-
ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATING
Item Symbol Condition Rated Value Unit
Supply voltage -0.5
voltage (against GND) -0.5
current
Storage temperature +150
Power Dissipation package
OPERATING RANGE
RECOMMENDED OPERATING CONDITIONS
Item Symbol Range Unit
Supply voltage
Operating temperature Topr
Conditions
Item Symbol Min. TVP. Max. Unit
Supply voltage
Operating temperature Top*
Input High Voltage Vim'
Input Voltage -0.3
2.0V.
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CHARACTERISTICS
(Vcc 10%,
Item Symbol Condition Specified Value Units
Min. Typ. Max.
Input high current 5.5V
Input current
Output leakage current (3-states bi-directional bus)
Output high voltage 4.5V
-400fiA
Output voltage
Standby power supply current Iccs 5.5V
INPUT/OUTPUT CAPACITANCE
Standard Values
Item Symbol Conditions Min. Typ. Max. Unit
Input terminal capacitance
Output terminal capacitance
Bi-directional terminal capacitance
CHARACTERISTICS
Item Symbol Min. Typ. Max. Unit
Prop NAND nsec.
F.O. Metal Length
Toggle
Operating Freq. fmax
Input Output Buffer tpLH 26.2 nsec.
Prop Delay tphtL 33.9 nsec.
Output Buffer Transition 32.3 nsec.
Time 12.3 nsec.
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Input Butter (BFIN) Propagation Delay Time Fanout
Output Buffer (BN) Propagation Delay Time Load Capacitance
(PF)
CELL LIBRARIES
table below following page lists MACRO BLOCKS FUNCTIONAL BLOCKS. Each functional block been fully characterized, data sheets each block available OKI's CMOS DESIGN MANUAL. func-
MACRO BLOCK LIST
Logic Function Macro Block Name Cells Comment
7442 BCD-to-Decimal Decoder (0042)
7485 4-Bit Magnitude Comparator (0085)
7491 8-Bit Shift Register (0091)
7492 Divide-by-twelve Counter (0092)
7493 4-Bit Binary Counter (0093)
7494 4-Bit Shift Register (0094)
7495 4-Bit Shift Register (0095)
74138 3-Line 8-Line Decoder Demultiplexer (0138)
74139 2-line 4-line Decoder/Demultiplexer (0139)
74148 8-line 3-line Priority Encoder (0148)
74151 8-line 1-line Data Selector/Multiplexer (0151)
74152 8-line 3-line Data Selector/Multiplexer (0152)
74153 Dual 4-line 1-line Data Selector/Multiplexer (0153)
74155 Dual 2-line 4-line Decoder /Demultiplexer (0155)
tionat blocks macro blocks libraries available floppy disk used DAISY MENTOR WORKSTATIONS.
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MACRO BLOCK LIST cont'd
Logic Function Macro Block Name Cells Comment
74157 Quadruple 2-line 1-line Data Selector/Multiplexer (0157)
74158 Quadruple 2-line 1-line Data Selector/Multiplexer (0158)
74160 Synchronous Decade Counter (0160)
74161 Synchronous 4-Bit Binary Counter (0161)
74162 Synchronous Decade Counter (0162)
74163 Synchronous 4-Bit Binary Counter (0163)
74164 8-Bit Parallel-Out Serial Shift Register (0164)
74165 Parallel-LOAD 8-Bit Shift Register (0165)
74166 8-Bit Shift Register (0166)
74169 Synchronous 4-Bit Binary Up/Down Counter (0169)
74175 Quadruple D-type Flip-Flops with Clear (0175)
74181 Arithmetic Logic Unit /Function Generator (0181)
74182 Look-Ahead Carry Generator (0182)
74190 Synchronous Up/Down Counter with Down/Up Mode Control (0190)
74191 Synchronous 4-Bit Binary Up/Down Counter with Down/Up Mode Control (0191)
74192 Synchronous Up/Down Dual Ciock Counter with Clear (0192)
74193 Synchronous 4-Bit Binary Up/Down Dual Clock Counter with Clear (0193)
74194 4-Bit Bidirectional Universal Shift Register (0194)
74195 4-Bit Parallel-Access Shift Register (0195)
74259 8-Bit Addressable Latches (0259)
74280 9-Bit Odd/Even Parity Generator/Checker (0280)
74283 4-Bit Binary Full Adder with Fast Carry (0283)
74298 Quadruple 2-input Multiplexer with Storage (0298)
74393 Dual 4-Bit Binary Counter (0393)
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FUNCTIONAL BLOCK LIST
Functional F.O.
Block Name Logical Function Unit Cells Max.
Inverter
2-lnput NAND
3-lnput NAND
4-In NAND
5-lnput NAND
6-lnput NAND
7-lnput NAND
8-lnput NAND
2-input
3-lnput
4-lnput
5-lnput
6-lnput
7-lnput
8-lnput
2-lnput
3-lnput
4-lnput
5-lnput
6-lnput
7-lnput
8-lnput
2-lnput
3-lnput
4-lnput
5-lnput
6-lnput
7-lnput
8-lnput
Exclusive
Exclusive
2-lnput 2-Wide AND-OR
3-lnput 3-Wlde AND-OR
4-lnput 4-Wide AND-OR
2-lnput 2-Wlde OR-AND
3-lnput 3-Wide OR-AND
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FUNCTIONAL BLOCK LIST cont'd
Functional Block Name Logical Function Unit Cells Max.
4-lnput 4-Wide OR-AND
1CRY Carry
Type Latch
D-Type Latch with Reset
D-Type Flip Flop with Reset
D-Type Flip Flop with Set/Reset
JKFR Flip Flop with Reset
Flop with Set/Reset
Toggle Flip Flop with Reset
INV2 Dual Inverter
2ND2 Dual 2-lnput NAND
3ND2 Dual 3-lnput NAND
4ND2 Dual 4-lnput NAND
2NR2 Dual 2-lnput
3NR2 Dual 3-lnput
4NR2 Dual 4-lnput
Dual Type Latch
DFR2 Dual D-Type Flip Flop with Reset
2AD2 Dual 2-lnput
3AD2 Dual 3-lnput
20R2 Dual 2-lnput
30R2 Dual 3-lnput
INV3 Triple Inverter
INV4 Quad Inverter
DLT4 Quad D-Type Latch with Reset
Clock Buffer-1 (Invert)
Clock Buffer-2 (Through)
Clock Buffer-3 (Through)
Fixed High Level
Fixed Level
BFIN Input Buffer (Through)
Output Buffer (Through)
Open Drain Output Driver
Current Force Output Driver
3-State Output Buffer (Through)
Common Buffer (Through)
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DEVELOPMENT PROCESS INTERFACE LEVEL
Development Process
INTERFACE LEVEL
OKI's Irrterlace/CAD assistance accosstoie three levels:
choose stage development most advantageous your individual resources.
CUSTOMER
Design Manual Complete technical data development tools procedures BINALY Manual Describes syntax procedures OKI's BINALY Logic Simulation.
Logic Diagram Test Vectors AC/DC Spec.
LEVEL
Guided CMOS Gate
Array Manual, provide with your logic schematic, test vectors AC/DC parameters. further development OKI's responsibility.
LEVEL
addition CMOS Manual, BJnaly Manual
logic simulation. After providing with logic schematic drawn OKI's format plus data base simulation results, takes over
LEVEL THREE
Having installed data base OKI's gate array your design automation system, deliver tape Sentry test tape. then completes development volume production processes.
Data Entry
Input schematic details into terminals.
Logic Simulation Accurate Simulation (Pre-layout timing simulation) Fault Simulation
Auto Placement Route Place interconnect logic cells optimize your specs.
Timing Simulation Calculates actual propagation delay time critical path.
P.G. Tape
Final pattern generated tape preparatory masking.
Mask Assembly
Wafer Final Test
Wafer Test
Prototypes shipped Customer
HIGH VOLUME PRODUCT/ON
Logic Diagram Test Vectors
Recheck original data entered simulation results.
Logic Diagram Recheck entire development process from data entered through simulation, place route.
Evaluation Approval
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LIST CMOS GATE ARRAY PACKAGES
Note: Available when desired customers Readily available customers available customers Available Available
Shape Series name
Material MSM60300 MSM60700 MSM61000
PLASTIC
CERAMIC
PLASTIC
CERAMIC
PLASTIC
CERAMIC
PLASTIC
CERAMIC
PLASTIC
CERAMIC
PLASTIC
CERAMIC
PLASTIC
CERAMIC
FLAT PLASTIC
PLASTIC
PLASTIC
PLASTIC
CERAMIC
PLASTIC
CERAMIC
CERAMIC
PLCC PLASTIC
PLASTIC
SEMICONDUCTOR, INC. MARY AVENUE, SUNNYVALE, 94086_
TELEPHONE: (408) 720-1900 TELEX (25) 910-3380508_
Semiconductor reserves right make changes specifications anytime without notice. information furnished Semiconductor this publication believed accurate reliable. However, responsibility assumed Semiconductor use; infringements patents other rights third parties resulting from license granted under patents patent rights OKI.
SEMICONDUCTOR, INC.
PRINTED
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MSM60300, MSM60700, MSM61000 CMOS GATE ARRAYS GENERAL DESCRIPTION

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