TIMERS SLFS043B SEPTEMBER 1983 REVISED 1997 Very Power Consu

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TIMERS SLFS043B SEPTEMBER 1983 REVISED 1997 Very Power Consu

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TLC555, TLC555Y
TIMERS
SLFS043B SEPTEMBER 1983 REVISED 1997
Very Power Consumption
Capable Operation Astable Mode CMOS Output Capable Swinging Rail Rail
High Output-Current Capability Sink Source Output Fully Compatible With CMOS, TTL,
Supply Current Reduces Spikes During Output Transitions Single-Supply Operation From Functionally Interchangeable With NE555; Same Pinout Protection Exceeds 2000 MIL-STD-883C, Method 3015.2
package (top view)
TRIG DISCH
]THRES
RESET[ CONT
package (top view)
TRIG
i_ii_ii_ii_ii_i
DISCH
THRES
internal connection
TLC555 monolithic timing circuit fabricated using process. timer fully compatible with CMOS, TTL,
logic operates frequencies MHz. Because high input impedance, this device uses smaller timing capacitors than those used E555. result, more accurate time delays oscillations possible. Power consumption across full range power supply voltage.
Like NE555, TLC555 trigger level equal approximately one-third supply voltage threshold level equal approximately two-thirds supply voltage. These levels altered control voltage terminal (CONT). When trigger input (TRIG) falls below trigger level, flip-flop output goes high. TRIG above trigger level threshold input (THRES) above threshold level, flip-flop reset output low. reset input (RESET) override other inputs used initiate timing cycle. RESET low, flip-flop reset output low. Whenever output low, low-impedance path provided between discharge terminal (DISCH) GND. unused inputs should tied appropriate logic level prevent false triggering.
While CMOS output capable sinking over sourcing over TLC555 exhibits greatly reduced supply-current spikes during output transitions. This minimizes need large decoupling capacitors required NE555.
TLC555C characterized operation from TLC555I characterized operation from 40cC TLC555M characterized operation over full military temperature range
This device contains circuits protect inputs outputs against damage high static voltages electrostatic fields. These circuits have been qualified protect this device against electrostatic discharges (ESD) according MIL-STD-883C, Method 3015; however, advised that precautions taken avoid application voltage higher than maximum-rated voltages these high-impedance circuits. During storage handling, device leads should shorted together device should placed conductive foam. circuit, unused inputs should always connected appropriated logic voltage level, preferably either supply voltage ground. Specific guidelines handling devices this type contained publication Guidelines Handling (ESDS) Devices Assemblies available from Texas Instruments.
LinCMOS trademark Texas Instruments Incorporated.
Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
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TLC555, TLC555Y
TIMERS
SLFS043B- SEPTEMBER 1983- REVISED 1997
available options
packaged devices chip form
range small outline ssop (db) chip carrier (fk) ceramic (jg) plastic tssop (pw)
TLC555CD TLC555CDBLE TLC555CP TLC555CPWLE TLC555Y
TLC555ID TLC555IP
TLC555MD TLC555MFK TLC555MJG TLC555MP
package available taped reeled. suffix device type (e.g., TLC555CDR). packages only available left-end taped reeled (indicated suffix device type; e.g., TLC555CDBLE). Chips tested
function table
RESET VOLTAGEt TRIGGER VOLTAGEt THRESHOLD VOLTAGEt OUTPUT DISCHARGE SWITCH
<MIN Irrelevant Irrelevant
>MAX <MIN Irrelevant
>MAX >MAX >MAX
>MAX >MAX <MIN previously established
conditions shown MAX, appropriate value specified under electrical characteristics.
functional block diagram
cont reset
numbers packages except package. RESET override TRIG, which override THRES.
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TLC555, TLC555Y
TIMERS
SLFS043B- SEPTEMBER 1983 REVISED 1997
TLC555Y chip information
This chip, when properly assembled, displays characteristics similar TLC555. Thermal compression ultrasonic bonding used doped aluminum bonding pads. Chips mounted with conductive epoxy gold-silicon preform.
BONDING ASSIGNMENTS
'111 '111111 N11111 '111 '111
CONT RESET
1(5)
THRES
TRIG
JiU!>
DISCH
RESET override TRIG, which override THRES.
CHIP THICKNESS: TYPICAL BONDING PADS: MINIMUM Tjmax TOLERANCES 10%. DIMENSIONS MILS.
INTERNALLY CONNECTED BACKSIDE CHIP.
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Template Release Date: 7-11-94
TLC555, TLC555Y TIMERS
SLFS043B SEPTEMBER 1983 REVISED 1997
"tZL
"t=L
o-vw-
i-AA/V-f jC?-
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TLC555, TLC555Y
TIMERS
_SLFS043B- SEPTEMBER 1983- REVISED 1997
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage, (see Note
Input voltage range, (any Input) -0.3
Sink current, discharge output
Source current, output,
Continuous total power dissipation Dissipation Rating Table
Operating free-air temperature range, C-suffix
l-suffix
M-suffix
Storage temperature range
Case temperature seconds: package
Lead temperature (1/16 inch) from case seconds: package
Lead temperature (1/16 inch) from case seconds: package
Stresses beyond those listed under "absolute maximum ratings" cause permanent damage device. These stress ratings only functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. NOTE voltage values with respect network GND.
DISSIPATION RATING TABLE
PACKAGE POWER RATING DERATING FACTOR ABOVE POWER RATING POWER RATING POWER RATING
1375 11.0
1050
1000
recommended operating conditions
UNIT
Supply voltage,
TLC555C
Operating free-air temperature range, TLC555I
TLC555M
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TLC555, TLC555Y
TIMERS
SLFS043B- SEPTEMBER 1983- REVISED 1997_
electrical characteristics specified free-air temperature, TLC555C,
PARAMETER test TLC555C TLC555I UNIT
CONDITIONS
Threshold voltage 0.95 1.33 1.65
Full range 0.85 1.75
Threshold current
VI(TRIG) Trigger voltage 0.67 0.95 0.71 1.29
Full range 1.05 0.61 1.39
'l(TRIG) Trigger current
VI(RESET) Reset voltage
Full range
'l(RESET) Reset current
Control voltage (open circuit) percentage supply voltage 66.7% 66.7%
Discharge switch on-stage 0.03 0.03
voltage Full range 0.25 0.375
Discharge switch off-stage
current
High-level output voltage =-300nA
Full range
Low-level output voltage Iq|_ 0.07 0.07
Full range 0.35
Supply current Note
Full range
Full range TLC555C TLC555I. conditions shown MAX, appropriate value specified
recommended operating conditions table. NOTE These values apply expected operating configurations which THRES connected directly DISCH TRIG.
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TLC555, TLC555Y
TIMERS
SLFS043B SEPTEMBER 1983 REVISED 1997
electrical characteristics specified free-air temperature,
parameter test tlc555c tlc555i tlc555m unit
conditions
Threshold voltage
Full range
Threshold current
5000
VI(TRIG) Trigger voltage 1.36 1.66 1.96 1.36 1.66 1.96 1.36 1.66 1.96
Full range 1.26 2.06 1.26 2.06 1.26 2.06
'l(TRIG) Trigger current
5000
Vi(RESET) Reset voltage
Full range
Preset) Reset current
5000
Control voltage (open circuit) percentage supply voltage 66.7% 66.7% 66.7%
Discharge switch 0.14 0.14 0.14
on-state vollage Full range
Discharge switch
off-state current
High-level output IOH=
voltage Full range
0.21 0.21 0.21
Full range
Low-level output 0.13 0.13 0.13
voltage Full range 0.45
0.08 0.08 0.08
Full range 0.35 0.35
Supply current Note
Full range
Full range TLC555C, TLC555I, TLC555M. conditions shown
MAX, appropriate value specified recommended operating conditions table. NOTE These values apply expected operating configurations which THRES connected directly DISCH TRIG.
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TLC555, TLC555Y
TIMERS
SLFS043B- SEPTEMBER 1983- REVISED 1997
electrical characteristics specified free-air temperature,
PAR&MPTPR test tlc555c tlc555i tlc555m unit
conditions
Threshold voltage 9.45 10.55 9.45 10.55 9.45 10.55
Full range 9.35 10.65 9.35 10.65 9.35 10.65
Threshold current
5000
VI(TRIG) Trigger voltage 4.65 5.35 4.65 5.35 4.65 5.35
Full range 4.55 5.45 4.55 5.45 4.55 5.45
'l(TRIG) Trigger current
5000
VI(RESET| Reset voltage
Full range
'l(RESET) Reset current
5000
Control voltage (open circuit) percentage supply voltage 66.7% 66.7% 66.7%
Discharge switch IQI_ 0.77 0.77 0.77
on-state voltage Full range
Discharge switch
off-state current
12.5 14.2 12.5 14.2 12.5 14.2
Full range 12.5 12.5 12.5
High-level output 13.5 14.6 13.5 14.6 13.5 14.6
voltage Full range 13.5 13.5 13.5
14.2 14.9 14.2 14.9 14.2 14.9
Full range 14.2 14.2 14.2
'OL= 1.28 1.28 1.28
Full range
Low-level output 0.63 0.63 0.63
voltage Full range
IOL= 0.12 0.12 0.12
Full range 0.45
Supply current Note
Full range 1000
Full range TLC555C, TLC555I, 125"C TLC555M. conditions shown MAX, appropriale value
specified recommended operating conditions table. NOTE These values apply expected operating configurations which THRES connected directly DISCHor TRIG.
operating characteristics, (unless otherwise noted)
PARAMETER TEST CONDITIONS UNIT
Initial error timing interval^ VDD=5Vto15V, kfltolOOkii, 0.1|aF, Note
Supply voltage sensistivity timing interval
Output pulse rise time R[_=10Mi},
Output pulse fall time
'max Maximum frequency astable mode 47012, 200Q, Note
Timing interval error defined difference between measured value average value random sample from each process run.
NOTE defined Figure
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TLC555, TLC555Y
TIMERS
SLFSQ43B- SEPTEMBER 1983 REViSED 1997
electrical characteristics
PARAMETER TEST CONDITIONS UNIT
Threshold voltage
Threshold current
VI(TRIG) Trigger voltage 1.36 1.66 1.96
'l(TRIG) Trigger current
V|(RESET) Reset voltage
(RESET) Reset current
Control voltage (open circuit) percentage supply voltage 66.7%
Discharge switch on-state voltage 0.14
Discharge switch off-state current
High-level output voltage
0.21
Low-level output voltage 0.13
0.08
Supply current Note
NOTE These values apply expected operating configurations which THRES connected directly DISCH TRIG.
TYPICAL CHARACTERISTICS
DISCHARGE SWITCH ON-STATE RESISTANCE
FREE-AIR TEMPERATURE
Free-Air Temperature
Figure
PROPAGATION DELAY TIMES DISCHARGE OUTPUT FROM TRIGGER THRESHOLD SHORTED TOGETHER
SUPPLY VOLTAGE
'O(on)
Supply Voltage
effects load resistance these values must taken into account separately.
Figure
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TLC555, TLC555Y
TIMERS
SLFS043B SEPTEMBER 1983 REVISED 1997
APPLICATION INFORMATION
tplh
numbers shown packages except package.
circuit
trigger threshold voltage waveform
Figure Astable Operation
Connecting TRIG THRES, shown Figure causes timer multivibrator. capacitor charges through threshold voltage level (approximately 0.67 VDD) then discharges through only value trigger voltage level (approximately 0.33 Vdd)- output high during charging cycle (tc(H))and during discharge cycle (tc(L)). duty cycle controlled values shown equations below.
lc(H)
0.693)
'c(L) Period
c(H) lc(L)
Output driver duty cycle
2RB)
lc(L)
lc(H)
Output waveform duty cycle
C(H)
c(H) lc(L)
0.1-^F capacitor CONT Figure decreases period about 10%.
formulas shown above allow propagation delay times from TRIG THRES inputs DISCH. These delay times directly period create differences between calculated actual values that increase with frequency. addition, internal on-state resistance during discharge adds provide another source timing error calculation when very very high.
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TLC555, TLC555Y
TIMERS
SLFS043B- SEPTEMBER 1983 REVISED 1997
APPLICATION INFORMATION
equations below provide better agreement with measured values.
*c(H)
^(L) ron)
-expl
-expl
ron)
These equations those given earlier similar that time constant multiplied logarithm number function. limit values logarithmic terms must between frequencies extremely high frequencies. duty cycle close 50%, appropriate constant logarithmic terms substituted
with good results. Duty cycles less than
c(H)
conditions difficult obtain.
lc(H) lc(L)
require that C(H) possibly ron. These
c(L)
monostable applications, trip point TRIG voltage applied toCONT. input voltage between supply voltage from resistor divider with least 500-)iA bias provides good results.
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TIMERS
SLFSQ43B- SEPTEMBER 1983- REVISED 1997_
MECHANICAL DATA
(R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
SHOWN
0.050(1,27)
0.020 (0,51) 0.014(0,35)
0.010(0,25)
0.244 (6,20) 0.228 (5,80)
0.157 (4,00) 0.150(3,81)
0.197 (5,00) 0.344 (8,75) 0.394 (10,00)
0.189 (4,80) 0.337 (8,55) 0.386 (9,80)
0.008 (0,20)
0.069 (1,75)
0.010(0,25) 0.004(0,10)
Seating Plane
0.004(0,10)
0.010(0,25)
0.044(1,12) 0.016(0,40)
4040047/D 10/96
NOTES: linear dimensions inches (millimeters).
This drawing subject change without notice.
Body dimensions include mold flash protrusion, exceed 0.006 (0,15).
Falls within JEDEC MS-012
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TLC555, TLC555Y
TIMERS
_SLFS043B SEPTEMBER 1983 REVISED 1997
MECHANICAL INFORMATION (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
SHOWN
3,30 6,50 6,50 7,50 8,50 10,50 10,50 12,90
2,70 5,90 5,90 6,90 7,90 9,90 9,90 12,30
4040065/C 10/95
NOTES: linear dimensions millimeters.
This drawing subject change without notice.
Body dimensions include mold flash protrusion exceed 0,15.
Falls within JEDEC MO-150
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TLC555, TLC555Y
TIMERS
SLFS043B- SEPTEMBER 1983- REVISED 1997
(S-CQCC-N**)
TERMINAL SHOWN
MECHANICAL INFORMATION
LEADLESS CERAMIC CHIP CARRIER
TERMINALS
0.342 (8,69) 0.358 (9,09) 0.307 (7,80) 0.358 (9,09)
0.442 (11,23) 0.458 (11,63) 0.406 (10,31) 0.458 (11,63)
0.640 (16,26) 0.660 (16,76) 0.495 (12,58) 0.560 (14,22)
0.739 (18,78) 0.761 (19,32) 0.495 (12,58) 0.560 (14,22)
0.938 (23,83) 0.962 (24,43) 0.850 (21,6) 0.858 (21,8)
1.141 (28,99) 1.165 (29,59) 1.047 (26,6) 1.063 (27,0)
0.020 (0,51) 0.010(0,25)
0.055 (1,40) 0.045(1,14)
0.020 (0,51) 0.010(0,25)
0.028 (0,71) 0.022 (0,54)
0.050 (1,27)
0.045 (1,14) 0.035 (0,89)
0.045(1,14) 0.035 (0,89)
NOTES: linear dimensions inches (millimeters).
This drawing subject change without notice.
This package hermetically sealed with metal lid.
terminals gold plated.
Falls within JEDEC MS-004
0.080 (2,03) 0.064(1,63)
4040140/D 10/96
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TLC555, TLC555Y
TIMERS
SLFS043B SEPTEMBER 1983 REVISED 1997
MECHANICAL INFORMATION
(R-GDIP-T8)
CERAMIC DUAL-IN-LINE PACKAGE
0.400 (10,20) 0.355 (9,00)
>.065 (1,65) I.045 (1,14)
0.280 (7,11) 0.245 (6,22)
0.020 (0,51)
0.063(1,60) 0.015(0,38)
0.310(7,87) 0.290 (7,37)
0.100(2,54)
0.200 (5,08)
^_Seating Plane
0.130 (3,30)
0.023 (0,58)
0.015(0,38)
0.014(0,36) 0.008 (0,20)
4040107/C 08/96
NOTES: linear dimensions inches (millimeters).
This drawing subject change without notice.
This package hermetically sealed with ceramic using glass frit.
Index point provided terminal identification only press ceramic glass frit seal only.
Falls within MIL-STD-1835 DIP1-T8
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TLC555, TLC555Y
TIMERS
SLFS043B- SEPTEMBER 1983- REVISED 1997
MECHANICAL DATA
(R-PDIP-T8) PLASTIC DUAL-IN-LINE PACKAGE
0.400 (10,60) 0.355 (9,02)
0.260 (6,60) 0.240 (6,10)
0.070(1,78)
0.020 (0,51)
0.125 (3,18)
0.100(2,54)
0.021 (0,53) 0.015(0,38)
-0-| 0.010(0,25)
NOTES: linear dimensions inches (millimeters).
This drawing subject change without notice.
Falls within JEDEC MS-001
0.200 (5,08)
_Seating Plane
0.310(7,87) 0.290 (7,37)
0.010(0,25)
4040082/B 03/9
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TLC555, TLC555Y
TIMERS
SLFS043B SEPTEMBER 1983 REVISED 1997
(R-PDSO-G**) SHOWN
MECHANICAL INFORMATION
PLASTIC SMALL-OUTLINE PACKAGE
0,65
0,30
0.10'
4,50 6,60 4,30 6,20
0,15
0,75 0,50
Jiuimiuuili
1,20 0,05
3,10 5,10 5,10 6,60 7,90 9,80
2,90 4,90 4,90 6,40 7,70 9,60
4040064/ 08/96
NOTES: linear dimensions millimeters.
This drawing subject change without notice.
Body dimensions include mold flash protrusion exceed 0,15.
Falls within JEDEC MO-153
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IMPORTANT NOTICE
Texas Instruments (Tl) reserves right make changes products discontinue semiconductor product service without notice, advises customers obtain latest version relevant information verify, before placing orders, that information being relied current.
warrants performance semiconductor products related software specifications applicable time sale accordance with Tl's standard warranty. Testing other quality control techniques utilized extent deems necessary support this warranty. Specific testing parameters each device necessarily performed, except those mandated government requirements.
Certain applications using semiconductor products involve potential risks death, personal Injury, severe property environmental damage ("Critical Applications").
SEMICONDUCTOR PRODUCTS DESIGNED, INTENDED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT APPLICATIONS, DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS.
Inclusion products such applications understood fully risk customer. products such applications requires written approval appropriate officer. Questions concerning potential risk applications should directed through local sales office.
order minimize risks associated with customer's applications, adequate design operating safeguards should provided customer minimize inherent procedural hazards.
assumes liability applications assistance, customer product design, software performance, infringement patents services described herein. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right covering relating combination, machine, process which such semiconductor products services might used.
Copyright 1996, Texas Instruments Incorporated
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TIMERS SLFS043B SEPTEMBER 1983 REVISED 1997 Very Power Consu

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