MC2671 programmable keyboard communications controller jPKCC) MOS/LSI

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MC2671 programmable keyboard communications controller jPKCC) MOS/LSI

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PROGRAMMABLE KEYBOARD COMMUNICATIONS CONTROLLER (PKCC)
MC2671 programmable keyboard communications controller jPKCC) MOS/LSI device which provides versatile keyboard encoder independent full-duplex asynchronous communications controller. intended microprocessor-based systems provides 8-bit data interface.
Applications MC2671 include: terminals, hard-copy terminals, word-processing systems, data-entry terminals, small business computers.
Keyboard Interface
Contact Capacitive Keyboard
Keys 8x16 Matrix
Encoded Unencoded Operation
Four Code Levels
Latched Option Separate Depress Release Codes
Programmable Scan Rate Debounce Time
Programmable Rollover Modes
Programmable Auto-Repeat Selected Keys
Tone Output Frequencies
Asynchronous Communication Interface
Internat Baud-Rate Generator Rates
Full-Duplex Operation
Detection Start Break
Programmable Break Generation
Programmable Character Parameters
Auto-Echo Maintenance Loopback Modes
Polled Interrupt Operation
Interrupt Priority Controller Vector Generator
Operates Directly from Crystal External Clocks
Compatible
Single Volt Power Supply
ORDERING INFORMATION
Package Type Frequency Temperature Order Number
Ceramic Suffix MC2671AL
Cerdip Suffix MC2671
Plastic Suffix MC2671AP
MC2671
HMOS
(HIGH-DENSITY N-CHANNEL, SILCON-GATE)
PROGRAMMABLE KEYBOARD COMMUNICATIONS CONTROLLER
SUFFIX
CERAMIC PACKAGE CASE
SUFFIX
CERDIP PACKAGE CASE
SUFFIX
PLASTIC PACKAGE CASE
ASSIGNMENT
KDRES
KCLK
XTAL2/BRCLK
XTAL1
REPEAT
SHIFT
CONTROL
TONE INTA
KRET
INTR
XINTR
This document contains information product Specifications information herein subject change without notice
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BLOCK DIAGRAM
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MAXIMUM RATINGS
Characteristics Symbol Rating Unit
Supply Voltage +7.0
Input Voltage -0.3 +7.0
Operating Temperature Range
Storage Temperature Tstg
THERMAL CHARACTERISTICS
This device contains circuitry protect inputs against damage high static voltages electric fields; however, advised that normal precautions taken avoid application voltage higher than maximum-rated voltages this high-impedance circuit. Reliability operation enhanced unused inputs tied appropriate logic voltage level (e.g., either Vcc'-
Characteristics Symbol Rating Unit
Thermal Resistance
Plastic
Cerdip
Ceramic
POWER CONSIDERATIONS
average chip-junction temperature, obtained from:
Tj=TA (PD*fljA)
Where:
Ambient Temperature,
0JAS Package Thermal Resistance, Junction-to-Ambient, PD=P|NT PP0RT
P|NT VCC- Watts Internal Power PpORT=-Port Power Dissipation, Watts Determined most applications PpORT"*pINT neglected. PpORT become significant device configured drive Darlington bases sink loads.
approximate relationship between PpoRT's neglected)
PD=K-HTj
Solving equations gives:
Where constant pertaining particular part. determined from equation measuring equilibrium) known Using this value values obtained solving equations iteratively value
ELECTRICAL CHARACTERISTICS
Parameter Symbol Unit
Input Voltage
Input High Voltage XTAL1, XTAL2 Other Inputs
Output Voltage (IQL
Output High Voltage (Except INTR) (l0H
Input Leakage Current XTAL2/BRCLK IV|n Vcc> Other Inputs -100
Data Hi-Z Leakage Current VCC)
Power Supply Current
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ELECTRICAL SPECIFICATIONS READ CYCLE (See Figure
Parameter
Address Setup Time
Setup Time
Read Cycle Pulse Width
Address Hold Time from
Hold Time from
Data Delay Time Read Cycle
Data Floating Time Read Cycle
Access Delay Time from Read Next Read Write
Symbol
FIGURE READ CYCLE TIMING DIAGRAM
ELECTRICAL SPECIFICATIONS WRITE CYCLE
+5%) (See Figure
Parameter
Address Setup Time Setup Time
Symbol
Write Cycle Pulse Width Address Hold Time from
Hold Time from
Data Setup Time
Data Hold time
Access Delay Time from Write Next Read Write
Access Delay Time from Reset Command Next Read Write
FIGURE WRITE CYCLE TIMING DIAGRAM
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ELECTRICAL SPECIFICATIONS INTERRUPT KNOWLEDGE (See Figure
Parameter Symbol Unit
INTA Pulse Width tpwi
Data Delay Time Interrupt Vector 'DDI
Data Floating Time after INTA
INTA INTA Access Delay Time
FIGURE INTERRUPT KNOWLEDGE TIMING
-'PWI-
VlH"
DO-D7_ (Interrupt Vector)
-'DDI
-<ADI-
*DFI
ELECTRICAL SPECIFICATIONS INTERRUPT RESET (See Figure
Parameter Symbol Unit
INTR Delay Time from:
Read RxHR (RxRDY)
Read (KRDY)
Reset Commands (KOVR, KERR, BREAK)
Load TxHR (TxEMT, TxRDY)
Mask Reset
FIGURE INTERRUPT RESET TIMING DIAGRAM
_VlH-
-tRI-
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ELECTRICAL SPECIFICATIONS KEYBOARD (See Figures
Parameter Symbol Unit
KCLK Frequency fKCLK
KRi, KCi, KRET Sample Delay Time: Fast Scan Slow Scan *KBD 12.0 55.0
Scan Time Matrix Position: Fast Scan Slow Scan tpos
KDRES Delay Time from KCLK 'KRD
KDRES Hold Time from KCLK lKRH
Delay Time from KCLK <HYSD
KRi, Delay Time from KCLK tRCD
FIGURE KEYBOARD SCAN TIMING DIAGRAM
-IPOS-J
KCLK
>KRD -KDRES
.-"'KCLK
IKRH
_,HYSD
'RCD
-tKBD-
KRET, Shift Control, Repeal Sample Time
NOTE: Scan timing shown fast scan (KMR1 slow scan IKMR1 signals except KLCK shown rates.
FIGURE KEYBOARD TIMING
-LTFLTUJlJWUJlJmr^
Scan Cycle-
n_M_i
KRDY (KSROl-
KERR (KSR1I-
INTR
KRET
-tkr=Vs
Read (K1)
N-Key Rollover Modes Only
Rollover Inhibit
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ELECTRICAL SPECIFICATIONS UART (See Figures
Parameter Symbol Unit
Setup Time IRxS
Hold Time 'RxH
Delay Time from Falling Edge *TxD
Skew Between Transition Falling Edge Output (C[_
XTAL1 Clock High (see Figures lBRH
XTAL1 Clock (see Figures <BRL
Input Frequency <BRG 4.915 5.075
Input Frequency Clock Rate Factor 16X, 32X, Clock Rate Factor <R/T
Clock High 1R/TH
Clock tR/TL
FIGURE CLOCK, TRANSMIT, RECEIVE TIMING DIAGRAMS
CLOCK
TRANSMIT
RECEIVE
(IX)
-tRXH-
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FIGURE TRANSMITTER TIMING DIAGRAM
(5-Bit Characters, Parity, Stop Bits)
rLnJuinjuimnjiruiJij^
-_ri
TxEN
Write TxRDY
icsRir
TxEMT (CSR2)
Data
Data
Data
Transmit Break CSR3
Write
Start First Stop Second Stop Mark
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FIGURE RECEIVER TIMING DIAGRAM
<5-Bit Characters, Parity, Stop Bits)
RxEN
Ready
RxRDY ICSRO)
ROVRUNJ (CSR5)
njiTLiiruumrLrL^^
Data Data Data Data
Received Break (CSR4)-CE Reset Command with ISR5 (Break Detect Change)
Start First Stop Second Stop
FIGURE CRYSTAL CONNECTIONS CLOCK
4.9152
MC2671 XTAL1
FIGURE CONNECTION EXTERNAL CLOCK SOURCE
4.9152
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SIGNAL DESCRIPTION
input output signals PKCC described following paragraphs.
Power supplied PKCC using these pins. uolt supply around connection.
DATA (D0-D7)
This 8-bit three-state bidirectional data makes data, command, status transfers. least significant most signficant bit.
ADDRESS (A0-A2I
These input lines used select internal PKCC registers commands.
READ STROBE
This input, when low, gates selected PKCC register onto data chip enable also low.
WRITE STROBE
This input, when low, gates contents data into selected PKCC register chip enable also low.
CHIP ENABLE (tE)
This input, when high, places data output drivers high-impedance condition. chip enable low, data transfers enabled conjunction with read write inputs.
INTERRUPT REQUEST (TNTRl
Using this active open-dra'hn output, several conditions programmed request interrupt CPU. This will inactive after power-on reset master reset command.
INTERRUPT ACKNOWLEDGE (INTA)
This input used indicate that interrupt request been accepted CPU. When INTA goes low, PKCC outputs 8-bit address vector D0-D7 corresponding highest priority interrupt currently active.
EXTERNAL INTERRUPT (XINTR)
This active external interrupt input PKCC interrupt priority receiver.
TRANSMITTER CLOCK (TxC]
function this input/output depends baud-rate control register (BRR7). external transmitter clock selected (BRR7 =0), this input transmitter clock. internal transmitter clock selected (BRR7 this output which multiple actual baud rate (IX, 16X) selected BRR5. data transmitted falling edge TxC. This input after power after master reset communications reset commands.
RECEIVER CLOCK (RxC)
function this input/output depends BRR6. external receiver clock selected (BRR6 this input receiver clock. internal receiver clock selected (BRR6 this output which multiple actual baud rate 16X) selected BRR4. received data sampled rising edge RxC. This input after power after master reset communications reset commands.
TRANSMITTER DATA (TxD)
This output transmitted serial data; least significant transmitted first. This high after power-on reset reset command that affects transmitter.
RECEIVER DATA (RxD)
This input serial data input receiver. least significant received first.
CONNECTIONS CRYSTAL (XTAL1, XTAL2/BRCLKI
crystal connections provide on-chip clock generator internal baud-rate generator keyboard interface logic. external clock provided, XTAL2 clock input. Figures
timing parameters such keyboard scan times, tone frequency, baud rate assume clock input specified input frequency. this frequency different, timing parameters will vary proportionately.
KEYBOARD SCAN (KR0-KR2)
This output decoded externally selects eight rows.
KEYBOARD COLUMN SCAN (KC0-KC3)
This output decoded externally selects columns.
RETURN (KRET)
This input, when active high, indicates that being scanned closed.
SHIFT (SHIFT)
This active input from shift key. combination SHIFT CONTROL inputs selects four possible codes from internal encoding ROM.
CONTROL (CONTROL)
This active input from CONTROL key. combination SHIFT CONTROL inputs selects four possible codes from internal encoding ROM.
REPEAT (REPEAT)
This active input from REPEAT which causes depression currently active repeated rate approximately times second.
KEYBOARD CLOCK (KCLK)
This high frequency (approximately kHz) output used scan capacttive keyboards.
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DETECT RESET (KDRES)
This output resets analog detector before scanning key- used capacitive keyboards.
HYSTERESIS OUTPUT (HYS)
This output sent analog detector capacitive keyboard applications. indicates currently scanned been recognized previous scan cycles.
SQUARE WAVE OUTPUT (TONE!
This output used tone generation.
FUNCTIONAL DESCRIPTION
programmable keyboard communications controller (PKCC) consists major sections. These transmitter, receiver, timing, operation control, keyboard encoder, priority encoded interrupt control unit. These sections communicate with each other internal data internal control bus. internal interfaces microprocessor data bidirectional data buffer.
OPERATION CONTROL
This functional block stores configuration operation commands from generates appropriate signals various internal sections control overall device operation. contains read write circuits permit communications with microprocessor data contains mode registers CMR, command decoder, status registers CSR. Details operating modes status information presented OPERATION. register addressing specified Table
TABLE REGISTER ADDRESSING
Function
Three-State Data
Reset Command
Read Interrupt Status Register (ISRh
Read/Write Communications Mode Register (CMR)
Write Transmit Holding Register (TxHRI
Read Receiver Holding Register (RxHR)
Write Baud-Rate Mode Register IBRRI
Read Communications Status Register (CSR)
Read/Write Interrupt Mask Register IIMR)
Read/Write Keyboard Mode Register (KMR)
Read Keyboard Holding Register (KHR)
Read Keyboard Status Register (KSR)
Miscellaneous Commands
Don't Care
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TIMING
PKCC contains baucl-iate generator (BRGI which programmable accept external transmit receive clocks divide external clock perform data communications. unit generate baud rates, which selected full-duplex operation. external clock baud-rate generator applied directly XTAL2 input (see Figure generated internally connecting crystal across XTAL1, XTAL2 inpu' pins. clock input also utilized keyboard section. Thus, clock must provided even external transmitter receiver clocks used.
RECEIVER
receiver accepts serial data pin, converts this serial input parallel format, checks break conditions, framing parity errors, loads "assembled" character receive holding register access CPU.
TRANSMITTER
transmitter accepts parallel data loaded into transmit holding register converts serial stream framed start bit, calculated parity specified), stop bit(s). composite serial stream data transmitted output pin.
KEYBOARD ENCODER
keyboard encoder provides encoded scanning signals matrix keyboard. depressions detected KRET input. debounced verified codes matrix addresses) loaded into holding register access CPU. Figures illustrate PKCC interface contact capacitive keyboards, respectively.
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MC2671
FIGURE CONTACT KEYBOARD INTERFACE
Contact Keyboard Matrix
FIGURE CAPACITIVE KEYBOARD INTERFACE
Analog
Keyboard Matrix
INTERRUPT CONTROL
interrupt controller unit contains software programmable interrupt mask register which selectively enables status conditions from keyboard encoder communication controller generate interrupts. interrupts priority encoded individually generate 8-bit vector which output data response interrupt acknowledge INTA input pin.
OPERATION
KEYBOARD ENCODER
keyboard continuously scanned KC0-KC3 KR0-KR2 which decoded externally handle possible keys (see Figures 13). KC0-KC3 select columns KR0-KR2 multiplex eight return lines into KRET pin. Debouncing accomplished remembering state KRET when being addressed verifying scan later. Once verified code loaded into keyboard
data register (KDRI. keyboard holding register empty, contents will transferred immediately; full (i.e., read previous codel, transfer will held until read. data transfer causes keyboard data IKRDYI keyboard status register.
capacitive keyboards, high frequency output KCLK used gate column scan keyboard (see Figure 13). detector reset (KDRES) output resets analog detector prior scanning each location. output from analog multiplexer sensed then latched analog detector. output controls sense level. zero will lower sense level causing hysteresis, will raise sense level with hysteresis.
REPEAT input enables keyboard logic recognize repeatedly, times second. Additionally, certain keys programmed repeat automatically depressed more than one-half second.
square wave output TONE when issues ring tone command PKCC.
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KEYBOARD MODE REGISTER
Operating modes selected programming keyboard mode register (KMR), whose format illustrated Figure
KMR7 used testing device. normal operation, this should always written zero.
Bits KMR6-KMR5 select rollover modes keyboard processing:
N-Key Rollover. this mode, code corresponding each depression loaded into soon that debounced, independent release other keys. more closures occurring within scan cycle considered simultaneous which will keyboard error keyboard status register (KSR1). soon keyboard holding register empty code transferred KRDY status (KSRO).
N-Key Rollover with Latched Keys. This mode same regular N-key rollover, except that keys which assigned keyboard
matrix (KR2-KRO 000) produce code both when depressed when released. codes independent states inputs SHIFT CONTROL. more latched keys depressed when keyboard enabled (after keyboard reset), corresponding codes will sent keys scanned debounced. Note that simultaneous latched keys will KERR (KSR1) that latched keys will auto-repeat will affected REPEAT input.
Two-Key Rollover. first code loaded into immediately second code loaded only after first released. Simultaneous keys will KERR (KSR1). three more keys remain closed given time, KERR will also set. keys must then released before next KRET will processed.
Two-Key Inhibit. keys must released between keystrokes; otherwise, KERR (KSR11 will set.
FIGURE KEYBOARD MODE REGISTER FORMAT
Test Mode
Enable Disable
Rollover Modes-
N-Key with
Latched Keys
N-Key
Two-Key Inhibit
Encoded-
Keyboard
Non-Encoded
Keyboard
Tone Select
Auto Repeat
Disable
Enable
Matrix Scan
Size Time
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KMR4 specifies encoding mode. Each assigned four 8-bit codes, corresponding states SHIFT CONTROL inputs. encoded mode programmed, row/column address detected used load four codes into Table code assignments. non-encoded mode programmed, row/column address loaded directly into with following format:
L-KR2, KR1,
-KC3, KC2, KC1,
momentary keys latched keys release latched keys depress
TABLE STANDARD CODES (HEX)
(KR3-KR0)
Column (KC3 KCO)
Continued
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TABLE STANDARD CODES (HEX! [Continuedl
(KR3-KR0I
IKC3-KC0)
This contains latched keys when that mode selected (KMR6, KMR5 00).
CONTROL (Pin 13=0)
codes
SHIFT
Latched code release Latched code "for depress
ASCII equivalent any) Indicates Auto-Repeat keys
KMR3 enables auto-repeat mode. this mode, that programmed auto-repeat depressed longer than one-half second, code will loaded into approximately times second until that released. Only non-control codes will auto-repeat, i.e., CONTROL=1. Table specifies auto-repeat keys.
KMR2 KMR1 select matrix size debounce time (scan rate). keyboard outputs (KR2, KR1, KRO) always scan from column
outputs (KC3, KC2, KC1, KCO) scan from 128-key matrix from 80-key matrix.
KMRO selects between frequency output TONE response ring tone command.
KEYBOARD STATUS REGISTER
keyboard status register (KSR) provides operational feedback CPU. format illustrated Figure
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FIGURE KEYBOARD STATUS REGISTER FORMAT
Control Shift
Shift Lock -Repeat
KRDY
KERR
KOVR
Keyboard Enabled
KSR7, KSR6, KSR4 reflect state inputs corresponding pins. CONTROL SHIFT latched time accepted. verified codes loaded into KDR, corresponding states CONTROL SHIFT loaded into KSR. REPEAT updated every matrix example. status bits complements input levels.
KSR5 reflects state internal shift lock flag which controlled set/reset shift lock commands.
KSR3 indicates that keyboard controller enabled. controlled set/clear keyboard enable command.
Keyboard overrun (KSR2) when both full third validated. original content preserved content overwritten with code. This specified IMR1) generate interrupt cleared reset command with
Keyboard error (KR1) when operator depresses more keys than allowed selected rollover mode, when keys depressed simultaneously (within scan cycle). This specified IMR3) generate interrupt cleared reset command with
Keyboard data ready (KSRO) when code address transferred from KHR. This specified IMR2) generate interrupt. cleared when reads KHR.
COMMUNICATIONS CONTROLLER
communications controller section PKCC comprises full duplex asynchronous receiver/transmitter (UART) with baud-rate generator. Registers associated with these elements communications mode register (CMR), baud-rate control register (BRR), communications status register {CSR).
RECEIVER
receiver accepts serial data pin, converts serial input parallel format, checks start bit, stop bit, parity any), break condition, presents assembled character CPU. receiver looks high-to-low (mark-to-space) transition start input pin. transition detected, state sampled again after delay half time. then high, start invalid search valid start begins again. still low, valid start assumed
receiver continues sample input time intervals theoretical center bit, until proper number data bits parity any) have been assembled, stop been detected. least significant received first. data then transferred receive holding register (RxHR) RxRDY one. character length less than eight bits, most significant unused bits RxHR zero.
After stop detected, receiver will immediately look next start bit. However, non-zero character received without stop (i.e., framing error) remains half period after stop sampled, then space interpreted start bit.
parity error, framing error, overrun error any) strobed into received character boundary. break condition detected (RxD entire character including stop bit) only character consisting zeros will transferred RxHR received break (RxRDY when break received). input must return high condition time before search next start begins.
TRANSMITTER
transmitter accepts parallel data from converts serial stream output pin. automatically sends start followed data bits, optional parity bit, programmed number stop bits. least significant sent first. Following transmission stop bits, character available transmit holding register (TxHR), output remains high TxEMT will one. Transmission resumes TxEMT cleared when loads character into TxHR. transmitter forced send continuous condition transmit break command.
transmitter disabled, continues operating until character currently being transmitted completely sent out.
COMMUNICATION MODE REGISTER
Figure illustrates format CMR, which controls operational mode communications controller character parameters.
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FIGURE COMMUNICATIONS MODE REGISTER FORMAT
Operating Mode_
Normal
Auto Echo
Local Loopback Remote Loopback
Parity
Odd/Force
Even/Force
Character Length 11=7
Stop Bits Stop
Parity Mode
With Parity
Force Parity Parity AHowed
Bits CMR1 -CMRO select character length five, six, seven, eight bits. character length does include parity, start, stop bits.
CMR2 selects transmitted character framing stop bits. receiver always checks stop bit.
parity format selected bits CMR4 CMR3. parity force parity selected, parity added transmitted character receiver performs parity check incoming data. CMR5 selects even parity determines polarity parity force parity mode.
bits mode register affecting character assembly disassembly (CMR5-CMRO) changed dynamically affect characters currently being assembled RxSR transmitted TxSR. affect assembly received character, must updated within times receipt that character's start bit. affect transmitted character, must updated within times transmitting that character's start smaller character lengths).
UART operate four modes, illustrated Figure operating modes selected
bits CMR7 CMR6, which should only changed when both transmitter receiver operating independently. CMR7 CMR6 places UART automatic-echo mode, which automatically retransmits received data. following conditions true while automatic-echo mode:
Data assembled receiver automatically placed transmit holding register retransmitted output.
receive clock used transmitter.
receiver must enabled, transmitter need enabled.
Status TxRDV set. TxEMT operates normally.
received parity checked, regenerated transmission, i.e., transmitted parity received.
Only first character break condition echoed; output will high until next received character assembled.
CPU-to-receiver communication continues normally, CPU-to-transmitter link disabled.
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FIGURE OPERATING MODES MC2671 UART
Normal Operating Mode
Automatic Echo Mode
Local Loopback Mode
Remote Loopback Mode
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diagnostic modes also configured. local loopback mode (CMR7 CMR6 10):
transmitter output internally connected receiver input.
transmit clock used receiver.
output held high.
input ignored.
transmitter must enabled, receiver need enabled.
CPU-to-transmitter receiver communications continue normally.
second diagnostic mode remote loopback mode (CMR7 CMR6 11). this mode:
Data assembled receiver automatically placed transmit holding register retransmitted output.
receive clock used transmitter.
data sent local CPU, error status conditions (parity framing) required.
received parity checked, regenerated transmission, i.e., transmitted parity received.
receiver must enabled, transmitter need enabled.
BAUD-RATE CONTROL REGISTER
baud-rate control register (BRR) controls frequency generated baud-rate generator (BRG) clock source used receiver transmitter. format illustrated Figure
BRR3-BRR0 select sixteen frequencies genefated BRG. Table
BRR7 BRR6 select source transmit receive clocks. external clocks chosen (BRR7 BRR6 then clock rate factor determined BRR5 BRR4. external clock input(s) should desired baud rate multiplied clock rate factor.
FIGURE BAUD-RATE CONTROL REGISTER FORMAT
Clock Snur^p
External
Internal (BRG)
Clock Source
External
Internal (BRGI
Baud Rate Select Table
Clock Rate Factor External Clocks
internal clocks these bits specify output frequency Table
TABLE BAUD RATE GENERATOR CHARACTERISTICS
(BRCLK 4.9152 MHz)
Actual
Baud Frequency Percent
BRR3-0 Rate Clock Error Divisor
0000 6144
0001 1.7598 -0.01 2793
0010 134.5 2284
0011 2048
0100 1536
0101 1024
0110
1050 16.8329 0.20
1000 1200 19.2
1001 1800 28.7438 -0.20
1010 2000 31.9168 -0.26
2400 38.4
1100 4800 76.8
9600 153.6
1110 19200 307.2
1111 38400 614.4
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internal clock(s) specified, (BRR7 BRR6 clock supplied internal baud-rate generator selected baud rate. clock rate factor internally generated clocks always Pins become outputs transmit receive clocks, respectively. Table description selection these outputs.
COMMUNICATIONS STATUS REGISTER
Figure illustrates format communications status register ICSR), which provides UART status CPU.
Receiver ready (CSRO) indicates that received character assembled transferred RxHR ready read CPU. This specified IMRO) generate interrupt reset reading RxHR.
Transmitter ready (CSR1 indicates that TxHR empty ready loaded with character. This will cleared when TxHR loaded transferred character transmit shift register (TxSR). TxRDY reset when transmitter disabled. will
when transmitter enabled, provided that data loaded into TxHR during time transmitter disabled. This specified IMR7) generate interrupt.
Transmitter empty (CSR2I indicates that transmitter underrun, i.e., both TxHR TxSR empty. This only after transmission least character, cleared when TxHR loaded CPU. TxEMT reset when transmitter disabled. This specified IMR6I generate interrupt.
CSR3 will when PKCC receives command transmit break. This will cleared after break completed.
Received break (CSR4) indicates that zero character programmed length been received without stop bit. Breaks originating middle received character detected. This cleared when returns high state least time.
Receiver overrun (CSR5) indicates that previous character RxHR been read that character been loaded into RxHR. This cleared reset command with
TABLE BAUD-RATE CONTROL REGISTER
Clock Source Functions
BRR7- BRR3-BRR0
BRR4 Baud Rate Selection
baud rates
listed Table
1111
NOTES
Clock rate factor external clocks
External clock.
Internal clock (BRG).
clock outputs times actual baud rate. receive, output actual data sample
clock
BRR7 -BRR6 permitted automatic echo remote loopback modes unless BRR5-BRR4
FIGURE COMMUNICATIONS STATUS REGISTER FORMAT
Parity Error Framing Error Overrun Error
Received Break
RxRDY TxRDY TxEMT
Transmit Break
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Framing error (CSR6) indicates that stop been detected. stop check made middle first stop position. This cleared reset command with
Parity error (CSR7) indicates that character received with incorrect parity when 'with parity' enabled. This cleared reset command with
INTERRUPT CONTROLLER
MC2671 contains maskable interrupt status register (ISR) which enabled generate active interrupt request INTR output. eight interrupt conditions individually enabled writing into corresponding interrupt mask register (IMRI.
Each interrupt conditions assigned priority vector. When enabled set, MC2671 asserts INTR output. activates INTA input, MC2671 responds placing corresponding 8-bit data (D7-DO). multiple interrupts pending, vector corresponds condition with highest priority. interrupt will persist until pending interrupt conditions cleared.
also polled reading address 000. pending interrupt conditions which enabled will read independent priority.
assignments corresponding vectors priorities listed Table
COMMANDS
addition control exercised programming PKCC control registers, several functions performed executing command operations. There classes commands which initiated writing MC2671 address (reset command) address A2-A0-111 (miscellaneous commands). Individual commands specified pattern data DO).
RESET COMMANDS
reset command format illustrated Figure detailed command descriptions given Table
reset command with 111XXXX1 master reset MC2671. This command must given following power-on condition release internal power-on reset latch which deactivates MC2671 power
MISCELLANEOUS COMMANDS
miscellaneous command format illustrated Figure
TABLE INTERRUPT MASK REGISTER (IMRI INTERRUPT STATUS REGISTER (ISR)
Interrupt Vector D7-DO
IMR/ISR Condition Priority Binary Condition Reset
IMRO/ISRO RxRDY 11001111 Read RxHR
IMRI /ISR KOVR 11010111 Reset
IMR2/ISR2 KRDY 11011111 Read
IMR3/ISR3 KERR 11100111 Reset
IMR4/ISR4 XINTl 11101111 External
IMR5/ISR5 ABREAK2 11110111 Reset
IMR6/ISR6 TxEMT 11000111 Load TxHR
IMR7/ISR7 TxRDY 11000111 Load TxHR
NOTES:
XINT input from external interrupt source, active {pin 21).
ABREAK refers change received break condition.
FIGURE RESET COMMAND FORMAT
Effect-
Reset
Reset
Communications Reset
Break Detect Change Reset
Keyboard Reset KERR Reset
KOVR Reset
Communications Error Reset
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TABLE RESET COMMAND DESCRIPTION
Resets Comments
Keyboard Reset KMR7-KMR0 KSR5, KSR2-KSR0 IMR3-IMR1 keyboard controller reset, ignoring input KRET.
KSR1 Keyboard error status reset.
KOVR Reset KSR2 Keyboard overrun status reset.
Communications CSR7-CSR5 Resets receiver overrun, parity, framing error status bits.
Break Detect ISR5 Resets break detect change interrupt status register.
note Enables receiver operation.
Reset CSR7-CSR4, CSRO note Disables receiver.
note Enables transmitter operation
Reset CSR3-CSR1 note Disables transmitter. Sets output after transmitting character TxSR.
Communications Reset CMR. CSR, BRR, TxE, RxE, IMR7-IMR5, IMRO Resets communication controller. input ignored output one.
Master Reset CMR, CSR, BRR, TxE, RxE, KMR, KSR5, KSR3-KSR0, IMR7-IMR0. Releases internally latched power-on reset. Resets keyboard communication controllers. Inputs KRET ignored output one.
NOTE: Command does affect BRR.
FIGURE MISCELLANEOUS COMMANDS FORMAT
Clear Keyboard Enable-Set Keyboard Enable
Clear Shift Lock-
Shift Lock-
Transmit Character Break Transmit Timed Break
-Ring Tone Short
_Ring Tone Long
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MC2671
transmit break commands force break (steady output) immediately after character TxSR any) transmitted. timed break lasts approximately milliseconds, character break lasts character time including parity stop time. either case, TxRDY (CSR1) will beginning break which extended indefinitely milliseconds character time increments) reasserting command response TxRDY. Note that these commands reset TxRDY. When transmit break command asserted, CSR3 will set. This will cleared after break completed.
keyboard enable command enables keyboard controller sets KSR3 keyboard status register. clear keyboard enable command resets KSR3 disables processing KRET input. keyboard controller reset this command, current state keyboard (key depressions latched states) preserved internally. When keyboard subsequently enabled, processing resumes, keys debounced, latched keys encoded there been change their state.
MASK PROGRAMMABLE OPTIONS
ring tone commands cause tone generator output square wave TONE output. tone durations specified commands.
Ring tone short milliseconds Ring tone long milliseconds tone frequency either kHz, specified KMRO.
set/clear shift tock commands control state internal shift lock flip flop. When shift lock keyboard controller encodes depressions SHIFT input asserted. state shift lock flip flop reflected KSR5.
Characteristics certain portions PKCC internally programmed means ready-only memory.
items which programmed are:
codes
Auto-repeat keys
Scan times, tone frequency, tone duration
Baud rates
Interrupt vectors
Consult your local Motorola representative costs, minimum quantities, data submission requirements customized versions PKCC.
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MC2671 programmable keyboard communications controller jPKCC) MOS/LSI

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