NJU641 MATRIX 64-OUT SEGMENT DRIVER NJU6417B serial input, 6

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NJU641 MATRIX 64-OUT SEGMENT DRIVER NJU6417B serial input, 6

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NJU641
MATRIX 64-OUT SEGMENT DRIVER
NJU6417B serial input, 64-out segment driver matrix LCDs, especial useful extension driver controller drivers like NJU6408B.
consists 64-bit (two 32-bit) shift register, 64-bit latch, high voltage drivers.
shift direction each 32-bit shift register independently each other, consequently efficient extension driver allocation according number characters easy wiring with panel performed.
64-driver have level voltage inputs drive LCD, adjustable driving voltage according panel supplied from external power source.
NJU6417BF
FEATURES
Segment Drivers
64-bit Shift Register
32-bit Shift Registers
Shift Direction each 32-bit
Shift Registers Selection Shift Direction Select Terminal Duty Ratio 1/16
Fast Data Transmission Shift Clock max.) External Power Supply Driving Voltage Driving Voltage 13.5V Operating Voltage
Package Outline C-MOS Technology
BLXK DIAGRAM
SEGt
SEGJI
SEG.
SHLi
IOAs IOBi SHLi
IOBi
0005332
This Material Copyrighted Respective
Qapan Radia Co.,IM.
10-267
NJU64
CONFIGURATION
ooooooooooooooooooooooou
<n<n tntfKnwwwcnin
nnnnnnnnnrnnnnnnnnnnnnnn
SEGe,
SEGsa
SEG6<
IOB2
SHL1
SHL2
NJIIB417BF
UUUUUUUUUUUUUUUUUUUUUUU
WUJWWWUULJJCJJUWWWWUUWWWUJ
seg36
SEGss
SEG34
seg33
IOA1
IOB1
IOA2
seg,
seg2
SEGs
seg.
TERMINAL DESCRIPTION
SYMBOL FUNCTION
SEG,~ SEGs segment driving terminal. Each terminal corresponds each shift register
Data input/output terminals 32th bits shift register. Display data input (output) syncronized with clock pulse. Input output selected SHLi terminal.
Data input/output terminals 33rd 64th bits shift register. Display data input (output) syncronized with clock pulse. Input output selected SHL2 terminal.
Shift register clock pulse input terminal. data shifted shift register falling edge clock pul$e. data setup time hpld time required between data input SCL. Clock pulse rising time falling time should less than 50ns respectively.
Latch pulse input terminal. data shift register latched Latch.bv this signal. Data writing, Data latch
Alternate signal input driving.
driving power source terminals.
Power supply terminal (connect controller's terminal) Power supply terminal (connect controller's terminai)
SHLi gfnft direction input/putpyt control terminaliPull-gp Open Shift direction from 32nd b|t. Shift direction from 32nd bit.
SHL2 Shift direction input/putpyt control terminal(Pull-up Open Shift direction from 33rd 64th bit. Shift direction from 64th 33rd bit.
connection.
0005333
This Mate
10-268
Respective Manufac
fapan Radio Co., lid.
NJU641
FUNCTIONAL DESCRIPTION Shift register control
64-bit shift register devided into 32-bit shift register. shift direction each 32-bit shift register independently each other shown below.
Control Terminal Input Shift Direction
SHLi Open lOAi IOA2
lOAi IOA2
SHL2 Open IOBi IOB2
IOBi IOB2
When terminals SHLi SHL2 open, data shift from SEGi SEGei.
(IN)
shift Reg.
shift Reg.
MOB, (OUT)
SHLi lOAj IOBi
When terminals SHLi SHL2 "L", data shift from SEG64 SEGi.
(IN)
SHL,
32bit
shift Reg.
a-tr
IOA, IOBi
SHL,
(OUT)
Reversed sift direction each other also available.
SEGi SEG32 SEGb4 SEG33 example shown below:
SHL, IOA2 IOB, SHLi
This Material Copyrighted Respective Man'
faon Radio Co.,Iid-
-10-269
driver output truth table.
Input Data Selection/Non-se1ect Driver Output (SEGi SEGe*)
Selection
Non-selection
ABSOLUTE MAXIMUM RATINGS
Ta=25"C
PARAMETER SYMBOL RATINGS UNIT
Supply Voltage
Supply Voltage Note Vdd-13.5 Vdd+0.3
Input Voltage Vdd+0.3
Operating Temperature Topr
Storage Temperature Tstg
Note relation must maintained.
ELECTRICAL CHARACTERISTICS
Characteristics Ta=-20
PARAMETER SYMBOL CONDITIONS UNIT
Input Voltage SHLi, SHL2 Terminals 0.8Vdd
0.2Vdd
Input Current Vih=Vdd Terminals
Vil=0V
V,h=Vdd SHLi, SHL2 Terminals
Vil=0V
Output Voltage lo=" 40uA IH:: Ift'. Terminals
400uA
Driver On-resistance ld=0.05mA SEGi ~SEG64 Terminals
LM,LP=130us.cycle, SCL=1.5MHz Every Inverted Data. Load. 0.85
WMrK?t) ssho LM,LP=130us.cycle, SCL=1.5MHz :very Inverted Data. Load.
Driving Voltage Vlcd
This Mater|
biblflfla 0005335
10-270 NowQopotiRodio Co.,IM.
Characteristics
PARAMETER SYMBOL CONDITIONS UNIT
Propagation Delay Time Tplh(hl)
Maximum Operating Frequency Duty
Pulse Width
Pulse Width
Time Tset
Time
Time
Data Hold Time Thold
Rise, Fall Time Tfs,
Rise. Fall Time Tfl.
IOA.j B,.,
A,,, B2.i
-jf- 0.8Vdd 0.8Vou j-ji O.SVdd
Tset Tiioi.d
0.8vdd\^~
0.8Vdu
TSET
TpLH(HL)
/\0.2Vw
;Tl;
).8Vdd ).2Vdd
0.8Vm>
[wl_
bSbTflfl3
This Material Copyrighted Respective Manu
NJU641
TIMING CHART
Bias, 1/16 Duty Ratio
Fraae
LATCH DATA
Signal
[]Line[]Line[]Line[] Line pLineflLineflLinefjLinenLinef]
ru~Ln_rLn_n
DATA A(_A
jij~Lin_ru_rLru~u~L_rLn
LATCH
I]_n
LATCH-1
DATA
_rLR_n_n.
SEGMENT SIGNAL OUTPUT TIMING
PARAMETER SYMBOL CONDITIONS UNIT
Output Delay Tine Tlpsd 100PF
Output Delay Tine Tlmsd 100PF
^5^003
10-272-New fapanRadio Co,lid.
MatericTL Copyri^nted Respective Manufacturer
NJU641
DRIVING WAVEFORM EXAMPLE Bias, 1/16 Duty Ratio
Couon
Coimon COM2-Segient SEGi (Non-selection
bSbSfifi3 0D0S33S
This Material Copyrighted Respective Manu
fapan Radio Co.Iid.
ufactuKS'
10-273
NJU641
APPLICATION CIRCUITS
20-character 2-line Display Example Combine with NJU6408B
40-character Display Example NJUB408B NJU6417B NJU6407B
This Mater
DDDS33T llfl
Respective Co.,XU.

NJU641 MATRIX 64-OUT SEGMENT DRIVER NJU6417B serial input, 6

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