4-LINE WITH EXTENSION FUNCTION MATRIX CONTROLLER DRIVER GENE
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4-LINE WITH EXTENSION FUNCTION
MATRIX CONTROLLER DRIVER
GENERAL DESCRIPTION
NJU6426 Matrix controller driver 8-character 24-character 4-line with icon display single coirbine with some extension driver.
contains voltage converter, bleeder resistance, osciIlator, microprocessor interface circuits, instruction decoder controller, character generator ROM/RAM, high voltage operation camion segment drivers extension driver interface circuits.
voltage converter bleeder resistance generates about twofold voltageOOV) bias voltage driving waveform internally from single power sipply (5V). Consequently, high-contrast display performed though simple power sipply circuits.
oscillator incorporates therefore external conponents oscillation required.
microprocessor interface circuits which operate 2MHz, connected directly 4/8bit microprocessor.
character generator consists 9,600 bits bytes RAM.
33-caimon character, icon 40-segment drivers operated 13.5V, icon cannon driver display icon single confcine with some extension driver.
FEATURES
8-character 4-line Matrix Controller Driver
Maximum icon Display (Using COMss)
Microprocessor Direct Interface
Display Data bits Maximum 24-character 4-1ine Display
Character Generator 9,600 bits Characters Dots
Character Generator bits Patterns( Dots
High Voltage Driver 33-ccmmon 40-segment
Maximum Display Character Number
Disp. Line Ext. Display Char. Disp. Line Ext. Display Char.
Lines NJU6407C NJU6407C NJU6417C Characters Characters Characters Characters bits Lines NJU6417C Characters Characters bits
NJU6416 6415 Characters bits
Useful Instruction Clear Display, Return Home, Display ON/OFF Cont, Cursor ON/OFF Cont,
Display Blink, Cursor Shift, Character Shift
Extension Function
Power Initialize Hardware Reset Finction
Voltage Converter Bleeder Resistance On-chip
Osci Nation Circuit On-chip
Power Consumption
Operating Voltage
Package Outline Chip
C-M0S Technology
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PACKAGE OUTLINE
NJU6426F
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CONFIGURATION
SSSS SSSSSSS3.2:
uuuiuuuuuuu oooo oooooo
oooo
cocovotoococ/ifcooo
BLOCK DIAGRAM
ose,
0SC2
R/W-:
Instruction Decoder
e-y-
RESET
Reset
Address Counter
Display Data RAM)
Busy Flag
Character Generator
RAH)
512b
tage Conv.
tttt
V50ut
Character Generator ROH)
9600b
Parallel serial Convertor
Tiding
Gen.
Shift Reg.
COM, COMs:
SEC, ~SEGai
ODDLDID
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TERMINAL DESCRIPTION
SYMBOL FUNCTION
Power Source
Power Source
30,31,32 V2,V3,V5 Driving Voltage Output Extension Driver Driving Voltage Adjust Terminals.
osci 0sc2 Oscillation Frequency Adjust Terminals. Normally Open. (Oscillation incorporated, Freq.=330kHz) external clock operation, clock should irput OSCi.
Register selection signal irputCPull-up resistance On-chip) Instruction Register (Writing) Busy Flag, Address Counter (Reading) Data Register (Writing/Reading)
Read/Write selection signal inpirt(Pul l-ip Resistance On-chip) Write Read
Read/Write activation signal input
45-48 3-state Data Bus(Upper) transfer data between NJU6426. also used Busy Flag reading.
41-44 3-state Data Bus(Lower) transfer data between NJU6426. These used 4-bit operation.
Latch Clock Output Serial Data
Shift Clock Output Serial Data
Alternating signal Driving Output Terminal
Serial Data Output Terminal serial character pattern data output correspond each common signals. No-active Active
68-61 9-16 60-53 17-24 9~c0mi6 C0Mi7~c0m24 com25~com32 Common Driving Signal used, please keep open
COM33 Icon Common Driving Signal
69-100 SEG33' SEG40 Segment Driving Signal
Capacitor Voltage Doubler Connecting Terminal Capacitor Voltage Doubler Connecting Terminal
Input Terminal Voltage Doubler (Normally Vdd)
v50ut Voltage Doubler Output Terminal
RESET Reset Terminal. When level input over 1.2ms this terminal, system will reset(fosc=330kHz)
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FUNCTIONAL DESCRIPTION
Description each blocks Register
NJU6426 incorporates 8-bit registers, Instruction Register Data Register(DR). Register(IR) stores instruction codes such "Clear Display" "Return Home", address data Display Data RAMCDD RAM) Character Generator RAM(CG RAM).
write instruction code address data Register(IR), cannot read from Register(IR).
RegisterCDR) temporary stored register, data stored RegisterCDR) written into read from RAM.
data RegisterCDR) written transferred automatically internal operation.
When address data written into Register(IR), addressed data transferred RegisterCDR). read data RegisterCDR), data transmitting process performed completely.
After reading data RegisterCDR) MPU, next address data transferred automatically RegisterCDR) provide next reading.
These registers selected selection signal shown below.
Table shows register operation controlled signals.
Table Register Operation
Selected Register Operation
Write
Read busy flagCDB?) address counter CDBo~DB6)
Write CRegisterCDR) RAM)
Read RegisterCDR))
Busy Flag CBF)
When internal circuits operation mode, busy flag CBF) "1", instruction reading inhibited. busy flag CBF) output when RS="0" R/W="1" shown Table next instruction should written after busy flagCBF) goes "0".
Address Counter (AC)
address counterCAC) addressing RAM.
When address setting instruction written into RegisterClR), address information transferred from Register(IR) CounterCAC). selection either also determined this instruction.
After writing reading) display data from) RAM, Counter (AC) increments decrements) automatically.
address data Counter(AC) output from when RS="0" R/W-V shown Table
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(1-4) Display Data RAM)
display data RAM) consists bits stores 96-character display data represented 8-bit code. Normally, only bits display data RAM) using specially bits using 24-character display.
unused display data memory area used general data memory area. address data address counter(AC) represented Hexadecimal.
order
AC[7E
Lower order bit-
Hexadecimal
Hexadecimal
Example) address
16-character 2-line Display N=0, E1=0, E0=0
relation between address display position shown below.
Line Line
NJU6426(C0Mi~C0Ms)
Display Position
Address (Hexadecimal)
NJU6426(C0Ml7~C0M24)
NJU6426(C0M25~C0M32)
Note lines display mode, line address defined (00)h (27)h (67)h. Please note that line address beginning address consecutive.
When display shift performed, address changes follows:
Left Shift Display
(00)-
Right Shift Display
-(OF) -(4F)
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-4-2) 24-character Display (N=O,El=0,E0=D.(Extension Driver NJU6407C)
relation between address display position shown below: NJU6426(C0M NJU6407C NJU6426(C0M9~C0M16) NJU6407C
Line Line
,r4B
Display Position
Address (Hexadecimal)
NJU6426(C0Mi NJU6407C NJU6426(COM25~COM32) NJU6407C When display shift performed, address changes follows: Left Shift Display
Right Shift Display
_i_j_i_
15:16:17
i_i_*
-4-3) 32-character 2-line Display (N=0,E1=1,E0=0).(Extension Driver NJU6407C) relation between address display position shown below: NJU6426(C0Mi ~COMs) NJU6407C NJU6426(C0M9~C0Ml6) NJU6407C
Line Line
16'17
NJU6426(C0Mi7~C0M24) NJU6407C NJU6426(C0M?S-C0MS2) NJU6407C When display shift performed, address changes follows: Left Shift Display
Display Position
Address (Hexadecimal)
59~j~
-i-1
Right Shift Display
\3E]
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ODDbOm
5-345
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-4-4) 40-character Display (N=0,E1=1.EO=1).(Extension Driver NJU6417) relation between address display position shown below: NJU6407C NJU6426(COM9~COM16) NJU6407C
Line Line
20'21
13:14
ic"f
'"27":
[671
Display Position
Address (Hexadecimal)
NJU6426(C0M17~C0M24) NJU6407C NJU6426(C0M25~C0M32) NJU6407C When display shift performed, address changes follows: Left Shift Display
(40)
14:15
Right Shift Display)
-4-5) 8-character 4-line Display (N=1,E0=0)
relation between address display position shown below: Display Position
COMj Line
COM9 -COMie Line
C0Mi?~C0M?4 Line
COM?5~COM32 Line
Address (Hexadecimal)
When display shift performed, address changes follows:
Left Shift Display
Right Shift Display
>(07) >(47) >(67)
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u6426
-4-6) 16-character 4-line Display (N=1,E0=0).(Extension Driver NJU6407C) relation between address display position shown below:
COMi Line
COM9 Line
C0M17~C0M24 Line
COM25-com Line
nju6426
NJU6407C
Display Position
Address (Hexadecimal)
When display shift performed, address changes follows! Left Shift Display
(40)
(60)
Right Shift Display
>(2f) k4f) >(6f)
-4-7) 20-character 4-line Display (N=1,EO=0). (Extension Driver NJU6417C)
relation between address display position shown below:
NJU6407C
nju6426
COMi -COMe Line
C0M9 -COMie Line
C0Mi7~C0Mz4 Line
COM25~COM32 Line
Display Position
Address (Hexadecimal)
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EURq
When display shift performed, address changes follows:
Left Shift Display
j_1_i-
Right Shift Display
T.Hi
;_i_i_<_i_i_j
_I_1_I_1_I_J
(1-4-8) 24-character 4-line Display (N=1,E0=D.(Extension Driver NJU6416) relation between address display position shown below:
COMi -COMs Line
COM9 Line
Line
C0M25~C0M32 Line
NJU6426
NJU6416
to:"
i37-:57
177"
When display shift performed, address changes follows: Left Shift Display
Right Shift Display
Display Position
Address
(Hexadecimal)
26:27
>(37) >(57) >(77)
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000b017
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(1-5) Character Generator ROM)
Character Generator ROM) generates dots character pattern represented 8-bit character codes. storage capacity kinds dots character pattern. correspondence between character code standard character pattern NJU6426 shown Table 2-2. User-defined character patterns (Custom Font) also avai Iable mask option.
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Table 2-1. Character Pattern version
Upper bits Hexadecimal
(01)
<02)
I*!"
'04) '.y.v.
(051
(06)
(071
108)
(01)
(02)
(03)
(04)
(05)
(06) :::::
(07)
(08)
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Table 2-2. Character Pattern version
Upper bits Hexadecimal
(01)
(02)
(03)
(04)
(05)
(06)
(07) SSS**
(08)
(01) SS'SS
(02) :::::
(03)
(04)
(05) :::::
::::: sssss
(07)
(08) MtlS
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pR<3
Character Generator
character generator store kind character pattern dots written user program display user's original character pattern icon data. store kind character dots mode kind character dots mode icon data.
display user's original character pattern stored RAM, address data (00)h -(07)h (08)h (0F)h should written shown Table 2-2. Table show correspondence among character pattern, address Data. Unused memory area also used general data memory area.
Table Correspondence address, character code
character pattern( dots
Notes
Character Code Data) Address Character Pattern Data)
Upper Lower Upper Lower l)it Upper Lower
0000*000
0*001
0*111
Character Pattern Example(l)
"-Cursor Position
Character Pattern Exanple(2)
"-Cursor Position
Don't Care
Character code correspond add. 5(3bits:8 patterns). address designate character pattern line position. line cursor position display performed logical with cursor. Therefore, case cursor display, line should there ine, always displayed cursor position regardless cursor existence.
Character pattern position correspond data bits shown above. bits5 appear display meaning display), memory elements existing, therefore used general purpose RAM.
character patterns selected when character code bits
Nand addressed character code bitsO Therefore, address (09)h,-, (07)H (0F)h select same chapter pattern shown Table 2-2.
data corresponds display display Off.
address (30)h (3F)h using both character pattern memory icon data memory.
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6426
Icon Display Function
NJU6426 display only bits character pattern also maximun icons. icon display writing each data address (30)^ (3F)h RAM.
icon display data affected except writing display ON/OFF instruction. relation between address icon display position fixed even display shift executed. relation shown below:
Notel) corresponds (3F)h RAM. terminal
icon splay
data
address 76543210 terminal
###00110 76-80
###11100 71-75
###00000
###00000 61-65
###00000 56-60
###00000 51-55
###00000 46-50
###00000 41-45
###00000 36-40
###00000 31-35
###00000 26-30
###00000 21-25
###00100 16-20
###00000 11-15
###00100 6-10
###00000
Icon Disp. Number Max. Chara Nimber Note
Chara.
Icons Chara. (07) (0F)h Character Memory.
Icons Chara. (06)h,(07)h,(0E)h (0F)H Character Memory.
Note2) When icon display function using, system should initialized software initialization because does initialize except software initialization.
texinxi Icon Diso Number
Line Digit Extent Driver Max. Icon Disp. Nuttier Line Digit Extent Driver Max. Icon Disp.Number
NJU6407C, NJU6407CR NJU6407C, NJU6407CR
NJU6407C, NJU6407CR NJU6417C
NJU6417C NJU6415, NJU6416
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CjrcJ
Timing Generator
timing generator generates timing signals RAM, RAM, other internal circuits operation.
read timing display internal operation timing access separately generated, that they interfere with each other.
Therefore, when data write example, there will undesirable influence, such flickering, areas other than display area.
This circuit also generates control signals extension driver NJU6407C, 6417C 6416.
Driver
driver consist 33-common driver 40-segment driver.
When line nunber selected program, required common drivers output common driving waveform other cannon drivers output non-selection waveform automatical
bits character pattern data shifted shift-register latched when bits shift performed conpletely. This latched data controls display driver output driving waveform.
(1-10) Cursor Blinking Control Circuit
This circuits controls cursor On/Off cursor position character blinks. cursor blinks appear digit residing address address counter (AC).
When address counter (08)h, cursor position shown follows:
(AC)
Display
Cursor position
Display
Display position address (Hexadecimal)
Display position
address (Hexadecimal)
Cursor position
(Note) cursor blinks also appear when address coulter (AC) selects RAM. displayed cursor blink meaningless.
storing address data, cursor blink displayed meaningless position.
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Power Initialization internal circuits Initial ization Software
NJU6426 automatically initialized internal power initialization circuits when power turned internal power initialization, following instructions executed. During Internal power initialization, busy flag (BF) this status kept after rises 4.5V.
Initialization flow shown below:
Entry Mode
Display On/Off Control
Clear Display
Function
DL=1 :8-bit long
interface data :2-Line Display E1=0, E0=1 24-character Display
display Cursor Cursor Blink
NOTE
condition power supply rise time described Electrical Characteristics satisfied, internal Power Initialization Circuits will operated initialization will performed.
this case initialization software required.
I/D=1: Increment Shift
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(2-2) Initial ization Hardware
NJU6426 incorporates RESET terminal initialize system. When level input over 1.2ms RESET terminal, reset sequence executed. this time, busy signal output during 10ms after RESET terminal goes "H".
Reset Circuit
Timing Chart
External Reset Signal
Counter Output
RS-F/F Output Internal Reset Signal
Busy
Over 1.2ms
I_T~L
10ms
Instructions
NJU6426 incorporates registers, Instruction Register (IR) Data Register (DR). These registers store control information temporarily allow interface between NJU6426 peripheral operating different cycles. operation NJU6426 determined this control signal from MPU. control information includes register selection signals (RS), read/write signals (B/HO data signals (DBo DB?). Table shows each instruction operating time.
Note execution time mentioned Table based fosc=330kHz.
osci llation frequency changed, execution time also changed. Note When reset function executed, 40-character 2-line selected.
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EJRCgj
Table Table Inst actions
u6426
INSTRUCTIONS CODE DESCRIPTION EXEC TIME
Maker Testing 0000000000 code using maker testing. 30us
Clear Display 0000000001 Display clear sets address 1.24ms
Return Home 000000001 Sets address returns display being shifted original position. contents remain unchanged 1.24ms
Entry Mode 0000000 11/DS Sets cursor move direction specifies shift display performed data read/write. I/D=1: Increment, l/D=0:Decrement S=1lAcconpanies display shift 30us
Display On/Off Control 0000001 Sets display On/Off(D), cursor On/Off(C) blink cursor position 30us
Cursor Display Shift Moves cursor shifts display without changing contents S/C=1 Display shift S/C=0 Cursor shift R/L=1 Shift right R/L=0 Shift left 45us
Function Sets interface data length(DL), number display lines(N) display character number. Character font fixed DL=1 bits DL=0 bits 4-line 2-line Please refer 30us
Address Sets address. After this instruction, data transferred to/from RAM. 30us
Address Sets address. After this instruction, data transferred to/from RAM. 30us
Read Busy Flag Address Reads busy flag contents. BF=1 Internal operating BF=0 accept instruction
Write Data Write Writes data into RAMs. 30us
Read Data from Read Data Reads data from RAMs. 45us
Explanation Abbreviation Display data Character generator address address, Corresponds cursor address Address counter used both RAMs
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Description each instructions Maker Testing
Code
code 4-bit length using device testing mode only maker
Therefore, please avoid input meaning Enable signal irput data
(Especially please attention output condition Enable signal when power
on.)
Clear Display
Code
Clear display instruction executed when code written into DBo. When this instruction executed, space code (20)h written into every address, address into address counter entry mode increment.
cursor blink displayed, they returned left (the left line display mode).
entry mode does change. Note: character pattern character code (20)h must blank code user-defined character pattern(Custom font).
Return Heurte
Code
Don't care
Return home instruction executed when code written into DBi. When this instruction executed, address into address counter. Display returned original position shifted, cursor blink returned left (the left line 2-line display mode) cursor blink display.
contents change.
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R<g3
ISIU
Entry Mode
Entry mode instruction which sets cursor moving directi display shift On/Off, executed when code written into codes (l/D) written into DBi(l/D) DBo(S), shown below.
(I/D) sets address increment decrement, sets entire display shift writing.
Function
Address increment: address increment when read/write, cursor blink move right.
Address decrement: address decrement when read/write, cursor blink move left.
Entire display shift.
shift direction determined l/D.: shift left l/D=1 shift right l/D=0. shift operated only character, that looks cursor stands still display moves. display does shift when reading from writing/reading into/from RAM.
display does shifting.
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Display On/Off Control
Code
Display On/Off control instruction which controls whole display On/Off, cursor cursor position character blink, executed when code written into codes CD). written into DB2(D), DBiCC) DB0(B). shown below.
Function
Display
Display Off. this mode, display data remains that retrieved immediately difeplay when change
Cursor cursor displayed dots line.
Cursor Off. Even display data write, does change.
Function
cursor position character blinking. Blinking rate 518.4ms fosc=330kHz 24-character 4-1ine 433.2ms fCP=300kHz others. cursor blink displayed simultaneously._
character does blink.
Note) blink time alters proportionately 1/fosc 1/fc. example, when fcP=300kHz 518.4 (330/300) 570.2ms. (For 24-Character 4-Line) 433.2 (330/300) 476.5ms. (For others)
Character Font dots Cursor display exanple
Alternating display Blink display exanple
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Cursor/Display Shift
Code Don't care
Cursor/Display shift instruction shifts cursor position display right left without writing reading display data. This function used correct search display. 2-line display, cursor moves line when passes 40th digit line. Notice that line displays will shift same time. When displayed data shifted repeatedly, each line moves only horizontally.
line display does shift into line position.
contents address counter(AC) does change operation display shift only.
This instruction executed when code written into codes (S/C) (R/L) written into DB3(S/C) DB2(R/L), shown below.
Shifts cursor position left ((AC) Shifts cursor cwsition the.right
decremented
cu'ii" -"v?"' iieiii v,\AC) incremented Shifts entire display left cursor follows
Function
Code Don't care
Function instruction which sets interface data length number display lines, executed when code written into codes (DL), (N), (Ei) (E0) written into DB4(DL), DB3(N), DBi(Ei) DBo(Eo), shown below (character font fixed dots).
(DL) sets interface data length sets nuntier display lines either 2-line 4-line (Ei), (Eo) select display character nunber.
NOTE
This function instruction must performed head program prior other existing instruct ions(except Busy flag/Address read). This function instruction executed afterwards unless interface data length change.
interface data length bits (DB7 DBo)
interface data length bits (DB? data must sent received twice this mode.
Display lines Display Digit Extension Driver
Character Character Character Character NJU64Q7C, NJU6407CR NJL6407C, NJU6407CR NJU6417C
4-line Character Character NJU6417C NJU6416, NJU6415
000b030
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Address
Code
order
Lower order
written into
address instruction executed when code address written into shown above.
address data mentioned binary code AAAAAA written into address counter (AC) together with addressing condition. After this instruction execution, data writing/reading performed into/from RAM.
Address
Code
"-Higher order
Lower order bit-
address instruction executed when code written into address written into shown above.
address data mentioned binary code AAAAAAA written into address counter (AC) together with addressing condition. After this instruction execution, data writing/reading performed into/from RAM.
case 2-1ine display(N=0), address data (00)h (27)h line (67)h line. 20-character 4-line display(N=1. E0=0), TAAAAAAAJ (00)H (13)h line, (33)h ine, (40)h line line. However, case 24-character 4-line(N=1, E0=1), TAAAAAAAJ line, line, line ine.
Note
Display Line Line Line Line
2-Line (40)
20-Char. 4-Line (00) (40) (60)
24-Char. 4-Line (17)h
Read Busy Flag Address
Code
order
Lower order bit-
This instruction reads internal status NJU6426. When this instruction executed, busy flag (BF) which indicate internal operation read from address read from (the address determined previous instruction).
(BF)-V indicates that internal operation progress. next instruction inhibited when (BF)='T. Check (BF) status "before next write operation.
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Write Data
Code
"-Higher order
Lower order code
written into
Write Data instruction executed when (RS) code written into (R/W).
execution this instruction, binary data DDDDDDDD written into RAM. selection determined previous instruction. After this instruction execution, address renient (+1) decrement (-1) performed automatically according entry mode set. display shift also executed according previous entry mode set.
Read Data from
"-Higher order
Lower order bit-
Read Data from instruction executed when code written into (RS) (R/W).
execution this instruction, binary data DDDDDDDD read from RAM. selection determined previous instruction.
Before executing this instruction, either address address must executed, otherwise first read data invalidated.
When this instruction serially executed, next address data normally read from second read.
address instruction required cursor shift instruction executed just beforehand (only reading).
cursor shift instruction same function address set, that after reading RAM, address increment decrement executed automatically according entry mode.
display shift does occur regardless entry mode.
Note". address counter (AC) automatically incremented decremented after write instruction either RAM. Even read instruction executed after this instruction, addressed data read correctly. correct data read out, either address instruction cursor shift instruction (only with RAM) must implemented just before this instruction from second time read instruction execution read instruction executed times consecutively.
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Initialization using internal reset circuits
16-character display 8-bit operation (Using internal reset circuits).
16-character display, Function set, Display On/Off Control Entry Instruction must executed before data input, shown below.
NJU6426 store characters, explained before, therefore advertising moving display available when combined with display shift operation. Since display shift operation changes only display position contents remain unchanged, display data which entered first output when return home operation performed.
Power
data DD/CG Instruction
Function
Disp.0n/0ff Cont
Entry Mode
Initialized. display appears.
8-bit operation, 16-character. display, dots Font.
Turns display cursor. Entire display space mode initialization.
Example address increment cursor right shift when data write RAM.
16-character 4-bit operation (Using internal reset circuits).
4-bit operation, function must performed user programming.
When power turned 8-bit operation selected automatically, therefore first input performed under 8-bit operation. this operation, full instruction input because terminals connection. Therefore, same instruction must rewritten DB*, shown below. Since operation conpleted accesses 4-bit operation mode, rewrite required instruction code full.
16-character 2-1ine 4-bit operation shown follows:
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U6426
Power
Function
Function
Disp.On/Oft Cont
Entry Mode
Initialized. display appears.
4-bit operation.
This step executed 8-bit mode
initialization.
4-bit operation 16-character 2-line display, dots Font. 4-bit operation starts from this step.
Turn display cursor.
Entire display space mode
initialization.
Example address increment cursor right shift when data write RAM.
Write data DD/CG Instruction
20-character 4-line 8-bit operation (Using internal reset circuits). From Iine displays shift same time.
Power
Function
Disp.On/Off Cont
Entry Mode
Initialized. display appears.
8-bit operation, 20-character 4-1ine display, dots Font.
Turns display cursor. Entire display space mode initialization.
Example address increment cursor right shift when data
Write data DD/CG Instruction
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Initialization instruction
power supply conditions correct operation internal reset circuits met, NJU6426 must initialized instruction.
Initialization Instruction 8-bit interface length.
Power
Initialized. display appears.
Wait more than 15ms after rises 4.5V
Function
Wait more than 4.1ms
Function
Wait more than lOOus
Function
Function
Display
Display Clear
DB,,
Entry Mode
Write data DD/CG Instruction
Function
(8-bit interface length
Function
(8-bit interface length
Function
(8-bit interface length
Busy Flag(BF) checked before this step, checked after this step. After this step, busy flag(BF) check longer waiting time than each ruct execut time required.
8-bit operation, 24-character 4-1ine display, dots Font.
Exanple address increment cursor right shift when data write RAM.
5-366-
Co.,XJdr
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u6426
Initialization Instruction 4-bit interface length
Power
Wait more than 15ms after rises 4.5V
Function
Wait more than 4.1ms
Function
Wait more than lOOus
Function
Function
Function
Display
Display Clear
Entry Mode
Write data DD/CG Instruction
Initialized. display appears.
Function
(8-bit interface length
Function
(8-bit interface length
Function
(8-bit interface length
Busy Flag (BF) checked before this step, checked after this step.
After this step, busy flag (BF) check longer waiting time than each instruction execution time requi red.
Function
4-bit interface length 8-bit interface length.
4-bit operation, 40-character 2-1ine display dots Font.
Example address increment cursor right shift when data write RAM.
laaan Radio
000b03b
5-367
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DISPLAY
Power Sipply Driving
NJU6426 incorporate voltage doubler generate driving high voltage bleeder resistance. voltage doubler generate about twofold voltage from input voltage 9.5V lout=2mA Vc!=5V bleeder resistance generate each driving voltage.
bleeder resistance bias suitable 1/36 duty ratio each resistance value
Driving Voltage Duty Ratio
Power supply Duty Ratio 1/36
Bias
50ut Vlcd
NJU6426
v50ut
"TTC"
Vlcd
Vlcd
Bias(1/36 Duty)
(Voltage Dottier unused example)
Bias(1/36 Duty)
(Voltage Doubler used exanple)
5-368-Abu Wfadio CaJM-
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(4-2) Relation between oscillation frequency frame frequency.
NJU6426 incorporate oscillation capacitor resistance oscillation, 330kHz oscillation available without external components. frame frequency exanple mentioned below based 330kHz oscillation. clock 3.0us
1/36 duty
^-100 clock I.,36
Frame_1 Frame
20-character 4-Iine Display 24-character 4-1ine Display
frame 3.0(us) 10.8(ms) frame 3.0(us) 13(ms) Frame frequency 1/10.8(ms) 92.6(Hz) Frame frequency 1/13.0(ms) 76.9(Hz)
gapan Radio JM.-5-369
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Interface with
NJU6426 interfaced with both 4/8-bit two-time 4-bit one-time 8-bit data transfer available.
(5-1 4-bit interface
When interface length 4-bit, data transfer performed lines connected (DBo used). data transfer with completed two-time 4-bit data transfer.
data transfer executed sequence upper 4-bit (the data 8-bit length) lower 4-bit (the data 8-bit length).
busy flag check must executed after two-time 4bit data transfer instruction execution). this case data busy flag address counter also output twice.
Interniti Status
r*tion
777^^1//^.;\/c,m
Instruction Writing
Busy Check
Busy Check
list Writing
XXcTX XDRX
IRJX
DB.,
Xa^X
Writing instruction into instruction Register(IR)
Readout Busy FIag(BF)
Adress counter(AC)
Readout data RegisterCDR)
(5-2) 8-bit interface
Internal Status
^iiifm^m^r^mm,
Writing Idstrvctioi into
Chock
Besy Flag Cheek
Busy Check
Writing
struct into
5-370-New freon Radio
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[jpg
ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL RATINGS UNIT
Supply Voltage
Input Voltage Vdd+0.3
Operating Temperature Tcpr
Storage Temperature Tstg
stroyed. Using within electrical characteristics normal operation. beyond electric characteristics function poor IiabiIity. Note voltage values specified Note relation Vcc^VciM^VsouT Vss=0V must maintained.
Turn same time turn first then turn turn sequence does meet above conditions, latch wiII occur. Note Decoupling capacitor(CD) should connected between stabiIized operation voltage doubler.
strongly recomended conditions will cause mal-
must required.
ELECTRICAL CHARACTERISTICS
Ta=-20
PARAMETER SYMBOL CONDITIONS unit n9te
Operating Voltage
Input Voltage
Output Voltage -loh=0.205mA
Iol=1.6mA
Driver On-resist.(COM) Rcom com. term.)
Driver On-resist.(SEG) Rseg seg.term.)
Input Leakage Current Vin=0
Pull-ip Resist Current Vdd=5V,RS,R/W,DB Terminals
Operating Current Vdd=5V. fosc=330kHz
Voltage Doubler Output tage V50UT Terminal lout-5mA -3.0 -4.0
1out=1mA -4.6 -4.8
Input Volt.
Conv. Effici 95.0 99.9
Built-in Bleeder resistance (For Driving Voltage) 1.00
1.00
2.00
1.00
1.00
Oscillation Frequency fose Vdd=5V,
Driving Voltage Vlcd v50ut Terminal, Vdd=5V Vdd- Vdd" 13.5
Note Input/Output structure except driver shown below:
Input Terminal Structure
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Input/Output Terminal Structure
PIOS
nmos
Terminal
RS.R/W Terminals
"nos
ENABLE
Terminals
-New fapcut Radio Co,JUd
5-371
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Note Apply Output Input/Output Terminal.
Note Except pull-up resistance current output driver current.
Note Except Input/output current including current flow bleeder resistance.
input level mediun, current consumption will increase penetration current. Therefore, input level must fixed "L".
Operating Current Measurement Circuit
v50ut
Note Rcom Rseg resistance values between power sieply terminals (Vdd, V5out) each cannon terminal (COMi COM33), supply voltage (Vdd, Ysout) each segment terminal(SEGi SEG40) respectively, measured when current flown every common segment terminals same time.
NotelO) Apply output voltage from each less than +0.15V against driving constant voltage (Vdd, V-t, load condition.
Voltage Doit) Measurement Circuit
Internal Bleeder Resistance
Voltage Doubler Internal Clock Frequency 5kHz
5-372-
-New ihfxut Radio Co^lkL
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timing characteristics (Vdd +75"C) Write operation Write from NJU6426
PARAMETER SYMBOL CONDITION UNIT
Enable Cycle Time tCYCE
Enable Pulse Width "High" level
Enable Rise Time, Fall Time tEr,
Time R/W, fig.1
Address Hold Time
Data Time
Data Hold Time
Timing Characteristics (Write operation)
Vili
Vili
~-DBt
PSeh
"vTht
VILI
Vili
Vili
Valid Data
Vili
tCYCE
Vili
fig.
Read deration Read from NJU6426
PARAMETER SYMBOL CONDITION UNIT
Enable Cycle Time tCYCE
Enable Pulse Width "High" level PwEH
Enable Rise Time, Fall Time ter,
Time R/W, fig.2
Address Hold Time
Data Delay Time
Data Hold Time
Newfapan Radio Co,IM.
DOGbGME
This Material Copyrighted Respective Manufacturer
5-373
ejrct3
Timing Characteristics (Read operation)
~DBt
vili
VilN
PWrh
VlLl-
tDDR
<jH)HR>
Valid Data
Voli
Voli
tCYCE
Vili
fig.
Segment Extension Signal Timing Characteristics
PARAMETER SYMBOL CONDITION UNIT
Clock Pulse Width "High" level tcWH
Clock Pulse Width "Low" level tcWL
Clock Time tcsu
Data Time fig.3
Data Hold Time
Delay Time -1000 1000
Clock Rise Time, Time
fig.
5-374-N&o Qapan. Radia Co^Hdr
b5b1&fiB QD0bG43
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load circuit
Segment signal load circuit
5.0V
RL=2.4ICQ
Test Point
Test Point
rr^i
130pF
777"
60pF
Input Condition when using Hardware Reset Circuit Input Timing
RESET
2Vdd-
PARAMETER SYMBOL CONDITION UNIT
Reset Input Level Width fosc=330kHz
Power Supply Condition when using internal initialization circuitCa +7ETC)
PARAMETER SYMBOL CONDITION UNIT
Power Sipply Rise Time
Power Sipply Time toFF
Since internal initialization circuits will operate normally unless above conditions met, such case initialize instruction. (Refer initialization instruction)
toFF specifies power time short period cyclical on/off.
fapan. Radio JutcL.-5-375
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u6426
DRIVING WAVEFORM
1/36 Duty Driving
5-376
CoJM
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APPLICATION CIRCUITS
16-character 2-line Display Example (1/6 Bias, 1/36 Duty)
-Alaj,i IfuuML Onrtin Jbi~
000b04b
5-377
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CjrcJ
40-character Display Example (1/6 Bias, 1/36 Duty)
Panel (40-Character 2-Line)
Icon Display
5-378-
Qapan Radio
fjj-
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ejrc3
8-characler Display Example (1/6 Bias, 1/36 Duty)
Panel (8-Character 4-Line)
Icon Display
bSb^flfla
5-379
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24-character Display Example (1/6 Bias, 1/36 Duty)
Panel (24-Character 4-Line)
Icon Display
5-380-
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DOObOin
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.oss.
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trade mark Inc.
interface example driving voltage supplied from external power sipply
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