54LS 74LS SWITCHING CHARACTERISTICS FUNCTION TABLE CONFIGURA

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54LS 74LS SWITCHING CHARACTERISTICS FUNCTION TABLE CONFIGURA

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SPEED/PACKAGE AVAILABILITY
54LS 74LS
SWITCHING CHARACTERISTICS
FUNCTION TABLE CONFIGURATION
(EACH GATE)
INPUTS OUTPUT
high level level
FROM LIMITS
PARAMETER* (INPUT) TEST CONDITIONS UNIT
lPLH *PHL 'PLH 'PHL Other input Other input high 15pF, 2kfi
A,F,W PACKAGE
POSITIVE LOGIC:
*tpLH propagation delay
SPEED/PACKAGE AVAILABILITY
54LS 74LS
DESCRIPTION
S54LS670 N74LS670 16-bit register files incorporate equivalent gates. register file organized words bits each separate on-chip decoding provided addressing four word locations either write-in retrieve data. This permits simultaneous writing into location reading from another word location.
Four data inputs available which used supply 4-bit word stored. Location word determined write-address inputs conjunction with write-enable signal. Data applied inputs should true form. That highlevel signal desired from output, high-level applied data input that particular location. latch inputs arranged that data will accepted only both internal address gate inputs high. When this condition exists, data input transferred latch output. When write-enable input, high, data inputs inhibited their levels cause change information stored internal latches. When read-enable input, high, data outputs inhibited into high-impedance state.
individual address lines permit direct acquisition data stored four latches. Four individual decoding gates used complete address reading word. When read address made conjunction with read-enable signal, word appeaars four outputs.
This addressing separate from data-read addressing individual sense recovery times, permits simultaneous reading writing, limited speed only write time nanoseconds typical). register file nondestructive readout that data lost when addressed.
Inputs except read enable write enable buffered lower drive requirements Series 54LS/74LS standard load, input-clamping diodes minimize switching transients simplify system design. High-speed, double-ended AND-OFt-INVERT gates employed read-address function have high-sink-current, three-state outputs. these outputs wire-AND connected Increasing capacity words. number these registers paralleled provide n-bit word length.
CONFIGURATION
B,F,W PACKAGE
DATA WRITE-SELECT
SELECT
03[7
EigmmEE
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54LS 74LS SWITCHING CHARACTERISTICS FUNCTION TABLE CONFIGURA

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