Jeff Dunnihoo David Rivenburg FDC37C957FR Ultra controller advanc

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Jeff Dunnihoo David Rivenburg FDC37C957FR Ultra controller advanc

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APPLICATION NOTE 6.10 FLASH EPROM Applications FDC37C95x Ultra Controllers
Jeff Dunnihoo David Rivenburg
FDC37C957FR Ultra controller advanced Plug-and-Play device that includes advanced 8051 microcontroller core with shared FLASH EPROM interface. This 8051 control over multiple chip sub-functions including PS/2 keyboard interface logic, keyboard scanner, power-management functions, Access.Bus interface block, Real Time Clock, Parallel Port, Serial Port, Pulse Width Modulators, Port, over General Purpose pins. FLASH sharing mechanism allows 8051 keyboard/power management code reside same FLASH block host CPU's BIOS code. host access shared FLASH 64KB blocks 8051 access 32KB blocks time. addition, 8051 bytes executable internal that loaded with 8051 interrupt vectors small power-management handlers that allow 8051 control modify flash without executing example, 8051 jump into internal execute FLASH power-down mode connecting FLASH 8051-controllable GPIO. power down, 8051 jumps into internal RAM, de-asserts FLASH CE#. When interrupt occurs, 8051 reassertes CE#, then jump back into FLASH. Traditionally, Host BIOS resided it's 128KB EPROM, while other microcontroller code resided elsewhere embedded board. PCs, especially laptops, expanded role "keyboard controllers" include power management, consumer desktop server reliability diagnostic control, total microcontroller space grown. This required multiple microcontrollers with different mask ROMs multiple versions each during product cycle. FLASH EPROMs simplified this problem with Host BIOS because manufacturing could easily update that firmware with improved features. FDC37C95x expands that model allowing motherboard firmware updated simultaneously under Host control 8051 control. typical architecture with shared FLASH, 8051 begin executing FLASH while asserting RESET CPU, deasserting POWER_GOOD chipset. Once 8051 finished housekeeping tasks, enter hibernation pass control over Host. Host then copy required code RAM, jump into return control FLASH back 8051. split-ROM architecture used, this handshaking required. Some applications require large amounts non-volatile storage, such diskless workstations DBCS character ROMs Japan. circuit shown below shows implement larger banks FLASH, well traditional split-ROM architectures.
Since 8051 access only 32KB pages code Host only select 64KB pages, built-in page select registers 8051 Host (KMEM HMEM respectively-See FDC37C95xFR Data Sheet "Shared FLASH Interface Section"). These allow 256Kx8 FLASH module controlled with [FA0.17]. More address lines added using 8051 controlled GPIOs single 512K module. multiple FLASH modules added controlled individually with GPIOs connected lines. GPIO lines power inputs, pullups/pulldowns should used insure that initial code fetches only come from device. split-ROM mode, ROMCS# pulled inactive such that Host cannot access directly. Host must 8051's 60/64 keyboard port hidden mailbox registers proxy 8051 read modify FLASH. separate buffered FLASH used Host only. Additionally, Mask-ROM used 8051. flexibility, 8051 programmed load patch overlay from Access.BUS serial EEPROM, from Host FLASH. This provides greatest security, allows simultaneous Host 8051 operation. SHARED ADVANTAGES: Cheaper, more efficient space Less physical board space 8051 read/write Host code, vice versa SPLIT-ROM ADVANTAGES: Maximum flexibility security Simplified code development Size Type mixing (1kROM+256KFLASH, etc)
Arkay Drive Hauppauge, 11788 (631) 435-6000 (631) 273-3123
Copyright SMSC 2004. rights reserved. Circuit diagrams other information relating SMSC products included means illustrating typical applications. Consequently, complete information sufficient construction purposes necessarily given. Although information been checked believed accurate, responsibility assumed inaccuracies. SMSC reserves right make changes specifications product descriptions time without notice. Contact your local SMSC sales office obtain latest specifications before placing your product order. provision this information does convey purchaser described semiconductor devices licenses under patent rights other intellectual property rights SMSC others. sales expressly conditional your agreement terms conditions most recently dated version SMSC's standard Terms Sale Agreement dated before date your order (the "Terms Sale Agreement"). product contain design defects errors known anomalies which cause product's functions deviate from published specifications. Anomaly sheets available upon request. SMSC products designed, intended, authorized warranted life support other application where product failure could cause contribute personal injury severe property damage. such uses without prior written approval Officer SMSC further testing and/or modification will fully risk customer. Copies this document other SMSC literature, well Terms Sale Agreement, obtained visiting SMSC's website http://www.smsc.com. SMSC registered trademark Standard Microsystems Corporation ("SMSC"). Product names company names trademarks their respective holders. SMSC DISCLAIMS EXCLUDES WARRANTIES, INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES MERCHANTABILITY, FITNESS PARTICULAR PURPOSE, TITLE, AGAINST INFRINGEMENT LIKE, WARRANTIES ARISING FROM COURSE DEALING USAGE TRADE. EVENT SHALL SMSC LIABLE DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, CONSEQUENTIAL DAMAGES; LOST DATA, PROFITS, SAVINGS REVENUES KIND; REGARDLESS FORM ACTION, WHETHER BASED CONTRACT; TORT; NEGLIGENCE SMSC OTHERS; STRICT LIABILITY; BREACH WARRANTY; OTHERWISE; WHETHER REMEDY BUYER HELD HAVE FAILED ESSENTIAL PURPOSE, WHETHER SMSC BEEN ADVISED POSSIBILITY SUCH DAMAGES.

Jeff Dunnihoo David Rivenburg FDC37C957FR Ultra controller advanc

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