Read/Write analog front 125kHz RFID Basestation Description EM409
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EM4095
Read/Write analog front 125kHz RFID Basestation
Description EM4095 (previously named P4095) chip CMOS integrated transceiver circuit intended RFID basestation perform following functions: antenna driving with carrier frequency modulation field writable transponder demodulation antenna signal modulation induced transponder communicate with microprocessor simple interface. Features Integrated system achieve self adaptive carrier frequency antenna resonant frequency external quartz required carrier frequency range Direct antenna driving using bridge drivers Data transmission (100% Amplitude Modulation) using bridge driver Typical Operating Configuration Read Only Mode
RDY/CLK
Data transmission Amplitude Modulation with externally adjustable modulation index using single ended driver Multiple transponder protocol compatibility (Ex: EM4102, EM4200, EM4450 EM4205/EM4305) Sleep mode compatible power supply range +85°C temperature range Small outline plastic package SO16
Applications immobiliser Hand held reader cost reader
Assignment
SO16
CDC2 CFCAP DEMOD_OUT CAGND CDEC
RDY/CLK ANT1 FCAP DEMOD_OUT AGND CDEC_IN CDEC_OUT
CRES CDV1 CDV2
EM4095 P4095
DVDD DVSS ANT2 DEMOD_IN
Fig.
Fig.
Read/Write Mode
RDY/CLK
CDC2 CFCAP DEMOD_OUT CAGND CDEC
CRES CDV1 CDV2
EM4095 P4095
Fig.
Copyright 2009, Microelectronic-Marin 09/09 rev.G
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EM4095
System principle
Transponder
Transceiver configuration
RDY/CLK
Coil1 Read Only Chip Coil2
CDV1 CDV2
CDC2 CFCAP DEMOD_OUT CAGND CDEC
CRES
EM4095
UPLINK
Signal Transponder coil
DOWNLINK
Signal Transceiver coil
Signal Transceiver coil Signal Transponder coil
Carrier
Data
Carrier
Data
Fig.
Copyright 2009, Microelectronic-Marin 09/09 rev.G
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EM4095
Absolute Maximum Ratings Parameter Storage temperature Maximum voltage Minimum voltage Max. voltage other pads Min. voltage other pads Max. junction temperature Electrostatic discharge max. MIL-STD-883C method 3015 against Electrostatic discharge max. MIL-STD-883C method 3015 (only pins ANT1 ANT2) against Maximum Input/Output current pads except VDD, VSS, DVDD, DVSS, ANT1, ANT2, RDY/CLK Maximum peak current ANT1 ANT2 pads duty cycle Symbol Conditions TSTO +150°C VDDmax VSS+6V VDDmin -0.3V VMAX +0.3V VMIN -0.3V TJMAX +125°C VESD VESD_ANT 4000V Handling Procedures This device built-in protection against high static voltages electric fields; however, anti-static precautions must taken other CMOS component. Unless otherwise specified, proper operation only occur when terminal voltages kept within voltage range. Unused inputs must always tied defined logic voltage level. Operating Conditions Parameter Operating junction temperature Supply voltage Antenna circuit resonant frequency peak current ANT1 ANT2 pads CFCAP CDEC CDC2 CAGND Package thermal resistor SO16 Symb FRES IANT 6.80 +110 Units °C/W
8000V
IIMAX IOMAX IANTmax
10mA
300mA
Stresses above these listed maximum ratings cause permanent damages device. Exposure beyond specified operating conditions affect device reliability cause malfunction.
±10% tolerance capacitors should used According 1S2P JEDEC test board antenna driver current internal junction temperature higher than ambient temperature. Please calculate ambient temperature range from max. antenna current package Thermal Resistor. user's responsibility guarantee that remains below 110°C. Supply voltage (VDD DVDD pads) must blocked 100nF capacitor VSS) close possible chip
Copyright 2009, Microelectronic-Marin 09/09 rev.G
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EM4095
Electrical Switching Characteristics: Parameters specified below valid only case device used according Operating Conditions defined previous page. VSS=DVSS=0V, =DVDD 110°C, unless otherwise specified Parameter Symbol Test Conditions Units Supply current sleep mode IDDsleep Supply current excluding drivers IDDon current AGND level VAGND Note 2.35 2.65 Logic signals SHD, MOD, DEMOD_OUT Input logic high Input logic Output logic high Output logic pull down resistor pull resistor Antenna capture frequency range Antenna locking frequency range Drivers drivers output resistance RDY/CLK driver output resistance demodulation DEMOD_IN common mode range DEMOD_IN input sensitivity Vsense Note 0.85 mVpp Note AGND EM4095 internal reference point. external connection except specified capacitor lead device malfunction. Note Modulating signal 2Khz square wave carrier, total signal inside
Vsense
0.8VDD 0.2VDD ISOURCE=1mA ISINK=1mA 0.2VDD 0.8VDD 0.9VDD 0.1VDD
FANT_C FANT_L
IANT=100mA IRDY/CLK=10mA
Copyright 2009, Microelectronic-Marin 09/09 rev.G
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EM4095
Timing Characteristics: Parameters specified below valid only case device used according Operating Conditions defined previous page. VSS=DVSS=0V, VDD=DVDD Parameter Symbol Test Conditions Units Set-up time after sleep period Tset Time from full power modulation Tmdon antenna circuit specifications: state Q=15,FRES=125Khz modulation index: 100% demodulation: Delay time from Modulating signal 2Khz square input output wave 10mVpp Recovery time reception after Trec Note antenna modulation Note period time period transmitted outputs 8µs). Trec after antenna modulation receiver chain ready demodulate. condition course that amplitude antenna already reached steady state that time (this depends antenna). also Application Notes. Block Diagram
AGND
blocks blocks blocks BIAS AGND BIAS AGND blocks SHORT DETECTION READY
RDY/CLK
FCAP
LOOP FILTER HOLD
LOCK SEQUENCER ANTENNA DRIVERS
DVDD ANT1 ANT2 DVSS
SYNCHRO
DMOD_IN
SAMPLER
FILTER
COMPARATOR
DMOD_OUT
CDEC_OUT
CDEC_IN
Fig.
Copyright 2009, Microelectronic-Marin 09/09 rev.G
www.emmicroelectronic.com
EM4095
Functional Description General EM4095 intended used with attached antenna circuit microcontroller. external components needed achieve filtering, current sensing power supply decoupling. stabilised power supply provided. Please refer EM4095 Application Notes advice. Device operation controlled logic inputs MOD. When high EM4095 sleep mode, current consumption minimised. power input high enable correct initialisation. When circuit enabled emit field, starts demodulate amplitude modulation (AM) signal seen antenna. This digital signal coming from demodulation block provided through DEMOD_OUT microcontroller decoding processing. High level forces tri-state main antenna drivers synchronously with carrier. While high demodulation chain kept state before went high. This ensures fast recovery after released. switching demodulation delayed clocks after falling edge MOD. this demodulation operating points perturbed startup antenna resonant circuit. Analog Blocks circuit performs functions RFID basestation, namely: transmission reception. Transmission involves antenna driving modulation field. antenna drivers deliver current into external antenna generate magnetic field. Reception involves demodulation antenna signal modulation induced transponder. This achieved sensing absorption modulation applied (transponder). Transmission Referring block diagram, transmission achieved Phase Locked Loop (PLL) antenna drivers. Drivers antenna drivers supply reader basestation antenna with appropriate energy. They deliver current resonant frequency which typically kHz. Current delivered drivers depends external resonant circuit. strongly recommended that design antenna circuit done that maximum peak current never exceeded (see Typical Operating Configuration antenna current calculation). Another limiting factor antenna current Thermal Convection package. Maximum peak current should designed that internal junction temperature does exceed maximum junction temperature maximum application ambient temperature. 100% modulation (field stop) done switching drivers. drivers protected against antenna short circuit power supplies. When short circuit been detected RDY/CLK pulled while main driver forced tri-state. circuit restarted activating pin. Phase locked loop composed loop filter, Voltage Controlled Oscillator (VCO), phase comparator blocks. using external capacitive divider, DEMOD_IN gets information about actual high voltage signal antenna. Phase this signal compared with signal driving antenna drivers. Therefore able lock carrier frequency resonant frequency antenna. Depending antenna type resonant frequency system anywhere range from kHz. Wherever resonant frequency this range will maintained Phase Lock Loop. Reception demodulation input signal reception block voltage sensed antenna. DEMOD_IN also used input Reception chain. signal level DEMOD_IN input must lower than VDD-0.5V higher than VSS+0.5V. input level adjusted external capacitive divider. Additional capacitance divider must compensated accordingly smaller resonant capacitor. demodulation scheme based Synchronous Demodulation" technique. reception chain composed sample hold, offset cancellation, bandpass filter comparator. voltage signal DEMOD_IN AGND internal resistor. signal sampled, sampling synchronised clock from VCO. component removed from this signal CDEC capacitor. Further filtering remove remaining carrier signal, high frequency noise made second order highpass filter CDC2. amplified filtered receive signal asynchronous comparator. Comparator output buffered output DEMOD_OUT.
Copyright 2009, Microelectronic-Marin 09/09 rev.G
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EM4095
Signal RDY/CLK This signal provides external microprocessor with clock signal which synchronous with signal ANT1 with information about EM4095 internal state. Clock signal synchronous with ANT1 indicates that lock that Reception chain operation point set. When high RDY/CLK forced low. After high transition starts-up, reception chain switched After time TSET locked reception chain operation point been established. this moment same signal which being transmitted ANT1 also RDY/CLK indicating microprocessor that start observing signal DEMOD_OUT giving same time reference clock signal. Clock RDY/CLK continuous, also present during time drivers high level pin. During time TSET from high transition RDY/CLK pulled down pull down resistor. reason this additional functionality RDY/CLK case modulation with index which lower then 100%. that case used auxiliary driver which maintains lower amplitude coil during modulation. (see also Typical Operating Configuration) Remark: Please refer AN4095 external components calculation limits. Typical Operating Configuration Read Only Mode
RDY/CLK
Read/Write mode (High factor antenna)
RDY/CLK
RSER CRES CDV1 CDV2
CDC2 CFCAP DEMOD_OUT CAGND CDEC
P4095 EM4095
Fig.
Read/Write mode modulation)
RDY/CLK
CDC2 CFCAP DEMOD_OUT CAGND CDEC
CRES CDV1 CDV2
EM4095 P4095
Fig.
CDC2 CFCAP DEMOD_OUT CAGND CDEC
Figure presents EM4095 used Read Only mode. used. recommended connect VSS.
CRES CDV1 CDV2
P4095 EM4095
Figure presents typical configuration communication protocol reader transponder (eg. EM4150). recommended used with factor antennas 15). When antenna quality high using configuration figure voltage antenna arrive range hundred volts antenna peak current exceed maximum value. such case capacitive divider ratio high thus limiting sensitivity. such case better reduce antenna circuit quality adding serial resistor. this antenna current lower thus power dissipation reduced with practically same performance (Fig. case modulation communication protocol reader transponder (eg. EM4069) needed single ended configuration used (figure When pulled high driver ANT1 three state, driver RDY/CLK continues driving thus maintaining lower antenna current. Modulation index adjusted resitor RAM. mentioned above RDY/CLK signal becomes active only after demodulation chain operating point set. Before pulled down high impedance pull down resistor (100 order load ANT1 output. case modulation configuration total antenna current change moment RDY/CLK becomes
Fig.
Read/Write mode (Low factor antenna)
RDY/CLK
CDC2 CFCAP DEMOD_OUT CAGND CDEC
CRES CDV1 CDV2
P4095 EM4095
Fig.
Copyright 2009, Microelectronic-Marin 09/09 rev.G
www.emmicroelectronic.com
EM4095
active, external microprocessor wait another TSET before start observing DEMOD_OUT. Read Only mode with external peak detector
RDY/CLK
CDC2 CFCAP DEMOD_OUT CAGND CDEC
CRES CDV1 CDV2
EM4095 P4095
mentioned above high antennas voltage antenna high read sensitivity limited demodulator sensitivity capacitive divider. Read sensitivity (and thus reading range) increased using external envelope detector circuit. Input taken antenna high voltage side output directly CDEC_IN pin. However, capacitor divider still needed locking. Such configuration shown figure envelope detector formed three components: configuration presented figure also used read write applications drawback case fast recovery reading needed after communication reader transponder finished. reason fact that voltage after diode lost during modulation takes very long time before established again.
Fig.
Read/Write mode with external peak detector
RDY/CLK
CDC2 CFCAP DEMOD_OUT CAGND CDEC
Figure presents solution that problem. high voltage NMOS transistor blocks discharge path during modulation, operating point preserved. signal controlling NMOS gate synchronously with signal MOD, high only after amplitude antenna recovered after modulation. Layout Refer "EM4095 Application Note" (App. Note 404)
CRES CDV1 CDV2
P4095 EM4095
Fig.
Copyright 2009, Microelectronic-Marin 09/09 rev.G
www.emmicroelectronic.com
EM4095
Description SOIC package GND: IPD: Name Description Negative power supply (substrate) RDY/CLK Ready flag clock output, driver modulation ANT1 Antenna driver Positive power supply antenna drivers DVDD Negative power supply antenna drivers DVSS ANT2 Antenna driver Positive power supply DEMOD_IN Antenna sensing voltage CDEC_OUT blocking capacitor connection CDEC_IN blocking capacitor connection Analog ground AGND High level voltage modulates antenna DEMOD_OUT Digital signal representing seen antenna High level voltage forces circuit into sleep mode FCAP Loop filter capacitor decoupling capacitor reference ground PWR: power supply input with internal pull down IPU: input with internal pull Type analog signal output
ANA:
Package Ordering Information Dimensions SOIC Package (table millimeters) Common Dimensions (mm) 1.55 1.63 1.73 0.127 0.15 0.25 0.35 0.41 0.49 0.19 0.20 0.25 9.80 9.93 9.98 3.81 3.94 3.99 5.84 5.99 6.20 0.41 0.64 0.89
Symbol
Fig.
Ordering Information Please make sure give complete part number when ordering. EM4095 available following package:
Part Number EM4095HMSO16A Package SOIC package Delivery Form stick
Product Support Check Site under Products/RF Identification section. Questions sent cid@emmicroelectronic.com
Copyright 2009, Microelectronic-Marin 09/09 rev.G
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EM4095
Appendix
Equations Antenna resonant frequency Peak peak voltage antenna defined following equation:
ANTpp
Where resonant capacitor composed CRES, CDV1 CDV2:
CRES
ensure correct operation demodulation chain, peak peak voltage DEMOD_IN (VDMOD_INpp) inside common mode range. Once peak peak voltage antenna known capacitor divider division factor calculated:
DMOD INpp ANTpp
Usually antenna coil specified inductance (LA) factor (QA). Serial resistance antenna defined following equation:
Power dissipation composed power dissipated drivers internal power consumption:
DDon (VDD
equations which follow valid bridge configuration defined Figures figures RSER considered current amplitude resonant frequency defined follows:
Temperature increase power dissipation
Where Package thermal resistor.
RSER
antenna current (important power dissipation calculation):
Microelectronic-Marin (EM) makes warranty products, other than those expressly contained Company's standard warranty which detailed EM's General Terms Sale located Company's site. assumes responsibility errors which appear this document, reserves right change devices specifications detailed herein time without notice, does make commitment update information contained herein. licenses patents other intellectual property granted connection with sale products, expressly implications. EM's products authorized components life support devices systems.
Copyright 2009, Microelectronic-Marin 09/09 rev.G
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