440GX Power 440GX Embedded Processor PowerPC® processor core
|
|
|
Top Searches for this datasheet
Part Number 440GX Revision 1.20 June 2009
440GX
Power 440GX Embedded Processor
PowerPC® processor core operating 667MHz with 32KB D-caches (with parity checking) On-chip 256KB SRAM configurable Code store Ethernet Packet store memory Selectable processor:bus clock ratios (Refer Clocking chapter PPC440GX Embedded Processor User's Manual details) Double Data Rate (DDR) Synchronous DRAM (SDRAM) interface operating 166MHz External Peripheral bits) eight devices with external mastering support external peripherals, internal UART memory PCI-X V1.0a interface bits, 133MHz) with support conventional V2.3 Ethernet 10/100/1000Mbps half- fullduplex interfaces. Operational modes supported SMII, GMII, RGMII, RTBI. TCP/IP Acceleration Hardware (TAH) provided 10/100/1000 Mbps ports that performs checksum processing, segmentation, includes support jumbo frames Programmable Interrupt Controller supports interrupts from variety sources. Messaging unit message transfer between PCI-X Programmable General Purpose Timers (GPT) serial ports (16750 compatible UART) interfaces General Purpose (GPIO) interface available JTAG interface board level testing Processor boot from memory Available ceramic (RoHs non-RoHS compliant versions) plastic packages (RoHS non-RoHS compliant versions).
Description
Designed specifically address high-end embedded applications, PowerPC 440GX (PPC440GX) provides high-performance, power solution that interfaces wide range peripherals incorporating on-chip power management features lower power dissipation. This chip contains high-performance RISC processor core, SDRAM controller, configurable 256KB SRAM used cache softwarecontrolled on-chip memory, PCI-X interface, Gigabit Ethernet interfaces, TCP/IP acceleration hardware, messaging unit, control external peripherals, with scatter-gather support, serial ports, interface, general purpose I/O. Technology: CMOS Cu-11, 0.13m Packages: 25mm, 552-ball Ceramic Ball Grid Array (CBGA) Plastic Ball Grid Array (PBGA) standard RoHS compliant versions Power (estimated): Less than: typical @533MHz typical @667MHz Supply voltages required: 3.3V, 2.5V, 1.5V
AMCC
440GX Power 440GX Embedded Processor
Revision 1.20 June 2009
Contents
Ordering Information Address Maps PowerPC Processor Core Internal Buses PCI-X Interface SDRAM Memory Controller On-Chip SRAM External Peripheral Controller (EBC) Ethernet Controller Interface Controller Serial Port Interface General Purpose Timers (GPT) General Purpose (GPIO) Controller Universal Interrupt Controller (UIC) Performance Monitor Messaging Unit (IMU) JTAG Signal Lists Signal Description Heat Sink Mounting Information (Ceramic Package Only) Test Conditions Spread Spectrum Clocking SDRAM Specifications SDRAM Write Operation SDRAM Read Operation Initialization Strapping Serial EEPROM
AMCC
Revision 1.20 June 2009
Figures
440GX Power 440GX Embedded Processor
PPC440GX Functional Block Diagram 25mm, 552-Ball Ceramic (CBGA) Package 25mm, 552-Ball Plastic (FC-PBGA) Package Heat Sink Attached With Spring Clip Heat Sink Attached With Adhesive Timing Waveform Input Setup Hold Waveform Output Delay Float Timing Waveform SDRAM Simulation Signal Termination Model SDRAM Write Cycle Timing SDRAM MemClkOut0 Read Clock Delay SDRAM Read Data Path SDRAM Read Cycle Timing-Example SDRAM Read Cycle Timing-Example SDRAM Read Cycle Timing-Example
Tables
Order Part Numbers System Memory Address Address Signals Listed Alphabetically Signals Listed Ball Assignment Summary Signal Functional Description Absolute Maximum Ratings Package Thermal Specifications Recommended Operating Conditions Input Capacitance Power Supply Loads Clocking Specifications Peripheral Interface Clock Timings Specifications-All Speeds Specifications-500MHz-667MHz SDRAM Output Driver Specifications Timing-DDR SDRAM Timing-DDR SDRAM TSK, TSA, Timing-DDR SDRAM Timing-DDR SDRAM TSIN TDIN Strapping Assignments
AMCC
440GX Power 440GX Embedded Processor
Revision 1.20 June 2009
Ordering Information
information availability following parts, contact your local AMCC sales office.
Order Part Numbers
Product Name PPC440GX PPC440GX PPC440GX PPC440GX PPC440GX PPC440GX PPC440GX PPC440GX Notes: Package code: leaded ceramic, plastic, reduced-lead ceramic (RoHS compliant), lead-free plastic (RoHS compliant). Case Temperature Range code: parts shipped tray. Revision code: 2.1, 3.1. 667MHz ceramic parts operated 533MHz less, operational temperature range extended +105°C Order Part Number (See Notes drawing) PPC440GX-3CF533C PPC440GX-3CF667C PPC440GX-3FF533C PPC440GX-3FF667C PPC440GX-3RF533C PPC440GX-3RF667C PPC440GX-3NF533C PPC440GX-3NF667C Processor Frequency 533MHz 667MHz 533MHz 667MHz 533MHz 667MHz 533MHz 667MHz Package 25mm, CBGA 25mm, CBGA 25mm, PBGA 25mm, PBGA 25mm, CBGA 25mm, CBGA 25mm, PBGA 25mm, PBGA Level Value 0x51B21894 0x51B21894 0x51B21894 0x51B21894 0x51B21894 0x51B21894 0x51B21894 0x51B21894 JTAG 0x52054049 0x52054049 0x52054049 0x52054049 0x52054049 0x52054049 0x52054049 0x52054049
667MHz plastic parts operated 533MHz less, operational temperature range extended +100°C.
Each part number contains revision code. This mask revision number included part number identification purposes only. (Processor Version Register) JTAG register software accessible (read-only) contain information that uniquely identifies part. Refer PPC440GX User's Manual details accessing these registers. Order Part Number
PPC440GX-3CF667C
Part Number Grade Reliability Package
Case Temperature Range Processor Speed Revision Level
AMCC
Revision 1.20 June 2009
PPC440GX Functional Block Diagram
Universal Interrupt Controller Clock Control Reset Timers internal external Power Mgmt
440GX Power 440GX Embedded Processor
DCRs
PPC440
Processor Core JTAG 32KB D-Cache Trace 32KB I-Cache
Timers
GPIO
UART
On-chip Peripheral (OPB) Controller (4-Channel)
Controller
SRAM 256KB
Bridge
Processor Local (PLB) External External Master Controller Controller 83MHz 32-bit addr 32-bit data
10/100 10/100/ 1000 Ethernet RGMII Bridge ZMII Bridge
Messaging
PCI-X Bridge
SDRAM Controller
133MHz 166MHz 32/64-bit data 13-bit addr 32/64-bit data
GMII RGMII RTBI
RMII SMII
PPC440GX designed using IBM® Microelectronics Blue Logicmethodology which major functional blocks integrated together create application-specific product (ASIC). This approach provides consistent create complex ASICs using CoreConnect BusArchitecture. Note: CoreConnect buses provide: 128-bit interfaces 32-bit interfaces 83.33MHz, 333MB/s
Address Maps
PPC440GX incorporates address maps. first fixed processor system memory address map. This address defines possible contents various address regions which processor access. second address Device Configuration Registers (DCRs). DCRs accessed software running PPC440GX processor through mtdcr mfdcr instructions.
AMCC
440GX Power 440GX Embedded Processor
Revision 1.20 June 2009
System Memory Address
Function SDRAM Local Memory1 SRAM Reserve Reserved UART0 Reserved UART1 Reserved IIC0 Reserved IIC1 Reserved Arbiter Reserved Internal Peripherals
(Sheet
Function Start Address 0000 0000 8000 0000 8000 4000 FFFF 0000 0000 0000 4000 0000 4000 0200 4000 0208 4000 0300 4000 0308 4000 0400 4000 0420 4000 0500 4000 0520 4000 0600 4000 0640 4000 0700 4000 0780 4000 0790 4000 07A0 4000 0800 4000 0900 4000 0A00 4000 0B00 4000 0C00 4000 0D00 4000 0E00 4000 0F00 F000 0000 FFE0 0000 Address 7FFF FFFF 8000 3FFF FFFE FFFF FFFF FFFF 3FFF FFFF 4000 01FF 4000 0207 4000 02FF 4000 0307 4000 03FF 4000 041F 4000 04FF 4000 051F 4000 05FF 4000 063F 4000 06FF 4000 077F 4000 078F 4000 079F 4000 07FF 4000 08FF 4000 09FF 4000 0AFF 4000 0BFF 4000 0CFF 4000 0DFF 4000 0EFF EFFF FFFF FFDF FFFF FFFF FFFF 254MB 256B 256B 256B 256B 256B 256B 256B 128B 64KB Size 256KB
GPIO Controller Ethernet ZMII Ethernet GMII Reserved Ethernet Controller Ethernet Controller General Purpose Timer TCPIP Accelerator Ethernet Controller TCPIP Accelerator Ethernet Controller Reserved Expansion ROM2 Boot ROM2,
AMCC
Revision 1.20 June 2009
System Memory Address
Function Reserved PCI-X Reserved
440GX Power 440GX Embedded Processor
(Sheet
Function Start Address 0000 0000 0800 0000 0C00 0000 0EC0 0000 0EC0 0008 0EC8 0000 0EC8 0100 0ED0 0000 0EE0 0000 Address 07FF FFFF 0BFF FFFF 0EBF FFFF 0EC0 0007 0EC7 FFFF 0EC8 00FF 0EC8 00FF 0EDF FFFF FFFF FFFF 55.76 256B 64MB Size
PCI-X External Configuration Registers PCI-X Reserved PCI-X Bridge Core Configuration Registers Reserved PCI-X Special Cycle PCI-X Memory Notes:
SDRAM on-chip SRAM located anywhere Local Memory area memory map. Boot Expansion areas memory intended Flash-type devices. While locating volatile SDRAM SRAM this region supported, these regions this purpose recommended. When optional boot from PCI-X memory selected, PCI-X Boot address space begins FFFE 0000 (128 KB).
AMCC
440GX Power 440GX Embedded Processor
Revision 1.20 June 2009
Address Device Configuration Registers
Function Total Address Space1 function: Reserved Clocking Power Reset System DCRs Memory Controller External Controller External Master Performance Monitor SRAM Controller Reserved Bridge Reserved Bridge Power Management Reserved Interrupt Controller Interrupt Controller Clock, Control, Reset Reserved Controller Reserved Ethernet Base Interrupt Controller Interrupt Controller Reserved Notes: address space addressable with bits (1024 unique addresses). Each unique address represents single 32-bit (word) register. kiloword (1024W) equals (4096 bytes). 128W 480W Start Address Address Size (4KB)1
AMCC
Revision 1.20 June 2009
PowerPC Processor Core
440GX Power 440GX Embedded Processor
PowerPC processor core designed high-end applications: RAID controllers, SAN, ISCSI, routers, switches, printers, set-top boxes, etc. first processor core implement Book PowerPC embedded architecture first 128-bit version IBM's on-chip CoreConnect Architecture. Features include: 667MHz operation PowerPC Book architecture 32KB I-cache, 32KB D-cache UTLB Word Wide parity data address parity with exception force Three logical regions D-cache: locked, transient, normal D-cache full line flush capability 41-bit virtual address, 36-bit (64GB) physical address Superscalar, out-of-order execution 7-stage pipeline execution pipelines Dynamic branch prediction Memory management unit 64-entry, full associative, unified with parity Separate instruction data micro-TLBs Storage attributes write-through, cache-inhibited, guarded, little endian Debug facilities Multiple instruction data range breakpoints Data value compare Single step, branch, trap events Non-invasive real-time trace interface instructions Single-cycle multiply multiply-accumulate integer multiply 32-bit
Internal Buses
PowerPC 440GX features three standard on-chip buses: Processor Local (PLB), On-Chip Peripheral (OPB), Device Control Register (DCR). high performance, high bandwidth cores such PowerPC processor core, SDRAM memory controller, PCI-X bridge connect PLB. hosts lower data rate peripherals. daisy-chained provides lower bandwidth path passing status control information between processor core other on-chip cores. Features include: 128-bit implementation architecture Separate simultaneous read write data paths 64-bit address Simultaneous control, address, data phases Four levels pipelining Byte enable capability supporting unaligned transfers 64-byte burst transfers 166MHz, maximum 5.2GB/s (simultaneous read write) Processor:bus clock ratios
AMCC
440GX Power 440GX Embedded Processor
Revision 1.20 June 2009
Dynamic sizing 32-, 16-, 8-bit data path 36-bit address 83.33MHz, maximum 333MB/s 32-bit data path address
On-Chip SRAM
Features include: Four banks 64KB each total 256KB Configurable either Code (L2) cache software-controlled on-chip memory, SRAM Memory cycles supported: Single beat read write, bytes 64-byte burst transfers Guarded memory accesses Sustainable 2.6GB/s peak bandwidth 166MHz cache improves processor performance reduces load Cache coherency maintained hardware snoop mechanism software Data Array Array parity Unified data instruction cache 4-way associative 36-bit addressing Full replacement algorithm Write through, look aside Ethernet packet store allows Ethernet packets held processing unit
PCI-X Interface
PCI-X interface allows connection PCI-X devices PowerPC processor local memory. This interface designed Version 1.0a PCI-X Specification supports 64-bit PCI-X buses. 32/64-bit conventional mode, compatible with Version 2.3, also supported. Reference Specifications: PowerPC CoreConnect (PLB) Specification Version Specification Version Power Management Interface Specification Version Features include: PCI-X 1.0a Split transactions Frequency 133MHz 64-bit backward compatibility Frequency 66MHz 64-bit Host Bridge Adapter Device's interface Internal arbitration function, supporting external devices, that disabled with external arbiter Support Message Signaled Interrupts
AMCC
Revision 1.20 June 2009
440GX Power 440GX Embedded Processor
Simple message passing capability Asynchronous Power Management register addressable both from on-chip processor device sides Ability boot from PCI-X memory Error tracking/status Supports initiation transfer following address spaces: Single beat reads writes Single beat burst memory reads writes Single beat configuration reads writes (type type Single beat special cycles
SDRAM Memory Controller
Double Data Rate (DDR) SDRAM memory controller supports industry standard 184-pin DIMMs, SO-DIMMs, other discrete devices. four 512MB logical banks supported limited configurations. Global memory timings, address bank sizes, memory addressing modes programmable. Features include: Registered non-registered industry standard DIMMs 64-bit memory interface with optional 8-bit (SEC/DED) Sustainable 2.6GB/s peak bandwidth 166MHz (200MHz 800MHz parts) SSTL_2 logic chip selects latencies supported DDR200/266/333 support Page mode accesses eight open pages) with configurable paging policy Programmable address mapping timing Hardware software initiated self-refresh Power management (self-refresh, suspend, sleep)
External Peripheral Controller (EBC)
Features include: eight ROM, EPROM, SRAM, Flash memory, slave peripheral banks supported 83.33MHz operation (333MB/s) Burst non-burst devices 16-, 32-bit byte-addressable data 32-bit address, address space Peripheral Device pacing with external "Ready" Latch data Ready, synchronous asynchronous Programmable access timing device Wait States non-burst Burst Wait States first access Wait States subsequent accesses Programmable CSon, CSoff relative address Programmable OEon, WEon, WEoff clock cycles) relative Programmable address mapping External Slave Support
AMCC
440GX Power 440GX Embedded Processor
Revision 1.20 June 2009
External master interface Write posting from external master Read prefetching external master reads Bursting capable from external master Allows external master access non-EBC slaves External master control slaves access control
Ethernet Controller Interface
Ethernet support provided PPC440GX interfaces physical layer, included chip. Features include: four 10/100 interfaces running full- half-duplex modes full Media Independent Interface (MII) with 4-bit parallel data transfer Reduced Media Independent Interfaces (RMII) with 2-bit parallel data transfer Four Serial Media Independent Interfaces (SMII) GMII interfaces running full- half-duplex modes 10Mb/s 100Mb/s 1000Mb/s full Gigabit Media Independent Interface (GMII) with 8-bit parallel data transfer Reduced Gigabit Media Independent Interfaces (RGMII) with 4-bit parallel data transfer interfaces running full- half-duplex modes 10Mb/s 100Mb/s 1000Mb/s full Interface (TBI) with 10-bit parallel data transfer Reduced Interfaces (RTBI) with 4-bit parallel data transfer Jumbo frame support (9016 byte) Support Ethernet formatted frames (RFC894) Support IEEE formatted frames (RFC1042) Handles VLAN-tagged frames
TCP/IP Acceleration Hardware (TAH)
Features include: Offloads Gigabit Ethernet protocol processing from Checksum verification TCP/UDP/IP headers receive path Checksum generation TCP/UDP/IP headers transmit path segmentation support transmit path
Controller
Features include: Supports following transfers: Memory-to-memory transfers Buffered peripheral memory transfers Buffered memory peripheral transfers Four channels Scatter/Gather capability programming multiple operations 16-, 32-bit peripheral support (OPB external) 64-bit addressing byte FIFO buffer Address increment decrement Supports internal external peripherals Support memory mapped peripherals
AMCC
Revision 1.20 June 2009
440GX Power 440GX Embedded Processor
Support peripherals running slower frequency buses
Serial Port
Features include: 8-pin UART 4-pin UART interface provided Selectable internal external serial clock allow wide range baud rates Register compatibility with 16750 register Complete status reporting capability Fully programmable serial-interface characteristics Supports using internal engine
Interface
Features include: interfaces provided Support Philips® Semiconductors Specification, dated 1995 Operation 100kHz 400kHz 8-bit data 7-bit address Slave transmitter receiver Master transmitter receiver Multiple masters Supports fixed interface independent byte data buffers Twelve memory-mapped, fully programmable configuration registers programmable interrupt request signal Provides full management protocols Programmable error recovery
General Purpose Timers (GPT)
Provides separate time base counter additional system timers addition those defined processor core. 32-bit Time Base Counter driven clock Seven 32-bit compare timers
General Purpose (GPIO) Controller
Controller functions GPIO registers programmed accessed memory-mapped master accesses. GPIOs pin-shared with other functions. DCRs control whether particular that GPIO capabilities acts GPIO used another purpose. Each GPIO output separately programmable emulate open drain driver (that drives zero, tri-stated output
AMCC
440GX Power 440GX Embedded Processor
Revision 1.20 June 2009
Universal Interrupt Controller (UIC)
Four Universal Interrupt Controllers (UIC) available. They provide control, status, communications necessary between external internal sources interrupts on-chip PowerPC processor. Note: Processor specific interrupts (for example, page faults) resources. Features include: external interrupts internal interrupts Edge triggered level-sensitive Positive negative active Non-critical critical interrupt on-chip processor core Programmable interrupt priority ordering Programmable critical interrupt vector faster vector processing
Performance Monitor
Performance Monitor (PPM) provides hardware counting certain events associated with transactions. contents counters read software analysis enhancement performance, software debug. data includes identification duration events.
Messaging Unit (IMU)
interfaces master slave allows messages transferred between masters (for example, PCI-X). Features include: Three messaging methods Message registers-2 inbound, outbound Doorbell registers-1 inbound, outbound Circular queues-2 inbound, outbound different interrupt outputs generated Support interrupt masking
JTAG
Features include: IEEE 1149.1 Test Access Port RISCWatch Debugger support JTAG Boundary Scan Description Language (BSDL)
AMCC
Revision 1.20 June 2009
440GX Power 440GX Embedded Processor
25mm, 552-Ball Ceramic (CBGA) Package
View
Chip Corner PPC440GX-3xxfffx
Part Number
Number
Capacitor Notes: dimensions RoHS compliant reduced-lead package available. Reduced-lead package dimensions parentheses (dimension).
Bottom View
25.0 23.0 25.0 0.04 Solderball (0.7 0.1) 1.00 2.31 (2.20 max) 1.89 (2.00 min)
AAAAAAAA
0.81 (0.60 max) 0.71 (0.40 max) 3.977 (3.707 max) 3.379 (3.179 min)
0.857 (0.907 max) 0.779 (0.779 min)
AMCC
440GX Power 440GX Embedded Processor
Revision 1.20 June 2009
25mm, 552-Ball Plastic (FC-PBGA) Package
View
Corner
PPC440GX
3xxfffx Number AAAAAAAA
Part Number
Notes: dimensions Available lead-free, RoHS compliant version.
Bottom View
25.0 23.0 0.66 Solderball 1.00
1.214
25.0
23.0
3.191 0.17
0.508
AMCC
Revision 1.20 June 2009
Signal Lists
440GX Power 440GX Embedded Processor
following table lists external signals alphabetical order shows ball (pin) number which signal appears. Multiplexed signals shown with default signal (following reset) brackets alternate signal brackets. Multiplexed signals appear alphabetically multiple times list-once each signal name ball. page number listed gives page "Signal Functional Description" page where signals indicated interface group begin. cases where signals same interface group (for example, Ethernet) have different names distinguish variations mode operation, names separated comma with primary name appearing first. These signals listed only once, appear alphabetically primary name.
Signals Listed Alphabetically
Signal Name APGND ASGND AMGND AMVDD APVDD ASVDD BankSel0 BankSel1 BankSel2 BankSel3 [BE0]PCIXC0 [BE1]PCIXC1 [BE2]PCIXC2 [BE3]PCIXC3 [BE4]PCIXC4 [BE5]PCIXC5 [BE6]PCIXC6 [BE7]PCIXC7 BusReq[TrcTS1] ClkEn0 ClkEn1 ClkEn2 ClkEn3
(Sheet
Ball AA11 AB11 AA16 SDRAM AD09 AB15 SDRAM AD11 AD05 PCI-X AA24 AB05 AD17 AB10 SDRAM External Master Peripheral SDRAM Power-MemClkOut analog voltage Power-PCI-X analog voltage Power-SysClk analog voltage Power-Analog ground Interface Group Page
AMCC
440GX Power 440GX Embedded Processor
Revision 1.20 June 2009
Signals Listed Alphabetically
Signal Name DMAAck0 DMAAck1 DMAAck2[GMCRxD0, GMC0RxD0, TBIRxD0, RTBI0RxD0] DMAAck3[GMCRxD1, GMC0RxD1, TBIRxD1, RTBI0RxD1] DMAReq0 DMAReq1 DMAReq2[GMCRxDV, GMC0RxCtl, TBIRxD8, RTBI0RxD4] DMAReq3[GMCTxEn, GMC0TxCtl, TBITxD8, RTBI0TxD4] DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8 DrvrInh2
(Sheet
Ball AA18 AB14 AA09 AA07 AC05 AC20 AC16 AC14 AB13 AC11 AC09 AA05 System SDRAM External Slave Peripheral External Slave Peripheral SDRAM Interface Group Page
AMCC
Revision 1.20 June 2009
Signals Listed Alphabetically
Signal Name ECC0 ECC1 ECC2 ECC3 ECC4 ECC5 ECC6 ECC7 EMCCD, EMC1RxErr, GMCGTxClk, GMC0TxClk, TBITxClk, RTBI0TxClk EMCCrS, EMC0CrSDV, GMCTxD7, GMC1TxD3, TBITxD7, RTBI1TxD3 EMCMDClk EMCMDIO EMCRxClk, GMCTxD5, GMC1TxD1, TBITxD5, RTBI1TxD1 EMCRxD0, EMC0RxD0, EMC0RxD EMCRxD1, EMC0RxD1, EMC1RxD EMCRxD2, EMC1RxD0, EMC2RxD, GMCTxD0, GMC0TxD0, TBITxD0, RTBI0TxD0 EMCRxD3, EMC1RxD1, EMC3RxD GMCTxD1, GMC0TxD1, TBITxD1, RTBI0TxD1 EMCRxDV, EMC1CrSDV, GMCTxD4, GMC1TxD0, TBITxD4, RTBI1TxD0 EMCRxErr, EMC0RxErr, GMCTxD6, GMC1TxD2, TBITxD6, RTBI1TxD2 EMCTxClk, EMCRefClk EMCTxD0, EMC0TxD0, EMC0TxD EMCTxD1, EMC0TxD1, EMC1TxD EMCTxD2, EMC1TxD0, EMC2TxD, GMCTxD2, GMC0TxD2, TBITxD2, RTBI0TxD2 EMCTxD3, EMC1TxD1, EMC3TxD, GMCTxD3, GMC0TxD3, TBITxD3, RTBI0TxD3 EMCTxEn, EMC0TxEn, EMCSync EMCTxErr, EMC1TxEn, GMCRxClk, GMC0RxClk, TBIRxClk0, RTBI0RxClk
440GX Power 440GX Embedded Processor
(Sheet
Ball AB07 AB06 AD06 SDRAM AC03 AB04 AD04 Ethernet Ethernet Ethernet Ethernet Ethernet Ethernet Interface Group Page
Ethernet Ethernet Ethernet
Ethernet
Ethernet Ethernet
AMCC
440GX Power 440GX Embedded Processor
Revision 1.20 June 2009
Signals Listed Alphabetically
Signal Name EOT0/TC0 EOT1/TC1 EOT2/TC2[GMCRxD2, GMC0RxD2, TBIRxD2, RTBI0RxD2] EOT3/TC3[GMCRxD3, GMC0RxD3, TBIRxD3, RTBI0RxD3] ExtAck[TrcTS2] ExtReq[TrcTS3] ExtReset [GMCCD, GMC1RxClk, RTBI1RxClk]TrcTS1[GPIO27] [GMCCrS, GMC1TxClk, RTBI1TxClk]TrcTS6 GMCRefClk [GMCRxD0, GMC0RxD0, TBIRxD0, RTBI0RxD0]DMAAck2 [GMCRxD1, GMC0RxD1, TBIRxD1, RTBI0RxD1]DMAAck3 [GMCRxD2, GMC0RxD2, TBIRxD2, RTBI0RxD2]EOT2/TC2 [GMCRxD3, GMC0RxD3, TBIRxD3, RTBI0RxD3]EOT3/TC3 [GMCRxD4, GMC1RxD0, TBIRxD4, RTBI1RxD0][GPIO28]TrcTS2 [GMCRxD5, GMC1RxD1, TBIRxD5, RTBI1RxD1][GPIO29]TrcTS3 [GMCRxD6, GMC1RxD2, TBIRxD6, RTBI1RxD2][GPIO30]TrcTS4 [GMCRxD7, GMC1RxD3, TBIRxD7, RTBI1RxD3][GPIO31]TrcTS5 [GMCRxDV, GMC0RxCtl, TBIRxD8, RTBI0RxD4]DMAReq2 GMCRxEr, GMC1RxCtl, TBIRxD9, RTBI1RxD4 GMCTxEr, GMC1TxCtl, TBITxD9, RTBI1TxD4 [GMCTxEn, GMC0TxCtl, TBITxD8, RTBI0TxD4]DMAReq3 [GMCTxClk, TBIRxClk1]GPIO11
(Sheet
Ball AA22 AB23 Ethernet Ethernet Ethernet Ethernet Note: Used initialization strapping input. Ethernet Ethernet External Master Peripheral External Master Peripheral External Master Peripheral Ethernet Ethernet Ethernet External Slave Peripheral Interface Group Page
AMCC
Revision 1.20 June 2009
Signals Listed Alphabetically
Signal Name
440GX Power 440GX Embedded Processor
(Sheet
Ball Power Interface Group Page
AMCC
440GX Power 440GX Embedded Processor
Revision 1.20 June 2009
Signals Listed Alphabetically
Signal Name
(Sheet
Ball Power Interface Group Page
AMCC
Revision 1.20 June 2009
Signals Listed Alphabetically
Signal Name
440GX Power 440GX Embedded Processor
(Sheet
Ball AA02 AA06 AA10 AA13 AA17 AA21 AC04 AC08 AC12 AC15 AC19 Power Interface Group Page
AMCC
440GX Power 440GX Embedded Processor
Revision 1.20 June 2009
Signals Listed Alphabetically
Signal Name [GPIO00]IRQ00 [GPIO01]IRQ01 [GPIO02]IRQ02 [GPIO03]IRQ03 [GPIO04]IRQ04 [GPIO05]IRQ05 [GPIO06]IRQ06 [GPIO07]IRQ07 [GPIO08]IRQ08 [GPIO09]IRQ09 [GPIO10]IRQ10 GPIO11[GMCTxClk, TBIRxClk1] [GPIO12]UART1_Rx [GPIO13]UART1_Tx [GPIO14]UART1_DSR/CTS [GPIO15]UART1_RTS/DTR [GPIO16]IIC1SClk [GPIO17]IIC1SDA [GPIO18]TrcBS0[IRQ13] [GPIO19]TrcBS1[IRQ14] [GPIO20]TrcBS2[IRQ15] [GPIO21]TrcES0[IRQ16] [GPIO22]TrcES1[IRQ17] [GPIO23]TrcES2 [GPIO24]TrcES3 [GPIO25]TrcES4 [GPIO26]TrcTS0 [GPIO27]TrcTS1[GMCCD, GMC1RxClk, RTBI1RxClk] [GPIO28]TrcTS2[GMCRxD4, GMC1RxD0, TBIRxD4, RTBI1RxD0] [GPIO29]TrcTS3[GMCRxD5, GMC1RxD1, TBIRxD5, RTBI1RxD1] [GPIO30]TrcTS4[GMCRxD6, GMC1RxD2, TBIRxD6, RTBI1RxD2] [GPIO31]TrcTS5[GMCRxD7, GMC1RxD3, TBIRxD7, RTBI1RxD3]
(Sheet
Ball System Interface Group Page
AMCC
Revision 1.20 June 2009
Signals Listed Alphabetically
Signal Name Halt HoldAck[TrcTS4] HoldReq[TrcTS5] IIC0SClk IIC0SDA IIC1SClk[GPIO16] IIC1SDA[GPIO17] IRQ00[GPIO00] IRQ01[GPIO01] IRQ02[GPIO02] IRQ03[GPIO03] IRQ04[GPIO04] IRQ05[GPIO05] IRQ06[GPIO06] IRQ07[GPIO07] IRQ08[GPIO08] IRQ09[GPIO09] IRQ10[GPIO10] [IRQ11]PCIReq1 [IRQ12]PCIGnt1 [IRQ13][GPIO18]TrcBS0 [IRQ14][GPIO19]TrcBS1 [IRQ15][GPIO20]TrcBS2 [IRQ16][GPIO21]TrcES0 [IRQ17][GPIO22]TrcES1
440GX Power 440GX Embedded Processor
(Sheet
Ball Interrupts System External Master Peripheral External Master Peripheral Peripheral Peripheral Peripheral Peripheral Interface Group Page
AMCC
440GX Power 440GX Embedded Processor
Revision 1.20 June 2009
Signals Listed Alphabetically
Signal Name MemAddr00 MemAddr01 MemAddr02 MemAddr03 MemAddr04 MemAddr05 MemAddr06 MemAddr07 MemAddr08 MemAddr09 MemAddr10 MemAddr11 MemAddr12 MemClkOut0 MemClkOut0
(Sheet
Ball AD20 AB20 AD18 AD16 AB18 SDRAM SDRAM Interface Group Page
AMCC
Revision 1.20 June 2009
Signals Listed Alphabetically
Signal Name MemData00 MemData01 MemData02 MemData03 MemData04 MemData05 MemData06 MemData07 MemData08 MemData09 MemData10 MemData11 MemData12 MemData13 MemData14 MemData15 MemData16 MemData17 MemData18 MemData19 MemData20 MemData21 MemData22 MemData23 MemData24 MemData25 MemData26 MemData27 MemData28 MemData29 MemData30 MemData31
440GX Power 440GX Embedded Processor
(Sheet
Ball AD21 AB21 AC22 AA20 AD19 AB19 AB16 AC18 AB17 SDRAM AA14 AD15 AD13 AD14 AB12 Interface Group Page
AMCC
440GX Power 440GX Embedded Processor
Revision 1.20 June 2009
Signals Listed Alphabetically
Signal Name MemData32 MemData33 MemData34 MemData35 MemData36 MemData37 MemData38 MemData39 MemData40 MemData41 MemData42 MemData43 MemData44 MemData45 MemData46 MemData47 MemData48 MemData49 MemData50 MemData51 MemData52 MemData53 MemData54 MemData55 MemData56 MemData57 MemData58 MemData59 MemData60 MemData61 MemData62 MemData63 MemVRef1 MemVRef2
(Sheet
Ball AD12 AD10 AB08 AD08 AC07 AB09 SDRAM AA01 AA03 AB02 AB03 SDRAM Interface Group Page
AMCC
Revision 1.20 June 2009
Signals Listed Alphabetically
Signal Name ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball
440GX Power 440GX Embedded Processor
(Sheet
Ball physical ball does exist these ball coordinates. AB01 AB24 AC01 AC02 AC23 AC24 AD01 AD02 AD03 AD22 AD23 AD24 Interface Group Page
AMCC
440GX Power 440GX Embedded Processor
Revision 1.20 June 2009
Signals Listed Alphabetically
Signal Name OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD PCIX133Cap PCIXAck64
(Sheet
Ball AA23 PCI-X PCI-X Power Interface Group Page
AMCC
Revision 1.20 June 2009
Signals Listed Alphabetically
Signal Name PCIXAD00 PCIXAD01 PCIXAD02 PCIXAD03 PCIXAD04 PCIXAD05 PCIXAD06 PCIXAD07 PCIXAD08 PCIXAD09 PCIXAD10 PCIXAD11 PCIXAD12 PCIXAD13 PCIXAD14 PCIXAD15 PCIXAD16 PCIXAD17 PCIXAD18 PCIXAD19 PCIXAD20 PCIXAD21 PCIXAD22 PCIXAD23 PCIXAD24 PCIXAD25 PCIXAD26 PCIXAD27 PCIXAD28 PCIXAD29 PCIXAD30 PCIXAD31
440GX Power 440GX Embedded Processor
(Sheet
Ball PCI-X Interface Group Page
AMCC
440GX Power 440GX Embedded Processor
Revision 1.20 June 2009
Signals Listed Alphabetically
Signal Name PCIXAD32 PCIXAD33 PCIXAD34 PCIXAD35 PCIXAD36 PCIXAD37 PCIXAD38 PCIXAD39 PCIXAD40 PCIXAD41 PCIXAD42 PCIXAD43 PCIXAD44 PCIXAD45 PCIXAD46 PCIXAD47 PCIXAD48 PCIXAD49 PCIXAD50 PCIXAD51 PCIXAD52 PCIXAD53 PCIXAD54 PCIXAD55 PCIXAD56 PCIXAD57 PCIXAD58 PCIXAD59 PCIXAD60 PCIXAD61 PCIXAD62 PCIXAD63
(Sheet
Ball PCI-X Interface Group Page
AMCC
Revision 1.20 June 2009
Signals Listed Alphabetically
Signal Name PCIXC0[BE0] PCIXC1[BE1] PCIXC2[BE2] PCIXC3[BE3] PCIXC4[BE4] PCIXC5[BE5] PCIXC6[BE6] PCIXC7[BE7] PCIXCap PCIXClk PCIXDevSel PCIXFrame PCIXGnt0 PCIXGnt1[IRQ12] PCIXGnt2 PCIXGnt3 PCIXGnt4 PCIXGnt5 PCIXIDSel PCIXINT PCIXIRDY PCIXM66En PCIXParHigh PCIXParLow PCIXPErr PCIXReq0 PCIXReq1[IRQ11] PCIXReq2 PCIXReq3 PCIXReq4 PCIXReq5 PCIXReq64 PCIXReset PCIXSErr
440GX Power 440GX Embedded Processor
(Sheet
Ball PCI-X PCI-X PCI-X PCI-X PCI-X PCI-X PCI-X PCI-X PCI-X PCI-X PCI-X PCI-X PCI-X PCI-X PCI-X PCI-X PCI-X Interface Group Page
AMCC
440GX Power 440GX Embedded Processor
Revision 1.20 June 2009
Signals Listed Alphabetically
Signal Name PCIXStop PCIXTRDY PerAddr00 PerAddr01 PerAddr02 PerAddr03 PerAddr04 PerAddr05 PerAddr06 PerAddr07 PerAddr08 PerAddr09 PerAddr10 PerAddr11 PerAddr12 PerAddr13 PerAddr14 PerAddr15 PerAddr16 PerAddr17 PerAddr18 PerAddr19 PerAddr20 PerAddr21 PerAddr22 PerAddr23 PerAddr24 PerAddr25 PerAddr26 PerAddr27 PerAddr28 PerAddr29 PerAddr30 PerAddr31
(Sheet
Ball External Slave Peripheral Note: PerAddr00 most significant (msb) this bus. PCI-X PCI-X Interface Group Page
AMCC
Revision 1.20 June 2009
Signals Listed Alphabetically
Signal Name PerBLast PerClk PerCS0 PerCS1 PerCS2 PerCS3 PerCS4 PerCS5 PerCS6 PerCS7
440GX Power 440GX Embedded Processor
(Sheet
Ball External Slave Peripheral Interface Group External Slave Peripheral External Master Peripheral Page
AMCC
440GX Power 440GX Embedded Processor
Revision 1.20 June 2009
Signals Listed Alphabetically
Signal Name PerData00 PerData01 PerData02 PerData03 PerData04 PerData05 PerData06 PerData07 PerData08 PerData09 PerData10 PerData11 PerData12 PerData13 PerData14 PerData15 PerData16 PerData17 PerData18 PerData19 PerData20 PerData21 PerData22 PerData23 PerData24 PerData25 PerData26 PerData27 PerData28 PerData29 PerData30 PerData31 [PerErr]TrcTS6 PerOE
(Sheet
Ball External Master Peripheral External Slave Peripheral External Slave Peripheral Note: PerData00 most significant (msb) this bus. Interface Group Page
AMCC
Revision 1.20 June 2009
Signals Listed Alphabetically
Signal Name PerPar0 PerPar1 PerPar2 PerPar3 PerReady[RcvrInh] PerR/W PerWBE0 PerWBE1 PerWBE2 PerWBE3 PerWE [RcvrInh]PerReady RefVEn SVDD SVDD SVDD SVDD SVDD SVDD SVDD SVDD SVDD SysClk SysErr SysReset TestEn TmrClk
440GX Power 440GX Embedded Processor
(Sheet
Ball External Slave Peripheral External Slave Peripheral AD07 AA08 AA15 AC06 AC13 AC21 AB22 System System System JTAG JTAG JTAG System System JTAG Power External Slave Peripheral SDRAM System System External Slave Peripheral External Slave Peripheral Interface Group Page
AMCC
440GX Power 440GX Embedded Processor
Revision 1.20 June 2009
Signals Listed Alphabetically
Signal Name TrcBS0[GPIO18][IRQ13] TrcBS1[GPIO19][IRQ14] TrcBS2[GPIO20][IRQ15] TrcClk TrcES0[GPIO21][IRQ16] TrcES1[GPIO22][IRQ17] TrcES2[GPIO23] TrcES3[GPIO24] TrcES4[GPIO25] TrcTS0[GPIO26] TrcTS1[GPIO27][GMCCD, GMC1RxClk, RTBI1RxClk] [TrcTS1]BusReq TrcTS2[GPIO28][GMCRxD4, GMC1RxD0, TBIRxD4, RTBI1RxD0] [TrcTS2]ExtAck TrcTS3[GPIO29][GMCRxD5, GMC1RxD1, TBIRxD5, RTBI1RxD1] [TrcTS3]ExtReq TrcTS4[GPIO30][GMCRxD6, GMC1RxD2, TBIRxD6, RTBI1RxD2] [TrcTS4]HoldAck TrcTS5[GPIO31][GMCRxD7, GMC1RxD3, TBIRxD7, RTBI1RxD3] [TrcTS5]HoldReq TrcTS6[GMCCrS, GMC1TxClk, RTBI1TxClk] TrcTS6[PerErr] TRST UART0_CTS UART0_DCD
(Sheet
Ball AA24 AA22 AB23 Trace Trace Trace Trace Trace Trace Trace Trace Trace Trace Trace Trace Trace JTAG UART Peripheral UART Peripheral Note: Used initialization strapping input. UART Peripheral Note: Used initialization strapping input. UART Peripheral UART Peripheral UART Peripheral UART Peripheral Trace Trace Trace Interface Group Page
UART0_DSR UART0_DTR UART0_RI UART0_RTS UART0_Rx
AMCC
Revision 1.20 June 2009
Signals Listed Alphabetically
Signal Name UART0_Tx UART1_DSR/CTS[GPIO14] UART1_RTS/DTR[GPIO15] UART1_Rx[GPIO12] UART1_Tx[GPIO13] UARTSerClk
440GX Power 440GX Embedded Processor
(Sheet
Ball Power UART Peripheral UART Peripheral UART Peripheral UART Peripheral UART Peripheral UART Peripheral Interface Group Page
AMCC
440GX Power 440GX Embedded Processor
Revision 1.20 June 2009
Signals Listed Alphabetically
Signal Name
(Sheet
Ball Power AA04 AA12 AA19 AC10 AC17 SDRAM Interface Group Page
AMCC
Revision 1.20 June 2009
440GX Power 440GX Embedded Processor
following table, only primary (default) signal name shown each pin. Multiplexed multifunction signals marked with asterisk (*). determine what signals functions multiplexed those pins, look primary signal name "Signals Listed Alphabetically" page
Signals Listed Ball Assignment
Ball Signal Name ball ball ball PCIXAD51 DrvrInh2 PCIXAD58 EMCRxD2 PCIXAD42 UARTSerClk PCIXAD05 PCIXFrame PerAddr03 PerAddr12 PCIXM66En PCIXAD09 PerAddr11 PCIXPErr PCIXSErr PerAddr04 PCIXAD21 PCIXAD22 ball ball ball Ball ball ball
(Sheet
Ball Signal Name ball PCIXAD41 PCIXC5 PCIXAD50 EMCTxErr PCIXAD57 PerBLast PCIXC4 PCIXAD55 PCIXAD04 PerAddr01 PCIXTRDY UART0_CTS PerAddr14 PCIXAD10 PCIXAD14 PCIXAD00 UART1_Rx PCIXC2 PerAddr10 PCIXAD23 PCIXGnt1 PCIXAD28 ball Ball Signal Name PCIXAD36 OVDD PCIXAD45 PCIXAD53 PCIXAD61 PCIXAck64 OVDD PerAddr00 PerAddr15 PCIXAD15 OVDD PerAddr05 PCIXAD20 PCIXAD30 PCIXAD31
Signal Name
PCIXAD46 OVDD PCIXAD54 PCIXAD62 PCIXAD01 PerAddr02 OVDD PerAddr13 PCIXAD13 UART0_DTR OVDD PerAddr16 PCIXAD25 ball ball
AMCC
440GX Power 440GX Embedded Processor
Revision 1.20 June 2009
Signals Listed Ball Assignment
Ball Signal Name EMCRxD1 PCIXAD40 PCIXClk PCIXAD49 UART1_RTS/DTR PCIXAD56 PCIXAD60 PCIXAD63 PCIXReq64 PCIXAD03 PerAddr06 PCIXIRDY PCIXDevSel PerAdd09 PCIXAD11 PCIXC1 PerCS0 PCIXAD16 PCIXAD17 PCIXReq2 PCIXReq1 PCIXGnt0 PCIXAD27 PCIXReq0 Ball
(Sheet
Ball Signal Name APVDD PCIXAD39 EMCRxD0 PCIXAD48 PCIXAD43 UART1_DSR/CTS PCIXIDSel PCIX133Cap PCIXC6 PCIXAD02 IIC0SClk PCIXAD07 IIC0SDA PCIXAD08 PCIXAD12 UART0_RTS UART0_Rx PCIXAD19 PerData04 PerData03 PCIXAD26 SysClk PCIXReq4 ASVDD SysClk Ball Signal Name PCIXAD33 PCIXAD32 PCIXAD38 OVDD PCIXAD47 EMCRxD3 OVDD IIC1SClk OVDD IIC1SDA UART0_RI PerData05 PerData02 OVDD PerData01 PerData00
Signal Name PCIXAD35 PCIXAD44 PCIXAD52 PCIXAD59 OVDD PCIXC7 PCIXAD06 PCIXC0 OVDD PCIXParLow PCIXAD18 PCIXC3 PCIXAD24 OVDD PCIXAD29
AMCC
Revision 1.20 June 2009
Signals Listed Ball Assignment
Ball Signal Name APGND EMCRxClk EMCTxD3 EMCTxD2 PCIXAD37 EMCTxClk EMCCD EMCMDClk PerData19 PerData18 PerData17 PerData16 PerData15 PerData14 PerData13 UART1_Tx PerData12 PerData11 PerData10 PerData9 PerData8 PerData7 PerData6 ASGND Ball
440GX Power 440GX Embedded Processor
(Sheet
Ball Signal Name GMCRefClk RefVEn PerCS4 PCIXParHigh EMCMDIO EMCTxEn GMCTxEr PCIXAD34 EMCTxD0 PerCS1 UART0_Tx PCIXStop PerCS6 PerData20 PerAddr17 PerData31 PerData30 IRQ03 PerData29 IRQ01 PerAddr18 PerAddr19 PCIXCap PerAddr22 Ball Signal Name PerAddr21 OVDD PerAddr07 TestEn PCIXINT PerOE DMAReq1 IRQ06 EOT3/TC3 OVDD PCIXGnt3 IRQ05 PerAddr20 PCIXReset
Signal Name EMCRxDV EMCRxErr OVDD EMCTxD1 EMCCrS OVDD PerData28 PerData27 PerData26 PerData25 PerData24 OVDD PerData23 PerData22 PerData21
AMCC
440GX Power 440GX Embedded Processor
Revision 1.20 June 2009
Signals Listed Ball Assignment
Ball Signal Name PerAddr08 PerAddr28 DMAAck0 PerReady OVDD TrcES2 DMAReq2 IRQ04 TrcBS0 IRQ00 IRQ08 PCIXGnt2 OVDD TRST Ball
(Sheet
Ball Signal Name TrcTS6 DMAReq0 TrcClk OVDD TrcTS2 TrcTS4 MemData42 MemData14 EOT0/TC0 OVDD PCIXReq5 PCIXReq3 OVDD PCIXGnt4 PerAddr25 Ball Signal Name DQS7 SysErr PerCS5 TrcTS0 TrcES4 TrcTS5 MemData61 MemData56 MemVRef2 MemData38 MemData37 MemData35 MemData22 MemVRef1 MemData18 ExtReset PerWBE0 PerAddr24 TrcBS2 TrcES0 PerPar1 PerPar0 PerCS3
Signal Name DMAReq3 PerWE TrcTS1 GMCRxEr PerR/W DMAAck2 DMAAck1 TrcES3 TrcTS3 SysReset DMAAck3 MemData28 GPIO11 EOT1/TC1 EOT2/TC2 TrcBS1 IRQ07 PCIXGnt5 IRQ02 TrcTS6 IRQ09 TrcES1 PerAddr23
AMCC
Revision 1.20 June 2009
Signals Listed Ball Assignment
Ball Signal Name TmrClk PerCS7 OVDD MemData63 MemData57 ECC4 MemData36 SVDD MemData21 SVDD MemData04 PerClk OVDD PerPar3 PerAddr26 PerAddr27 Ball
440GX Power 440GX Embedded Processor
(Sheet
Ball Signal Name MemData58 OVDD MemData59 MemData62 ECC3 ClkEn3 SVDD MemData32 BankSel1 MemAddr10 SVDD MemData08 PerPar2 PerWBE2 PerWBE3 Ball Signal Name MemData51 MemData53 DQS6 MemData46 MemData43 MemData47 ClkEn2 MemData34 MemAddr11 MemData30 MemData27 MemAddr7 MemData23 MemData20 MemData10 MemData13 MemAddr00 MemAddr02 HoldAck HoldReq
Signal Name MemData55 UART0_DSR PerCS2 Halt MemData60 MemData54 MemClkOut0 MemClkOut0 MemAddr12 MemAddr9 MemData31 MemAddr8 MemData26 MemData19 MemData09 MemData05 IRQ10 PerWBE1 PerAddr29 PerAddr31 PerAddr30 UART0_DCD
AMCC
440GX Power 440GX Embedded Processor
Revision 1.20 June 2009
Signals Listed Ball Assignment
Ball AA01 AA02 AA03 AA04 AA05 AA06 AA07 AA08 AA09 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24 Signal Name MemData48 MemData49 DQS8 SVDD AMGND MemData16 SVDD MemData03 ExtAck OVDD BusReq Ball AB01 AB02 AB03 AB04 AB05 AB06 AB07 AB08 AB09 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24 ball
(Sheet
Ball AC01 AC02 AC03 AC04 AC05 AC06 AC07 AC08 AC09 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 Signal Name ball ball ECC5 SVDD MemData44 DQS5 DQS4 SVDD DQS2 DQS1 MemData12 DQS0 SVDD MemData02 ball ball Ball AD01 AD02 AD03 AD04 AD05 AD06 AD07 AD08 AD09 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 Signal Name ball ball ball ECC7 BankSel3 ECC2 MemData41 MemData39 BankSel2 MemData33 MemData24 MemData25 MemData17 MemAddr5 ClkEn0 MemAddr4 MemData06 MemAddr01 MemData00 ball ball ball
Signal Name
MemData50 MemData52 ECC6 ECC1 ECC0 MemData40 MemData45 ClkEn1 AMVDD MemClk MemData29 DQS3 BankSel0 MemData11 MemData15 MemAddr6 MemData07 MemAddr3 MemData01 ExtReq ball
AMCC
Revision 1.20 June 2009
Signal Description
440GX Power 440GX Embedded Processor
PPC440GX embedded controller provided 552-ball, ball grid array package. following tables describe package level pinout.
Summary
Group
Signal pins, non-multiplexed Signal pins, multiplexed Total Signal Pins AxVDD AxGnd OVDD SVDD Total Power Pins Reserved Total Pins
Pins
table "Signal Functional Description" page each signal listed along with short description function. Active-low signals (for example, RAS) marked with overline. Please "Signals Listed Alphabetically" page (ball) number which each signal assigned. Multiplexed Signals Some signals multiplexed same that used different functions. most cases, signal names shown this table accompanied signal names that multiplexed same pin. need know what, any, signals multiplexed with particular signal, look name "Signals Listed Alphabetically" page expected that single application particular will always programmed serve same function. flexibility multiplexing allows single chip offer richer selection than would otherwise possible. Multipurpose Signals addition multiplexing, some pins also multi-purpose. example, peripheral controller address pins (PerAddr00:31) used outputs PPC440GX broadcast address external slave devices when PPC440GX control external bus. When during course normal chip operation external master gains ownership external bus, these same pins used inputs which driven external master received PPC440GX. this example, pins also bidirectional, serving both inputs outputs. Multimode Signals some cases (for example, Ethernet) function vary with different modes operation. When multiple signal names assigned distinguish different modes operation, names shown.
AMCC
440GX Power 440GX Embedded Processor
Revision 1.20 June 2009
Strapping Pins group pins used strapped inputs during system reset. These pins function strapped inputs only during reset used other functions during normal operation (see "Strapping" page 89). Note that these multiplexed pins since function pins programmable.
AMCC
Revision 1.20 June 2009
Signal Functional Description
440GX Power 440GX Embedded Processor
(Sheet Notes: Receiver input hysteresis Must pull (recommended value 3.3V) Must pull down (recommended value used, must pull (recommended value 3.3V) used, must pull down (recommended value GND) Strapping input during reset; pull-up (recommended value 3.3V) pull-down (recommended value GND) required
Signal Name PCI-X Interface PCIXAD00:63 PCIXC0:7[BE0:7] PCIXCap PCIX133Cap PCIXClk Address/Data (bidirectional). PCI-X Command[Byte Enables]. Capable PCI-X operation. PCI-X devices capable. Provides timing interface transactions. Note: PCI-X interface being used, drive this with 3.3V clock signal frequency between 66MHz Indicates driving device decoded address target current access. Driven current master indicate beginning duration access. Indicates that specified agent granted access bus. When using external PCI/PCI-X arbiter, connect external arbiter's Grant line this signal. Indicates that specified agent granted access bus. Indicates that specified agent granted access bus. Used chip select during configuration read write transactions. Level sensitive interrupt. Indicates initiating agent's ability complete current data phase transaction. Capable 66MHz operation. Even parity across PCIAD32:63 PCIXC0:3[BE4:7]. Even parity across PCIAD0:31 PCIXC0:3[BE0:3]. Reports data parity errors during transactions except Special Cycle. indication PCI-X arbiter that specified agent wishes bus. When using external PCI/PCI-X arbiter, connect external arbiter's Request line this signal. indication PCI-X arbiter that specified agent wishes bus. Asserted current master, indicating 64-bit transfer. Indicates target transfer data using bits. Brings device registers logic consistent state. Reports address parity errors, data parity errors Special Cycle command, other catastrophic system errors. Indicates current target requesting master stop current transaction. 3.3V 3.3V 3.3V LVTTL 3.3V 3.3V Description Type
Notes
PCIXDevSel PCIXFrame PCIXGnt0 PCIXGnt1 PCIXGnt2:5 PCIXIDSel PCIXINT PCIXIRDY PCIXM66En PCIXParHigh PCIXParLow PCIXPErr PCIXReq0 PCIXReq1:5 PCIXReq64 PCIXAck64 PCIXReset PCIXSErr PCIXStop
3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V LVTTL w/pull-up 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V
AMCC
440GX Power 440GX Embedded Processor
Revision 1.20 June 2009
Signal Functional Description
(Sheet Notes: Receiver input hysteresis Must pull (recommended value 3.3V) Must pull down (recommended value used, must pull (recommended value 3.3V) used, must pull down (recommended value GND) Strapping input during reset; pull-up (recommended value 3.3V) pull-down (recommended value GND) required
Signal Name PCIXTRDY SDRAM Interface BA0:1 BankSel0:3 ClkEn0:3 DM0:8 DQS0:8 ECC0:7 MemAddr00:12 MemClkOut0 MemClkOut0 MemData00:63 MemVRef1:2 Ethernet Interface EMCCD, EMC1RxErr, GMCGTxClk, GMC0TxClk, TBITxClk, RTBI0TxClk EMCCrS, EMC0CrSDV, GMCTxD7, GMC1TxD3, TBITxD7, RTBI1TxD3 EMCMDClk EMCMDIO MII: Collision detection RMII Receive error GMII: 1000Mbps Transmit clock RGMII: Transmit clock TBI: Transmit clock RTBI: Transmit clock MII: Carrier sense RMII Carrier sense data valid GMII: Transmit data RGMII Transmit data TBI: Transmit data RTBI Transmit data RMII: Management data clock RMII: Transfer command status information between Bank Address supporting four internal banks. Selects four external SDRAM banks. Column Address Strobe. Clock Enable. each bank. Memory write data byte lane masks. MEMDM8 byte lane mask byte lane. Byte lane data strobe. DQS8 data strobe byte lane. check bits 0:7. Memory address bus. Subsystem clock. Memory data bus. Memory reference voltage (SVREF) input. Address Strobe. Write Enable. 2.5V SSTL_2 2.5V SSTL_2 2.5V SSTL_2 2.5V SSTL_2 2.5V SSTL_2 2.5V SSTL_2 2.5V SSTL_2 2.5V SSTL_2 2.5V SSTL_2 2.5V SSTL_2 Voltage Receiver 2.5V SSTL_2 2.5V SSTL_2 Description Type 3.3V
Notes
Indicates target agent's ability complete current data phase transaction.
3.3V tolerant 2.5V CMOS
3.3V tolerant 2.5V CMOS
3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS
AMCC
Revision 1.20 June 2009
Signal Functional Description
440GX Power 440GX Embedded Processor
(Sheet Notes: Receiver input hysteresis Must pull (recommended value 3.3V) Must pull down (recommended value used, must pull (recommended value 3.3V) used, must pull down (recommended value GND) Strapping input during reset; pull-up (recommended value 3.3V) pull-down (recommended value GND) required
Signal Name EMCRxD0:3, EMC0RxD0:1, EMC1RxD0:1, EMC0RxD, EMC1RxD, EMC2RxD, EMC3RxD, GMCTxD0:1, GMC0TxD0:1, TBITxD0:1, RTBI0TxD0:1 EMCRxDV, EMC1CrSDV, GMCTxD4, GMC1TxD0, TBITxD4, RTBI1TxD0 EMCRxClk, GMCTxD5, GMC1TxD1, TBITxD5, RTBI1TxD1 EMCRxErr, EMC0RxErr, GMCTxD6, GMC1TxD2, TBITxD6, RTBI1TxD2 EMCTxClk, EMCRefClk EMCTxD0:3, EMC0TxD0:1, EMC1TxD0:1, EMC0TxD, EMC1TxD, EMC2TxD, EMC3TxD, GMCTxD2:3, GMC0TxD2:3, TBITxD2:3, RTBI0TxD2:3 EMCTxEn, EMC0TxEn, EMCSync EMCTxErr, EMC1TxEn, GMCRxClk, GMC0RxClk, TBIRxClk0, RTBI0RxClk GMCCD, GMC1RxClk, RTBI1RxClk MII: Receive data RMII Receive data RMII Receive data SMII Receive data SMII Receive data SMII Receive data SMII Receive data GMII: Transmit data RGMII Transmit data TBI: Transmit data RTBI Transmit data MII: Receive data valid RMII Carrier sense data valid GMII: Transmit data RGMII Transmit data TBI: Transmit data RTBI Transmit data MII: Receive clock GMII: Transmit data RGMII Transmit data TBI: Transmit data RTBI Transmit data MII: Receive error RMII Receive error GMII: Transmit data RGMII Transmit data TBI: Transmit data RTBI Transmit data MII: Transmit clock RMII SMII: Reference clock MII: Transmit data RMII Transmit data RMII Transmit data SMII Transmit data SMII Transmit data SMII Transmit data SMII Transmit data GMII: Transmit data RGMII Transmit data TBI: Transmit data RTBI Transmit data MII: Transmit data enabled RMII Transmit data enabled SMII: Sync signal MII: Transmit error: RMII: Transmit data enabled GMII: Receive clock RGMII: Receive clock TBI: Receive clock RTBI: Receive clock GMII: Collision detection RGMII: Receive clock RTBI: Receive clock Description Type
Notes
3.3V tolerant 2.5V CMOS
3.3V tolerant 2.5V CMOS
3.3V tolerant 2.5V CMOS
3.3V tolerant 2.5V CMOS
3.3V tolerant 2.5V CMOS
3.3V tolerant 2.5V CMOS
3.3V tolerant 2.5V CMOS
3.3V tolerant 2.5V CMOS
3.3V tolerant 2.5V CMOS
AMCC
440GX Power 440GX Embedded Processor
Revision 1.20 June 2009
Signal Functional Description
(Sheet Notes: Receiver input hysteresis Must pull (recommended value 3.3V) Must pull down (recommended value used, must pull (recommended value 3.3V) used, must pull down (recommended value GND) Strapping input during reset; pull-up (recommended value 3.3V) pull-down (recommended value GND) required
Signal Name GMCCrS, GMC1TxClk, RTBI1TxClk GMCRefClk GMCRxD0:3, GMC0RxD0:3, TBIRxD0:3, RTBI0RxD0:3 GMCRxD4:7, GMC1RxD0:3, TBIRxD4:7, RTBI1RxD0:3 GMCRxDV, GMC0RxCtl, TBIRxD8, RTBI0RxD4 GMCRxEr, GMC1RxCtl, TBIRxD9, RTBI1RxD4 GMCTxEn, GMC0TxCtl, TBITxD8, RTBI0TxD4 GMCTxEr, GMC1TxCtl, TBITxD9, RTBI1TxD4 GMCTxClk TBIRxClk1 GMII: Carrier sense RGMII: Transmit clock RTBI: Transmit clock GMII, RGMII, RTBI: Gigabit reference clock GMII: Receive data RGMII: Receive data TBI: Receive data RTBI: Receive data GMII: Receive data RGMII: Receive data TBI: Receive data RTBI: Receive data GMII: Receive data valid RGMII: Receive control TBI: Receive data RTBI: Receive data GMII: Receive error RGMII: Receive control TBI: Receive data RTBI: Receive data GMII: Transmit data enable RGMII: Transmit control TBI: Transmit data RTBI: Transmit data GMII: Transmit error RGMII: Transmit control TBI: Transmit data RTBI: Transmit data GMII: 10/100Mbps Transmit clock TBI: Receive clock Description Type 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS
Notes
3.3V tolerant 2.5V CMOS
3.3V tolerant 2.5V CMOS
3.3V tolerant 2.5V CMOS
3.3V tolerant 2.5V CMOS
3.3V tolerant 2.5V CMOS 3.3V LVTTL
External Slave Peripheral Interface DMAAck0:3 DMAReq0:3 EOT0:3/TC0:3 Used PPC440GX indicate that data transfers have occurred. Used slave peripherals indicate they prepared transfer data. Transfer/Terminal Count. Peripheral address used PPC440GX when external master mode, otherwise used external master. Note: PerAddr00 most significant (msb) this bus. External peripheral data byte enables. Used either peripheral controller, controller, external master indicates last transfer memory access. External peripheral device select. 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL
PerAddr00:31 PerWBE0:3 PerBLast PerCS0:7
AMCC
Revision 1.20 June 2009
Signal Functional Description
440GX Power 440GX Embedded Processor
(Sheet Notes: Receiver input hysteresis Must pull (recommended value 3.3V) Must pull down (recommended value used, must pull (recommended value 3.3V) used, must pull down (recommended value GND) Strapping input during reset; pull-up (recommended value 3.3V) pull-down (recommended value GND) required
Signal Name PerData00:31 Description Peripheral data used PPC440GX when external master mode, otherwise used external master. Note: PerData00 most significant (msb) this bus. Used either peripheral controller controller depending upon type transfer involved. When PPC440GX master, enables selected device drive bus. External peripheral data byte parity. Used peripheral slave indicate ready transfer data. Used PPC440GX when external master mode, output either peripheral controller controller depending upon type transfer involved. High indicates read from memory, indicates write memory. Otherwise, used external master input indicate direction transfer. Write Enable. when four PerWBE0:3 signals low. Type 3.3V LVTTL
Notes
PerOE PerPar0:3 PerReady
3.3V LVTTL 3.3V LVTTL 3.3V LVTTL
PerR/W
3.3V LVTTL
PerWE
3.3V LVTTL
External Master Peripheral Interface BusReq ExtAck ExtReq ExtReset HoldAck HoldReq PerClk PerErr UART Peripheral Interface UARTSerClk UART0_Rx UART0_Tx UART0_DCD UART0_DSR UART0_CTS Serial clock input that provides alternative internally generated serial clock. Used cases where allowable internally generated clock rates satisfactory. This input individually connected either both UART0 UART1. UART0 Receive data. UART0 Transmit data. UART0 Data Carrier Detect. UART0 Data Ready. UART0 Clear Send. 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL Request. Used when PPC440GX needs regain control peripheral interface from external master. External Acknowledgement. Used PPC440GX indicate that data transfer occurred. External Request. Used external master indicate prepared transfer data. Peripheral Reset. Used external master synchronous peripheral slaves. Hold Acknowledge. Used PPC440GX transfer ownership peripheral external master. Hold Request. Used external master request ownership peripheral bus. Peripheral Clock. Used external master synchronous peripheral slaves. External Error. Used input record external master errors external slave peripheral errors. 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL
AMCC
440GX Power 440GX Embedded Processor
Revision 1.20 June 2009
Signal Functional Description
(Sheet Notes: Receiver input hysteresis Must pull (recommended value 3.3V) Must pull down (recommended value used, must pull (recommended value 3.3V) used, must pull down (recommended value GND) Strapping input during reset; pull-up (recommended value 3.3V) pull-down (recommended value GND) required
Signal Name UART0_DTR UART0_RTS UART0_RI UART1_Rx UART1_Tx UART1_DSR/CTS UART1_RTS/DTR Peripheral Interface IIC0SClk IIC0SDA IIC1SClk IIC1SDA Interrupts Interface IRQ00:10 IRQ11:12 IRQ13:17 JTAG Interface Test Clock. Test Data Test Data Out. Test Mode Select. Test Reset. During chip power-up, this signal must from start ramp-up until least SysClk cycles after stable order initialize JTAG controller. 3.3V LVTTL w/pull-up 3.3V LVTTL w/pull-up 3.3V LVTTL 3.3V LVTTL w/pull-up 3.3V LVTTL w/pull-up External interrupt Requests through External interrupt Requests through External interrupt Requests through 3.3V LVTTL 3.3V 3.3V LVTTL IIC0 Serial Clock. IIC0 Serial Data. IIC1 Serial Clock. IIC1 Serial Data. 3.3V LVTTL 3.3V LVTTL 3.3V 3.3V Description UART0 Data Terminal Ready. UART0 Request Send. UART0 Ring Indicator. UART1 Receive data. UART1 Transmit data. UART1 Data Ready Clear Send. choice determined register setting. UART1 Request Send Data Terminal Ready. choice determined register setting. Type 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL
Notes
TRST
AMCC
Revision 1.20 June 2009
Signal Functional Description
440GX Power 440GX Embedded Processor
(Sheet Notes: Receiver input hysteresis Must pull (recommended value 3.3V) Must pull down (recommended value used, must pull (recommended value 3.3V) used, must pull down (recommended value GND) Strapping input during reset; pull-up (recommended value 3.3V) pull-down (recommended value GND) required
Signal Name System Interface SysClk SysErr Main system clock input. when machine check generated. Main system reset. External logic drive this bidirectional (minimum cycles) initiate system reset. system reset also initiated software. signal implemented open-drain output (two states; open circuit). During chip power-up, this signal must from start ramp-up until least SysClk cycles after stable. Processor timer external input clock. Halt from external debugger. General purpose through access these functions, software must register bits. Test Enable. Receiver Inhibit. Active only when TestEn active. Reference Voltage Enable. connect normal operation. Pull Boundary Scan Description Language (BSDL) testing. Driver Inhibit. Used test purposes only. normal operation Clock 3.3V LVTTL 3.3V LVTTL Description Type
Notes
SysReset
3.3V LVTTL
TmrClk Halt GPIO00:31 TestEn RcvrInh RefVEn DrvrInh2
3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V tolerant 2.5V CMOS 3.3V LVTTL 3.3V LVTTL w/pull-down 3.3V LVTTL w/pull-up
AMCC
440GX Power 440GX Embedded Processor
Revision 1.20 June 2009
Signal Functional Description
(Sheet Notes: Receiver input hysteresis Must pull (recommended value 3.3V) Must pull down (recommended value used, must pull (recommended value 3.3V) used, must pull down (recommended value GND) Strapping input during reset; pull-up (recommended value 3.3V) pull-down (recommended value GND) required
Signal Name Trace Interface TrcBS0:2 TrcClk TrcES0:4 Trace branch execution status. Trace data capture clock, runs frequency processor. Trace Execution Status presented every fourth processor clock cycle. 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL Description Type
Notes
Additional information trace execution branch status. Note: trace signals, TrcTS0:6, duplicated sets TrcTS0:5 chip balls multiplexed with other signals both cases. (multiplexed with GPIO signals) This allows users choose which multiplexed signals they wish along with TrcTS0:6 signals. trace signals this primary signals. TrcTS1:5 (multiplexed with signals) TrcTS6 (multiplexed with Ethernet signals) Power Pins AxGND AxVDD OVDD SVDD (analog) voltage ground. Ground. 1.5V-Filtered voltages input PLLs (analog circuits) Note: separate filter each three voltages recommended. 3.3V supply-I/O (except SDRAM, Ethernet) 2.5V supply-DDR SDRAM, Ethernet 1.5V supply-Logic voltage. Additional information trace execution branch status. Note: trace signals this secondary signals. Additional information trace execution branch status. Note: This trace signal primary signal.
3.3V tolerant 2.5V CMOS
3.3V LVTTL
3.3V LVTTL
AMCC
Revision 1.20 June 2009
440GX Power 440GX Embedded Processor
Absolute Maximum Ratings
absolute maximum ratings below stress ratings only. Operation beyond these maximum ratings cause permanent damage device. None performance specification contained this document guaranteed when operating these maximum ratings.
Characteristic Supply Voltage (Internal Logic) Supply Voltage (I/O Interface, except SDRAM) Supply Voltages Supply Voltage (DDR SDRAM Logic) Input Voltage (3.3V LVTTL receivers) Storage Temperature Range Case Temperature under bias Notes: analog voltages used on-chip PLLs derived from logic voltage, must filtered before entering PPC440GX. separate filter, shown below, recommended each voltage: AxVDD ferrite bead chip, Murata BLM31A700S equivalent. ceramic AxGND This value specification operational temperature range; stress rating only. Symbol OVDD AxVDD SVDD TSTG Value +1.65 +3.6 +1.65 +2.7 +3.6 +150 +120 Unit Notes
AMCC
440GX Power 440GX Embedded Processor
Revision 1.20 June 2009
Package Thermal Specifications
Thermal resistance values CBGA PBGA packages convection environment follows:
Airflow ft/min (m/sec) Junction-to-case thermal resistance (0.51) <0.1 17.7 20.8 Range Junction-to-ball (typical) Notes: Case temperature, measured center case surface with device soldered circuit board. case-to-ambient thermal resistance measured JEDEC JESD51-6 standard environment; accurately predict thermal performance production equipment environments. operational case temperature must maintained. Modeled standard JEDEC 2S2P card, 50x50mm °C/W theoretical using infinite heat sink. larger number applies module mounted 1.8mm thick, card using 1oz. copper power planes, with effective heat transfer area 75mm2. °C/W °C/W (1.02) <0.1 16.3 °C/W °C/W °C/W °C/W
Parameter
Symbol
Package
Unit
Notes
Ceramic Plastic Ceramic Plastic
<0.1 18.9
Case-to-ambient thermal resistance (w/o heat sink)
Ceramic Plastic
AMCC
Revision 1.20 June 2009
440GX Power 440GX Embedded Processor
Heat Sink Mounting Information (Ceramic Package Only)
Proper thermal design primarily dependent upon multiple system-level effects; that effects heat sink, flow, thermal interface material. reduce die-junction temperature, heat sinks attached package several methods: adhesive, spring clips printed-circuit board package, mounting clip screw assembly. When attaching heat sinks, important avoid placing excessive mechanical stress bonding chip substrate package board.
Heat Sink Attached With Spring Clip
Heat sink Heat sink clip Thermal grease CBGA package Printed circuit board Spring clip package Static compression (spring force)-2.27kg maximum
Heat sink Heat sink clip Thermal grease CBGA package Printed circuit board Spring clip board Static compression (spring force)-2.27kg maximum1
Note Force limited allowable compression die. Allowable package compression force 4.4kg.
Heat Sink Attached With Adhesive
Heat sink Adhesive CBGA package Printed circuit board Printed circuit board CBGA package Adhesive
Heat sink
Weight force Weight force Heat sink weight force-60g maximum
Important: guidelines indicated above diagrams must evaluated adjusted account shock vibration effects particular application.
AMCC
440GX Power 440GX Embedded Processor
Revision 1.20 June 2009
Recommended Operating Conditions
Device operation beyond conditions specified recommended. Extended operation beyond recommended conditions affect device reliability.
Parameter Logic Supply Voltage (533MHz) Logic Supply Voltage (667MHz) Supply Voltage SDRAM Supply Voltage (DDR clock 166MHz) Supply Voltages (533MHz) Supply Voltage (667MHz) SDRAM Reference Voltage Input Logic High (2.5V SSTL) Input Logic High (2.5V CMOS, 3.3V tolerant receiver) Input Logic High (3.3V PCI-X) Input Logic High (3.3V LVTTL) Input Logic (2.5V SSTL) Input Logic (2.5V CMOS, 3.3V tolerant receiver) Input Logic (3.3V PCI-X) Input Logic (3.3V LVTTL) Output Logic High (2.5V SSTL) Output Logic High (2.5V CMOS, 3.3V tolerant receiver) Output Logic High (3.3V PCI-X) Output Logic High (3.3V LVTTL) Output Logic (2.5V SSTL) Output Logic (2.5V CMOS, 3.3V tolerant receiver) Output Logic (3.3V PCI-X) Output Logic (3.3V LVTTL) Input Leakage Current pull-up pull-down) Input Leakage Current Pull-Down Input Leakage Current Pull-Up Input Allowable Overshoot (3.3V LVTTL) Input Allowable Undershoot (3.3V LVTTL) Output Allowable Overshoot (3.3V LVTTL) IIL1 IIL2 IIL3 VIMAO VIMAU VOMAO -0.6 +3.9 (LPDL) -150 (LPDL) Symbol OVDD SVDD AxVDD AxVDD SVREF Minimum +1.4 +1.5 +3.0 +2.3 +1.4 +1.5 +1.15 SVREF+0.18 0.5OVDD +2.0 -0.3 OVDD+0.5 +3.6 SVREF-0.18 -0.5 +1.95 0.9OVDD +2.4 OVDD OVDD 0.55 0.1OVDD +0.4 (MPUL) (MPUL) +3.9 0.35OVDD +0.8 SVDD Typical +1.5 +1.55 +3.3 +2.5 +1.5 +1.55 +1.25 Maximum +1.6 +1.6 +3.6 +2.7 +1.6 +1.6 +1.35 SVDD+0.3 Unit Notes
AMCC
Revision 1.20 June 2009
440GX Power 440GX Embedded Processor
Recommended Operating Conditions
(Continued) Device operation beyond conditions specified recommended. Extended operation beyond recommended conditions affect device reliability.
Parameter Output Allowable Undershoot (3.3V LVTTL) Case Temperature rating Notes: PCI-X drivers meet PCI-X specifications. SVREF SVDD/2 analog voltages used on-chip PLLs derived from logic voltage, must filtered before entering PPC440GX. "Absolute Maximum Ratings" page There OVDD, VDD, SVDD power supply power-up sequence requirements. However, external voltage should applied chip pins before OVDD applied chip. power-down cycle should complete (OVDD should both below 0.4V) before power- cycle started. LPDL least positive down level; MPUL most positive level. Case temperature, measured center case surface with device soldered circuit board. 667MHz ceramic parts operated 533MHz less, operational temperature range extended +105°C 667MHz plastic parts operated 533MHz less, operational temperature range extended +100°C. Symbol VOMAU3 Minimum -0.6 Typical Maximum Unit Notes
Input Capacitance
Parameter Group (2.5V SSTL I/O) Group (3.3V LVTTL I/O) Group (PCI-X I/O) Group (Receivers) Group (3.3V tolerant CMOS I/O) Symbol CIN1 CIN2 CIN3 CIN4 CIN5 Maximum Unit Notes
AMCC
440GX Power 440GX Embedded Processor
Revision 1.20 June 2009
Power Supply Loads
Parameter active operating current Symbol Frequency (MHz) Typical 1.37 1.49 Maximum 1.69 Unit Notes
OVDD active operating current
IODD
SVDD active operating current AxVDD input current
ISDD IADD
Notes: "Absolute Maximum Ratings" page filter recommendations. maximum current values listed above guaranteed highest obtainable. These values dependent many factors including type applications running, clock rates, internal functional capabilities, external interface usage, case temperature, power supply voltages. Your specific application produce significantly different results. (logic) current power primarily dependent applications running internal chip functions (DMA, PCI, Ethernet, on). OVDD (I/O) current power primarily dependent capacitive loading, frequency, utilization external buses. following information provides details about conditions under which listed values were obtained: general, values measured using PPC440GX Evaluation Board Ethernet mode PCI-X running 100MHz with Intel 1000, Agilent Test card, EBMI test card, UART wrap plug, 128MB Micron DIMM while running applications designed maximize power consumption. external master heavily loads with transfers targeting SDRAM, while internal controller further increases SDRAM traffic. System clock rates follows: SysClk 33MHz, 667MHz, 167MHz, 83MHz. Typical current characterized +1.5V, OVDD +3.3V, SVDD +2.5V, Maximum current characterized +1.6V, OVDD +3.6V, SVDD +2.7V, Estimated values.
Test Conditions
Clock timing switching characteristics specified accordance with operating conditions shown table "Recommended Operating Conditions." specifications characterized with 1.5V, 10pF test load shown figure right.
Output
10pF
AMCC
Revision 1.20 June 2009
440GX Power 440GX Embedded Processor
Clocking Specifications
Symbol SysClk Input Frequency Period Edge stability (cycle-to-cycle jitter) High time time 33.33 nominal period nominal period 83.33 ±0.15 nominal period nominal period Parameter Minimum Maximum Units Notes
Note: Input slew rate 1V/ns Frequency Period 0.75 1334 1.66
Processor Clock (CPU Clock) Frequency Period
MemClkOut Clock Clock Notes: maximum supported processor clock frequency part specified part number (see "Ordering Information" page order support 1Gbps Ethernet data rate, minimum clock frequency 66.66Mhz. Ethernet application limited 100Mbps, minimum clock frequency 33.33Mhz. order support 1Gbps Ethernet data rate, minimum clock frequency 83.33Mhz. Ethernet application limited 100Mbps, minimum clock frequency 33.33Mhz Frequency Period 83.33 Frequency Period 66.66 83.33 Frequency-533, Period-533, High time nominal period 166.66 nominal period
AMCC
440GX Power 440GX Embedded Processor
Revision 1.20 June 2009
Timing Waveform
2.0V 1.5V 0.8V
AMCC
Revision 1.20 June 2009
Spread Spectrum Clocking
440GX Power 440GX Embedded Processor
Care must taken when using spread spectrum clock generator (SSCG) with PPC440GX. This controller uses clock generation inside chip. accuracy with which follows SSCG referred tracking skew. bandwidth phase angle determine much tracking skew there between SSCG given frequency deviation modulation frequency. When using SSCG with PPC440GX following conditions must met: frequency deviation must violate minimum clock cycle time. Therefore, when operating PPC440GX with more internal clocks their maximum supported frequency, SSCG only lower frequency. maximum frequency deviation cannot exceed -3%, modulation frequency cannot exceed 40kHz. some cases, on-board PPC440GX peripherals impose more stringent requirements. Peripheral Clock logic that synchronous peripheral since this clock tracks modulation. SDRAM MemClkOut since also tracks modulation. PCI-X maximum spread spectrum modulated between 30kHz 33kHz. Notes: serial port baud rates synchronous modulated clock. serial port tolerance approximately 1.5% baud rate before framing errors begin occur. 1.5% tolerance assumes that connected device running precise baud rates. Ethernet operation unaffected. operation unaffected. Important: system designer ensure that SSCG used with PPC440GX meets above requirements does adversely affect other aspects system.
AMCC
440GX Power 440GX Embedded Processor
Revision 1.20 June 2009
Peripheral Interface Clock Timings
Parameter PCIXClk input frequency (asynchronous mode) PCIXClk period (asynchronous mode) PCIXClk input high time PCIXClk input time EMCMDClk output frequency EMCMDClk period EMCMDClk output high time EMCMDClk output time EMCTxClk input frequency MII(RMII) EMCTxClk period MII(RMII) EMCTxClk input high time EMCTxClk input time EMCRxClk input frequency MII(RMII) EMCRxClk period MII(RMII) EMCRxClk input high time EMCRxClk input time GMCRefClk input frequency GMCRefClk period GMCRefClk input high time GMCRefClk input time PerClk output frequency (for ext. master sync. slaves) PerClk period PerClk output high time PerClk output time UARTSerClk input frequency UARTSerClk period UARTSerClk input high time UARTSerClk input time nominal period nominal period 2.5(5) 40(20) nominal period nominal period 2.5(5) 40(20) nominal period nominal period nominal period nominal period 33.33 nominal period nominal period 2TOPB+2 TOPB+1 TOPB+1 nominal period nominal period 83.33 nominal period nominal period 1000/(2TOPB1+2ns) 133.33 nominal period nominal period 25(50) 400(200) 25(50) 400(200) Units Notes
AMCC
Revision 1.20 June 2009
440GX Power 440GX Embedded Processor
Peripheral Interface Clock Timings (Continued)
Parameter TmrClk input frequency TmrClk period TmrClk input high time TmrClk input time Notes: TOPB period clock. internal clock runs integral divisor ratio frequency clock. maximum clock frequency 83.33 MHz. Refer Clocking chapter PPC440GX Embedded Processor User's Manual details. When PCI-X interface used support legacy interface, maximum PCIXClk frequency 66.66MHz. nominal period nominal period nominal period nominal period Units Notes
AMCC
440GX Power 440GX Embedded Processor
Revision 1.20 June 2009
Input Setup Hold Waveform
Clock
Inputs Valid
Output Delay Float Timing Waveform
Clock
Outputs
High (Drive) Float (High-Z) (Drive) Valid Valid
AMCC
Revision 1.20 June 2009
440GX Power 440GX Embedded Processor
Input Setup Hold Waveform RGMII Signals
GMCnRxClk
1.25V
Inputs Valid Valid
RGMII 1000Mb timing with reference raising falling edge GMCnRxClk. RGMII 10/100Mb timing with reference only raising edge GMCnRxClk.
Output Delay Hold Timing Waveform RGMII Signals
GMCnTxClk
1.25V
Outputs High (Drive) Float (High-Z) (Drive) Valid Valid Valid
Valid
RGMII 1000Mb timing with reference raising falling edge GMCnTxClk. RGMII 10/100Mb timing with reference only raising edge GMCnTxClk.
AMCC
440GX Power 440GX Embedded Processor
Revision 1.20 June 2009
Specifications-All Speeds
(Sheet Notes: Ethernet interface meets timing requirements defined IEEE 802.3 standard. PCI-X timings asynchronous operation 133MHz. PCI-X input setup time requirement 1.2ns 133MHz 1.7ns 66MHz. timings parentheses) asynchronous operation 66MHz. output hold time requirement 66MHz 33MHz. clock frequency RMII operation 50MHz 100ppm. clock frequency SMII operation 125MHz 100ppm. These signals that change both positive negative clock transitions.
Input (ns) Signal Setup Time (TIS min) Hold Time (TIH min) Output (ns) Valid Delay (TOV max) Hold Time (TOH min) Output Current (mA) (minimum) (minimum) Clock Notes
PCI-X Interface PCIXAD00:63 PCIXC3:0[BE3:0] PCIXParLow PCIParHigh PCIXFrame PCIXINT PCIXIRDY PCIXTRDY PCIXStop PCIXDevSel PCIXIDSel PCIXPErr PCIXSErr PCIXClk PCIXReset PCIXReq64 PCIXAck64 PCIXCap PCIX133Cap PCIXM66En PCIXReq0:5 PCIXGnt0:5 Note Note Note Note Note Note Note Note Note Note Note Note Note Note Note Note Note (Note (Note (Note (Note (Note (Note (Note (Note (Note (Note (Note (Note (Note (Note PCIXClk PCIXClk PCIXClk PCIXClk PCIXClk PCIXClk PCIXClk PCIXClk PCIXClk PCIXClk PCIXClk PCIXClk PCIXClk PCIXClk PCIXClk PCIXClk PCIXClk PCIXClk PCIXClk PCIXClk PCIXClk async async
AMCC
Revision 1.20 June 2009
Specifications-All Speeds
440GX Power 440GX Embedded Processor
(Sheet Notes: Ethernet interface meets timing requirements defined IEEE 802.3 standard. PCI-X timings asynchronous operation 133MHz. PCI-X input setup time requirement 1.2ns 133MHz 1.7ns 66MHz. timings parentheses) asynchronous operation 66MHz. output hold time requirement 66MHz 33MHz. clock frequency RMII operation 50MHz 100ppm. clock frequency SMII operation 125MHz 100ppm. These signals that change both positive negative clock transitions.
Input (ns) Signal Setup Time (TIS min) Hold Time (TIH min) Output (ns) Valid Delay (TOV max) Hold Time (TOH min) Output Current (mA) (minimum) (minimum) Clock Notes
Ethernet Interface EMCRxD0:3 EMCRxDV EMCRxClk EMCRxErr EMCTxD0:3 EMCTxEn EMCTxClk EMCTxErr EMCCrS EMCCD EMCMDIO EMCMDClk Ethernet RMII Interface EMC0RxD0:1 EMC0RxErr EMC0CrSDV EMC0TxD0:1 EMC0:1TxEn EMC1RxD0:1 EMC1RxErr EMC1CrSDV EMC1TxD0:1 EMCRefClk EMCRefClk EMCRefClk EMCRefClk EMCRefClk EMCRefClk EMCRefClk EMCRefClk EMCRefClk EMCRefClk async EMCMDClk EMCTxClk EMCRxClk EMCTxClk EMCTxClk EMCRxClk EMCRxClk async async async async async
AMCC
440GX Power 440GX Embedded Processor
Revision 1.20 June 2009
Specifications-All Speeds
(Sheet Notes: Ethernet interface meets timing requirements defined IEEE 802.3 standard. PCI-X timings asynchronous operation 133MHz. PCI-X input setup time requirement 1.2ns 133MHz 1.7ns 66MHz. timings parentheses) asynchronous operation 66MHz. output hold time requirement 66MHz 33MHz. clock frequency RMII operation 50MHz 100ppm. clock frequency SMII operation 125MHz 100ppm. These signals that change both positive negative clock transitions.
Input (ns) Signal Setup Time (TIS min) Hold Time (TIH min) Output (ns) Valid Delay (TOV max) Hold Time (TOH min) Output Current (mA) (minimum) (minimum) Clock Notes
Ethernet SMII Interface EMC0:1RxD EMC2:3RxD EMC0:1TxD EMC2:3TxD EMCRefClk Ethernet GMII Interface GMCRxClk GMCRxD0:7 GMCRxEr GMCRxDV GMCCrS GMCol GMCGTxClk GMCTxD0:7 GMCTxEr GMCTxEn GMCGTxClk GMCGTxClk GMCGTxClk GMCRxClk GMCRxClk GMCRxClk async async async async EMCRefClk EMCRefClk EMCRefClk EMCRefClk async
AMCC
Revision 1.20 June 2009
Specifications-All Speeds
440GX Power 440GX Embedded Processor
(Sheet Notes: Ethernet interface meets timing requirements defined IEEE 802.3 standard. PCI-X timings asynchronous operation 133MHz. PCI-X input setup time requirement 1.2ns 133MHz 1.7ns 66MHz. timings parentheses) asynchronous operation 66MHz. output hold time requirement 66MHz 33MHz. clock frequency RMII operation 50MHz 100ppm. clock frequency SMII operation 125MHz 100ppm. These signals that change both positive negative clock transitions.
Input (ns) Signal Setup Time (TIS min) Hold Time (TIH min) Output (ns) Valid Delay (TOV max) Hold Time (TOH min) Output Current (mA) (minimum) (minimum) Clock Notes
Ethernet RGMII Interface GMC0RxClk GMC0RxCtl GMC0RxD0:3 GMC0TxClk GMC0TxCtl GMC0TxD0:3 GMC1RxClk GMC1RxCtl GMC1RxD0:3 GMC1TxClk GMC1TxCtl GMC1TxD0:3 GMCRefClk Ethernet Interface TBIRxClk0 TBIRxClk1 TBIRxD0:9 TBITxClk TBITxD0:9 TBITxClk TBIRxClkx async async async GMC1TxClk GMC1TxClk GMC1RxClk GMC1RxClk GMC0TxClk GMC0TxClk GMC0RxClk GMC0RxClk async async async async async
AMCC
440GX Power 440GX Embedded Processor
Revision 1.20 June 2009
Specifications-All Speeds
(Sheet Notes: Ethernet interface meets timing requirements defined IEEE 802.3 standard. PCI-X timings asynchronous operation 133MHz. PCI-X input setup time requirement 1.2ns 133MHz 1.7ns 66MHz. timings parentheses) asynchronous operation 66MHz. output hold time requirement 66MHz 33MHz. clock frequency RMII operation 50MHz 100ppm. clock frequency SMII operation 125MHz 100ppm. These signals that change both positive negative clock transitions.
Input (ns) Signal Setup Time (TIS min) Hold Time (TIH min) Output (ns) Valid Delay (TOV max) Hold Time (TOH min) Output Current (mA) (minimum) (minimum) Clock Notes
Ethernet RTBI Interface RTBI0RxClk RTBI0RxD0:4 RTBI0TxClk RTBI0TxD0:4 RTBI1RxClk RTBI1RxD0:4 RTBI1TxClk RTBI1TxD0:4 GMCRefClk RTBI1TxClk async RTBI1RxClk async RTBI0TxClk async RTBI0RxClk async async
AMCC
Revision 1.20 June 2009
Specifications-All Speeds
440GX Power 440GX Embedded Processor
(Sheet Notes: Ethernet interface meets timing requirements defined IEEE 802.3 standard. PCI-X timings asynchronous operation 133MHz. PCI-X input setup time requirement 1.2ns 133MHz 1.7ns 66MHz. timings parentheses) asynchronous operation 66MHz. output hold time requirement 66MHz 33MHz. clock frequency RMII operation 50MHz 100ppm. clock frequency SMII operation 125MHz 100ppm. These signals that change both positive negative clock transitions.
Input (ns) Signal Setup Time (TIS min) Hold Time (TIH min) Output (ns) Valid Delay (TOV max) Hold Time (TOH min) Output Current (mA) (minimum) (minimum) Clock Notes
Internal Peripheral Interface IIC0SClk IIC0SDA IIC1SClk IIC1SDA UARTSerClk UART0_Rx UART0_Tx UART0_DCD UART0_DSR UART0_CTS UART0_DTR UART0_RI UART0_RTS UART1_Rx UART1_Tx UART1_DSR/CTS UART1_RTS/DTR Interrupts Interface IRQ00:17 JTAG Interface TRST 15.3 10.2 async async async async async 15.3 15.3 15.3 15.3 10.3 10.3 10.3 10.3 10.3 10.2 10.2 10.2 10.2
AMCC
440GX Power 440GX Embedded Processor
Revision 1.20 June 2009
Specifications-All Speeds
(Sheet Notes: Ethernet interface meets timing requirements defined IEEE 802.3 standard. PCI-X timings asynchronous operation 133MHz. PCI-X input setup time requirement 1.2ns 133MHz 1.7ns 66MHz. timings parentheses) asynchronous operation 66MHz. output hold time requirement 66MHz 33MHz. clock frequency RMII operation 50MHz 100ppm. clock frequency SMII operation 125MHz 100ppm. These signals that change both positive negative clock transitions.
Input (ns) Signal Setup Time (TIS min) Hold Time (TIH min) Output (ns) Valid Delay (TOV max) Hold Time (TOH min) Output Current (mA) (minimum) (minimum) Clock Notes
System Interface SysClk TmrClk SysReset Halt SysErr TestEn DrvrInh2 GPIO00:31 Trace Interface TrcClk TrcBS0:2 TrcES0:4 TrcTS0:5 (GPIO set) TrcTS1:5 (EBC set) TrcTS6 10.3 10.3 10.3 10.3 15.3 15.3 10.2 10.2 10.3 10.3 async async async async async
AMCC
Revision 1.20 June 2009
440GX Power 440GX Embedded Processor
Specifications-500MHz-667MHz
Notes: PerClk rising edge package with 10pF load trails internal clock approximately 1.3ns.
Input (ns) Signal Setup Time (TIS min) Hold Time (TIH min) Output (ns) Valid Delay (TOV max) Hold Time (TOH min) Output Current (mA) (minimum) (minimum) Clock Notes
External Slave Peripheral Interface PerData00:31 PerAddr00:31 PerPar0:3 PerWBE0:3 PerCS0:7 PerOE PerWE PerBLast PerReady[RcvrInh] PerR/W DMAReq0:3 DMAAck0:3 EOT0:3/TC0:3 15.3 15.3 15.3 15.3 15.3 15.3 15.3 15.3 15.3 15.3 10.2 10.2 10.2 10.2 10.2 10.2 10.2 10.2 10.2 10.2 PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk
External Master Peripheral Interface PerClk ExtReset HoldReq HoldAck ExtReq ExtAck BusReq PerErr 15.3 15.3 15.3 15.3 15.3 15.3 10.2 10.2 10.2 10.2 10.2 10.2 PerClk PerClk PerClk PerClk PerClk PerClk PerClk
AMCC
440GX Power 440GX Embedded Processor
Revision 1.20 June 2009
SDRAM Specifications
SDRAM controller times operation with internal clock signals generates MemClkOut0 from clock. clock internal signal that cannot directly observed. However MemClkOut0 same frequency clock signal phase with clock signal. Note: MemClkOut0 advanced with respect clock means SDRAM0_CLKTR programming register. typical system, users advance MemClkOut 90°. This depends specific application requires thorough understanding memory system general (refer SDRAM controller chapter PowerPC 440GX User's Manual). following sections, label MemClkOut0(0) refers MemClkOut0 when been phase-shifted, MemClkOut0(90) refers MemClkOut0 when been phase-advanced 90°. Advancing MemClkOut0 creates cycle setup time cycle hold time address control signals relation MemClkOut0(90). rising edge MemClkOut0(90) aligns with first rising edge signal. following data generated means simulation includes logic, driver, package RLC, lengths. Values calculated over best case worst case processes with speed, temperature, voltage follows: Best Case Fast process, -40°C, +1.6V Worst Case Slow process, +85°C, +1.4V Note: following tables timing diagrams, minimum values measured under best case conditions maximum values measured under worst case conditions. signals terminated indicated figure below timing data following sections. SDRAM Simulation Signal Termination Model
MemClkOut0 10pF MemClkOut0 10pF
PPC440GX
SVDD/2 Addr/Ctrl/Data/DQS
30pF
Note: This diagram illustrates model SDRAM interface used when generating simulation timing data. recommended physical circuit design this interface. actual interface design will depend many factors, including type memory used board layout.
AMCC
Revision 1.20 June 2009
440GX Power 440GX Embedded Processor
SDRAM Output Driver Specifications
Output Current (mA) Signal Path (maximum) Write Data MemData00:07 MemData08:15 MemData16:23 MemData24:31 MemData32:39 MemData40:47 MemData48:55 MemData56:63 ECC0:7 DM0:8 MemClkOut0 MemAddr00:12 BA0:1 BankSel0:3 ClkEn0:3 DQS0:8 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 (minimum)
AMCC
440GX Power 440GX Embedded Processor
Revision 1.20 June 2009
SDRAM Write Operation
following diagram illustrates relationship among signals involved with write operation. SDRAM Write Cycle Timing
MemClkOut0
MemClkOut0(90)
Addr/Cmd MemData
Delay from rising edge MemClkOut0(0) rising/falling edge signal (skew) Setup time address command signals MemClkOut0(90) Hold time address command signals from MemClkOut0(90) Setup time data signals (minimum time data valid before rising/falling edge DSQ) Hold time data signals (minimum time data valid after rising/falling edge DSQ) Delay from rising/falling edge clock rising/falling edge
AMCC
Revision 1.20 June 2009
440GX Power 440GX Embedded Processor
Notes: signals referenced MemClkOut0(0). values table include cycle indicated clock speed. obtain adjusted values lower clock frequencies, subtract from 166MHz values table cycle time lower clock frequency (TDS 0.75TCYC).
Clock Speed (MHz) Signal Name Minimum DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8 4.902 4.872 4.842 4.855 4.832 4.867 4.825 4.880 4.826 (ns) Maximum 5.601 5.535 5.511 5.546 5.504 5.525 5.488 5.543 5.484
Timing-DDR SDRAM
(Sheet Notes: referenced MemClkOut0(0). referenced MemClkOut0(90). obtain adjusted values lower clock frequencies, cycle time lower clock frequency subtract maximum 166MHz (0.75TCYC TSKmax). obtain adjusted values lower clock frequencies, cycle time lower clock frequency minimum 166MHz (0.25TCYC TSKmin).
Clock Speed (MHz) Signal Name Minimum MemAddr00:12 BA0:1 BankSel0:3 ClkEn0:3 MemAddr00:12 BA0:1 BankSel0:3 0.184 0.439 0.249 0.344 0.319 0.373 0.393 -0.283 -0.286 -0.270 (ns) Maximum 0.592 0.683 0.779 0.724 0.561 0.683 0.639 0.307 0.353 0.321 (ns) Minimum 3.908 3.817 3.721 3.776 3.939 3.817 3.816 3.443 3.397 3.429 (ns) Minimum 1.684 1.939 1.749 1.844 1.819 1.873 1.893 0.967 0.964 0.980
Timing-DDR SDRAM TSK, TSA,
AMCC
440GX Power 440GX Embedded Processor
Revision 1.20 June 2009
(Sheet Notes: referenced MemClkOut0(0). referenced MemClkOut0(90). obtain adjusted values lower clock frequencies, cycle time lower clock frequency subtract maximum 166MHz (0.75TCYC TSKmax). obtain adjusted values lower clock frequencies, cycle time lower clock frequency minimum 166MHz (0.25TCYC TSKmin).
Clock Speed (MHz) Signal Name Minimum ClkEn0:3 -0.280 -0.270 -0.263 -0.280 (ns) Maximum 0.298 0.294 0.311 0.288 (ns) Minimum 3.452 3.456 3.439 3.462 (ns) Minimum 0.970 0.980 0.987 0.970
Timing-DDR SDRAM TSK, TSA,
Timing-DDR SDRAM
Notes: measured under worst case conditions. time values table include cycle indicated clock speed. obtain adjusted values lower clock frequencies, subtract from values 166MHz table cycle time lower clock frequency (e.g., 0.25TCYC).
Clock Speed (MHz) Signal Names MemData00:07, MemData08:15, MemData16:23, MemData24:31, MemData32:39, MemData40:47, MemData48:55, MemData56:63, ECC0:7, MemData00:07, MemData08:15, MemData16:23, MemData24:31, MemData32:39, MemData40:47, MemData48:55, MemData56:63, ECC0:7, Reference Signal DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8 DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8 (ns) 1.240 1.236 1.223 1.221 1.238 1.286 1.234 1.257 1.237 0.916 1.018 1.017 0.951 1.030 1.014 0.994 0.994 1.000 (ns) 1.224 1.188 1.224 1.185 1.230 1.175 1.214 1.154 1.243 0.542 0.522 0.527 0.532 0.533 0.536 0.534 0.546 0.532 AMCC
Revision 1.20 June 2009
SDRAM Read Operation
440GX Power 440GX Embedded Processor
following examples timing SDRAM read operations based relationship between incoming data clock signal. Since clock cannot directly observed, delay MemClkOut(0) relative clock (TMD) provided. internal Read Clock signal, like MemClkOut0, derived from clock delayed relative clock programming RDCT RDCD fields SDRAM0_TR1 register. delay programmed from cycle steps using RDCT. Setting RDCD results cycle delay plus value RDCT. delay Read Clock relative clock (TRD) shown below assumes programmable Read Clock delay zero. SDRAM MemClkOut0 Read Clock Delay
MemClkOut0(0) TMDmin 567ps TMDmax 1705ps
Read Clock TRDmin -6ps TRDmax 183ps
operation, following receipt address read command from PPC440GX, SDRAM generates data signals coincident with MemClkOut0. data latched into PPC440GX using signal that delayed cycle. order accommodate timing variations introduced system designs using this chip, three-stage data path shown below used eliminate metastability allow data sampling adjusted minimum latency. This adjustment requires programming Read Clock delay selection Stage Stage Stage data sampling RDSP.
AMCC
440GX Power 440GX Embedded Processor
Revision 1.20 June 2009
SDRAM Read Data Path
Package pins Stage
RDSP
Stage
Stage
Data
Cycle Delay Clock
Programmed Read Clock Delay
Read Select (SDRAM0_TR1)
Timing: Input setup time 0.2ns Input hold time 0.1ns Propagation delay 0.4ns maximum
Flip-Flop Transparent Latch
AMCC
Revision 1.20 June 2009
440GX Power 440GX Embedded Processor
Timing-DDR SDRAM TSIN TDIN
Notes: TSIN Delay from package Stage TDIN Delay from data package Stage time values TSIN include cycle indicated clock speed.
Clock Speed (MHz) Signal Name DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8 DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8 TSIN (ns) minimum 2.132 2.132 2.127 2.116 2.100 2.103 2.144 2.110 2.122 1.942 1.920 1.938 1.945 1.932 1.936 1.938 1.943 1.952 TSIN (ns) maximum 2.884 2.867 2.873 2.851 2.845 2.844 2.902 2.864 2.860 2.365 2.314 2.361 2.370 2.332 2.348 2.356 2.360 2.381 Signal Name MemData00:07 MemData08:15 MemData16:23 MemData24:31 MemData32:39 MemData40:47 MemData48:55 MemData56:63 ECC0:7 MemData00:07 MemData08:15 MemData16:23 MemData24:31 MemData32:39 MemData40:47 MemData48:55 MemData56:63 ECC0:7 TDIN (ns) minimum 0.779 0.789 0.779 0.791 0.766 0.754 0.747 0.770 0.759 0.638 0.631 0.634 0.624 0.630 0.619 0.635 0.642 0.641 TDIN (ns) maximum 1.502 1.521 1.530 1.553 1.501 1.525 1.513 1.521 1.464 1.165 1.149 1.151 1.169 1.151 1.133 1.149 1.151 1.141
following examples, data strobes (DQS) data shown coincident. There actually slight skew specified SDRAM specifications, there additional skew loading signal routing. recommended that signal length eight signals matched.
AMCC
440GX Power 440GX Embedded Processor
Revision 1.20 June 2009
Example data-to-PLB clock timing shown example below, then read clock delayed Stage data sampled (1). Except small, frequency memory systems with memory located physically close PPC440GX, unlikely that Stage data sampled. When data comes later, necessary sample Stage Stage data. (see Examples Another desired data-to-PLB timing allow Stage sampling buffer MemClkOut0 skew enough guarantee timing. this example 1.27ns worst case conditions. SDRAM Read Cycle Timing-Example
Data TSIN Stage Data Stage TDIN High Data Stage
Data RDSP with
High
Clock
High Data RDSP
TSIN Delay from package Stage Propagation delay through TDIN Delay from data package Stage Propagation delay, Stage input RDSP input
AMCC
Revision 1.20 June 2009
Example
440GX Power 440GX Embedded Processor
this example Read Clock delayed almost cycle. Without ECC, Stage data sampled (2). enabled, Stage data must sampled (see Example this example, 1.27ns 3.589ns worst case conditions. SDRAM Read Cycle Timing-Example
Data TSIN
Stage Data Stage TDIN
High
Data Stage
Clock Read Clock Delayed High Data Stage High Data RDSP with High
Data RDSP without
Data RDSP without
High
Propagation delay from Stage input RDSP input Propagation delay from Stage input RDSP input with
AMCC
440GX Power 440GX Embedded Processor
Revision 1.20 June 2009
Example this example, enabled. This requires that Stage data sampled (3). disabled, system will still work, there will more latency before data sampled into RDSP. Again, 1.27ns 3.589ns worst case conditions. SDRAM Read Cycle Timing-Example
Data TSIN
Stage Data Stage TDIN
High
Data Stage
Clock Read Clock Delayed High Data Stage High Data RDSP with High
Data Stage with
Data RDSP with
High
Propagation delay from Stage input RDSP input Propagation delay from Stage input RDSP input with
AMCC
Revision 1.20 June 2009
Initialization
440GX Power 440GX Embedded Processor
PPC440GX provides option setting initial parameters based default values reading them from slave PROM attached IIC0 (see "Serial EEPROM" below). Some default values altered strapping external pins (see "Strapping" below).
Strapping
While SysReset input (system reset), state certain pins read enable certain default initial conditions prior PPC440GX start-up. actual capture instant nearest SysClk edge before deassertion reset. These pins must strapped using external pull-up (logical (recommended value 3.3V) pull-down (logical (recommended value GND) resistors select desired default conditions. They used strap functions only during reset. Following reset they used normal functions. following table lists strapping pins along with their functions strapping options:
Strapping Assignments
Ball Strapping Function Option (UART0_DCD) (UART0_DSR) (GMC1TxEr)
Serial device disabled. Each four options combination boot source, boot-source width, clock frequency specifications. Refer Bootstrap Controller chapter PPC440GX Embedded Processor User's Manual details.
Serial device enabled. option being selected IIC0 slave address that will respond with strapping data.
0x54 0x50
Serial EEPROM
During reset, initial conditions other than those obtained from strapping pins read from device connected IIC0 port. de-assertion SysReset, bootstrap controller enabled, PPC440GX sequentially reads bytes from device IIC0 port sets SDR0_SDSTP0, SDR0_SDSTP1, SDR0_SDSTP2, SDR0_SDSTP3 registers accordingly. initialization settings their default values covered detail PowerPC 440GX Embedded Processor User's Manual.
AMCC
440GX Power 440GX Embedded Processor
Revision 1.20 June 2009
Revision
Date 08/07/2002 08/30/2002 09/25/2002 10/22/2002 11/20/2002 01/07/2003 revision log. Change EMC0:1TxD0:1 EMC0:1TxEn from Update cache heat sink mounting information. Update timing data. Update PCI-X voltage specification. Correct package drawing Correct description SysReset signal. Update 533MHz parts power supply current values. Update SDRAM timing. Change RTBIxTX control signals data signals. 667MHz part numbers, update specifications, fill missing data points. Update information concerning higher speed parts, clock ratios, duplicate trace signals, initialization strapping pins. Update Ethernet signals with moved signals. Remove Confidential. Revise SDRAM section. Correct TrcTS6 signal data (pin assignment multiplexing). Restore VDD/OVDD voltage sequence restriction. three Revision part numbers. Update part number list. Update dimensions package drawing. Correct GMCTxClk signal description from input-only I/O. plastic package data, power data, update part number list. Upgrade 533MHz ceramic part 105°C rating. Correct dimensions ceramic package drawing. Replace missing 533MHz temperature range part. information minimum SysClk TRST duration during power-on reset. Remove power sequence restrictions note from Absolute Maximum Rating table. Restate power sequencing restrictions Recommended Operating Conditions table. Convert AMCC format. Restore "Preliminary" document classification. cache support) temperature range part numbers. reduced-lead ceramic lead-free plastic part numbers. Clarify SDRAM interface diagram. Remove metal-layer specification from technology description. logo number nomenclature package drawing. Update timing specs EMC0:3TxD, GMC0RxD0:3, GMC1RxD0:3, GMCRxDV, GMC1RxCtl, GMCRxD0:7, GMCRxEr, GMCCrS, GMCTxD0:7. AMCC Contents Modification
01/22/2003
03/25/2003 06/16/2003 07/15/2003 07/17/2003 12/02/2003 01/13/2004 02/12/2004 02/25/2004 03/04/2004 03/25/2004 05/12/2004 05/20/2004 06/15/2004 06/30/2004
11/01/2004
12/09/2004 06/16/2005 07/01/2005 10/17/2005 11/07/2005 12/22/2005
Revision 1.20 June 2009
Date 02/08/2006 04/04/2006 06/09/2006 09/11/2006
440GX Power 440GX Embedded Processor
Contents Modification Correct timing changes made 12/22/05 version. (two 533MHz four 677MHz). Remove shipping 3NF533C 3FF533C) Update clocking specs EEPROM information. four posts plastic package drawing. Reduce maximum temperature rating selected plastic parts. Remove five (end life) Add/change timing data (system SDRAM) 800MHz parts Increase minimum frequency from 300MHz 333MHz. Increase SVDD SDRAM parts operating 200MHz. ceramic 400MHz PNs. leaded other reduced-lead (R). Change values RGMII signals. Change technical support telephone number. Remove power supply power-up sequence requirements. Change package type ceramic PPC440GX-3RF400C (Doc Issue 549). Issue 408. Rename AGND pins according analog voltage with which they associated. Issue 483. RGMII timing waveforms. Issue 595. pull-up pull-down resistor values. Bugzilla Issue 4921. Increase clock minimum frequency specification. Bugzilla Issue 5432. Modified minimum maximum values MemClkOut PLB, OPB, Clocking Specifications table page Added notes Removed part numbers. Added Notes regarding operation 667MHz part 533MHz less higher temperatures (+105C ceramic +100C plastic). Removed 800MHz. Removed 200MHz timing.
09/26/2006
02/23/2007 03/05/2007 08/30/2007 04/03/2008 07/16/2008 09/16/2008 09/22/2008 11/06/2008 12/19/2008
06/09/2009
AMCC
440GX Power 440GX Embedded Processor
Revision 1.20 June 2009
Printed United States America, Thursday, June 2009 following trademarks AMCC United States, other countries, both: AMCC
Other company, product, service names trademarks service marks others.
information contained this document subject change withdrawal time without notice being provided basis without warranty indemnity kind, whether express implied, including without limitation, implied warranties non-infringement, merchantability, fitness particular purpose. products, services, programs discussed this document sold licensed under AMCC's standard terms conditions, copies which obtained from your local AMCC representative. Nothing this document shall operate express implied license indemnity under intellectual property rights AMCC third parties. Without limiting generality foregoing, performance data contained this document determined specific controlled environment submitted formal AMCC test. Therefore, results obtained other operating environments vary significantly. Under circumstances will AMCC liable damages whatsoever arising resulting from document information contained herein.
AMCC
Revision 1.20 June 2009
440GX Power 440GX Embedded Processor
Applied Micro Circuits Corporation Moffett Park Drive, Sunnyvale, 94089 Phone: (408) 542-8600 (800) 840-6055 Fax: (408) 542-8601 http://www.amcc.com
AMCC reserves right make changes products, data sheets, related documentation, without notice warrants products solely pursuant terms conditions sale, only substantially comply with latest available data sheet. Please consult AMCC's Term Conditions Sale warranties other terms, conditions limitations. AMCC discontinue semiconductor product service without notice, advises customers obtain latest version relevant information verify, before placing orders, that information current. AMCC does assume liability arising application product circuit described herein, neither does convey license under patent rights rights others. AMCC reserves right ship devices higher grade place those lower grade. AMCC SEMICONDUCTOR PRODUCTS DESIGNED, INTENDED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT APPLICATIONS, DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. AMCC registered Trademark Applied Micro Circuits Corporation. Copyright 2008 Applied Micro Circuits Corporation.
AMCC
Other recent searches
TMS28F010A - TMS28F010A TMS28F010A Datasheet
PTFA092201E - PTFA092201E PTFA092201E Datasheet
PTFA092201F - PTFA092201F PTFA092201F Datasheet
ML4833 - ML4833 ML4833 Datasheet
M74HCT02 - M74HCT02 M74HCT02 Datasheet
HY5DU56422D - HY5DU56422D HY5DU56422D Datasheet
HY5DU56822D - HY5DU56822D HY5DU56822D Datasheet
HY5DU561622D - HY5DU561622D HY5DU561622D Datasheet
HMU1356H - HMU1356H HMU1356H Datasheet
CRS09 - CRS09 CRS09 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
