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Q-SMINT®O 2B1Q Second Gen. Modular ISDN (Ordinary) 80912/80913 Version
Wired
Edition March 2001 Published Infineon Technologies St.-Martin-Strasse D-81541 Germany
Infineon Technologies 2001.
Rights Reserved. Attention please! information herein given describe certain components shall considered warranted characteristics. Terms delivery rights technical change reserved. hereby disclaim warranties, including limited warranties non-infringement, regarding circuits, descriptions charts stated herein. Infineon Technologies approved CECC manufacturer. Information further information technology, delivery terms conditions prices please contact your nearest Infineon Technologies Office Germany Infineon Technologies Representatives worldwide (see address list). Warnings technical requirements components contain dangerous substances. information types question please contact your nearest Infineon Technologies Office. Infineon Technologies Components only used life-support devices systems with express written approval Infineon Technologies, failure such components reasonably expected cause failure that life-support device system, affect safety effectiveness that device system. Life support devices systems intended implanted human body, support and/or maintain sustain and/or protect human life. they fail, reasonable assume that health user other persons endangered.
Q-SMINT®O 2B1Q Second Gen. Modular ISDN (Ordinary) 80912/80913 Version
Wired
80912/80913 Revision History: Previous Version: Page
March 2001 Preliminary Data Sheet 10.00
Subjects (major changes since last revision)
Editorial changes, addition notes clarification etc.
Table introduced version 80913 with extended performance U-interface Chapter Chapter 2.4.5.1 S-transceiver state machine: added note setting Test Mode pins TM0-2 '010' '011': Continuous Pulses Single Pulses, S-transceiver starts sending corresponding test signal, state transition invoked.' commands: removed 'unconditional command' from description C/I-command 'DR' Corrected figure: 'Complete Activation Initiated Exchange': info4 sent (not byTE)
Chapter 2.4.5.1 Figure
Chapter Absolute Maximum Ratings: Maximum Voltage VDD: 4.2V (before: 4.6V) Chapter Refined references requirements:' .(CDM), EIA/JESD22-A114B (HBM) Chapter Input/output leakage current 10µA (before: 1µA) Table Chapter 4.6.3 U-transceiver characteristics: enhanced S/N+D 80913 threshold level 80912 80913 distinguished Parameters UVD/POR Circuit: defined reduced range hysteresis: min. 30mV/max. 90mV relaxed upper limit Detection Threshold 2.92V (before: 2.9V) defined max. rising power-on
Chapter External circuitry T-SMINT updated
questions technology, delivery prices please contact Infineon Technologies Offices Germany Infineon Technologies Companies Representatives worldwide: webpage http://www.infineon.com
80912/80913
Table Contents 1.7.1 2.2.1 2.3.1 2.3.2 2.3.3 2.3.4 2.3.5 2.3.5.1 2.3.5.2 2.3.5.3 2.3.5.4 2.3.5.5 2.3.6 2.4.1 2.4.2 2.4.3 2.4.4 2.4.5 2.4.5.1 3.1.1 3.1.2 3.1.3 3.1.4 3.1.5 3.1.6
Page
Overview References Features 80912 Features 80913 Supported Configuration Block Diagram Definitions Functions Specific Pins System Integration Functional Description Reset Generation IOM-2 Interface IOM,-2 Functional Description U-Transceiver 2B1Q Frame Structure Cyclic Redundancy Check FEBE Scrambling/ Descrambling Codes State Machine Line Activation Deactivation Notation Standard State Machine (IEC-Q NTC-Q Compatible) Inputs U-Transceiver: Outputs U-Transceiver: Description NT-States Metallic Loop Termination S-Transceiver Line Coding, Frame Structure Channels, Multiframing Data Transfer between IOM,-2 Loopback State Machine State Machine Mode Operational Description Layer Activation/Deactivation Complete Activation Initiated Exchange Complete Activation Initiated Complete Deactivation Partial Activation Activation from Exchange with Active Activation from with Active
Data Sheet
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Table Contents 3.1.7 3.1.8 3.2.1 3.2.1.1 3.2.1.2 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 4.6.1 4.6.2 4.6.3 6.2.1 6.2.2 6.2.3
Page
Partial Deactivation with Active Loop Layer Loopbacks Loopback No.2 Complete Loopback Loopback No.2 Single Channel Loopbacks External Circuitry Power Supply Blocking Recommendation U-Transceiver S-Transceiver Oscillator Circuitry General Electrical Characteristics Absolute Maximum Ratings Characteristics Capacitances Power Consumption Supply Voltages Characteristics IOM-2 Interface Reset Undervoltage Detection Characteristics
Package Outlines Appendix: Differences between T-SMINT,O Pinning U-Transceiver U-Interface Conformity U-Transceiver State Machines Command/Indication Codes External Circuitry
Index
Data Sheet
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List Figures Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure
Page
Configuration Block Diagram Application Example Q-SMINT,O: Standard IOM-2 Frame Structure Q-SMINT,O U-Superframe Structure U-Basic Frame Structure U2B1Q Framer Data Flow Scheme U2B1Q Deframer Data Flow Scheme Explanation State Diagram Notation Standard State Machine (IEC-Q NTC-Q Compatible) (Footnotes: "Dependence Outputs" Page Pulse Streams Selecting Quiet Mode -Interface Line Code Frame Structure Reference Points (ITU I.430). State Diagram Notation State Machine Mode Complete Activation Initiated Exchange Complete Activation Initiated Complete Deactivation Initiated Exchange Partial Activation Activation from with Active Activation from with Active Partial Deactivation with Active Loop Test Loopbacks Power Supply Blocking External Circuitry U-Transceiver External Circuitry S-Interface Transmitter External Circuitry S-Interface Receiver Crystal Oscillator Maximum Sinusoidal Ripple Supply Voltage Input/Output Waveform Tests IOM®-2 Interface Synchronization Timing IOM-2 Interface Frame Synchronization Timing Reset Input Signal Undervoltage Control Timing NTC-Q Compatible State Machine Q-SMINT,O: 2B1Q IEC-T/NTC-T Compatible State Machine T-SMINT,O: 4B3T External Circuitry T-SMINT,O
Data Sheet
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List Tables Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table
Page
Products Generation Definitions Functions States. LP2I States Test Modes U-Superframe Format Transceiver Codes Timers Used. U-Interface Signals States with Operational Data IOM,-2 Signal Output C/I-Code Output ANSI Maintenance Controller States U-Transformer Parameters S-Transformer Parameters Crystal Parameters Maximum Input Currents S-Transceiver Characteristics U-Transceiver Characteristics Capacitances Reset Input Signal Characteristics Parameters UVD/POR Circuit Definitions Functions Related Documents U-Interface. Codes Dimensions External Components.
Data Sheet
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Overview
Overview
80912 80913 (Q-SMINT®O) offers features known from 8091 [11] hence replace latter applications. Table summarizes generation products.
Table
Products Generation PEF80912 PEF80913 PEF81912 PEF81913 PEF82912 PEF82913 Q-SMINT®O Q-SMINT®IX P-MQFP-64 P-TQFP-64 U+S+HDLC+ IOM-2 parallel IOM-2) Q-SMINT®I P-MQFP-64 P-TQFP-64 U+S+ IOM-2 parallel IOM-2)
Package Register access Access MCLK, watchdog timer, SDS, BCL, Dchannel arbitration, IOM-2 access manipulation etc. provided HDLC controller mode available Extended UPerformance 20kft
P-MQFP-44 n.a.
(only)
Data Sheet
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Overview
References
080, Transmission Multiplexing ISDN basic rate access; Digital transmission system metallic local lines, ETSI, November 1998 T1.601-1998 (Revision ANSI T1.601-1992), ISDN-Basic Access Interface Metallic Loops Application Network Side (Layer Specification), ANSI, 1998 ST/LAA/ELR/DNP/822, CNET, France RC7355E, 2B1Q Generic Physical Layer Specification, British Telecommunications plc., 1997 0095/01:1997-10, Technische Spezifikationen ISDN (NT-BA), Post Telekom Austria, 1997 Draft, ISDN; Basic User Network Interface (UNI), ETSI, November 1996 T1.605-1991, ISDN-Basic Access Interface Reference Points (Layer Specification), ANSI, 1991 I.430, ISDN User-Network Interfaces: Layer Recommendations, ITU, November 1988 IEC-Q, ISDN Echocancellation Circuit, 2091 V4.3, User's Manual 02.95, Siemens 1995 SBCX, Interface Circuit Extended, 2081 V3.4, User's Manual 11.96, Siemens 1996 NTC-Q, Network Termination Controller (2B1Q), 8091 V1.1, Data Sheet 10.97, Siemens 1997 INTC-Q, Intelligent Network Termination Controller (2B1Q), 8191 V1.1, Data Sheet 10.97, Siemens 1997 IOM-2 Interface Reference Guide, Siemens 03.91 SCOUT-S(X), Siemens Codec with S/T-Transceiver, 2138x V1.3, Preliminary Data Sheet 8.99, Infineon Technologies, 1999 PITA, Interface Telephony/Data Applications V0.3, SICAN GmbH, September 1997 Dual Channel SLICOFI-2, HV-SLIC; DUSLIC; PEB3265, 4265, 4266; Data Sheet DS2, Infineon Technologies, July 2000.
[10] [11] [12] [13] [14] [15] [16]
Data Sheet
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Overview
2B1Q Second Gen. Modular ISDN (Ordinary) Q-SMINT®O
80912/80913
Version
Features 80912
Features known from 8091 Single chip solution including S-transceiver Perfectly suited ISDN Fully automatic activation deactivation P-MQFP-44-2 U-interface (2B1Q) conform ETSI [1], ANSI CNET [3]: P-MQFT-44 Meets transmission requirements ETSI, ANSI CNET loops with margin Conform British Telecom's RC7355E Compliant with ETSI micro interruptions input decode logic (ANSI [2]) S/T-interface conform ETSI [6], ANSI Supports point-to-point configurations Meets exceeds transmission requirements programmable CSO-bit Optional IOM-2 interface eases chip testing evaluation Activation status supported
Type 80912/80913
Data Sheet
Package P-MQFT-44
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Overview
Features Reduced number external components external U-hybrid required Optional 2x20 resistors line side transformer (e.g. PTCs) Uref according external capacitor removed Improved instead <850 Inputs accept (open drain) accepts pull-up compatible with T-SMINT®O (2nd Generation) indicates Loopback (LBBD) Power-on reset Undervoltage Detection with external components Lowest power consumption power CMOS technology (0.35µ) Newly optimized power libraries High output swing S-line interface leads minimized power consumption Single Volt power supply (NTC-Q: power consumption with random data over ETSI Loop typical power consumption power down (NTC-Q:
Features 80913
Q-SMINT®O 80913 provides features 80912. Additionally, significantly enhanced performance U-interface compared ETSI [1], ANSI CNET requirements guaranteed: Transparent transmission 20kft AWG26 with 10-7 (without noise).
Pull-ups must avoided. so-called 'hot-electron-effect' would lead long term degradation.
Data Sheet
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Overview
Supported
Integrated U-hybrid 'NT-Star' with star point IOM®-2 (already supported NTC-Q). oscillator architecture changed with respect NTC-Q reduce power consumption. consequence, Q-SMINT®O always needs crystal connected external clock possible IEC-Q NTC-Q. This does limit Q-SMINT®O since designs crystals anyway.
Configuration
VDDa_SX VSSa_SX
/LP2I
/VDDDET VDDa_SR VSSa_SR XOUT BOUT VDDa_UX VSSa_UX AOUT
VSSD VDDD /ACT
Q-SMINTO 80912 80913
/RSTO
VDDD
VSSa_UR VDDa_UR
VSSD /TLL
/RST
pin_2.vsd
Figure
Data Sheet
Configuration
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Overview
Block Diagram
XOUT
VDDDET
RSTO
Clock Generation
POR/UVD
AOUT BOUT
S-Transceiver U-Tansceiver
Factory Test Test Modes
LP2I
IOM-2 Interface
Transceiver Control
block diagram.vsd
Figure
Block Diagram
Data Sheet
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Overview
Definitions Functions
Definitions Functions Symbol
VDDa_UR
Table
Type
Function Supply voltage U-Receiver (3.3 Analog ground U-Receiver Supply voltage U-Transmitter (3.3 Analog ground U-Transmitter Supply voltage S-Receiver (3.3 Analog ground S-Receiver Supply voltage S-Transmitter (3.3 Analog ground S-Transmitter Supply voltage digital circuits (3.3 Ground digital circuits Supply voltage digital circuits (3.3 Ground digital circuits Frame Sync: 8-kHz frame synchronization signal Data Clock: IOM-2 interface clock signal (double clock): Loopback indication: directly drive mA). LBBD received, Loopback closed Loopback closed. Data Downstream: Data IOM-2 interface Data Upstream: Data IOM-2 interface
VSSa_UR VDDa_UX
VSSa_UX VDDa_SR
VSSa_SR VDDa_SX
VSSa_SX VDDD
VSSD VDDD
VSSD
LP2I
Data Sheet
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Overview Table Definitions Functions (cont'd) Symbol Type Function Disable IOM-2: FSC, DCL, high FSC, DCL, push-pull Auto Activation: U-transceiver attempts automatic activation after reset. applications that require auto-start after reset. Cold Start Only: selects CSO-bit '0'. (normal) selects CSO-bit '1'. (special cases) only controls CSO-bit Uframe. U-transceiver itself always warm-start transceiver according ANSI ETSI. mode S-interface: passive S-bus (fixed timing) point-to-point extended passive S-bus (adaptive timing) Reset: active reset input. Schmitt-Trigger input with hysteresis typical used. Reset Output: active reset output. Triple-Last-Look Select validation algorithm received towards state machine: '0': '1': Test Mode Selects test pattern (see Page 11). Test Mode Selects test pattern (see Page 11). Test Mode Selects test pattern (see Page 11).
(PU)
RSTO
Data Sheet
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Overview Table Definitions Functions (cont'd) Symbol XOUT Type Function S-Bus Transmitter Output (positive) S-Bus Transmitter Output (negative) S-Bus Receiver Input S-Bus Receiver Input Crystal Connected 15.36 crystal Crystal Connected 15.36 crystal Differential U-interface Output Differential U-interface Output Differential U-interface Input Differential U-interface Input Detection: This selects detection active ('0') reset pulses generated RSTO whether deactivated ('1') external reset applied RST. Metallic Termination Input. Input evaluate Metallic Termination pulses. used. Power Status (primary). status passed overhead 'PS1' frame indicate status primary power supply ('1' ok). Power Status (secondary). status passed overhead 'PS2' frame indicate status secondary power supply ('1' ok).
AOUT BOUT
VDDDET
Data Sheet
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Overview Table Definitions Functions (cont'd) Symbol Type Function Activation LED. Indicates activation status Stransceiver. directly drive mA). Test Used factory device test. Test Used factory device test.
Internal pull-up resistor (typ. Input Output (Push-Pull) Output (Open Drain)
1.7.1
Specific Pins
Pins ACT, LP2I connected display four different states (off, slow flashing, fast flashing, on). displays activation status S-transceiver according Table with: Table States U_Deactivated U_Activated S_Activated
U_Deactivated: 'Deactivated State' defined Chapter 2.3.5.5. U_Activated: 'Synchronized 'Synchronized 'Wait ACT', 'Transparent', 'Error 'Pend. Deact. S/T', 'Pend. Deact. defined Chapter 2.3.5.5. S-Activated: 'Activated State' defined Chapter 2.4.5.
Data Sheet
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Overview Note: Optionally, drive second with inverse polarity (connect this additional only). Another connected LP2I indicate active Loopback according Table Table LP2I LP2I States EOC-Command LBBD received EOC-LBBD received after LBBD command. EOC-command LBBD (50) been received. Complete analog loop being closed S-interface.
Test Modes Different test patterns S-interface generated pins TM0-2 according Table Table
Test Modes Data Through3) Send Single Pulses4) Quiet Mode5) normal operation U-transceiver S-transceiver Reserved future use. Normal operation this version. Normal operation kHz1) Continuous Pulses kHz2) Single Pulses Normal operation
S-transceiver transmits pulses with alternating polarity rate resulting envelope. S-transceiver transmits pulses with alternating polarity rate resulting envelope. Forces U-transceiver into state 'Transparent' where transmits signal SN3T. Forces U-transceiver into state 'Test' send single pulses. pulses issued intervals have duration 12.5 U-transceiver hardware reset.
Data Sheet
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Overview
System Integration
Q-SMINTO provides functionality without microcontroller being necessary. Special selections done strapping (CSO, TLL, BUS, etc.). device interface. IOM-2 Interface serves only monitoring debugging purposes. regarded window internal IOM-2.
DC/DC-Converter IDCC PEB2023
Interface
Q-SMINTO PEF80912 80913
Interface
IOM-2
LEDs
Strap Mode Selection
Loop Ind. Disable Selection Activation Validation Algorithm Status Polarity Activation after Reset Test Pattern Selection
NT1_appl.vsd
Figure
Application Example Q-SMINTO: Standard
Data Sheet
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Functional Description
Functional Description
Reset Generation
External Reset Input input external reset applied forcing Q-SMINTO reset state. This external reset signal additionally RSTO output. Reset Ouput VDDDET active, then deactivation reset output RSTO delayed tDEACT (see Table 22). Reset Generation Q-SMINTO on-chip reset generator based Power-On Reset (POR) Under Voltage Detection (UVD) circuit (see Table 22). POR/UVD requires external components. POR/UVD circuit disabled VDDDET. requirements ramp-up during power-on reset described Chapter 4.6.3. Clocks Data Lines During Reset During reset data clock (DCL) frame synchronization (FSC) keep running. During reset high; with exception output code from U-Transceiver 'DR' 0000 output code from S-Transceiver 'TIM' 0000.
Data Sheet
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Functional Description
IOM-2 Interface
IOM-2 interface always operates mode according IOM-2 Reference Guide [13].
2.2.1
IOM-2 Functional Description
IOM-2 interface consists four lines: FSC, DCL, rising edge indicates start IOM-2 frame. clock signal synchronizes data transfer both data lines twice rate. bits shifted with rising edge first clock cycle. Note: possible write data IOM-2 into Q-SMINTO. IOM-2 interface enabled/disabled with DIO. signal frame sync signal. number timeslots transmit line determined frequency clock, with clock channel consisting timeslots available. IOM®-2 Frame Structure Q-SMINTO frame structure IOM-2 data ports (DU,DD) Q-SMINTO with clock shown Figure
Figure
IOM-2 Frame Structure Q-SMINTO
frame composed channel: Channel contains 144-kbit/s user signaling data MONITOR programming channel (not available Q-SMINTO) command/indication channel (CI0) control e.g. U-transceiver.
Data Sheet
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Functional Description
U-Transceiver
state machine U-Transceiver based state machine 8091 documentation [11]. Basic configurations selected strapping.
2.3.1
2B1Q Frame Structure
Transmission U2B1Q-interface performed rate kbaud. code used reducing bits quaternary symbol (2B1Q). Data grouped together into U-superframes each. Each superframe consists eight basic frames which begin with synchronization word contain bits information. first basic frame superframe starts with inverted synchword (ISW) compared other basic frames (SW). structure U-superframe illustrated Figure Figure Basic Frame Basic Frame Basic Frame
<-12 ms-> Figure
U-Superframe Structure User Data Bits (108 Quat)
(Inverted) Synch Word Quat) <-1,5 ms-> Figure
Maintenance Data Bits Quat)
U-Basic Frame Structure
information bits contain data from IOM®-frames, remaining bits used transmit maintenance information. Thus maintenance bits available U-superframe. They used transmit EOC-messages bit), Maintenance (overhead) bits checksum bit).
Data Sheet
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Functional Description
Table
U-Superframe Format Framing Quat Position Position Overhead Bits
Super Basic Sync Frame Frame Word 2,3.
ACT/ SCO/
FEBE
CRC1 CRC2
NCRC3 CRC4 CRC5 CRC6 CRC7 CRC8 CRC9
dir.
Inverted Synchronization Word (quad): Synchronization Word (quad): Cyclic Redundancy Check Embedded Operation Channel Activation
dir.
-3-3+3+3+3-3+3-3-3 +3+3-3-3-3+3-3+3+3 address data message information (data message) Layer ready communication 2001-03-29
Data Sheet
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Functional Description
FEBE NAIB Deactivation Cold Start Only U-Only Activation S-Activity Indicator Far-end Block Error FEBE Power Status Primary Source Power Status Secondary Source NT-Test Mode NAlarm Indication Network Indication Start Command only (currently defined ANSI/ETSI) informs that will turn NT-activation with cold start only U-only activated S-interface deactivated Far-end block error occurred Primary power supply Secondary power supply busy test mode Interruption (according ANSI) function (reserved network use)
accessed system interface proprietary principle signal flow depicted Figure Figure data first grouped bits that covered bits that not. After generation bits arranged proper sequence according 2B1Q frame format, encoded finally transmitted. receive direction data first decoded, descrambled, deframed handed over further processing.
Tone/Pulse Patterns
(M-bit handling acc. ETR080)
U2B1Q-Fram
nc/Inv.
M1,2,3 (EOC) 2B+D,
2B1Q Encoding
Scrambler
M5,6 except Generation 2B+D
Control
uframer.emf
Figure
U2B1Q Framer Data Flow Scheme
Data Sheet
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Functional Description
(M-bit handling acc. ETR080) M5,6 except
U2B1Q-Deframer
M1,2,3 (EOC)
2B1Q Decoding
Check
Descrambler
Sync/Inv. Sync
2B+D
Control
udeframer.emf
Figure
U2B1Q Deframer Data Flow Scheme
2.3.2
Cyclic Redundancy Check FEBE
error monitoring function implemented covering data transmission U-superframe Cyclic Redundancy Check (CRC). computed polynomial
modulo addition)
check digits (CRC bits CRC1, CRC2, CRC12) generated transmitted U-superframe. receiver will compute received data compare with received CRC-bits generated transmitter. CRC-error will indicated both sides U-interface, NEBE (Near-end Block Error) side where error detected, FEBE (Far-end Block Error) remote side. FEBE-bit will placed next available U-superframe transmitted originator.
2.3.3
Scrambling/ Descrambling
scrambling algorithm ensures that sequences permanent binary transmitted. scrambling descrambling process controlled fully QSMINTO. Hence, influence taken user.
Data Sheet
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Functional Description
2.3.4
Codes
operational status U-transceiver controlled Control/Indicate channel (C/I-channel). Table presents defined codes. indication issued permanently U-transceiver until indication needs forwarded. Because number states issue identical indications possible identify every state individually.
Table Code 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Transceiver Codes
Activation Indication AIL: Activation Indication Loop Activation Request ARL: Activation Request Local Loop Deactivation Confirmation Deactivation Indication Deactivation Request
Data Sheet 2001-03-29
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Functional Description Data Through test mode EI1: Error Indication Power-Up RES: Reset SSP: Send Single Pulses test mode TIM: Timing request
2.3.5 2.3.5.1
State Machine Line Activation Deactivation Notation
state machines control sequence signals U-interface that generated during start-up procedure. informations contained following state diagrams are:
State name U-signal transmitted Overhead bits transmitted C/I-code transmitted Transition criteria Timers
Figure shows interpret state diagrams.
Signal Transmitted U-Interface (general) State Name
Single Transmitted U-Interface
Indication Transmitted C/I-Channel (DOUT)
ITD04257.vsd
Figure
Explanation State Diagram Notation
Combinations transition criteria possible. Logical "AND" indicated DC), logical "OR" written "or" negation used. start timer indicated with "TxS" ("x" being equivalent timer number). Timers always started when entering state. action resulting after timer expired indicated path labelled "TxE".
Data Sheet 2001-03-29
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Functional Description
2.3.5.2
Standard State Machine (IEC-Q NTC-Q Compatible)
T14S
T14E T14S
Pending Timing
State C/I= 'SSP' T14S
Deactivated
Test
Awaked
Reset State Pin-RST C/I= 'RES'
NT-AUTO
T1S, T11S
Alerting
T12S T11S
Alerting
T11E T12S
T1S, T11S
T11E T12S
EC-Training
LSEC T12E LSUE
EC-Training
EC-Training
LSEC T12E
act=0 Wait
BBD1
BBD0
EQ-Training
T20S
SN3T act=0 Analog Loop Back
LSUE
T20E BBD0
Wait
SN3/SN3T act=1/0 Pend.Deact.
LSUE
dea=0
SN3/SN3T act=0 Synchronized
uoa=1
dea=0 LSUE uoa=0 dea=0 LSUE
SN3/SN3T act=0 Synchronized AR/ARL
SN3/SN3T act=1 Wait AR/ARL
act=1 act=0
uoa=0 dea=0 LSUE
State C/I='DT'
act=1 SN3T Transparent AI/AIL
act=1
uoa=0 dea=0 LSUE
SN3/SN3T act=0 Error act=0 AR/ARL
dea=0 uoa=0 LSUE
uoa=1
dea=1
Pend Receive Res. T13S
/LOF T13E
SN3/SN3T act=1/0 Pend.Deact.
Receive Reset
Figure
Standard State Machine (IEC-Q NTC-Q Compatible) (Footnotes: "Dependence Outputs" Page
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Data Sheet
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Functional Description Note: test modes 'Data Through` (DT), `Send Single Pulses` (SSP) `Quiet Mode` (QM) generated pins TM0-2 according Table Metallic Loop Termination used, then U-transceiver forced into states `Reset` `Transparent` valid pulse streams according Table
2.3.5.3
Inputs U-Transceiver:
Activation Indication downstream device issues this indication announce that layer-1 available. U-transceiver informs side setting "ACT" "1". Activation Request U-transceiver requested start activation process sending wakeup signal Activation Request Local Loop-back U-transceiver requested operate analog loop-back (close Uinterface) begin start-up sequence sending (without starting timer T1). This command issued only after U-transceiver been SWreset. This eases that EQ-coefficient updating algorithms converge correctly. ARL-command issued continuously long loop-back required. Deactivation Indication This indication used during deactivation procedure inform U-transceiver that enter deactivated (power-down) state. Data Through This unconditional command used test purposes only forces Utransceiver into "Transparent" state. Error Indication downstream device indicates error condition (loss frame alignment loss incoming signal). U-transceiver informs LT-side setting ACT-bit thus indicating that transparency been lost. Reset Unconditional command which resets U-transceiver. Send Single Pulses Unconditional command which requests transmission single pulses U-interface. Timing U-transceiver requested enter state 'IOM-2 Awaked'.
C/I-Commands:
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Functional Description U-Interface Events:
ACT-bit received from LT-side. requests U-transceiver transmit transparently both directions. case loop-backs, however, transparency both directions transmission established when receiver synchronized. indicates that layer-2 functionality available. DEA-bit received from LT-side informs U-transceiver that deactivation procedure been started LT-side. reflects case when detected faults e.g. transmission errors allows U-transceiver recover from this situation. UOA-bit received from network side informs U-transceiver that only U-interface activated. S/T-interface must deactivated. requests S/T-interface present) activate.
Timers start timers indicated TxS, expiry TxE. Table shows which timers used:
Table Timer
Timers Used Duration (ms) 15000 5500 15000 Function Supervisor start-up Hold time TN-transmission Supervisor EC-converge Frame synchronization Hold time Hold time Receive reset Alerting EC-training Pend. receive reset Pend. timing Wait State
Data Sheet
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Functional Description
2.3.5.4
Outputs U-Transceiver:
following signals indications issued IOM®-2 (C/I-indications) U-interface (predefined U-signals): C/I-Indications
Activation Indication U-transceiver established transparency transmission. downstream device requested establish layer-1 functionality. Activation Indication Loopback U-transceiver established transparency transmission. downstream device requested establish loopback Activation Request downstream device requested start activation procedure. Activation Request Loop-back U-transceiver detected loop-back command EOC-channel established transparency transmission direction IOM®-2 U-interface. downstream device requested start activation procedure establish loopback Deactivation Confirmation Idle code IOM®-2-interface. Deactivation Request U-transceiver detected deactivation request command from LT-side complete deactivation only deactivation. downstream device requested start deactivation procedure. Error Indication U-transceiver entered failure condition caused loss framing U-interface expiry timer
Signals U-Interface signals SNx, transmitted U-interface defined Table
Table Signal
Data Sheet
U-Interface Signals Synch. Word (SW) signal present present present Superframe (ISW) signal absent absent present
signal
M-Bits signal normal
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Functional Description Table Signal SN3T Test Mode SP2) Note: Note:
U-Interface Signals(cont'd) Synch. Word (SW) present test signal Superframe (ISW) present test signal normal test signal M-Bits normal test signal
Alternating symbols kHz. series single pulses spaced intervals alternating +/-3.
Input Signals State Machine related U-Signals table below summarizes input signals that control state machine that extracted from U-interface signal sequences.
LSEC
Loss framing This condition fulfilled framing lost Loss signal behind echo canceller Internal Signal which indicates that echo canceller converged Loss Signal U-Interface This signal indicates that loss signal level duration been detected U-interface. This short response time relevant cases where waits response signal level) from LTside. Loss Signal U-Interface Error condition After loss signal been noticed, timer started. When elapsed LSUE-criterion fulfilled. This long response time (see also LSU) valid cases where prepared lose signal level i.e. stopped transmission because loss framing, unsuccessful activation, transmission line interrupted. Frame Detected Super Frame Detected
LSUE
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Functional Description BBD0 BBD1 BBD0/1 Detected These signals either (BBD1) (BBD0) were detected subsequent basic frames. used criterion that receiver acquired frame synchronization both EQ-coefficients have converged. BBD0 corresponds received signal case normal activation, BBD1 corresponds internally received signal case analog loop back. Awake tone detected U-transceiver requested start activation procedure.
Signals IOM-2 Data (B+B+D) '1's states besides states listed Table
Table
States with Operational Data IOM-2
Synchronized1 Synchronized2 Wait Transparent Error Pend. Deac. Pend. Deac. Analog Loop Back Dependence Outputs Outputs denoted with Figure Signal output depends received command history state machine according Table
Table
Signal Output History State Machine influence Signal output SN3T
Command received 'LBBD'
received 'LBBD' 'RTN' state 'Transparent' been after 'LBBD' reached previously during this activation procedure state 'Transparent' been reached previously during this activation procedure
Data Sheet
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Functional Description Outputs denoted with Figure C/I-code output depends received EOC-command 'LBBD' according Table
Table
C/I-Code Output Synchroni Wait Transparent Error
Command received 'LBBD' 'RTN' after 'LBBD' received 'LBBD'
Outputs denoted with Figure States 'Pend. Deact. S/T' 'Pend. Deact. ACT-bit output depends value previous state. value issued SAI-bit depends received C/I-code: lead other C/I-code sets SAI-bit indicating activity downstream device. state Alerting entered from state Deactivated, then C/I-code 'PU' issued, else C/I-code 'DC' issued.
2.3.5.5
Description NT-States
following states used: Alerting wake-up signal transmitted period either response received wake-up signal start activation procedure LT-side. Alerting "Alerting state entered when wake-up tone received "Receive Reset" state deactivation procedure NT-side finished. transmission wake-up tone started. Analog Loop-Back Transparency achieved both directions transmission. This state left making unconditional command. Deactivated Only state Deactivated device enter power-down mode.
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Functional Description Training signal transmitted U-interface allow NT-receiver update EC-coefficients. automatic gain control (AGC), timing recovery updating algorithm disabled. EC-Training "EC-Training state entered transmission signal started deactivation procedure NT-side finished. EC-Training signal transmitted U-interface allow NT-receiver update EC-coefficients. automatic gain control (AGC), timing recovery updating algorithm disabled. EQ-Training receiver waits signal able update AGC, recover timing phase, detect synch-word (SW), update EQ-coefficients. Error downstream device error condition (EI1). LT-side informed setting ACT-bit (loss transparency NT-side). IOM-2-Awaked U-transceiver deactivated, enter power-down mode. Pending Deactivation U-transceiver received UOA-bit zero after complete activation T-interface. U-transceiver requests downstream device deactivate issuing Pending Deactivation U-Interface U-transceiver waits receive signal level turned (LSU) start deactivation procedure. Pending Receive Reset "Pending Receive Reset" state entered upon detection loss framing U-interface expiry timer This failure condition signalled LT-side turning transmit level (SN0). U-transceiver then waits response signal level LSU) from LT-side.
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Functional Description Pending Timing NT-mode pending timing state assures that C/I-channel code issued four times before entering 'Deactivated' state. Receive Reset state 'Receive Reset' reset Uk0-receiver performed, except case that state 'Receive Reset' entered from state 'Pend. Deact. Timer assures that activation procedure started from NT-side minimum period time This gives chance activate Reset state 'Reset' software-reset performed. Synchronized State 'Synchronized fully active state U-transceiver, while downstream device deactivated. Synchronized this state U-transceiver received This request activate downstream device. Test test signal issued long TM2-0 '101' further details Table Transparent This state entered upon detection received from LT-side corresponds fully active state. Wait Upon receipt waits response (ACT from LT-side. Wait signal sent U-interface receiver waits detection superframe. Wait This state entered case analog loop-back allows receiver update AGC, recover timing phase, update EQ-coefficients.
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Functional Description
2.3.6
Metallic Loop Termination
North American applications maintenance controller according ANSI T1.601 section implemented. maintenance pulse stream from U-interface Metallic Loop Termination circuit (MLT) MTI, usually optocoupler. digitally filtered decoded independently polarity maintenance controller according Table Therefore, maintenance controller capable detecting signaling format. Q-SMINTO automatically sets Utransceiver proper state issues interrupt. state selected indicated bits. Q-SMINTO reacts valid pulse stream independently current Utransceiver state. This includes power-down state. test mode valid seconds. during seconds valid pulse sequence detected timer starts again. After expiry timer maintenance controller goes back normal operation.
Table
ANSI Maintenance Controller States ANSI maintenance controller state ignored Quiet Mode ignored U-transceiver State Machine impact transition state 'Reset' start timer impact
Number counted pulses
Insertion Loss Measurement transition state 'Transparent' start timer ignored normal operation ignored impact transition state 'Reset' impact
Figure shows examples pulse streams with inverse polarity selecting Quiet Mode.
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Functional Description
tHIGH tLOW
tLOW tHIGH
mlt.vsd
Figure
Pulse Streams Selecting Quiet Mode
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Functional Description
S-Transceiver
S-Transceiver offers state machine described User's Manual V3.4 [10]. S-transceiver basic configurations performed strapping.
2.4.1
Line Coding, Frame Structure
Line Coding following figure illustrates line code. binary represented line signal. Binary ZEROs coded with alternating positive negative pulses with exceptions: required frame structure code violation indicated consecutive pulses same polarity. These pulses adjacent separated binary ONEs. configurations binary ZERO always overwrites binary ONE.
code violation
Figure
-Interface Line Code
Frame Structure Each frame consists bits nominal rate kbit/s. user data (B1+B2+D) frame structure applies data rate kbit/s (see Figure 12). direction frame transmitted with offset. details framing rules please refer I.430 section 6.3. following figure illustrates standard frame structure both directions with framing maintenance bits.
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Functional Description
Figure
Frame Structure Reference Points (ITU I.430) Framing D.C. Balancing D-Channel Data D-Channel Echo Auxiliary Framing B1-Channel Data B2-Channel Data Activation S-Channel Data Multiframing (0b) identifies frame (always positive pulse, always code violation) (0b) number binary ZEROs sent after last Signaling data specified user received E-bit equal transmitted D-bit section I.430 User data User data (0b) INFO transmitted (1b) INFO transmitted channel data (see note below) (1b) Start multi-frame
Note: I.430 standard specifies optional use.
2.4.2
Channels, Multiframing
channels supported.
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Functional Description
2.4.3
Data Transfer between IOM-2
state (Activated) bits transferred transparently from IOM-2 interface vice versa. other states '1's transmitted IOM-2 interface.
2.4.4
Loopback
commands close analog loop close S-interface possible. ETSI refers this loop under 'loopback ETSI requires, that channels have same propagation delay when being looped back. D-channel Echo bin. during analog loopback (i.e. loopback loop transparent. Note: After C/I-code been recognized S-transceiver, zeros looped back D-channels (DU) four frames.
2.4.5
State Machine
state diagram notation given Figure information contained state diagrams are: state name Signal received from line interface (INFO) Signal transmitted line interface (INFO) code received (commands) code transmitted (indications) transition criteria
transition criteria grouped into: commands Signals received from line interface (INFOs) Reset
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Functional Description
IOM-2 Interface code
Ind. Cmd.
Unconditional Transition
Interface INFO
macro_17.vsd
Figure
State Diagram Notation
seen from transition criteria, combinations multiple conditions possible well. stands logical combination. indicates logical combination. Test Signals Single Pulses (TM1) pulse with width period frame with alternating polarity. Continuous Pulses (TM2) Continuous pulses with pulse width period. Note: test signals generated pins TM0-2 according Table Reset States After active signal reset S-transceiver state machine reset state. Codes Reset State reset state code 0000 (TIM) issued. This state entered after hardware reset (RST). Codes Deactivated State S-transceiver state `Deactivated` receives code 0000 (TIM) issued until expiration timer. Otherwise, code 1111 (DI) issued.
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Functional Description Receive Infos INFO detected Level detected (signal different INFO detected INFO other than INFO
Transmit Infos INFO INFO INFO Send Single Pulses (TM1). Send Continuous Pulses (TM2).
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Functional Description
2.4.5.1
State Machine Mode
Reset State ARD1) ARD1)
Test Mode State
Pend. Deact. (i0*16ms)+32ms
Wait
Deactivated ARD1) (i0*8ms)
Detected ARD1)
Pend. Lost Framing Lost Framing ARD1) AID2) i3*ARD i3*ARD1) i3*AID2) AID2) i3*AID2) ARD1)
Wait
Activated
statem_nt_s.vsd
Figure
State Machine Mode
Note: setting Test Mode pins TM0-2 '010' '011': Continuous Pulses Single Pulses, S-transceiver starts sending corresponding test signal, state transition invoked.
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Functional Description Deactivated S-transceiver transmitting. There signal detected S/T-interface, activation command received channel. Activation possible from interface from IOM-2 interface. Detected INFO detected S/T-interface, translated "Activation Request" indication channel. S-transceiver waiting command, which normally indicates that transmission line upstream synchronized. Pending Activation result command, INFO sent S/T-interface. INFO received. case command, loop closed. wait INFO received, INFO continues transmitted while S-transceiver waits "switch-through" command from device upstream. Activated INFO sent S/T-interface result "switch through" command AID: D-channels transparent. command AIL, loop closed. Lost Framing This state reached when transceiver lost synchronism state activated. Lost Framing receiving command which usually indicates that synchronization been lost transmission line, S-transceiver transmits INFO Pending Deactivation This state triggered deactivation request unstable state. Indication (state wait DR") issued transceiver when: either INFO0 received duration internal timer expires.
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Functional Description wait Final state after deactivation request. S-transceiver remains this state until issued. Unconditional States Test Mode Send Single Pulses Test Mode Send Continuous Pulses Commands
Command Deactivation Request Reset
Abbr.
Code 0000 0001
Remark Deactivation Request. Initiates complete deactivation transmitting INFO Reset state machine. Transmission Info0. reaction incoming infos. unconditional command. Send Single Pulses. Send Continuous Pulses. Receiver synchronous Activation Request. This command used start activation. Activation request loop. transceiver requested operate analog loop-back close S/T-interface. Activation Indication. Synchronous receiver, i.e. activation completed.
Send Single Pulses Send Continuous Pulses Receiver Synchronous Activation Request Activation Request Loop Activation Indication
0010 0011 0100 1000 1010
1100
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Functional Description Command Activation Indication Loop Deactivation Confirmation Abbr. Code 1110 1111 Remark Activation Indication Loop Deactivation Confirmation. Transfers transceiver into deactivated state which activated from terminal (detection INFO enabled). Remark Interim indication during deactivation procedure. Receiver synchronous. INFO received from terminal. Activation proceeds. Illegal code violation received. This function enabled S_CONF0.EN_ICV. Synchronous receiver, i.e. activation completed. Timer expired INFO received duration after deactivation request.
Indication Timing Receiver Synchronous Activation Request Illegal Code Ciolation Activation Indication Deactivation Indication
Abbr.
Code 0000 0100 1000 1011 1100 1111
Data Sheet
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Operational Description
3.1.1
Operational Description
Layer Activation/Deactivation Complete Activation Initiated Exchange
Figure depicts procedure activation been initiated exchange side (LT).
IOM-2
S/T-Reference Point U-Reference Point
IOM-2
INFO INFO
(act
INFO
(act (act SL3T (act
INFO SN3T (act SL3T (act INFO
AR8/10 SBCX-X IPAC-X
Q-SMINTO
DFE-Q
ITD10035.vsd
Figure
Complete Activation Initiated Exchange
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Operational Description
3.1.2
Complete Activation Initiated
Figure depicts procedure activation been initiated terminal side (TE).
IOM-2 IOM-2
S/T-Reference Point
U-Reference Point
AR8/10
INFO INFO
INFO
(act (act SL3T (uoa
INFO INFO INFO (act SL3T (act SN3T
SBCX-X IPAC-X
INFO
Q-SMINTO
DFE-Q
ITD10041.vsd
Figure
Complete Activation Initiated
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Operational Description
3.1.3
Complete Deactivation
Figure depicts procedure deactivation been initiated. Deactivation layer always initiated exchange.
IOM-2
S/T-Reference Point U-Reference Point
IOM-2
INFO INFO
SL3T (act SN3T (act
DC1)
SL3T (act
DEAC
SBCX-X IPAC-X
INFO INFO
DFE-Q
Q-SMINTO
ITD10040.vsd 1)C/I-Code
might issued before C/I-Code case Validation Algorithm CRC&TLL selected
Figure
Complete Deactivation Initiated Exchange
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Operational Description
3.1.4
Partial Activation
Figure depicts procedure partial activation been initiated exchange.
IOM-2
S/T-Reference Point U-Reference Point
IOM-2
INFO INFO
(act (act SL3T (act (DC)
SBCX-X IPAC-X
Q-SMINTO
DFE-Q
ITD10036.vsd
Figure
Partial Activation
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Operational Description
3.1.5
Activation from Exchange with Active
Figure depicts procedure activation been initiated exchange with already being active.
IOM-2
S/T-Reference Point U-Reference Point
IOM-2
INFO INFO
SL3T (act (act
DC/UAR
INFO INFO SL3T (act (act (act SL3T (act SN3T
INFO AR8/10 SBCX-X IPAC-X
Q-SMINTO
DFE-Q
ITD10037.vsd
Figure
Activation from with Active
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Operational Description
3.1.6
Activation from with Active
Figure depicts procedure activation been initiated with already being active.
IOM-2
S/T-Reference Point U-Reference Point
IOM-2
AR8/10
INFO INFO
SL3T (act (act
INFO
(act SL3T (act
INFO INFO INFO (act SL3T (act SN3T SBCX-X IPAC-X DFE-Q
ITD10038.vsd
INFO
Q-SMINTO
Figure
Activation from with Active
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Operational Description
3.1.7
Partial Deactivation with Active
Figure depicts procedure partial deactivation been initiated exchange; i.e. remains active.
IOM-2
S/T-Reference Point U-Reference Point
IOM-2
INFO INFO
SL3T (act SN3T (act
INFO INFO SBCX-X IPAC-X
SL3T (act SN3T (act SN3T (act SL3T (act
Q-SMINTO
DFE-Q
ITD10039.vsd
Figure
Partial Deactivation with Active
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Operational Description
3.1.8
Loop
Figure depicts procedure loop closed opened.
IOM-2 AR8/10 S/T-Reference Point INFO INFO U-Reference Point SL3T (act SN3T (act IOM-2
2B+D EOC: LBBD;
LP2I
MON0: LBBD
2B+D EOC: RTN;
LP2I
MON0:
2B+D
SBCX-X IPAC-X
Q-SMINTO
DFE-Q
ITD10042.vsd
Figure
Loop
Note: Closing resolving loop provoke S-transceiver resynchronize. this case, following C/I-codes exchanged immediately upon receipt respectively: 'RSY', 'ARL', 'AI', 'AIL' 'AI'.
Data Sheet
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Operational Description
Layer Loopbacks
Test loopbacks specified national PTTs order facilitate location defect systems. Four different loopbacks defined. position each loopback illustrated Figure
S-BUS Loop S-Transceiver
IOM®-2
Loop U-Transceiver
IOM®-2
Loop U-Transceiver U-Transceiver Loop U-Transceiver
IOM®-2
Loop Layer-1 Controller U-Transceiver
IOM®-2
Repeater (optional)
Exchange
IOM-2
Loop Layer-1 Controller U-Transceiver
loop_2b1q.emf
Figure
Test Loopbacks
Loopbacks controlled exchange. Loopback controlled locally remote side. four loopback types transparent. This means bits that looped back will also passed onwards normal manner. Only data looped back internally processed; signals receive pins ignored. propagation delay actually looped channels data must identical loopbacks.
Data Sheet
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Operational Description
3.2.1
Loopback No.2
loopback several alternatives exist. Both type loopback location vary. following loopback types belong loopback-#2 category: complete loopback (B1,B2,D), downstream device B1-channel loopback, always performed U-transceiver B2-channel loopback, always performed U-transceiver loop variations performed U-transceiver closed near internal IOM-2 interface possible. Normally loopback controlled exchange. maintenance channel used this purpose. loopback functions latched. This allows channel channel looped back simultaneously.
3.2.1.1
Complete Loopback
When receiving request complete loopback, transceiver passes downstream device, e.g. S-bus transceiver. This achieved issuing C/Icode "Transparent" state states different than "Transparent"
3.2.1.2
Loopback No.2 Single Channel Loopbacks
Single channel loopbacks always performed directly U-Transceiver. difference between B1-channel B2-channel loopback control procedure exists.
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Operational Description
3.3.1
External Circuitry Power Supply Blocking Recommendation
following blocking circuitry suggested.
VDDa_UR VDDa_UX VDDa_SR VDDa_SX VDDD VDDD 100nF
3.3V
100nF
100nF
100nF
100nF
100nF
VSSD VSSD
VSSa_SX VSSa_SR VSSa_UX VSSa_UR
These capacitors should located near pins possible
blocking_caps_Smint.vsd
Figure
Power Supply Blocking
3.3.2
U-Transceiver
Q-SMINTO connected twisted pair transformer. Figure shows recommended external circuitry. recommended protection circuitry displayed. Note: integrated hybrid specified Version more available Version external hybrid required.
Data Sheet
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Operational Description
AOUT
RCOMP RPTC
Loop
RCOMP
RPTC
extcirc_U_Q2_exthybrid.emf
BOUT
Figure
External Circuitry U-Transceiver
U-Transformer Parameters following Table lists parameters typical U-transformers: Table U-Transformer Parameters Symbol Value 14.5 2.51)
U-Transformer Parameters U-Transformer ratio; Device side Line side Main inductance windings line side
Unit
Leakage inductance windings line side Coupling capacitance between windings device side windings line side resistance windings device side resistance windings line side
according equation[2]
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Operational Description Resistors External Hybrid Resistors Line Side RPTC Chip Side Optional 2x20 resistors (2xRPTC) line side transformer requires compensation resistors RCOMP depending RPTC: 2RPTC 8RCOMP 2RPTC 4(2RCOMP ROUT Table ROUT Table Capacitor achieve optimum performance capacitor should MKT. Ceramic capacitor recommended. Tolerances C=27 ±10-20% L=14.5 ±10%
3.3.3
S-Transceiver
order comply physical requirements recommendation I.430 considering national requirements concerning overvoltage protection electromagnetic compatibility (EMC), S-transceiver needs some additional circuitry. S-Transformer Parameters following Table lists parameters typical S-transformer:
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Operational Description
Table
S-Transformer Parameters Symbol Value typ. typ. typ. <100 typ. typ. Unit
Transformer Parameters Transformer ratio; Device side Line side Main inductance windings line side
Leakage inductance windings line side Coupling capacitance between windings device side windings line side resistance windings device side resistance windings line side Transmitter
transmitter requires external resistors Rstx order adjust output voltage pulse mask (nominal according I.430, tested with test mode "TM1") hand order meet output impedance minimum other hand tested with testmode 'Continuous Pulses') other hand. Note: resistance S-transformer must taken into account when dimensioning external resistors Rstx. transmit path contains additional components (e.g. choke), then resistance these additional components must taken into account, too.
20.40
Point
extcirc_S.vsd
Figure
External Circuitry S-Interface Transmitter
Data Sheet
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Operational Description Receiver receiver S-transceiver symmetrical. overall resistance recommended each receive path. preferable split resistance into resistors each line. This allows place high resistance between transformer diode protection circuit (required pass input impedance test I.430 300012-1). remaining resistance (1.8 protects Stransceiver itself from input current peaks.
Point
extcirc_S.vsd
Figure
External Circuitry S-Interface Receiver
3.3.4
Oscillator Circuitry
Figure illustrates recommended oscillator circuit.
XOUT 15.36
Figure
Crystal Oscillator
Data Sheet
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Operational Description
Table Parameter Frequency
Crystal Parameters Symbol Limit Values 15.36 +/-60 fundamental Unit
Frequency calibration tolerance Load capacitance Max. resonance resistance Max. shunt capacitance Oscillator mode External Components Parasitics
load capacitance computed from external capacitances CLD, parasitic capacitances CPar (pin capacitances ground VDD) stray capacitance between XOUT: specific crystal total load capacitance predefined, equation must solved external capacitances CLD, which usually only variable determined circuit designer. Typical values capacitances connected crystal
3.3.5
General
power LEDs input supports APC13112 AT&T LH1465AB discrete proposed Infineon
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Electrical Characteristics
Electrical Characteristics
Absolute Maximum Ratings
Symbol Limit Values -0.3 (max. 5.5) Unit
Parameter Ambient temperature under bias
Storage temperature TSTG Maximum Voltage Maximum Voltage with respect
ground
integrity (according EIA/JESD22-A114B (HBM)): Note: Stress above those listed here cause permanent damage device. Exposure absolute maximum ratings conditions extended periods affect device reliability. Line Overload Protection Q-SMINTO compliant tests according ANSI ESD-S 5.1-1993 (CDM), EIA/JESD22-A114B (HBM) Latch-up tests according JEDEC JESD78. From these tests following max. input currents derived (Table 17):
Table Test Latch-up
Maximum Input Currents Pulse Width -Current +/-200 Remarks repetitions repetitions, respectively
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Electrical Characteristics
Characteristics
VDD/VDDA VSS/VSSA Digital Pins except DD/DU ACT,LP2I MCLK DD/DU ACT,LP2I MCLK Parameter Input voltage Input high voltage Output voltage Output high voltage Output voltage Output high voltage (DD/DU push-pull) Input leakage current Input leakage current (internal pull-up) Analog Pins AIN, Input leakage current
Symbol Limit Values min. VOL1 VOH1 VOL2 VOH2 ILIPU 0.45 -0.3 max. 5.25 0.45
Unit
Test Condition
IOL1 IOH1 IOL2 IOH2
Output leakage current
Table SX1,2
S-Transceiver Characteristics Symbol Limit Values min. typ. max. 2.31 2.03 Unit Test Condition
Parameter Absolute value output pulse amplitude (VSX2 VSX1) S-Transmitter output impedance
SX1,2
2)3)
SR1,2 S-Receiver input impedance
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Electrical Characteristics
Requirement ITU-T I.430, chapter 8.5.1.1a): times except when transmitting binary zero, output impedance frequency range 2kHz MHz, shall exceed impedance indicated template Figure requirement applicable with applied sinusoidal voltage (r.m.s value)' Requirement ITU-T I.430, chapter 8.5.1.1b): 'When transmitting binary zero, output impedance shall Must external circuitry. Requirement ITU-T I.430, chapter 8.5.1.1b), Note: 'The output impedance limit shall apply nominal load impedance (resistive) output impedance each nominal load shall defined determining peak pulse amplitude loads equal nominal value 10%. peak amplitude shall defined amplitude midpoint pulse. limitation applies pulses both polarities.'
Table
U-Transceiver Characteristics Limit Values min. typ. max. (PEF 80912) (PEF 80913) peak Unit
Receive Path Signal (noise total harmonic distortion)1) 652) DC-level AD-output Threshold level detect (measured between with respect zero signal) Input impedance AIN/BIN Transmit Path Signal (noise total harmonic distortion)4) Common mode DC-level Offset between AOUT BOUT Absolute peak voltage single pulse measured between AOUT BOUT5) Output impedance AOUT/BOUT: Power-up Power-down
1.65 1.69 2.58
1.61 2.42
Test conditions: differential sine wave input AIN/BIN with long range (low, critical range). Versions 8x913 with enhanced performance U-interface tested with tightened limit values percentage "-values PDM-signal. Interpretation test conditions: noise total harmonic distortion, weighted with pass filter kHz, least below signal evenly distributed otherwise random sequence
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Electrical Characteristics
signal amplitude measured over period min. varies less than
Capacitances
VSSA VSSD MHz, unmeasured pins grounded. Table Parameter Digital pads: Input Capacitance Capacitance Analog pads: Load Capacitance Capacitances Symbol Limit Values Unit min. CI/O max. AIN, Remarks
Power Consumption
Power Consumption VDD=3.3 VSS=0 Inputs VSS/VDD, connected, bin. zeros, output loads except SX1,2 Parameter Operational enabled, IOM-2 Limit Values min. typ. Power Down
Unit Test Condition
max. ETSI loop ETSI Loop 2.(typical line)
S-bus.
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Electrical Characteristics
Supply Voltages
VDDD VDDA maximum sinusoidal ripple specified following figure:
(peak) Supply Voltage Ripple
Frequency
ITD04269.vsd
Frequency Ripple
Figure
Maximum Sinusoidal Ripple Supply Voltage
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Electrical Characteristics
Characteristics
Inputs driven logical logical "0". Timing measurements made logical logical "0". testing input/output waveforms shown Figure
Test Points
0.45
Device Under Test
CLoad=50
ITS00621.vsd
Figure
Input/Output Waveform Tests
Parameter Output Pins Fall time Rise time
Symbol
Limit values
Unit
Data Sheet
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Electrical Characteristics
4.6.1
IOM-2 Interface
DU/DD (Output) DU/DD (Output) first last
Figure
IOM®-2 Interface Synchronization Timing
Figure
IOM-2 Interface Frame Synchronization Timing
Note: start reset period, frame jump occur. This results high time min. after this specific event.
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Electrical Characteristics Parameter IOM®-2 Interface period high Symbol Limit values 1875 1953 2035 1105 1105 Unit
Output data from high impedance active (FSC high other than first timeslot) Output data from active high impedance Output data delay from clock high cycle time
advance DCL, rise/fall Data rise/fall tristate)
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Electrical Characteristics
4.6.2
Table Parameter
Reset
Reset Input Signal Characteristics Symbol tRST Limit Values min. typ. max. Power assumed long enough oscillator correctly After Power Unit Test Conditions
Length active state
clock cycles
tRST
ITD09823.vsd
Figure
Reset Input Signal
Data Sheet
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Electrical Characteristics
4.6.3
Undervoltage Detection Characteristics
VDET
VHYS
VDDmin
RSTO
tACT
tACT
tDEACT
tDEACT
VDDDET.VSD
Figure
Undervoltage Control Timing
Data Sheet
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Electrical Characteristics Table Parameters UVD/POR Circuit
VDD= VSS= Parameter Detection Threshold1) Hysteresis Max. rising/falling edge activation/ deactivation Max. rising power-on2) Min. operating voltage Delay activation RSTO Delay deactivation RSTO
Symbol min. VDET VHys dVDD/dt
Limit Values typ. max. 2.92
Unit Test Condition V/µs
VDDmin tACT tDEACT
Detection Threshold VDET below specified supply voltage range analog digital parts Q-SMINT Therefore, board designer must take into account that range voltages existing, where neither performance functionality Q-SMINT guaranteed, reset generated. integrated Power-On Reset Q-SMINTO selected (VDDDET '0') supply voltage ramped from 3.3V then Q-SMINTO kept reset during VDDmin VDET VHys. must ramped slowly that Q-SMINTO leaves reset state after oscillator circuit already finished start-up. start-up time oscillator circuit typically range between 12ms.
Data Sheet
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Package Outlines
Package Outlines
Plastic Package, P-MQFT-44 (Metric Quad Flat Package)
Data Sheet
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Appendix: Differences between T-SMINT,O
Appendix: Differences between T-SMINTO
Especially compatibility between T-SMINTO allows single design both series with only some mounting differences.
T-SMINTO have been designed compatible possible. However, some differences between them unavoidable different line codes 2B1Q 4B3T used data transmission line.
following chapter summarizes main differences between TSMINTO.
Table MQFT-44
Pinning
Definitions Functions Q-SMINTO: 2B1Q Triple-Last-Look (TLL) Metallic Termination Input (MTI) Auto Activation (AUA) Cold Start Only (CSO) Power Status (primary) (PS1) Power Status (secondary) (PS2) T-SMINTO: 4B3T
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Appendix: Differences between T-SMINT,O
6.2.1
Table Document
U-Transceiver U-Interface Conformity
Related Documents U-Interface Q-SMINTO: 2B1Q conform annex compliant interruptions T-SMINTO: 4B3T conform annex
ETSI:
ANSI: T1.601-1998 (Revision ANSI T1.6011992) CNET: ST/LAA/ELR/DNP/ RC7355E FTZ-Richtlinie
conform required input decode logic conform conform required required required conform
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Appendix: Differences between T-SMINT,O
6.2.2
U-Transceiver State Machines
T14S
T14E T14S
Pending Timing
State C/I= 'SSP' T14S
Deactivated
Test
Awaked
Reset State Pin-RST C/I= 'RES'
NT-AUTO
T1S, T11S
Alerting
T12S T11S
Alerting
T11E T12S
T1S, T11S
T11E T12S
EC-Training
LSEC T12E LSUE
EC-Training
EC-Training
LSEC T12E
act=0 Wait
BBD1
BBD0
EQ-Training
T20S
SN3T act=0 Analog Loop Back
LSUE
T20E BBD0
Wait
SN3/SN3T act=1/0 Pend.Deact.
LSUE
dea=0
SN3/SN3T act=0 Synchronized
uoa=1
dea=0 LSUE uoa=0 dea=0 LSUE
SN3/SN3T act=0 Synchronized AR/ARL
SN3/SN3T act=1 Wait AR/ARL
act=1 act=0
uoa=0 dea=0 LSUE
State C/I='DT'
act=1 SN3T Transparent AI/AIL
act=1
uoa=0 dea=0 LSUE
SN3/SN3T act=0 Error act=0 AR/ARL
dea=0 uoa=0 LSUE
uoa=1
dea=1
Pend Receive Res. T13S
/LOF T13E
SN3/SN3T act=1/0 Pend.Deact.
Receive Reset
Figure
NTC-Q Compatible State Machine Q-SMINTO: 2B1Q
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Appendix: Differences between T-SMINT,O
Awaked Start Awaking Awake Signal Sent T13S T13E Ack. Sent Received T05E) T12S Synchronizing T12E) T05S Pend. Deactivation T05S Synchronizing Wait Info Transparent Loss Framing T13S Sending Awake-Ack. T13S T05S T05S T05E Deactivating Deactivated
Test STATE Reset
NT_SM_4B3T_cust.emf
Figure
IEC-T/NTC-T Compatible State Machine T-SMINTO: 4B3T
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Appendix: Differences between T-SMINT,O
6.2.3
Table Code
Command/Indication Codes
Codes Q-SMINTO: 2B1Q T-SMINTO: 4B3T
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
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Appendix: Differences between T-SMINT,O
External Circuitry
external circuitry T-SMINTO equivalent; however, some external components U-transceiver hybrid must dimensioned different 2B1Q 4B3T. information external circuitry preliminary changed future documents.
AOUT
RCOMP RPTC
Loop
RCOMP
RPTC
extcirc_U_Q2_exthybrid.emf
BOUT
Figure
External Circuitry T-SMINTO
necessary protection circuitry displayed Figure
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Appendix: Differences between T-SMINT,O Table Component Transformer: Ratio Main Inductivity Resistance Resistance Resistance Capacitor RPTC RComp Dimensions External Components. Q-SMINTO: 2B1Q 14.5 2RPTC 8RComp T-SMINTO: 4B3T 1:1.6 1.75 (2RCOMP
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Index
Index
Package Outlines Configuration Definitions Functions Power Consumption Power Supply Blocking Power-On Reset
Absolute Maximum Ratings
Block Diagram
Codes U-Transceiver Cyclic Redundancy Check
Reset Generation Input Signal Characteristics Power-On Reset Under Voltage Detection
Characteristics Differences between T-SMINT
Channels Scrambling/ Descrambling S-Transceiver Functional Description State Machine, Supply Voltages System Integration
External Circuitry S-Transceiver U-Transceiver
Features
IOM®-2 Interface Characteristics Frame Structure Functional Description
Test Modes
U-Interface Hybrid Under Voltage Detection U-Transceiver Functional Description State Machine, Standard
Layer Loopbacks Pins Line Overload Protection
Metallic Loop Termination
Oscillator Circuitry
Data Sheet
2001-03-29
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