PCF2105 controller/driver Product specification Supersedes data 1

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PCF2105 controller/driver Product specification Supersedes data 1

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PCF2105 controller/driver
Product specification Supersedes data 1997 File under Integrated Circuits, IC12 1998
Philips Semiconductors
Product specification
controller/driver
CONTENTS 7.10 7.11 7.12 8.10 8.11 8.12 8.13 8.14 8.15 8.16 9.3.1 9.3.2 FEATURES APPLICATIONS GENERAL DESCRIPTION Packages Available types ORDERING INFORMATION BLOCK DIAGRAM PINNING FUNCTIONS Register Select (parallel control) R/W: read/write (parallel control) data clock (parallel control) DB0: data (parallel control) column driver outputs driver outputs VLCD: power supply OSC: oscillator SCL: serial clock line SDA: serial data line SA0: address input test input FUNCTIONAL DESCRIPTION bias voltage generator Oscillator External clock Power-on reset Registers Busy flag Address Counter (AC) Display Data (DDRAM) Character Generator (CGROM) Character Generator (CGRAM) Cursor control circuit Timing generator column drivers Programming rate Programming rate Reset function INSTRUCTIONS Clear display Return home Entry mode 9.4.1 9.4.2 9.4.3 9.6.1 9.6.2 9.10 9.11 11.1 11.2 11.3 11.4 11.5 11.6 17.1 17.2 17.3 17.4 17.5
PCF2105
Display control Cursor/display shift Function (parallel mode only) CGRAM address DDRAM address Read busy flag address Write data CGRAM DDRAM Read data from CGRAM DDRAM INTERFACE MICROCONTROLLER (PARALLEL INTERFACE) INTERFACE MICROCONTROLLER (I2C-BUS INTERFACE) Characteristics I2C-bus transfer START STOP conditions System configuration Acknowledge I2C-bus protocol LIMITING VALUES HANDLING CHARACTERISTICS CHARACTERISTICS TIMING DIAGRAMS APPLICATION INFORMATION 4-bit operation, display using internal reset 8-bit operation, display using internal reset 8-bit operation, display I2C-bus operation, display Initializing instruction BONDING LOCATIONS DEFINITIONS LIFE SUPPORT APPLICATIONS PURCHASE PHILIPS COMPONENTS
1998
Philips Semiconductors
Product specification
controller/driver
FEATURES
PCF2105
Single chip Liquid Crystal Display (LCD) controller/driver 2-line display characters line, 4-line display characters line character format plus cursor; kana (Japanese syllabary) user-defined symbols On-chip generation intermediate bias voltages On-chip oscillator requires external components (external clock also possible) Display data RAM: characters Character generator ROM: characters Character generator RAM: characters 8-bit parallel 2-wire I2C-bus interface (400 kHz) CMOS compatible row, column outputs Multiplex (MUX) rates Uses common 11-code instruction Logic supply voltage range: Display supply voltage range: VLCD power consumption I2C-bus address selection (SA0): 011101. APPLICATIONS Furthermore, fast I2C-bus interface (400 kHz) provided. PCF2105 optimized chip-on-glass applications. specific letter code character programmed Character Generator (CGROM) (see Fig.5). PCF2105 power CMOS controller/driver, designed drive split screen matrix lines characters lines characters with format. necessary functions display provided single chip, including on-chip generation bias voltages which results minimum external components lower system power consumption. allow partial shutdown protection system pads does diode connected VDD. chip contains character generator displays alphanumeric kana characters. PCF2105 interfaces most microcontrollers 8-bit parallel bus, 2-wire I2C-bus. Packages
Telecom equipment Portable instruments Point-of-sale terminals. GENERAL DESCRIPTION
PCF2105MU/2: chip with bumps tray. Available types
PCF2105MU/2: character CGROM.
PCF2105 integrated circuit similar PCF2114x (described "PCF2116 family" data sheet) does contain high voltage generator that device. ORDERING INFORMATION PACKAGE TYPE NUMBER NAME PCF2105MU/2 chip with bumps tray DESCRIPTION VERSION
1998
Philips Semiconductors
Product specification
controller/driver
BLOCK DIAGRAM
PCF2105
handbook, full pagewidth
BIAS VOLTAGE GENERATOR COLUMN DRIVERS
DRIVERS SHIFT REGISTER 32-BIT
DATA LATCHES SHIFT REGISTER 12-bit CURSOR DATA CONTROL CHARACTER GENERATOR (CGRAM) CHARACTERS CHARACTER GENERATOR (CGROM) CHARACTERS
PCF2105
OSCILLATOR
DISPLAY DATA (DDRAM) CHARACTERS ADDRESS COUNTER (AC) INSTRUCTION DECODER DATA REGISTER (DR) BUSY FLAG INSTRUCTION REGISTER (IR) BUFFER
TIMING GENERATOR
DISPLAY ADDRESS COUNTER
POWER RESET
MGK846
Pads correspond with symbols R29. Pads correspond with symbols R16. Pads correspond with symbols
Fig.1 Block diagram.
1998
Philips Semiconductors
Product specification
controller/driver
PINNING SYMBOL VLCD FUNCTIONS Register Select (parallel control) logic supply voltage I2C-bus address selection input logic ground driver outputs driver outputs driver outputs column driver outputs driver outputs driver outputs driver outputs I2C-bus serial clock input data clock input register select input read/write input test input 8-bit bidirectional data input/output I2C-bus serial data input/output supply voltage input DESCRIPTION oscillator/external clock input
PCF2105
DB0: data (parallel control)
selects register accessed read write when device controlled parallel interface. selects instruction register write busy flag address counter read. selects data register both read write. There internal pull-up resistor R/W: read/write (parallel control)
bidirectional, 3-state data transfers data between system controller PCF2105. acts busy flag, signalling that internal operations completed. 4-bit operations, used must left open-circuit. There internal pull-up resistor each data lines. Note that pads must left open-circuit when I2C-bus control used. column driver outputs
selects either read (R/W write (R/W operation when control parallel interface. There internal pull-up resistor R/W. data clock (parallel control)
Pads output data pairs columns. This arrangement permits optimized Chip-On-Glass (COG) layout 4-line characters. driver outputs
should HIGH signal start read write operation when device controlled parallel interface. Data clocked chip falling edge clock. Note that must connected (logic when I2C-bus control used.
Pads output select waveforms left right halves display. VLCD: power supply
Negative power supply liquid crystal display.
1998
Philips Semiconductors
Product specification
controller/driver
OSC: oscillator Oscillator
PCF2105
When on-chip oscillator used, must connected VDD. external clock signal, used, input OSC. SCL: serial clock line
on-chip oscillator provides clock signal display system. external components required. must connected VDD. External clock
input I2C-bus clock signal. 7.10 SDA: serial data line
input/output I2C-bus data line. 7.11 SA0: address input
external clock used, must input OSC. resulting display frame frequency given frame -2304 clock signal must always present, otherwise frozen state. Power-on reset
hardware subaddress line used program device subaddress different PCF2105s same I2C-bus. 7.12 test input
Power-on reset block initializes chip after power-on power failure. Registers
must connected VSS. user accessible. FUNCTIONAL DESCRIPTION
Figure shows block diagram PCF2105. Details explained subsequent sections. bias voltage generator
PCF2105 8-bit registers, Instruction Register (IR) Data Register (DR). Register Select (RS) signal determines which register will accessed. stores instruction codes such `clear display' `cursor shift', address information DDRAM CGRAM. system controller write data read data from instruction register. temporarily stores data read from DDRAM CGRAM. When reading, data from DDRAM CGRAM (corresponding address address counter) written prior being read `read data' instruction. Busy flag
intermediate bias voltages generated on-chip. This removes need external resistive bias chain significantly reduces system power consumption. optimum levels depend multiplex (MUX) rate selected automatically when number lines display defined. optimum value operating voltage depends rate, threshold voltage number bias levels. relationships, together with discrimination ratio given Table Using 5-level bias scheme rate allows most LCDs. effect display contrast negligible. Table RATE Optimum values NUMBER BIAS LEVELS
Busy Flag (BF) indicates free busy status PCF2105. indicates that chip busy further instructions will accepted. output when Instructions should only written after checking that waiting required number clock cycles. Address Counter (AC)
3.67 5.19
1.277 1.196
assigns addresses DDRAM CGRAM reading writing instructions `set CGRAM address' `set DDRAM address'. After read/write operation automatically incremented decremented contents output (pads DB0) when
1998
Philips Semiconductors
Product specification
controller/driver
Display Data (DDRAM) 8.11 Cursor control circuit
PCF2105
DDRAM stores characters display data, represented 8-bit character codes. DDRAM locations used storing display data used general purpose RAM. basic DDRAM-to-display mapping scheme shown Fig.2. With display shift, characters represented codes first DDRAM locations, starting address line displayed. Subsequent lines display data starting addresses hexadecimal (hex). Figures show DDRAM-to-display mapping scheme when display shifted. address range 1-line display 2-line display from (line (line 4-line display from lines respectively. 4-line displays address line start address next line successive. When display shifted each line wraps around independently others (see Figs When data written DDRAM, wrap-around occurs from 1-line display from 2-line display; from 4-line display. Character Generator (CGROM)
cursor control circuit generates cursor (underline and/or character blink shown Fig.7) DDRAM address contained address counter. When address counter contains CGRAM address cursor will inhibited. 8.12 Timing generator
timing generator produces various signals required drive internal circuitry. Internal chip operation disturbed operations data buses. 8.13 column drivers
PCF2105 contains drivers column drivers. They connect appropriate bias voltages sequence display, accordance with data displayed. bias voltages timing selected automatically when number lines display selected. Figures show typical waveforms. 1-line display (MUX rate 16), outputs driven pairs, example R1/R17 R2/R18. This allows output pairs connected parallel, thereby providing greater drive capability. Unused outputs should left unconnected.
CGROM generates character patterns format from 8-bit character codes. Figure shows character currently available. 8.10 Character Generator (CGRAM)
user-defined characters stored CGRAM. CGROM CGRAM common address space, which first column reserved CGRAM (see Fig.5). Figure shows addressing principle CGRAM.
1998
Philips Semiconductors
Product specification
controller/driver
PCF2105
Display handbook, columns Position (decimal)
non-displayed DDRAM addresses
DDRAM Address (hex)
1-line display non-displayed DDRAM address
DDRAM Address (hex)
line
MLA792
line
2-line display
handbook, columns
non-displayed DDRAM addresses line
line
DDRAM Address (hex)
line
line
line display
MLA793
Fig.2 DDRAM-to-display mapping; shift.
1998
Philips Semiconductors
Product specification
controller/driver
PCF2105
Display Position (decimal) DDRAM Address (hex)
Display Position (decimal) DDRAM Address (hex) line DDRAM Address (hex)
1-line display
1-line display
line
DDRAM Address (hex)
MLA802
line
MLA815
line
2-line display
2-line display
line
line
line DDRAM Address (hex)
line
DDRAM Address (hex)
line
line
line
line
MLA816
4-line display
MLA803
4-line display
Fig.3 DDRAM-to-display mapping; right shift.
Fig.4 DDRAM-to-display mapping; left shift.
1998
Philips Semiconductors
Product specification
controller/driver
PCF2105
handbook, full pagewidth upper
lower bits xxxx
bits
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
xxxx
0001
xxxx
0010
xxxx
0011
xxxx
0100
xxxx
0101
xxxx
0110
xxxx
0111
xxxx
1000
xxxx
1001
xxxx
1010
xxxx
1011
xxxx
1100
xxxx
1101
xxxx
1110
xxxx
1111
MGK847
Fig.5 Character CGROM.
1998
Philips Semiconductors
Product specification
controller/driver
PCF2105
handbook, full pagewidth
character codes (DDRAM data) lower order bits
CGRAM address lower order bits higher order bits
character patterns (CGRAM data)
higher order bits
higher order bits
lower order bits character pattern example character pattern example cursor position
MGA800
Character code bits correspond CGRAM address bits CGRAM address bits designate character pattern line position. line cursor position display performed logical with cursor. Data line will appear cursor position. Character pattern column positions correspond CGRAM data bits being left end, shown this figure. CGRAM character patterns selected when character code bits logic CGRAM data logic corresponds selection display. Only bits CGRAM address `set CGRAM address' instruction. using `set DDRAM address' instruction using auto-increment feature during CGRAM write. bits read using `read busy flag address' instruction.
Fig.6 Relationship between CGRAM addresses, data display patterns.
1998
Philips Semiconductors
Product specification
controller/driver
PCF2105
cursor character font alternating display
MGA801
cursor display example
blink display example
Fig.7 Cursor blink display examples.
1998
Philips Semiconductors
Product specification
controller/driver
PCF2105
handbook, full pagewidth
frame
frame
state (ON) state (ON)
1-line display (1:16)
0.25 state 0.25
0.25 state 0.25
MGA802
Fig.8 Typical waveforms; 1-line display.
1998
Philips Semiconductors
Product specification
controller/driver
PCF2105
handbook, full pagewidth
frame
frame
state (ON) state (ON)
2-line display (1:32)
state
0.15 0.15
state
0.15 0.15
MGA803
Fig.9 Typical waveforms; 2-line display.
1998
Philips Semiconductors
Product specification
controller/driver
8.14 Programming rate
PCF2105
program rate bits `function set' instruction must logic (see Table Figures show DDRAM addresses display characters. second each figure corresponds either right half 1-line display second line 2-line display. Wrap around data during display shift when writing data non-standard.
With rate PCF2105 used following ways: drive 1-line display characters drive 2-line display characters, resulting better contrast. internal data flow chip optimized this purpose.
handbook, full pagewidth
display position DDRAM address
display position DDRAM address
MLB899
Fig.10 DDRAM-to-display mapping; shift.
handbook, full pagewidth
display position DDRAM address
display position DDRAM address
MLB900
Fig.11 DDRAM-to-display mapping; right shift.
handbook, full pagewidth
display position DDRAM address
display position DDRAM address
MLB901
Fig.12 DDRAM-to-display mapping; left shift.
1998
Philips Semiconductors
Product specification
controller/driver
8.15 Programming rate
PCF2105
Instructions categories, those that: Designate PCF2105 functions such display format, data length, etc. internal addresses Perform data transfer with internal Others. normal use, category instructions used most frequently. However, automatic incrementing decrementing internal addresses after each data write lessens microcontroller program load. display shift particular performed concurrently with display data write, thus enabling designer develop systems minimum time with maximum programming efficiency. During internal operation, instruction other than `read busy flag address' will executed. Because busy flag logic while instruction being executed, advisable ensure that flag logic before sending next instruction wait maximum instruction execution time, given Table instruction sent while busy flag HIGH will executed. Clear display
With rate PCF2105 used following ways: drive 2-line display characters, instruction `function set' logic logic drive 4-line display characters, instruction `function set' both bits logic 8.16 Reset function
PCF2105 automatically initializes (resets) when power turned state after reset given Table (see Tables description bits). Table STEP clear display function set: 8-bit interface bits 1-line display used display control: display cursor blink entry mode set: +1(increment) used default address pointer DDRAM; busy flag indicates busy state until initialization ends; busy state lasts chip also initialized software; Tables I2C-bus interface reset State after reset DESCRIPTION
`Clear display' writes space code (hexadecimal) into DDRAM addresses (the character pattern character code must blank pattern), sets DDRAM address counter logic returns display original position shifted. Consequently, display disappears cursor blink position goes left edge display (the first line lines displayed) sets `entry mode set' logic (increment mode). `entry mode set' does change. instruction `clear display' requires extra execution time. This allowed checking Busy Flag (BF) waiting until elapsed. latter must applied where read-back options available, some Chip-On-Glass (COG) applications. Return home
INSTRUCTIONS
Only PCF2105 registers, Instruction Register (IR) Data Register (DR) directly controlled microcontroller. Before internal operation, control information stored temporarily these registers allow interface various types microcontrollers which operate different speeds allow interfacing peripheral control ICs. PCF2105 operation controlled instructions shown Table together with their execution time. Details explained subsequent sections.
`Return home' sets DDRAM address counter logic returns display original position shifted. DDRAM contents change. cursor blink position goes left display (the first line lines displayed). Bits `entry mode set' change.
1998
This text here white force landscape pages rotated correctly when browsing through Acrobat reader.This text here _white force landscape pages rotated correctly when browsing through Acrobat reader.This text here inThis text here white force landscape pages rotated correctly when browsing through Acrobat reader. white force landscape pages 1998 Function CGRAM address DDRAM address Read busy flag address Read data Write data Notes I2C-bus mode don't care. 8-bit mode assumed. I2C-bus mode control byte required when changed; control byte: R/W, command byte: DB0. Example: fosc kHz, 6.67 cycles cycles read data write data Philips Semiconductors Table Instructions (note
controller/driver
INSTRUCTION Clear display Return home
DESCRIPTION operation clears entire display sets DDRAM address Address Counter (AC) sets DDRAM address also returns shifted display original position; DDRAM contents remain unchanged sets cursor move direction specifies shift display; these operations performed during data write read sets entire display on/off (D), cursor on/off blink cursor position character moves cursor shifts display without changing DDRAM contents sets interface data length (DL), number display lines voltage generator control (G); used sets CGRAM address sets DDRAM address reads indicating internal operation being performed reads contents reads data from CGRAM DDRAM writes data CGRAM DDRAM
REQUIRED CLOCK CYCLES(2)
Entry mode
Display control
Cursor/display shift
Product specification
PCF2105
Philips Semiconductors
Product specification
controller/driver
Table 9.3.1 decrement display freeze display cursor character cursor position does blink cursor move left shift bits lines characters; rate reserved internal operation last control byte, only data bytes follow Entry mode Command identities, used Table LOGIC increment display shift display cursor character cursor position blinks display shift right shift bits lines characters; rate lines characters; rate internal operation progress LOGIC
PCF2105
next bytes data byte another control byte 9.4.3
When (0), DDRAM CGRAM address increments (decrements) when data written read from DDRAM CGRAM. cursor blink position moves right when incremented left when decremented. cursor blink inhibited when CGRAM accessed. 9.3.2
character indicated cursor blinks when blink displayed switching between display characters dots with period second when fosc (see Fig.7). other clock frequencies blink period equal cursor blink display simultaneously. Cursor/display shift
When entire display shifts either right (bit left (I/D during DDRAM write. Consequently, looks cursor stands still display moves. display does shift when reading from DDRAM, when writing reading from CGRAM. When display does shift. 9.4.1 Display control
display when when Display data DDRAM affected displayed immediately setting logic 9.4.2
`Cursor/display shift' moves cursor position display right left without writing reading display data. This function used correct character move cursor through display. 4-line display, cursor moves next line when passes last position line decimal). When displayed data shifted repeatedly lines shift same time; displayed characters shift into next line. Address Counter (AC) content does change only action performed shift display, increments decrements with cursor shift.
cursor displayed when inhibited when Even cursor disappears, display functions, I/D, etc. remain operation during display data write. cursor displayed using dots line (see Fig.7).
1998
Philips Semiconductors
Product specification
controller/driver
9.6.1 Function (PARALLEL MODE ONLY) Read busy flag address
PCF2105
sets interface data length. Data sent received bytes (DB7 DB0) when nibbles (DB7 DB4) when When 4-bit length selected, data transmitted cycles using parallel bus. 4-bit application left open (internal pull-ups). logic from I2C-bus interface. been logic parallel bus, programming I2C-bus interface complicated. 9.6.2
`Read busy flag address' reads Busy (BF). When indicates that internal operation progress. next instruction will executed until should checked before sending another instruction. same time, value expressed binary A[6] A[0] read out. address counter used both CGRAM DDRAM value determined previous instruction. 9.10 Write data CGRAM DDRAM
Bits number display lines. CGRAM address
`Write data' writes binary 8-bit data (D[7] D[0]) CGRAM DDRAM. Whether CGRAM DDRAM written determined previous specification CGRAM DDRAM address setting. After writing, address automatically increments decrements accordance with `entry mode set`. Only bits D[4] D[0] CGRAM data valid, bits D[7] D[5] `don't care'. 9.11 Read data from CGRAM DDRAM
`Set CGRAM address' sets bits CGRAM address (ACG Table into (binary A[5] A[0]). Data then written read from CGRAM. Only bits CGRAM address `set CGRAM address' instruction. using `set DDRAM address' instruction using auto-increment feature during CGRAM write. bits read using `read busy flag address' instruction. DDRAM address
`Read data' reads binary 8-bit data D[7] D[0] from CGRAM DDRAM. most recent `set address' instruction determines whether CGRAM DDRAM read. `read data' instruction gates content Data Register (DR) while HIGH. After goes again, internal operation increments decrements) stores data corresponding into Remark: only three instructions that update are: `Set CGRAM address' `Set DDRAM address' `Read data' from CGRAM DDRAM. Other instructions (e.g. `write data', `cursor/display shift', `clear display', `return home') will change data register content.
`Set DDRAM address' sets DDRAM address (ADD Table into (binary A[6] A[0]). Data then written read from DDRAM. Table Hexadecimal address ranges ADDRESS FUNCTION line characters lines characters lines characters
lines characters
1998
Philips Semiconductors
Product specification
controller/driver
INTERFACE MICROCONTROLLER (PARALLEL INTERFACE) PCF2105 send data either 4-bit modes 8-bit mode thus interface 8-bit microcontrollers. 8-bit mode data transferred 8-bit bytes using data lines DB0. control lines required. 4-bit mode data transferred cycles 4-bits each. higher order bits (corresponding
PCF2105
8-bit mode) sent first cycle lower order bits (DB3 8-bit mode) second cycle. Data transfer complete after 4-bit data transfers. should noted that cycles also required busy flag check. 4-bit mode selected instruction. Figs examples protocol. 4-bit mode, pads must left open-circuit. They pulled internally.
instruction write
busy flag address counter read
data register read
MGA804
Fig.13 4-bit transfer example.
1998
Philips Semiconductors
Product specification
controller/driver
PCF2105
internal
internal operation
busy
busy
instruction write
busy flag check
busy flag check
instruction write
MGA805
IR3: instruction bit. AC3: address counter bit.
Fig.14 example 4-bit data transfer timing sequence.
internal
internal operation
data instruction write
busy busy flag check
busy busy flag check
busy busy flag check
data instruction write
MGA806
Fig.15 Example busy flag check timing sequence.
1998
Philips Semiconductors
Product specification
controller/driver
INTERFACE MICROCONTROLLER (I2C-BUS INTERFACE) 11.1 Characteristics I2C-bus 11.5 Acknowledge
PCF2105
I2C-bus bidirectional, 2-line communication between different modules. lines serial data line (SDA) serial clock line (SCL). Both lines must connected positive supply pull-up resistor. Data transfer initiated only when busy. 11.2 transfer
data transferred during each clock pulse. data line must remain stable during HIGH-level period clock pulse changes data line this time will interpreted control signal (see Fig.16). 11.3 START STOP conditions
Both data clock lines remain HIGH when busy. HIGH-to-LOW transition data line, while clock HIGH defined START condition (S). LOW-to-HIGH transition data line while clock HIGH defined STOP condition (see Fig.17). 11.4 System configuration
number data bytes transferred between START STOP conditions from transmitter receiver unlimited. Each byte bits followed acknowledge bit. acknowledge HIGH signal transmitter during which time master generates extra acknowledge related clock pulse. slave receiver which addressed must generate acknowledge after reception each byte. Also master receiver must generate acknowledge after reception each byte that been clocked slave transmitter. device that acknowledges must pull-down line during acknowledge clock pulse, that line stable during HIGH period acknowledge related clock pulse (set-up hold times must taken into consideration). master receiver must signal data transmitter generating acknowledge last byte that been clocked slave. this event transmitter must leave data line HIGH enable master generate STOP condition (see Fig.19). 11.6 I2C-bus protocol
device generating message transmitter, device receiving message receiver. device that controls message master devices which controlled master slaves (see Fig.18).
Before data transmitted I2C-bus, device which should respond addressed first. addressing always carried with first byte transmitted after start procedure. I2C-bus configuration different PCF2105 read write cycles illustrated Figs
handbook, full pagewidth
data line stable; data valid change data allowed
MBC621
Fig.16 transfer.
1998
Philips Semiconductors
Product specification
controller/driver
PCF2105
handbook, full pagewidth
START condition STOP condition
MBC622
Fig.17 Definition START STOP conditions.
MASTER TRANSMITTER/ RECEIVER
SLAVE RECEIVER
SLAVE TRANSMITTER/ RECEIVER
MASTER TRANSMITTER
MASTER TRANSMITTER/ RECEIVER
MGA807
Fig.18 System configuration.
handbook, full pagewidth
DATA OUTPUT TRANSMITTER acknowledge DATA OUTPUT RECEIVER acknowledge FROM MASTER START condition clock pulse acknowledgement
MBC602
Fig.19 Acknowledgement I2C-bus.
1998
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acknowledgement from PCF2105
Philips Semiconductors
controller/driver
CONTROL BYTE
DATA
CONTROL BYTE
DATA
Fig.20 Master transmits slave receiver; write mode.
handbook, full pagewidth
slave address
bytes
byte
bytes
update data pointer
MGK848
PCF2105 slave address
Product specification
PCF2105
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acknowledgement from PCF2105
Philips Semiconductors
controller/driver
CONTROL BYTE
DATA
CONTROL
DATA
slave address
bytes
bytes
acknowledgement from PCF2105
Last data byte dummy byte (may omitted).
Fig.21 Master reads after setting word address; write word address, R/W; read data.
handbook, full pagewidth
SLAVE ADDRESS
acknowledgement from master
DATA
DATA
bytes
last byte update data pointer
MGK849
Product specification
PCF2105
Philips Semiconductors
Product specification
controller/driver
PCF2105
handbook, full pagewidth
acknowledgement from PCF2105
acknowledgement from master
acknowledgement from master
SLAVE ADDRESS
DATA
DATA
bytes
last byte update data pointer
MGK850
Fig.22 Master reads slave immediately after first byte; read mode previously defined).
LIMITING VALUES accordance with Absolute Maximum Rating System (IEC 134). SYMBOL VLCD VI(n) VO(n) II(n) IO(n) Ptot P/out Tstg logic supply voltage supply voltage input voltage pads OSC, R/W, output voltage pads R32, VLCD input current every output current every current VDD, VLCD total power dissipation power dissipation output storage temperature PARAMETER MIN. -0.5 MAX. +8.0 +150 UNIT
VLCD
HANDLING Inputs outputs protected against electrostatic discharge normal handling. However, totally safe, desirable take normal precautions appropriate handling devices (see "Handling Devices"
1998
Philips Semiconductors
Product specification
controller/driver
PCF2105
CHARACTERISTICS VLCD Tamb unless otherwise specified. SYMBOL Supplies VLCD IDD(ext) logic supply voltage supply voltage external supply current note fosc kHz; Tamb fosc kHz; Tamb II(LCD) VPOR Logic VIL(OSC) VIH(OSC) IOL(DB) IOH(DB) I2C-bus IOL(SDA) LOW-level input voltage HIGH-level input voltage leakage current input capacitance LOW-level output current note note pads logic (VSS) logic (VDD) note 0.7VDD 0.3VDD LOW-level input voltage pads R/W, HIGH-level input voltage pads R/W, LOW-level input voltage HIGH-level input voltage pull-up current pads DB0, LOW-level output current pads HIGH-level output current pads leakage current pads DB0, OSC, pads logic (VSS) pads logic (VSS) logic (VDD) 0.7VDD 0.04 -1.0 0.15 0.3VDD input current VLCD Power-on reset voltage level note note PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
1.00
1998
Philips Semiconductors
Product specification
controller/driver
PCF2105
SYMBOL outputs Ro(ROW) Ro(COL) Vbias(tol) Notes
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
output resistance pads column output resistance pads bias voltage tolerance pads
note note note
±130
outputs open-circuit; inputs VSS; inactive; internal external clock with duty factor 50%. Resets logic when VPOR. When voltages above below VSS, input current flow; this current must exceed ±0.5 Tested sample basis. Resistance output terminals (R32 with load current VLCD outputs measured time. outputs open-circuit. CHARACTERISTICS VLCD Tamb unless otherwise specified. SYMBOL ffr(LCD) fosc PARAMETER frame frequency (internal clock) oscillator frequency (external clock) CONDITIONS note MIN. TYP. MAX. UNIT
timing characteristics: Parallel Interface; notes WRITE OPERATION (WRITING DATA FROM MICROCONTROLLER PCF2105); Fig.23 Tcy(en) tW(en) tsu(A) th(A) tsu(D) th(D) Tcy(en) tW(en) tsu(A) th(A) td(D) th(D) enable cycle time enable pulse width address set-up time address hold time data set-up time data hold time
READ OPERATION (READING DATA FROM PCF2105 MICROCONTROLLER); Fig.24 enable cycle time enable pulse width address set-up time address hold time data delay time data hold time
1998
Philips Semiconductors
Product specification
controller/driver
PCF2105
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX. UNIT
Timing characteristics: I2C-bus interface; note Fig.25 fSCL tBUF tSU;STA tHD;STA tLOW tHIGH tSU;DAT tHD;DAT tSU;STO Notes timing values valid within operating supply voltage ambient temperature range referenced with input voltage swing VDD. total capacitance line fast mode I2C-bus device used standard-mode I2C-bus system, requirement tSU;DAT must then met. This will automatically case device does stretch period signal. such device does stretch period signal, must output next data line tr(max) tSU;DAT 1000 1250 (according standard-mode I2C-bus specification) before line released. device must internally provide hold time least signal (referred VIH(min) signal) order bridge undefined region falling edge SCL. maximum tHD;DAT only device does stretch tLOW signal. clock frequency tolerable spike width free time set-up time repeated START condition START condition hold time time HIGH time rise time fall time data set-up time data hold time set-up time STOP condition load capacitance each line note note note notes
1998
Philips Semiconductors
Product specification
controller/driver
TIMING DIAGRAMS
PCF2105
handbook, full pagewidth
tsu(A)
th(A) tW(en) th(A) th(D)
MGK851
tsu(D) valid data Tcy(en)
Fig.23 Parallel write operation sequence; writing data from microcontroller PCF2105.
handbook, full pagewidth
tsu(A)
th(A) tW(en)
th(A) th(D)
td(D)
Tcy(en)
MGK852
Fig.24 Parallel read operation sequence; reading data from PCF2105 microcontroller.
1998
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PROTOCOL START CONDITION (A7) (A6) ACKNOWLEDGE STOP CONDITION
handbook, full pagewidth
Philips Semiconductors
controller/driver
HD;STA HIGH t/fSCL
MGA811
SU;STO
Product specification
PCF2105
Fig.25 I2C-bus timing diagram; rise fall times refer VIH.
Philips Semiconductors
Product specification
controller/driver
APPLICATION INFORMATION
PCF2105
handbook, columns
P80CL51
PCF2105
MGK853
Fig.26 Direct connection 8-bit microcontroller; 8-bit bus.
handbook, columns
P80CL51
PCF2105
MGK854
Fig.27 Direct connection 8-bit microcontroller; 4-bit bus.
handbook, full pagewidth
VLCD
VLCD
24-CHARACTER DISPLAY (SPLIT SCREEN)
MGK855
PCF2105
Fig.28 Typical application using parallel interface.
1998
Philips Semiconductors
Product specification
controller/driver
PCF2105
handbook, full pagewidth
VLCD
VLCD
24-CHARACTER DISPLAY (SPLIT SCREEN)
PCF2105
VLCD
VLCD
12-CHARACTER DISPLAY
PCF2105
MGK856
MASTER TRANSMITTER PCF84C81
Fig.29 Application using I2C-bus interface.
1998
Philips Semiconductors
Product specification
controller/driver
17.1 4-bit operation, display using internal reset 17.3 8-bit operation, display
PCF2105
program must functions prior 4-bit operation. Table shows example. When power turned 8-bit operation automatically selected PCF2105 attempts perform first write 8-bit operation. Since nothing connected DB0, rewrite then required. However, since operation completed accesses 4-bit operation, rewrite required functions (see Table step Thus, `function set' written twice. 17.2 8-bit operation, display using internal reset
2-line display, cursor automatically moves from first second line after 40th digit first line been written. Thus, there only characters first line, DDRAM address must after character completed (see Table should noted that both lines display always shifted together, data does shift from line other. 17.4 I2C-bus operation, display
control byte required with most instructions (see Table 17.5 Initializing instruction
Table shows example 1-line display 8-bit operation. PCF2105 functions must `function set' instruction prior display. Since DDRAM store data characters, used advertising displays when combined with display shift operation. Since display shift operation changes display position only DDRAM contents remain unchanged. Display data entered first displayed when `return home' instruction performed.
power supply conditions correctly operating internal reset circuit met, PCF2105 must initialized instruction. Tables show this performed 8-bit 4-bit operation.
1998
Philips Semiconductors
Product specification
controller/driver
Table STEP Example 4-bit operation; 1-line display; using internal reset INSTRUCTION power supply (PCF2105 initialized internal reset circuit) function DISPLAY OPERATION initialized; display appears
PCF2105
sets 4-bit operation; this instance operation handled 8-bits initialization only this instruction completes with write
function sets 4-bit operation; selects display 4-bit operation starts from this point resetting needed
display control turns display cursor entire display blank after initialization
entry mode sets mode increment address shift cursor right time write DDRAM CGRAM display shifted
write data CGRAM DDRAM writes `P'; DDRAM already been selected initialization power-on cursor incremented shifted right
1998
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controller/driver
INSTRUCTION power supply (PCF2105 initialized internal reset function) function
DISPLAY
OPERATION initialized; display appears sets 8-bit operation; selects display
display control
turns display cursor entire display blank after initialization
entry mode
sets mode increment address shift cursor right time write DDRAM CGRAM; display shifted writes `P'; DDRAM already been selected initialization power-on; cursor incremented shifted right writes
write data CGRAM DDRAM
write data CGRAM DDRAM
write data CGRAM DDRAM PHILIPS_ Product specification HILIPS_ ILIPS writes writes space sets mode display shift time write PHILIPS_ writes
entry mode
write data CGRAM DDRAM
PCF2105
write data CGRAM DDRAM
This text here white force landscape pages rotated correctly when browsing through Acrobat reader.This text here _white force landscape pages rotated correctly when browsing through Acrobat reader.This text here inThis text here white force landscape pages rotated correctly when browsing through Acrobat reader. white force landscape pages 1998 Philips Semiconductors STEP INSTRUCTION DISPLAY write data CGRAM DDRAM MICROKO MICROKO ICROCO MICROCO MICROCO_ ICROCOM_ return home PHILIPS returns both display cursor original position (address Product specification writes shifts only cursor right shifts display cursor right writes (correction); display moves left shifts only cursor position left shifts only cursor position left MICROKO writes OPERATION
controller/driver
cursor display shift
cursor display shift
write data CGRAM DDRAM
cursor display shift
cursor display shift
write data CGRAM DDRAM
PCF2105
This text here white force landscape pages rotated correctly when browsing through Acrobat reader.This text here _white force landscape pages rotated correctly when browsing through Acrobat reader.This text here inThis text here white force landscape pages rotated correctly when browsing through Acrobat reader. white force landscape pages 1998 Philips Semiconductors Table STEP Example 8-bit operation; 2-line display; using internal reset
controller/driver
INSTRUCTION power supply (PCF2105 initialized internal reset function) function
DISPLAY
OPERATION initialized; display appears sets 8-bit operation; selects display
display control write data CGRAM DDRAM PHILIPS PHILIPS PHILIPS_
turns display cursor entire display blank after initialization
entry mode
sets mode increment address shift cursor right time write CGRAM DDRAM; display shifted writes `P'; DDRAM already been selected initialization power-on; cursor incremented shifted right
write data CGRAM DDRAM
writes
DDRAM address
sets DDRAM address position cursor head line
write data CGRAM DDRAM
writes
Product specification
PCF2105
write data CGRAM DDRAM
PHILIPS
writes
MICROCO_
This text here white force landscape pages rotated correctly when browsing through Acrobat reader.This text here _white force landscape pages rotated correctly when browsing through Acrobat reader.This text here inThis text here white force landscape pages rotated correctly when browsing through Acrobat reader. white force landscape pages 1998 Philips Semiconductors STEP INSTRUCTION write data CGRAM DDRAM HILIPS return home Table STEP I2C-bus start turns display cursor entire display shows character hexadecimal (blank ASCII-like character sets) Product specification selects 1-line display; pulse during acknowledge cycle starts execution instruction control byte sets following data bytes PHILIPS returns both display cursor original position MICROCOM (address writes `M'; display shifted left; first second lines shift together DISPLAY PHILIPS OPERATION sets mode display shift time write
controller/driver
MICROCO_
write data CGRAM DDRAM
ICROCOM_
Example I2C-bus operation; 1-line display; using internal reset (assuming VSS); note INSTRUCTION slave address write DISPLAY OPERATION initialized; display appears during acknowledge cycle will pulled-down PCF2105
send control byte function
function
display control
PCF2105
entry mode
sets mode increment address shift cursor right time write DDRAM CGRAM; display shifted
This text here white force landscape pages rotated correctly when browsing through Acrobat reader.This text here _white force landscape pages rotated correctly when browsing through Acrobat reader.This text here inThis text here white force landscape pages rotated correctly when browsing through Acrobat reader. white force landscape pages 1998 Philips Semiconductors STEP I2C-bus start INSTRUCTION write data DDRAM PHILIPS_ PHILIPS_ PHILIPS PHILIPS PHILIPS sets DDRAM address also returns shifted display original position; DDRAM contents unchanged; this instruction does update PHILIPS_ writes writes writes `P'; DDRAM been selected power-up; cursor incremented shifted right DISPLAY OPERATION writing data DDRAM, must logic therefore control byte needed
controller/driver
slave address write
send control byte write data
write data DDRAM
write data DDRAM
(optional stop) write step control byte
I2C-bus
I2C-bus
start slave address
return home
Product specification
PCF2105
control byte read
DDRAM content will read from following instructions; logic while still I2C-bus write mode
I2C-bus start
This text here white force landscape pages rotated correctly when browsing through Acrobat reader.This text here _white force landscape pages rotated correctly when browsing through Acrobat reader.This text here inThis text here white force landscape pages rotated correctly when browsing through Acrobat reader. white force landscape pages 1998 Philips Semiconductors STEP slave address read INSTRUCTION DISPLAY PHILIPS OPERATION during acknowledge cycle content loaded into internal I2C-bus interface shifted out; previous instruction neither `set address' `read data' been performed; therefore content unknown SCL; content loaded into interface during previous acknowledge cycle shifted over SDA; DB7; during master acknowledge content DDRAM address loaded into I2C-bus interface SCL; code letter read first; during master acknowledge code letter loaded into I2C-bus interface master acknowledge; after content I2C-bus interface register shifted internal action performed; data loaded interface register; updated; incremented cursor shifted
controller/driver
read data: master acknowledge; note
PHILIPS
read data: master acknowledge; note
PHILIPS
read data: master acknowledge; note
PHILIPS
Notes
I2C-bus stop
PHILIPS
don't care. left high-impedance microcontroller during READ acknowledge.
Product specification
PCF2105
Philips Semiconductors
Product specification
controller/driver
Table Initialization instruction; 8-bit interface (note STEP Power-on unknown state Wait after rises above VPOR DESCRIPTION
PCF2105
cannot checked before this instruction; function (interface 8-bits long) Wait
cannot checked before this instruction; function (interface 8-bits long) Wait more than
cannot checked before this instruction; function (interface 8-bits long) checked after following instructions; when checked, waiting time between instructions specified instruction time (see Table
function (interface 8-bits long); specify number display lines display Initialization ends clear display entry mode
Note don't care.
1998
Philips Semiconductors
Product specification
controller/driver
Table Initialization instruction; 4-bit interface; applicable I2C-bus operation STEP Power-on unknown state Wait after rises above VPOR DESCRIPTION
PCF2105
cannot checked before this instruction; function (interface 8-bits long) Wait
cannot checked before this instruction; function (interface 8-bits long) Wait
cannot checked before this instruction; function (interface 8-bits long) checked after following instructions; when checked, waiting time between instructions specified instruction time (see Table Initialization ends
function (set interface 4-bits long); interface 8-bits long function (interface 4-bits long) specify number display lines voltage generator characteristic display
clear display
entry mode
1998
Philips Semiconductors
Product specification
controller/driver
BONDING LOCATIONS
PCF2105
handbook, full pagewidth
5.63
PCF2105
VLCD
5.10
MGK857
Chip dimensions: approximately 5.10 5.63 Gold bump dimensions: approximately
Fig.30 Bonding locations.
1998
Philips Semiconductors
Product specification
controller/driver
Table Bonding locations (dimensions µm). coordinates referenced centre chip, Fig.30. SYMBOL 1998 -2184.5 -2024.5 -1864.5 -1704.5 -1339 -1179 -1019 -859 -699 -539 -379 -219 1061 1221 1381 1541 1701 1861 2021 2181 2350 2350 2350 2350 2350 2350 2350 2350 2350 2350 2350 -2637 -2637 -2637 -2637 -2637 -2637 -2637 -2637 -2637 -2637 -2637 -2637 -2637 -2637 -2637 -2637 -2637 -2637 -2637 -2637 -2637 -2637 -2637 -2637 -2637 -2637 -2637 -2445 -2285 -2125 -1965 -1805 -1645 -1485 -1325 -1165 -1005 -845 SYMBOL 2350 2350 2350 2350 2350 2350 2350 2350 2350 2350 2350 2350 2350 2350 2350 2350 2350 2350 2350 2350 2185 2025 1865 1705 1545 1385 1225 1065 -215 -375 -535
PCF2105
-685 -525 -365 -205 1075 1235 1395 1555 1715 1875 2035 2195 2355 2637.5 2637.5 2637.5 2637.5 2637.5 2637.5 2637.5 2637.5 2637.5 2637.5 2637.5 2637.5 2637.5 2637.5 2637.5 2637.5 2637.5 2637.5
Philips Semiconductors
Product specification
controller/driver
PCF2105
SYMBOL VLCD RECPAT RECPAT RECPAT
-695 -855 -1015 -1175 -1385 -1545 -1705 -1865 -2025 -2185 -2349 -2349 -2349 -2349 -2349 -2349 -2349 -2349 -2349 -2349 -2349 -2349 -2349 -2349 -2349 -2349 -2349 -2349 -2349 -2349 -2349 -2349 -2349 -2349 -2349 -2327.5 -2027.5 1982.5
2637.5 2637.5 2637.5 2637.5 2637.5 2637.5 2637.5 2637.5 2637.5 2637.5 2308 2148 1988 1828 1668 1508 1348 1188 1028 -233 -393 -668 -828 -1103 -1263 -1538 -1698 -1933 -2453 2427.5 -2512.5 2297.5
1998
Philips Semiconductors
Product specification
controller/driver
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
PCF2105
This data sheet contains target goal specifications product development. This data sheet contains preliminary data; supplementary data published later. This data sheet contains final product specifications.
Limiting values given accordance with Absolute Maximum Rating System (IEC 134). Stress above more limiting values cause permanent damage device. These stress ratings only operation device these other conditions above those given Characteristics sections specification implied. Exposure limiting values extended periods affect device reliability. Application information Where application information given, advisory does form part specification. LIFE SUPPORT APPLICATIONS These products designed life support appliances, devices, systems where malfunction these products reasonably expected result personal injury. Philips customers using selling these products such applications their risk agree fully indemnify Philips damages resulting from such improper sale. PURCHASE PHILIPS COMPONENTS
Purchase Philips components conveys license under Philips' patent components system provided system conforms specification defined Philips. This specification ordered using code 9398 40011.
1998
Philips Semiconductors worldwide company
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other countries apply Philips Semiconductors, International Marketing Sales Communications, Building BE-p, P.O. 218, 5600 EINDHOVEN, Netherlands, Fax. 24825 Philips Electronics N.V. 1998
SCA60
rights reserved. Reproduction whole part prohibited without prior written consent copyright owner. information presented this document does form part quotation contract, believed accurate reliable changed without notice. liability will accepted publisher consequence use. Publication thereof does convey imply license under patent- other industrial intellectual property rights.
Printed Netherlands
415106/1200/02/pp48
Date release: 1998
Document order number:
9397 04198

PCF2105 controller/driver Product specification Supersedes data 1

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