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PI7C7100 3-Port Bridge
Pericom Semiconductor Corporation
Complete Interface Solution
2380 Bering Drive, Jose, California 95131 Telephone: 1-877-PERICOM, (1-877-737-4266) Fax: (408) 435-1100, E-mail: nolimits@pericom.com Internet: http://www.pericom.com
2000 Pericom Semiconductor Corporation
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LIFE SUPPORT POLICY
Pericom Semiconductor Corporations products authorized critical components life support devices systems unless specific written agreement pertaining such intended executed between manufacturer officer PSC. 1.Life support devices systems devices systems which: intended surgical implant into body support sustain life whose failure perform, when properly used accordance with instructions provided labeling, reasonably expected result significant injury user. critical component component life support device system whose failure perform reasonably expected cause failure life support device system, affect safety effectiveness.Pericom Semiconductor Corporation reserves right make changes products specifications time, without notice, order improve design performance supply best possible product. Pericom Semiconductor does assume responsibility circuitry described other than circuitry embodied Pericom Semiconductor product. Company makes representations that circuitry described herein free from patent infringement other rights third parties which result from use. license granted implication otherwise under patent, patent rights other rights, Pericom Semiconductor Corporation. other trademarks their respective companies.
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Table Contents
3.2.1 3.2.2 3.2.3 3.2.4 3.2.5 3.2.6 4.5.1 4.5.2 4.5.3 4.5.4 4.5.5 4.5.6 4.6.1 4.6.2 4.6.3 4.6.4 4.6.5 4.6.6 4.7.1 4.7.2 4.7.3 4.7.4 4.8.1 4.8.2 4.8.3 4.8.4 Introduction/Product Features PI7C7100 Block Diagram Signal Definitions Signal Types Signals Primary Interface Signals Secondary Interface Signals Clock Signals Miscellaneous Signals JTAG Boundary Scan Signals Power Ground Operation Types Transactions Single Address Phase Device Select (DEVSEL#) Generation Data Phase Write Transactions Posted Write Transactions Memory Write Invalidate Transactions Delayed Write Transactions Write Transaction Address Boundaries Buffering Multiple Write Transactions Fast Back-to-Back Write Transactions Read Transactions Prefetchable Read Transactions Non-prefetchable Read Transactions Read Pre-fetch Address Boundaries Delayed Read Requests Delayed Read Completion with Target Delayed Read Completion Initiator Configuration Transactions Type Access PI7C7100 Type Type Conversion Type Type Forwarding Special Cycles Transaction Termination Master Termination Initiated PI7C7100 Master Abort Received PI7C7100 Target Termination Received PI7C7100 Target Termination Initiated PI7C7100
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5.2.1 5.2.2 5.3.1 5.3.2 5.4.1 5.4.2 7.2.1 7.2.2 7.2.3 7.2.4 9.2.1 9.2.2 9.2.3 10.1 10.2 11.1 11.2 11.3 12.1 12.2 13.1 13.2
Address Decoding Address Ranges Address Decoding Base Limit Address Registers Mode Memory Address Decoding Memory-Mapped Base Limit Address Registers Prefetchable Memory Base Limit Address Registers Support Mode Snoop Mode Transaction Ordering Transactions Governed Ordering Rules General Ordering Guidelines Ordering Rules Data Synchronization Error Handling Address Parity Errors Data Parity Errors Configuration Write Transactions Configuration Space Read Transactions Delayed Write Transactions Posted Write Transactions Data Parity Error Reporting Summary System Error (SERR#) Reporting Exclusive Access Concurrent Locks Acquiring Exclusive Access across PI7C7100 Ending Exclusive Access Arbitration Primary Arbitration Secondary Arbitration Secondary Arbitration Using Internal Arbiter Secondary Arbitration Using External Arbiter Parking Clocks Primary Clock Inputs Secondary Clock Outputs Reset Primary Interface Reset Secondary Interface Reset Chip Reset Supported Commands Primary Interface Secondary Interface Configuration Registers Config Register Config Register
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13.2.1 13.2.2 13.2.3 13.2.4 13.2.5 13.2.6 13.2.7 13.2.8 13.2.9 13.2.10 13.2.11 13.2.12 13.2.13 13.2.14 13.2.15 13.2.16 13.2.17 13.2.18 13.2.19 13.2.20 13.2.21 13.2.22 13.2.23 13.2.24 13.2.25 13.2.26 13.2.27 13.2.28 13.2.29 13.2.30 13.2.31 13.2.32 13.2.33 13.2.34 13.2.35 13.2.36 13.2.37 13.2.38 13.2.39 13.2.40 13.2.41 13.2.42 13.2.43 13.2.44 13.2.45 13.2.46 13.2.47 13.2.48 13.2.49 13.2.50
Config Register 2:Vendor Register (read only, 15-0; offset 00h) Config Register Device Register (read only, 31-16; offset 00h) Config Register Device Register (read only, 31-16; offset 00h) Config Register Command Register (bit 15-0; offset 04h) Config Register Command Register (bit 15-0; offset 04h) Config Register Status Register (for primary bus, 31-16; offset 04h) Config Register Revision Register (read only, 7-0; offset 08h) Config Register Class Code Register (read only, 31-8; offset 08h) Config Register Cache Line Size Register (read/write, 7-0; offset 0Ch) Config Register Primary Latency Timer Register (read/write, 15-8; offset 0Ch) Config Register Primary Latency Timer Register (read/write, 15-8; offset 0Ch) Config Register Header Type Register (read only, 23-16; offset 0Ch) Config Register Header Type Register (read only, 23-16; offset 0Ch) Config Register Primary Number Register (read/write, 7-0; offset 18h) Config Register Primary Number Register (read/write, 7-0; offset 18h) Config Register Secondary Number Register (read/write, 15-8; offset 18h) Config Register Subordinate Number Register (read/write, 23-16; offset 18h) Config Register Secondary Latency Timer (read/write, 31-24; offset 18h) Config Register Base Register (read/write, 7-0; offset 1Ch) Config Register Limit Register (read/write, 15-8; offset 1Ch) Config Register Secondary Status Register (bit 31-16; offset 1Ch) Config Register Memory Base Register (read/write, 15-0; offset 20h) Config Register Memory Limit Register (read/write, 31:16; offset 20h) Config Register Prefetchable Memory Base Register (read/write, 15-0;offset 24h) Config Register Prefetchable Memory Limit Register (read/write, 31-16; offset 24h) Config Register Base Address Upper Bits Register (read/write, 15-0; offset 30h) Config Register Limit Address Upper Bits Register (read/write, 31-16; offset 30h) Config Register Subsystem Vendor (read/write, 15-0; offset 34h) Config Register Subsystem (read/write, 31-16; offset 34h) Config Register Interrupt Register (read only, 15-8; offset 3Ch) Config Register Bridge Control Register (bit 31-16; offset 3Ch) Config Register Diagnostic/Chip Control Register (bit 15-0; offset 40h) Config Register Arbiter Control Register (bit 31-16; offset 40h) Config Register Primary Prefetchable Memory Base Register (Read/Write, 15-0; offset 44h) Config Register Primary Prefetchable Memory Base Register (Read/Write, 15-0; offset 44h) Config Register Primary Prefetchable Memory Limit Register (Read/Write, 31-16; offset 44h) Config Register Primary Prefetchable Memory Limit Register (Read/Write, 31-16; offset 44h) Config Register P_SERR# Event Disable Register (bit 7-0; offset 64h) Config Register Secondary Clock Control Register (bit 15-0; offset 68h) Config Register Secondary Clock Control Register (bit 15-0; offset 68h) Config Register Non-Posted Memory Base Register (read/write, 15-0; offset 70h) Config Register Non-Posted Memory Limit Register (read/write, 31-16; offset 70h) Config Register Port Option Register (bit 15-0; offset 74h) Config Register Port Option Register (bit 15-0; offset 74h) Config Register Master Timeout Counter Register (read/write, 31-16; offset 74h) Config Register Retry Counter Register (read/write, 31-0; offset 78h) Config Register Sampling Timer Register (read/write, 31-0; offset 7Ch) Config Register Successful Read Count Register (read/write, 31-0; offset 80h) Config Register Successful Write Count Register (read/write, 31-0; offset 84h) Config Register Successful Memory Read Count Register (read/write, 31-0; offset 88h)
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13.2.51 13.2.52 13.2.53 13.2.54 13.2.55 14.1 14.2 14.3 14.3.1 14.3.2 14.3.3 14.3.4 15.1 15.1.1 15.1.2 15.2 15.3 15.4 15.5 15.6 16.1 16.2 16.3 16.4 17.1
Config Register Successful Memory Write Count Register (read/write, 31-0; offset 8Ch) Config Register Primary Successful Read Count Register (read/write, 31-0; offset 90h) Config Register Primary Successful Write Count Register (read/write, 31-0; offset 94h) Config Register Primary Successful Memory Read Count Register (read/write, 31-0; offset 98h) Config Register Primary Successful Memory Write Count Register (read/write, 31-0; offset 9Ch) Bridge Behavior Bridge Actions Various Cycle Types Transaction Ordering Abnormal Termination (Initiated Bridge Master) Master Abort Parity Error Reporting Reporting Parity Errors Secondary IDSEL mapping IEEE 1149.1 Compatible JTAG Controller Boundary Scan Architecture Pins Instruction Register Boundary Scan Instruction Test Data Registers Bypass Register Boundary-Scan Register Controller Electrical Timing Specifications Maximum Ratings 3.3V Specifications 3.3V Specifications Primary Secondary buses clock timing 256-Pin PBGA Package Part Number Ordering Information
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List Figures
1-1. 1-2. 1-3. 2-1. 9-1. 15-1. 17-1. PI7C7100 System Board PI7C7100 Redundant Applications PI7C7100 Network Switching PI7C7100 Block Diagram Secondary Arbiter Example Test Access Port Block Diagram 256-Pin PBGA Package Drawing
List Tables
4-1. 4-2. 4-3. 4-4. 4-5. 4-6. 4-7. 4-8. 4-9. 6-1. 7-1. 7-2. 7-3. 7-4. 7-5. 7-6. 7-7. 15-1. 15-2. Transaction Write Transaction Forwarding Write Transaction Disconnect Address Boundaries Read Pre-fetch Address Boundaries Read Transaction Pre-fetching Device Number IDSEL S1_AD S2_AD Mapping Posted Write Target Termination Response Responses Posted Write Target Termination Responses Delayed Read Target Termination Summary Tranaction Ordering Setting Primary Interface Detected Parity Error Setting Secondary Interface Detected Parity Error Setting Primary Interface Data Parity Detected Setting Secondary InterfaceData Parity Detected Assertion P_PERR# Assertion S_PERR# Assertion P_SERR# Data Parity Errors Pins JTAG Boundary Register Order
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Appendix Timing Diagrams
Configuration Read Transaction Configuration Write Transaction .A-3 Type Type Configuration Read Transaction .A-3 Type Type Configuration Write Transaction .A-4 Upstream Type Special Cycle Transaction Downstream Type Special Cycle Transaction Downstream Type Type Configuration Read Transaction .A-5 Downstream Type Type Configuration Write Transaction .A-6 Upstream Delayed Burst Memory Read Transaction .A-6 Downstream Delayed Burst Memory Read Transaction .A-7 Downstream Delayed Memory Read Transaction (P/33MHz S/33MHz) Downstream Delayed Memory Read Transaction (S2/33MHz S1/33MHz) .A-8 Downstream Delayed Memory Read Transaction (S1/33MHz S2/33MHz) .A-8 Upstream Delayed Memory Read Transaction (S/33MHz P/33MHz) .A-9 Downstream Posted Memory Write Transaction (P/33MHz S/33MHz) Downstream Posted Memory Write Transaction (S2/33MHz S1/33MHz) A-10 Downstream Posted Memory Write Transaction (S1/33MHz S2/33MHz) A-10 Upstream Posted Memory Write Transaction (S/33MHz P/33MHz) A-11 Downstream Flow-Through Posted Memory Write Transaction (P/33MHz S/33MHz) A-11 Downstream Flow-Through Posted Memory Write Transaction (S2/33MHz S1/33MHz) A-12 Downstream Flow-Through Posted Memory Write Transaction (S1/33MHz S2/33MHz) A-12 Upstream Flow-Through Posted Memory Write Transaction (S/33MHz P/33MHz) A-13 Downstream Delayed Read Transaction A-13 Downstream Delayed Read Transaction (S2/33MHz S1/33MHz) A-14 Downstream Delayed Read Transaction (S1/33MHz S2/33MHz) A-14 Downstream Delayed Read Transaction (S/33MHz P/33MHz) A-15 Downstream Delayed Write Transaction A-15 Downstream Delayed Write Transaction (S2/33MHz S1/33MHz) A-16 Downstream Delayed Write Transaction (S1/33MHz S2/33MHz) A-16 Upstream Delayed Write Transaction A-17
Appendix Evaluation Board User's Manual
General Information Frequently Asked Questions
Appendix Three-Port Bridge Evaluation Board Schematics
Chip Edge Connector Secondary Secondary View
viii
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Introduction Product Description
PI7C7100 first triple port PCI-to-PCI Bridge device designed fully compliant with 32-bit, 33MHz implementation Local Specification, Revision 2.1. PI7C7100 supports only synchronous transactions between devices primary secondary buses operating MHz. primary secondary buses also operate concurrent mode, resulting added increase system performance. Concurrent operation off-loads isolates unnecessary traffic from primary bus; thereby enabling master target device same secondary communicate even while primary busy.
Product Features
32-bit Primary Secondary Ports three ports compliant with Local Specification, Revision Compliant with PCI-to-PCI Bridge Architecture Specification, Revision 1.0. memory commands Type Type configuration conversion Type Type configuration forwarding Type configuration-write special cycle conversion Concurrent primary secondary operation independent intra-secondary port channel reduce traffic primary port Provides internal arbitration sets eight secondary masters Programmable 2-level priority arbiter Disable control external arbiter Supports posted write buffers directions Three byte FIFOs Enhanced address decoding 32-bit address range 32-bit memory-mapped address range addressing palette snooping ISA-aware mode legacy support first 64KB address range Interrupt Handling interrupts routed through external interrupt concentrator Supports system transaction ordering rules Hot-plug support secondary buses 3-State control output buffers IEEE 1149.1 JTAG interface support 3.3V core; 3.3V interface with Tolerant 256-pin plastic package
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System Memory PI7C7100 Device Device
PI7C7100 3-Port Bridge
Figure 1-1. PI7C7100 System Board
Master Controller
System Primary
Figure 1-2. PI7C7100 Redundant Application
Slot
Slot
Redundant Controller
System Primary
PI7C7100
PI7C7100
Core Logic
32/33
Fast Ethernet Internal Slot
Cache
32/33
PI7C7100
PI7C7100
PI7C7100
Daughter Board Isolate Traffic
Figure 1-3. PI7C7100 Network Switching
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PI7C7100 Block Diagram
Configuration Register Arbiter
Transaction Queue Primary Primary Interface
Secondary Interface
Secondary
Transaction Queue Secondary
Transaction Queue
Secondary Interface
Configuration Register
Arbiter
Figure 2-1. PI7C7100 Block Diagram
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Signal Definitions
Signal Types
Input (3.3V, tolerant) Input (3.3V, tolerant) with weak pull-up 3-state bidirectional (3.3V, tolerant) Output (3.3V) PSTS Sustained 3-state bidirectional (Active signal which must driven inactive cycle before being 3-stated ensure HIGH performance shared signal line) 3-state Output Output which either drives (active state) 3-stated CMOS Input CMOS Input with weak pull-up CMOS Input with weak pull-down CMOS 3-state Output Note: I/Os operate 3.3V
Signals (Note: Signal name that ends with character active LOW.)
3.2.1 Primary Interface Signals
P_AD [31:0] W10, V10, Y11, V11, U11, Y12, W12, V12, V16, W16, Y16, W17, Y17, U18, W18, Y18, U19, W19, Y19, U20, V20, Y20, T17, U12, U16, escription Primary Address/D ata. Multi plexed address data bus. Address cated P_FRAME# asserti data stable vali when P_IRD asserted read data stable vali when P_TRD asserted. transferred clock edges when both P_IRD P_TRD asserted. dle, PI7C 7100 P_AD vali logi level when P_GNT# asserted.
BE[3:0]
Primary ommand/B Enables. Multi plexed command byte enable eld. address phase, ator transacti type these After that ator byte enables duri data phases. dle, PI7C 7100 BE[3:0] vali logi level when P_GNT# asserted. Primary Parity. Pari even across P_AD [31:0], BE[3:0], P_PAR even number '1's). P_PAR nput vali stable cycle after address phase cated asserti P_FRAME#) address pari data phases, P_PAR nput vali clock after P_IRD asserted. read data phase, P_PAR output vali clock after P_TRD asserted. gnal P_PAR -stated cycle after 3-stated. dle, PI7C 7100 PPAR vali logi level when P_GNT# asserted. Primary (Activ LOW). ator transacti cate begi durati access. de-asserti P_FRAME# cates data phase requested ator. Before 3-stated, de-asserted state cycle. Primary (Activ LOW). ator transacti cate complete current data phase mary Once asserted data phase, de-asserted unti data phase. Before 3-stated, de-asserted state cycle. Primary (Activ LOW). target transacti cate complete current data phase mary Once asserted data phase, de-asserted unti data phase. Before 3-stated, de-asserted state cycle.
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P_PAR
P_FRAME#
PSTS
P_IRD
PSTS
P_TRD
PSTS
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3.2.1 Primary Interface Signals (continued)
PSTS escription Primary Select (Activ LOW). Asserted target cati that devi accepti transacti master, PI7C 7100 asserti gnal cycles P_FRAME# asserti otherwi termi nate master abort. Before 3-stated, de-asserted state cycle. Primary STOP (Activ LOW). Asserted target cati that target requesti ator stop current transacti Before 3-stated, de-asserted state cycle. Primary (Activ LOW). Asserted master multi transacti complete. Primary Select. Used select Type confi gurati access PI7C 7100 confi gurati space. Primary Parity Error (Activ LOW). Asserted when data pari error detected data recei mary nterface. Before 3-stated, deasserted state cycle. Primary stem Error (Activ LOW). devi cate system error condi PI7C 7100 Address pari error Posted data pari error target Secondary S1_SERR# S2_SERR# asserted Master abort duri posted transacti Target abort duri posted transacti Posted transacti scarded elayed request scarded elayed read request scarded elayed transacti master meout gnal requi external pull-up resi stor proper operati Primary equest (Activ LOW). asserted PI7C 7100 cate that wants start transacti mary bus. PI7C 7100 de-asserts least clock cycles before asserti agai Primary Grant (Activ LOW). When asserted, PI7C 7100 access mary bus. P_GNT# asserted, PI7C 7100 P_AD P_PAR vali logi levels. Primary ESET (Activ LOW). When P_RESET# acti gnals should asynchronously 3-stated. Primary FIFO (Activ LOW). When P_FLUSH# acti mary FIFO(s) cleared nvali date mary transacti ons). gnal should pulled stati gh." eserv Future Must ground.
P_STOP#
PSTS
P_LOC P_ID P_PERR#
PSTS PSTS
P_SERR#
P_REQ#
P_GNT#
P_RESET# P_FLUSH#
P_M66EN
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3.2.2 Secondary Interface Signals
S1_AD [31:0], F19, F17, G20, G19, L20, L19, L18, M20, M19, M17, N20, N19, N18, N17, P17, R20, R19, R18, T20, E20, G18, K17, escription Secondary Address/D ata. Multi plexed address data bus. Address cated S1_FRAME# S2_FRAME# asserti data stable vali when S1_IRD S2_IRD asserted read data stable vali when S1_TRD S2_TRD asserted. transferred clock edges when both S1_IRD S1_TRD S2_IRD S2_TRD asserted. dle, PI7C 7100 S1_AD S2_AD vali logi level when S1_GNT# S2_GNT# asserted respecti vely.
S2_AD [31:0]
S1_C BE[3:0], S2_C BE[3:0]
Secondary ommand/B Enables. Multi plexed command byte enable eld. address phase, ator transacti type these After that ator byte enables duri data phases. dle, PI7C 7100 S1_C BE[3:0] S2_C BE[3:0] vali logi level when nternal grant asserted. Secondary Parity. Pari even across S1_AD [31:0], S1_C BE[3:0], S1_PAR S2_AD [31:0], S2_C BE[3:0], S2_PAR even number '1's). S1_PAR S2_PAR nput vali stable cycle after address phase cated asserti S1_FRAME# S2_FRAME#) address pari data phases, S1_PAR S2_PAR nput vali clock after S1_IRD S2_IRD asserted. read data phase, S1_PAR S2_PAR output vali clock after S1_TRD S2_TRD asserted. gnal S1_PAR S2_PAR 3-stated cycle after S1_AD S2_AD -stated. dle, PI7C 7100 S1_PAR S2_PAR vali logi level when nternal grant asserted. Secondary (Activ LOW). ator transacti cate begi durati access. e-asserti S1_FRAME# S2_FRAME# cates data phase requested ator. Before 3-stated, de-asserted state cycle. Secondary (Activ LOW). ator transacti cate complete current data phase mary Once asserted data phase, de-asserted unti data phase. Before 3-stated, de-asserted state cycle. Secondary (Activ LOW). target transacti cate complete current data phase mary Once asserted data phase, de-asserted unti data phase. Before 3-stated, de-asserted state cycle. Secondary Select (Activ LOW). Asserted target cati that devi accepti transacti master, PI7C 7100 asserti gnal cycles S1_FRAME# S2_FRAME# asserti otherwi termi nate master abort. Before 3-stated, de-asserted state cycle.
S1_PAR, S2_PAR
S1_FRAME#, S2_FRAME#
H20,
PSTS
S1_IRD S2_IRD
H19,
PSTS
S1_TRD S2_TRD
H18,
PSTS
PSTS
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3.2.2 Secondary Interface Signals (continued)
S1_STOP#, S2_STOP# PSTS escription Secondary STOP (Activ LOW). Asserted target cati that target requesti ator stop current transacti Before 3-stated, de-asserted state cycle. Secondary (Activ LOW). Asserted master multi transacti complete. Secondary Parity Error (Activ LOW). Asserted when data pari error detected data recei secondary nterface. Before 3-stated, de-asserted state cycle. Secondary stem Error (Activ LOW). devi cate system error condi Secondary equest (Activ LOW). asserted external devi cate that wants start transacti Secondary bus. nput externally pulled through resi stor
S1_LOC S2_LOC S1_PERR#, S2_PERR# S1_SERR#, S2_SERR# S1_REQ#[7:0],
B11, A12, B12,
PSTS PSTS
S2_REQ#[7:0]
S1_GNT#[7:0],
S2_GNT#[7:0]
Secondary Grant (Activ LOW). PI7C 7100 asserts access secondary bus. PI7C 7100 de-asserts least clock cycles before asserti agai S1_GNT# S2_GNT# asserted, PI7C 7100 S1_AD S1_C S1_PAR S2_AD S2_C S2_PAR vali logi levels.
S1_RESET#, S2_RESET#
Secondary ESET (Activ LOW). Asserted when followi condi met: gnal P_RESET# asserted. Secondary reset control regi ster confi gurati space set. When asserted, control gnals 3-stated zeros S1_AD S1_C S1_PAR S2_AD S2_C S2_PAR. Secondary Enable (Activ When S1_EN S2_EN nacti secondary asynchronously 3-stated. eserv Future Must ground. Secondary entral Function ontrol Pin. When LOW, enables nternal arbi ter. When HIGH, external arbi must used. S1_REQ0# S2_REQ0# reconfi gured secondary grant nput, S1_GNT0# S2_GNT0# reconfi gured secondary request output.
S1_EN, S_M66EN
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3.2.3 Clock Signals
escription Primary lock Input. Provi transacti mary nterface. Secondary lock Output. Provi secondary clocks phase synchronous
LKOUT [15:0] N3,M4, J1,A11,
3.2.4 Miscellaneous Signals
BYPASS PLL_S_C LKIN escription eserv Future Must HIGH. eserv Future Must LOW. Secondary Test lock Input. should normal mode. also secondary clock nput secondary buses both AN_TM# AN_EN connected logi "1". Full-scan Test Mode enable (Activ LOW). When AN_TM# acti twelve scan chai enabled. scan clock scan nputs outputs follows: S1_REQ[7], S1_REQ[6], S1_REQ[5], S1_REQ[4], S1_REQ[3], S1_REQ[2], S2_REQ[7], S2_REQ[6], S2_REQ[5], S2_REQ[4], S2_REQ[3], S2_REQ[2] S1_GNT[7], S1_GNT[6], S1_GNT[5], S1_GNT[4], S1_GNT[3], S1_GNT[2], S2_GNT[7], S2_GNT[6], S2_GNT[5], S2_GNT[4], S2_GNT[3], S2_GNT[2] respecti vely Full-scan Enable ontrol. When AN_EN LOW, full-scan operati AN_TM# acti When AN_EN HIGH, full-scan parallel operati AN_TM# acti AN_EN should normal mode. AN_TM# AN_EN connected logi "1", LKIN clock source nternal secondary clock. AN_TM# connected logi AN_EN connected logi "0", clock source nternal secondary clock. ote: power-up, AN_EN reset gnal on-chi PLL. eserv Future eserv
AN_TM#
AN_EN
MPO1 Reserved
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3.2.5 JTAG Boundary Scan Signals
escription Test lock. Used clock state nformati data PI7C 7100 duri boundary scan. Test Mode Select. Used control state Test Access Port controller. Test Output. When ANEN HIGH used conjuncti data Test Access Port (TAP) seri stream. Test Input. When ANEN HIGH used conjuncti data nstructi Test Access Port (TAP) seri stream. Test eset. Acti gnal reset Test Access Port (TAP) controller state.
TRST#
3.2.6 Power Ground
F18, L17, P19, U10, V15, G17, H17, K19, M18, P18, T18, U14, escription +3.3V igital Power
igital Ground
AGND
Analog 3.3V Analog Ground
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Operation
This chapter offers information about transactions, transaction forwarding across PI7C7100, transaction termination. PI7C7100 three 128-byte buffers buffering upstream downstream transactions. These hold addresses, data, commands, byte enables used both read write transactions.
Types Transactions
This section provides summary transactions performed PI7C7100. Table lists command code name each transaction. Master Target columns indicate support each transaction when PI7C7100 initiates transactions master, primary secondary (S1, buses, when PI7C7100 responds transactions target, primary secondary (S1, buses.
Table 4-1. Transactions
Transactions Initiates Master Primary 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Interrupt acknowledge Speci cycle read Reserved Reserved Memory read Memory Reserved Reserved onfi gurati read onfi gurati Memory read multi address cycle Memory read Memory nvali date (Type only) Secondary esponds Target Primary Secondary (Type only)
indicated Table following commands supported PI7C7100: PI7C7100 never initiates transaction with reserved command code and, target, PI7C7100 ignores reserved command codes. PI7C7100 does generate interrupt acknowledge transactions. PI7C7100 ignores interrupt acknowledge transactions target. PI7C7100 does respond special cycle transactions. PI7C7100 cannot guarantee delivery special cycle transaction downstream buses because broadcast nature special cycle command inability control transaction target. generate special cycle transactions other buses, either upstream downstream, Type configuration write must used. PI7C7100 neither generates Type configuration transactions primary responds Type configuration transactions secondary buses. PI7C7100 does support (Dual Address Cycle) transactions.
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Single Address Phase
32-bit address uses single address phase. This address driven P_AD[31:0], command driven P_CBE[3:0]. PI7C7100 supports linear increment address mode only, which indicated when lowest address bits equal zero. either lowest address bits nonzero, PI7C7100 automatically disconnects transaction after first data transfer.
Device Select (DEVSEL#) Generation
PI7C7100 always performs positive address decoding (medium decode) when accepting transactions either primary secondary buses. PI7C7100 never does subtractive decode.
Data Phase
address phase transaction followed more data phases. data phase completed when IRDY# either TRDY# STOP# asserted. transfer data occurs only when both IRDY# TRDY# asserted during same clock cycle. last data phase transaction indicated when FRAME# de-asserted both TRDY# IRDY# asserted, when IRDY# STOP# asserted. Section further discussion transaction termination. Depending command type, PI7C7100 support multiple data phase transactions. detailed description PI7C7100 imposes disconnect boundaries, Section 4.5.4 write address boundaries Section 4.6.3 read address boundaries.
Write Transactions
Write transactions treated either posted write delayed write transactions. Table shows method forwarding used each type write operation.
Table 4-2. Write Transaction Forwarding
Transaction Memory Memory nvali date Type confi gurati Forwarding Posted Posted elayed elayed
timing diagrams, Figures 15-22 27-30 Appendix
4.5.1 Posted Write Transactions
Posted write forwarding used Memory Write Memory Write Invalidate transactions. When PI7C7100 determines that memory write transaction forwarded across bridge, PI7C7100 asserts DEVSEL# with medium timing TRDY# same cycle, provided that enough buffer space available posted memory write queue address least DWORD data. Under this condition, PI7C7100 accepts write data without obtaining access target bus. PI7C7100 accept DWORD write data every clock cycle. That target wait state inserted. write data stored internal posted write buffers subsequently delivered target. PI7C7100 continues accept write data until following events occurs: initiator terminates transaction de-asserting FRAME# IRDY#. internal write address boundary reached, such cache line boundary aligned boundary, depending transaction type. posted write data buffer fills
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When last events occurs, PI7C7100 returns target disconnect requesting initiator this data phase terminate transaction. Once posted write data moves head posted data queue, PI7C7100 asserts request target bus. This occur while PI7C7100 still receiving data initiator bus. When grant target received target detected idle condition, PI7C7100 asserts FRAME# drives stored write address target bus. following cycle, PI7C7100 drives first DWORD write data continues transfer write data until write data corresponding that transaction delivered, until target termination received. long write data exists queue, PI7C7100 drive DWORD write data each clock cycle; that master wait states inserted. write data flowing through PI7C7100 initiator stalls, PI7C7100 have insert wait states target queue empties. PI7C7100 ends transaction target when following conditions met: posted write data been delivered target. target returns target disconnect target retry (PI7C7100 starts another transaction deliver rest write data). target returns target abort (PI7C7100 discards remaining write data). master latency timer expires, PI7C7100 longer target grant (PI7C7100 starts another transaction deliver remaining write data). Section 4.8.3.2 provides detailed information about PI7C7100 responds target termination during posted write transactions.
4.5.2 Memory Write Invalidate Transactions
Posted write forwarding used Memory Write Invalidate transactions. PI7C7100 always converts Memory Write Invalidate transactions Memory Write transactions. PI7C7100 disconnects Memory Write Invalidate commands aligned cache line boundaries. cache line size value cache line size register gives number DWORD cache line. value cache line size register does meet memory write invalidate conditions, PI7C7100 returns target disconnect initiator either cache line boundary when posted write buffer fills. When Memory Write Invalidate transaction disconnected before cache line boundary reached, typically because posted write buffer fills, transaction converted Memory Write transaction.
4.5.3 Delayed Write Transactions
Delayed write forwarding used write transactions Type configuration write transactions. delayed write transaction guarantees that actual target response returned back initiator without holding initiating wait states. delayed write transaction limited single DWORD data transfer. When write transaction first detected initiator bus, PI7C7100 forwards delayed transaction, PI7C7100 claims access asserting DEVSEL# returns target retry initiator. During address phase, PI7C7100 samples command, address, address parity cycle later. After IRDY# asserted, PI7C7100 also samples first data DWORD, byte enable bits, data parity. This information placed into delayed transaction queue. transaction queued only other existing delayed transactions have same address command, delayed transaction queue full. When delayed write transaction moves head delayed transaction queue ordering constraints with posted data satisfied. PI7C7100 initiates transaction target bus. PI7C7100 transfers write data target. PI7C7100 receives target retry response write transaction target bus, continues repeat write transaction until data transfer completed, until error condition encountered. PI7C7100 unable deliver write data after 224(default) 232(maximum) attempts, PI7C7100 ceases further write attempts returns target abort initiator. delayed transaction removed from delayed transaction queue. PI7C7100 also asserts P_SERR# primary SERR# enable command register. Section information assertion P_SERR#. When initiator repeats same write transaction (same command, address, byte enable bits, data), completed delayed transaction head queue, PI7C7100
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claims access asserting DEVSEL# returns TRDY# initiator, indicate that write data transferred. initiator requests multiple DWORD, PI7C7100 also asserts STOP# conjunction with TRDY# signal target disconnect. Note that only those bytes write data with valid byte enable bits compared. byte enable bits turned (driven HIGH), corresponding byte write data compared. initiator repeats write transaction before data been transferred target, PI7C7100 returns target retry initiator. PI7C7100 continues return target retry initiator until write data delivered target, until error condition encountered. When write transaction repeated, PI7C7100 does make entry into delayed transaction queue. Section 4.8.3.1 provides detailed information about PI7C7100 responds target termination during delayed write transactions. PI7C7100 implements discard timer that starts counting when delayed write completion head delayed transaction queue. initial value this timer values, selectable through both primary secondary master timeout bits bridge control register. initiator does repeat delayed write transaction before discard timer expires, PI7C7100 discards delayed write transaction from delayed transaction queue. PI7C7100 also conditionally asserts P_SERR# (see Section 7.4).
4.5.4 Write Transaction Address Boundaries
PI7C7100 imposes internal address boundaries when accepting write data. aligned address boundaries used prevent PI7C7100 from continuing transaction over device address boundary provide upper limit maximum latency. PI7C7100 returns target disconnect initiator when reaches aligned address boundaries under conditions shown Table Table 4-3. Write Transaction Disconnect Address Boundaries
Transaction elayed Posted memory Posted memory Posted memory nvali date Posted memory nvali date ondition Memory sconnect control
Aligned Address oundary sconnects after data transfer gned address boundary sconnects cache boundary gned address boundary cache boundary, where cache boundary reached less than free WORD posted buffer space remai 16-D WORD gned address boundary
Memory sconnect control ache equal ache
Posted memory nvali date
ache
Note Memory-write-disconnect-control chip control register offset configuration space.
4.5.5 Buffering Multiple Write Transactions
PI7C7100 continues accept posted memory write transactions long space least DWORD data posted write data buffer remains. posted write data buffer fills before initiator terminates write transaction, PI7C7100 returns target disconnect initiator. Delayed write transactions posted long least open entry delayed transaction queue exists. Therefore, several posted delayed write transactions exist data buffers same time. Chapter information about multiple posted delayed write transactions ordered.
4.5.6 Fast Back-to-Back Write Transactions
PI7C7100 recognize post fast back-to-back write transactions. When PI7C7100 cannot accept second transaction because buffer space limitations, returns target retry initiator.
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Read Transactions
Delayed read forwarding used read transactions crossing PI7C7100. Delayed read transactions treated either prefetchable non-prefetchable. Table shows read behavior, prefetchable non-prefetchable, each type read operation. Timing diagrams, Figures 11-14 23-26 Appendix
4.6.1 Prefetchable Read Transactions
prefetchable read transaction read transaction where PI7C7100 performs speculative DWORD reads, transferring data from target before requested from initiator. This behavior allows prefetchable read transaction consist multiple data transfers. However, byte enable bits cannot forwarded data phases done single data phase non-prefetchable read transaction. prefetchable read transactions, PI7C7100 forces byte enable bits turned data phases. Prefetchable behavior used memory read line memory read multiple transactions, well memory read transactions that fall into prefetchable memory space. amount data that pre-fetched depends type transaction. amount pre-fetching also affected amount free buffer space available PI7C7100, read address boundaries encountered. Pre-fetching should used those read transactions that have side effects target device, that control status registers, FIFOs, target devices base address register registers indicate memory address region prefetchable.
4.6.2 Non-prefetchable Read Transactions
non-prefetchable read transaction read transaction where PI7C7100 requests only DWORD from target disconnects initiator after delivery first DWORD read data. Unlike prefetchable read transactions, PI7C7100 forwards read byte enable information data phase. Non-prefetchable behavior used configuration read transactions, well memory read transactions that fall into non-prefetchable memory space. extra read transactions could have side effects, example, when accessing FIFO, non-prefetchable read transactions those locations. Accordingly, important retain value byte enable bits during data phase, non-prefetchable read transactions. these locations mapped memory space, memory read command target into non-prefetchable (memory-mapped I/O) memory space non-prefetching behavior.
4.6.3 Read Pre-fetch Address Boundaries
PI7C7100 imposes internal read address boundaries read pre-fetched data. When read transaction reaches these aligned address boundaries, PI7C7100 stops pre-fetched data, unless target signals target disconnect before read pre-fetched boundary reached. When PI7C7100 finishes transferring this read data initiator, returns target disconnect with last data transfer, unless initiator completes transaction before pre-fetched read data delivered. leftover pre-fetched data discarded. Prefetchable read transactions flow-through mode pre-fetch nearest aligned address boundary, until initiator de-asserts FRAME#. Section 4.6.6 describes flow-through mode during read operations. Table shows read pre-fetch address boundaries read transactions during non-flow-through mode. Table 4-4. Read Pre-fetch Address Boundaries
Transaction onfi read read Memory read Memory read Memory read Memory read Memory read Memory read multi Memory read multi Address Space Non-prefetchable Prefetchable Prefetchable ache Line equal equal equal
Pre-fetch Aligned Address oundary WORD pre-fetch) WORD pre-fetch) WORD pre-fetch) 16-D WORD gned address boundary ache address boundary 16-D WORD gned address boundary ache boundary 32-D WORD gned address boundary cache boundary
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Table 4-5. Read Transaction Pre-Fetching
Transaction read onfi gurati read Memory read Memory read Memory read multi ehav Pre-fetchi never done Pre-fetchi never done ownstream: pre-fetchi used address prefetchable space Upstream: pre-fetchi used pre-fetch sable (default) Pre-fetchi always used Pre-fetchi always used
Section detailed information about prefetchable non-prefetchable address spaces.
4.6.4 Delayed Read Requests
PI7C7100 treats read transactions delayed read transactions, which means that read request from initiator posted into delayed transaction queue. Read data from target placed read data queue directed toward initiator interface transferred initiator when initiator repeats read transaction. When PI7C7100 accepts delayed read request, first samples read address, read command, address parity. When IRDY# asserted, PI7C7100 then samples byte enable bits first data phase. This information entered into delayed transaction queue. PI7C7100 terminates transaction signaling target retry initiator. Upon reception target retry, initiator required continue repeat same read transaction until least data transfer completed, until target response (target abort master abort) other than target retry received.
4.6.5 Delayed Read Completion with Target
When delayed read request reaches head delayed transaction queue, PI7C7100 arbitrates target initiates read transaction only previously queued posted write transactions have been delivered. PI7C7100 uses exact read address read command captured from initiator during initial delayed read request initiate read transaction. read transaction non-prefetchable read, PI7C7100 drives captured byte enable bits during next cycle. transaction prefetchable read transaction, drives byte enable bits zero data phases. PI7C7100 receives target retry response read transaction target bus, continues repeat read transaction until least data transfer completed, until error condition encountered. transaction terminated normal master termination target disconnect after least data transfer been completed, PI7C7100 does initiate further attempts read more data. PI7C7100 unable obtain read data from target after 224(default) 232(maximum) attempts, PI7C7100 ceases further read attempts returns target abort initiator. delayed transaction removed from delayed transaction queue. number attempts programmable. PI7C7100 also asserts P_SERR# primary SERR# enable command register. Section information assertion P_SERR#. Once PI7C7100 receives DEVSEL# TRDY# from target, transfers data read opposite direction read data queue, pointing toward opposite interface, before terminating transaction. example, read data response downstream read transaction initiated primary placed upstream read data queue. PI7C7100 accept DWORD read data each clock cycle; that master wait states inserted. number DWORD transferred during delayed read transaction depends conditions given Table (assuming disconnect received from target).
4.6.6 Delayed Read Completion Initiator
When transaction been completed target bus, delayed read data head read data queue, ordering constraints with posted write transactions have been satisfied, PI7C7100 transfers data initiator when initiator repeats transaction. memory read transactions, PI7C7100 aliases memory read, memory read line, memory read multiple commands when matching command transaction command delayed transaction queue. PI7C7100 returns target disconnect along with transfer last DWORD read data initiator. PI7C7100 initiator terminates transaction before read data been transferred, remaining read data left data buffers discarded.
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When master repeats transaction starts transferring prefetchable read data from data buffers while read transaction target still progress before read boundary reached target bus, read transaction starts operating flow-through mode. Because data flowing through data buffers from target initiator, long read bursts then sustained. this case, read transaction allowed continue until initiator terminates transaction, until aligned address boundary reached, until buffer fills, whichever comes first. When buffer empties, PI7C7100 reflects stalled condition initiator de-asserting TRDY# until more read data available; otherwise, PI7C7100 does insert target wait states. When initiator terminates transaction, PI7C7100 de-assertion FRAME# initiator forwarded target bus. remaining read data discarded. PI7C7100 implements discard timer that starts counting when delayed read completion head delayed transaction queue, read data head read data queue. initial value this timer programmable through configuration register. initiator does repeat read transaction before discard timer expires, PI7C7100 discards read transaction read data from queues. PI7C7100 also conditionally asserts P_SERR# (see Section 7.4). PI7C7100 capability post multiple delayed read requests, maximum four each direction. initiator starts read transaction that matches address read command read transaction that already queued, current read command posted already contained delayed transaction queue. Section discussion delayed read transactions ordered when crossing PI7C7100.
Configuration Transactions
Configuration transactions used initialize system. Every device configuration space that accessed configuration commands. registers accessible configuration space only. addition accepting configuration transactions initialization configuration space, PI7C7100 also forwards configuration transactions device initialization hierarchical systems, well special cycle generation. support hierarchical systems, types configuration transactions specified: Type Type Type configuration transactions issued when intended target resides same initiator. Type configuration transaction identified configuration command lowest bits address 00b. Type configuration transactions issued when intended target resides another bus, when special cycle generated another bus. Type configuration command identified configuration command lowest address bits 01b. register number found both Type Type formats gives DWORD address configuration register accessed. function number also included both Type Type formats indicates which function multifunction device accessed. single-function devices, this value decoded. addresses Type configuration transaction include 5-bit field designating device number that identifies device target that accessed. addition, number Type transactions specifies which transaction targeted. timing diagrams, Figures Appendix
4.7.1 Type Access PI7C7100
configuration space accessed Type configuration transaction primary interface. configuration space cannot accessed from secondary bus. PI7C7100 responds Type configuration transaction asserting P_DEVSEL# when following conditions during address phase: command configuration read configuration write transaction. Lowest address bits P_AD[1:0] must 00b. Signal P_IDSEL must asserted. Function code either configuration space configuration space PI7C7100 multi-function device. PI7C7100 limits configuration access single DWORD data transfer returns target-disconnect with first data transfer additional data phases requested. Because read transactions configuration space have side effects, bytes requested DWORD returned, regardless value byte enable bits.
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Type configuration write read transactions data buffers; that these transactions completed immediately, regardless state data buffers. PI7C7100 ignores Type transactions initiated secondary interface.
4.7.2 Type Type Conversion
Type configuration transactions used specifically device configuration hierarchical system. PCIto-PCI bridge only type device that should respond Type configuration command. Type configuration commands used when configuration access intended device that resides other than where Type transaction generated. PI7C7100 performs Type Type translation when Type transaction generated primary intended device attached directly secondary bus. PI7C7100 must convert configuration command Type format that secondary device respond Type Type translations performed only downstream direction; that PI7C7100 generates Type transaction only secondary bus, never primary bus. PI7C7100 responds Type configuration transaction translates into Type transaction secondary when following conditions during address phase: lowest address bits P_AD[1:0] 01b. number address field P_AD[23:16] equal value secondary number register configuration space. command P_CBE[3:0] configuration read configuration write transaction. When PI7C7100 translates Type transaction Type transaction secondary interface, performs following translations address: Sets lowest address bits S1_AD[1:0] S2_AD[1:0] 00b. Decodes device number drives pattern specified Table S1_AD[31:16] S2_AD[31:16] purpose asserting devices IDSEL signal. Sets S1_AD[15:11] S2_AD[15:11] Leaves unchanged function number register number fields. PI7C7100 asserts unique address line based device number. These address lines used secondary IDSEL signals. mapping address lines depends device number Type address bits P_AD[15:11]. Table presents mapping that PI7C7100 uses
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Table Device Number IDSEL S1_AD S2_AD Mapping
P_AD <15: 00000 00001 00010 00011 00100 00101 0110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000-11110 11111 Secondary S1_AD [31: S2_AD [31: 0000 0000 0000 0001 0000 0000 0000 0010 0000 0000 0000 0100 0000 0000 0000 1000 0000 0000 0001 0000 0000 0000 0010 0000 0000 0000 0100 0000 0000 0000 1000 0000 0000 0001 0000 0000 0000 0010 0000 0000 0000 0100 0000 0000 0000 1000 0000 0000 0001 0000 0000 0000 0010 0000 0000 0000 0100 0000 0000 0000 1000 0000 0000 0000 0000 0000 0000 0000 Generate speci cycle (P_AD [7:2] 00h) 0000 0000 0000 0000 (P_AD [7:2] 00h)
umber 10h-1Eh
S1_AD S2_AD
PI7C7100 assert unique address lines used IDSEL signals devices secondary bus, device numbers ranging from through Because elec3cal loading constraints bus, more than IDSEL signals should necessary. However, device numbers greater than desired, some external method generating IDSEL lines must used, upper address bits then asserted. configuration transaction still translated passed from primary secondary bus. IDSEL asserted secondary device, transaction ends master abort. PI7C7100 forwards Type Type configuration read write transactions delayed transactions. Type Type configuration read write transactions limited single 32-bit data transfer.
4.7.3 Type Type Forwarding
Type Type transaction forwarding provides hierarchical configuration mechanism when more levels PCIto-PCI bridges used. When PI7C7100 detects Type configuration transaction intended downstream from secondary bus, PI7C7100 forwards transaction unchanged secondary bus. Ultimately, this transaction translated Type configuration command special cycle transaction downstream PCI-to-PCI bridge. Downstream Type Type forwarding occurs when following conditions during address phase: lowest address bits equal 01b. number falls range defined lower limit (exclusive) secondary number register upper limit (inclusive) subordinate number register.
command configuration read write transaction.
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PI7C7100 also supports Type Type forwarding configuration write transactions upstream support upstream special cycle generation. Type configuration command forwarded upstream when following conditions met: lowest address bits equal 01b. number falls outside range defined lower limit (inclusive) secondary number register upper limit (inclusive) subordinate number register. device number address bits AD[15:11] equal 11111b. function number address bits AD[10:8] equal 111b. command configuration write transaction. PI7C7100 forwards Type Type configuration write transactions delayed transactions. Type Type configuration write transactions limited single data transfer.
4.7.4 Special Cycles
Type configuration mechanism used generate special cycle transactions hierarchical systems. Special cycle transactions ignored acting target forwarded across bridge. Special cycle transactions generated from Type configuration write transactions either upstream downstream direction. PI7C7100 initiates special cycle target when Type configuration write transaction being detected initiating following conditions during address phase: lowest address bits AD[1:0] equal 01b. device number address bits AD[15:11] equal 11111b. function number address bits AD[10:8] equal 111b. register number address bits AD[7:2] equal 000000b. number equal value secondary number register configuration space downstream forwarding equal value primary number register configuration space upstream forwarding. command CBE# configuration write command. When PI7C7100 initiates transaction target interface, command changed from configuration write special cycle. address data forwarded unchanged. Devices that special cycles ignore address decode only command. data phase contains special cycle message. transaction forwarded delayed transaction, this case target response forwarded back (because special cycles result master abort). Once transaction completed target bus, through detection master abort condition, PI7C7100 responds with TRDY# next attempt configuration transaction from initiator. more than data transfer requested, PI7C7100 responds with target disconnect operation during first data phase.
Transaction Termination
This section describes PI7C7100 returns transaction termination conditions back initiator. initiator terminate transactions with following types termination: Normal termination Normal termination occurs when initiator de-asserts FRAME# beginning last data phase, deasserts IRDY# last data phase conjunction with either TRDY# STOP# assertion from target. Master abort master abort occurs when target response detected. When initiator does detect DEVSEL# from target within five clock cycles after asserting FRAME#, initiator terminates transaction with master abort. FRAME# still asserted, initiator de-asserts FRAME# next cycle, then de-asserts IRDY# following cycle. IRDY# must asserted same cycle which FRAME# de-asserts. FRAME# already de-asserted, IRDY# de-asserted next clock cycle following detection master abort condition.
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target terminate transactions with following types termination: Normal terminationTRDY# DEVSEL# asserted conjunction with FRAME# de-asserted IRDY# asserted. Target retrySTOP# DEVSEL# asserted with TRDY# de-asserted during first data phase. data transfers occur during transaction. This transaction must repeated. Target disconnect with data transferSTOP#, DEVSEL# TRDY# asserted. signals that this last data transfer transaction. Target disconnect without data transferSTOP# DEVSEL# asserted with TRDY# de-asserted after previous data transfers have been made. Indicates that more data transfers will made during this transaction. Target abortSTOP# asserted with DEVSEL# TRDY# de-asserted. Indicates that target will never able complete this transaction. DEVSEL# must asserted least cycle during transaction before target abort signaled.
4.8.1 Master Termination Initiated PI7C7100
PI7C7100, initiator, uses normal termination DEVSEL# returned target within five clock cycles PI7C7100s assertion FRAME# target bus. initiator, PI7C7100 terminates transaction when following conditions met: During delayed write transaction, single DWORD delivered. During non-prefetchable read transaction, single DWORD transferred from target. During prefetchable read transaction, pre-fetch boundary reached. posted write transaction, write data transaction transferred from data buffers target. burst transfer, with exception Memory Write Invalidate transactions, master latency timer expires PI7C7100s grant de-asserted. target terminates transaction with retry, disconnect, target abort. PI7C7100 delivering posted write data when terminates transaction because master latency timer expires, initiates another transaction deliver remaining write data. address transaction updated reflect address current DWORD delivered. PI7C7100 pre-fetching read data when terminates transaction because master latency timer expires, does repeat transaction obtain more data.
4.8.2 Master Abort Received PI7C7100
initiator initiates transaction target does detect DEVSEL# returned target within five clock cycles assertion FRAME#, PI7C7100 terminates transaction with master abort. This sets receivedmaster-abort status register corresponding target bus. delayed read write transactions, PI7C7100 able reflect master abort condition back initiator. When PI7C7100 detects master abort response delayed transaction, when initiator repeats transaction, PI7C7100 does respond transaction with DEVSEL# which induces master abort condition back initiator. transaction then removed from delayed transaction queue. When master abort received response posted write transaction, PI7C7100 discards posted write data makes more attempt deliver data. PI7C7100 sets received-master-abort status register when master abort received primary bus, sets received master abort secondary status register when master abort received secondary interface. When master abort detected posted write transaction with both master-abort-mode (bit bridge control register) SERR# enable (bit command register secondary set, PI7C7100 asserts P_SERR# master-abort-on-posted-write set. master-abort-on-posted-write P_SERR# event disable register (offset 64h). Note: When PI7C7100 performs Type special cycle conversion, master abort expected termination special cycle target bus. this case, master abort received set, Type configuration transaction disconnected after first data phase.
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4.8.3 Target Termination Received PI7C7100
When PI7C7100 initiates transaction target target responds with DEVSEL#, target transaction with following types termination: Normal termination (upon de-assertion FRAME#) Target retry Target disconnect Target abort PI7C7100 handles these terminations different ways, depending type transaction being performed. 4.8.3.1 Delayed Write Target Termination Response When PI7C7100 initiates delayed write transaction, type target termination received from target passed back initiator. Table shows response each type target termination that occurs during delayed write transaction. PI7C7100 repeats delayed write transaction until following conditions met: PI7C7100 completes least data transfer. PI7C7100 receives master abort. PI7C7100 receives target abort. PI7C7100 makes 224(default) 232(maximum) write attempts resulting response target retry. Table 4-7. Posted Write Target Termination Response
Target Termination Normal Target retry Target sconnect Target abort Returni sconnect ator data transfer only multi data phases requested. Returni target retry ator. onti attempts target. Returni sconnect ator data transfer only multi data phases requested. Returni target abort ator.Set recei target abort target nterface status regi ster.Set gnaled target abort ator nterface status regi ster.
After PI7C7100 makes 224(default) attempts same delayed write transaction target bus, PI7C7100 asserts P_SERR# SERR# enable (bit command register secondary delayed-writenon-delivery set. delayed-write-non-delivery P_SERR# event disable register (offset 64h). PI7C7100 stops initiating transaction response that delayed write transaction. delayed write request discarded. Upon subsequent write transaction attempt initiator, PI7C7100 returns target abort. Section description system error conditions. 4.8.3.2 Posted Write Target Termination Response When PI7C7100 initiates posted write transaction, target termination cannot passed back initiator. Table shows response each type target termination that occurs during posted write transaction.
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Table 4-8. Responses Posted Write Target Termination
Target Termination Normal Target retry Target sconnect Target abort addi onal acti Repeati transacti target. transacti deli veri remai posted data. recei ved-target-abort target nterface status regi ster. Assert P_SERR# enabled, gnaled-system-error mary status regi ster.
Note that when target retry target disconnect returned posted write data associated with that transaction remains write buffers, PI7C7100 initiates another write transaction attempt deliver rest write data. there target retry, exact same address will driven initial write transaction attempt. target disconnect received, address that driven subsequent write transaction attempt will updated reflect address current DWORD. initial write transaction Memory-Write-and-Invalidate transaction, partial delivery write data target performed before target disconnect received, PI7C7100 will memory write command deliver rest write data. because incomplete cache line will transferred subsequent write transaction attempt. After PI7C7100 makes 224(default) write transaction attempts fails deliver posted write data associated with that transaction, PI7C7100 asserts P_SERR# primary SERR# enable (bit command register secondary posted-write-non-delivery set. posted-write-non-delivery P_SERR# event disable register (offset 64h). write data discarded. Section discussion system error conditions. 4.8.3.3 Delayed Read Target Termination Response When PI7C7100 initiates delayed read transaction, abnormal target responses passed back initiator. Other target responses depend much data initiator requests. Table shows response each type target termination that occurs during delayed read transaction. PI7C7100 repeats delayed read transaction until following conditions met: PI7C7100 completes least data transfer. PI7C7100 receives master abort. PI7C7100 receives target abort. PI7C7100 makes 224(default) read attempts resulting response target retry. Table 4-9. Responses Delayed Read Target Termination
Target Termination Normal Target retry Target sconnect Target abort prefetchable, target sconnect only ator requests more data than read from target. non-prefetchable, target sconnect data phase. read transacti target. ator requests more data than read from target, return target sconnect ator. Return target abort ator. recei target abort target nterface status regi ster. gnaled target abort ator nterface status regi ster.
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After PI7C7100 makes 224(default) attempts same delayed read transaction target bus, PI7C7100 asserts P_SERR# primary SERR# enable (bit command register secondary delayedwrite-non-delivery set. delayed-write-non-delivery P_SERR# event disable register (offset 64h). PI7C7100 stops initiating transactions response that delayed read transaction. delayed read request discarded. Upon subsequent read transaction attempt initiator, PI7C7100 returns target abort. Section description system error conditions.
4.8.4 Target Termination Initiated PI7C7100
PI7C7100 return target retry, target disconnect, target abort initiator reasons other than detection that condition target interface. 4.8.4.1 Target Retry PI7C7100 returns target retry initiator when cannot accept write data return read data result internal conditions. PI7C7100 returns target retry initiator when following conditions met: delayed write transactions: transaction being entered into delayed transaction queue. Transaction already been entered into delayed transaction queue, target response been received. Target response been received progressed head return queue. delayed transaction queue full, transaction cannot queued. transaction with same address command been queued. locked sequence being propagated across PI7C7100, write transaction locked transaction. target locked write transaction locked transaction. more than clocks accept this transaction. delayed read transactions: transaction being entered into delayed transaction queue. read request already been queued, read data available. Data been read from target, head read data queue, posted write transaction precedes delayed transaction queue full, transaction cannot queued. delayed read request with same address command already been queued. locked sequence being propagated across PI7C7100, read transaction locked transaction. PI7C7100 currently discarding previously pre-fetched read data. target locked write transaction locked transaction. more than clocks accept this transaction. posted write transactions: posted write data buffer does have enough space address least DWORD write data. locked sequence being propagated across PI7C7100, write transaction locked transaction. When target retry returned initiator delayed transaction, initiator must repeat transaction with same address command well data write transaction, within time frame specified master timeout value. Otherwise, transaction discarded from buffers.
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4.8.4.2 Target Disconnect PI7C7100 returns target disconnect initiator when following conditions met: PI7C7100 hits internal address boundary. PI7C7100 cannot accept more write data. PI7C7100 more read data deliver. Section 4.5.4 description write address boundaries, Section 4.6.3 description read address boundaries. 4.8.4.3 Target Abort PI7C7100 returns target abort initiator when following conditions met: PI7C7100 returning target abort from intended target. PI7C7100 unable obtain delayed read data from target deliver delayed write data target after (default) attempts. When PI7C7100 returns target abort initiator, sets signaled target abort status register corresponding initiator interface.
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Address Decoding
PI7C7100 uses three address ranges that control memory transaction forwarding. These address ranges defined base limit address registers configuration space. This chapter describes these address ranges, well ISA-mode VGA-addressing support.
Address Ranges
PI7C7100 uses following address ranges that determine which memory transactions forwarded from primary secondary bus, from secondary primary bus: 32-bit address ranges 32-bit memory-mapped (non-prefetchable memory) ranges 32-bit prefetchable memory address ranges Transactions falling within these ranges forwarded downstream from primary secondary buses. Transactions falling outside these ranges forwarded upstream from secondary buses primary bus. address translation required PI7C7100. addresses that marked downstream always forwarded upstream. However, address transaction initiated from located marked address range downstream marked address range downstream bus, transaction will forwarded instead primary bus. same token, address transaction initiated from located marked address range downstream marked address range downstream bus, transaction will forwarded instead primary bus.
Address Decoding
PI7C7100 uses following mechanisms that defined configuration space specify address space downstream upstream forwarding: base limit address registers enable mode snoop This section provides information address registers mode. Section provides information modes. enable downstream forwarding transactions, enable must command register configuration space. transactions initiated primary will ignored enable set. enable upstream forwarding transactions, master enable must command register. masterenable set, PI7C7100 ignores memory transactions initiated secondary bus. masterenable also allows upstream forwarding memory transactions set. CAUTION configuration state affecting transaction forwarding changed configuration write operation primary same time that transactions ongoing secondary bus, PI7C7100 response secondary transactions predictable. Configure base limit address registers, enable bit, mode bit, snoop before setting enable master enable bits, change them subsequently only when primary secondary buses idle.
5.2.1 Base Limit Address Registers
PI7C7100 implements base limit address registers configuration space that define address range port downstream forwarding. PI7C7100 supports 32-bit addressing, which allows addresses downstream PI7C7100 mapped anywhere address space.
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transactions with addresses that fall inside range defined base limit registers forwarded downstream from primary secondary bus. transactions with addresses that fall outside this range forwarded upstream from secondary primary bus.
range turned setting base address value greater than that limit address. When range turned off, transactions forwarded upstream, transactions forwarded downstream. range minimum granularity aligned boundary. maximum range size. base register consists 8-bit field configuration address 1Ch, 16-bit field address 30h. bits 8-bit field define bits [15:12] base address. bottom bits read only indicate that PI7C7100 supports 32-bit addressing. Bits [11:0] base address assumed which naturally aligns base address boundary. bits contained base upper bits register configuration offset define AD[31:16] base address. bits read/write. After primary reset chip reset, value base address initialized 0000 0000h. limit register consists 8-bit field configuration offset 16-bit field offset 32h. bits 8-bit field define bits [15:12] limit address. bottom bits read only indicate that 32-bit addressing supported. Bits [11:0] limit address assumed FFFh, which naturally aligns limit address address block. bits contained limit upper bits register configuration offset define AD[31:16] limit address. bits read/write. After primary reset chip reset, value limit address reset 0000 0FFFh. Note: initial states base limit address registers define range 0000 0000h 0000 0FFFh, which bottom space. Write these registers with their appropriate values before setting either enable master enable command register configuration space.
5.2.2 Mode
PI7C7100 supports mode providing enable bridge control register configuration space. mode modifies response PI7C7100 inside address range order support mapping space presence system. This only affects response PI7C7100 when transaction falls inside address range defined base limit address registers, only when this address also falls inside first 64KB space (address bits [31:16] 0000h). When enable set, PI7C7100 does forward downstream transactions addressing bytes each aligned block. Only those transactions addressing bottom bytes aligned block inside base limit address range forwarded downstream. Transactions above 64KB address boundary forwarded defined address range defined base limit registers. Accordingly, enable set, PI7C7100 forwards upstream those transactions addressing bytes each aligned block within first 64KB space. master enable command configuration register must also enable upstream forwarding. other transactions initiated secondary forwarded upstream only they fall outside address range. When enable set, devices downstream PI7C7100 have space mapped into first bytes each chunk below 64KB boundary, anywhere space above 64KB boundary.
Memory Address Decoding
PI7C7100 three mechanisms defining memory address ranges forwarding memory transactions: Memory-mapped base limit address registers Prefetchable memory base limit address registers mode This section describes first mechanisms. Section 5.4.1 describes mode. enable downstream forwarding memory transactions, memory enable must command register configuration space. enable upstream forwarding memory transactions, master-enable must command register. master-enable also allows upstream forwarding transactions set.
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CAUTION configuration state affecting memory transaction forwarding changed configuration write operation primary same time that memory transactions ongoing secondary bus, response secondary memory transactions predictable. Configure memory-mapped base limit address registers, prefetchable memory base limit address registers, mode before setting memory enable master enable bits, change them subsequently only when primary secondary buses idle.
5.3.1 Memory-Mapped Base Limit Address Registers
Memory-mapped also referred non-prefetchable memory. Memory addresses that cannot automatically prefetched that conditionally pre-fetched based command type should mapped into this space. Read transactions non-prefetchable space exhibit side effects; this space have non-memory-like behavior. PI7C7100 pre-fetches this space only memory read line memory read multiple commands used; transactions using memory read command limited single data transfer. memory-mapped base address memory-mapped limit address registers define address range that PI7C7100 uses determine when forward memory commands. PI7C7100 forwards memory transaction from primary secondary interface transaction address falls within memory-mapped address range. PI7C7100 ignores memory transactions initiated secondary interface that fall into this address range. transactions that fall outside this address range ignored primary interface forwarded upstream from secondary interface (provided that they fall into prefetchable memory range forwarded downstream mechanism). memory-mapped range supports 32-bit addressing only. PCI-to-PCI Bridge Architecture Specification does provide 64-bit addressing memory-mapped space. memory-mapped address range granularity alignment 1MB. maximum memory-mapped address range 4GB. memory-mapped address range defined 16-bit memory-mapped base address register configuration offset 16-bit memory-mapped limit address register offset 22h. bits each these registers correspond bits [31:20] memory address. bits hardwired lowest bits memorymapped base address assumed 0000h, which results natural alignment boundary. lowest bits memory-mapped limit address assumed FFFFh, which results alignment block. Note: initial state memory-mapped base address register 0000 0000h. initial state memorymapped limit address register 000F FFFFh. Note that initial states these registers define memory-mapped range bottom block memory. Write these registers with their appropriate values before setting either memory enable master enable command register configuration space. turn memory-mapped address range, write memory-mapped base address register with value greater than that memory-mapped limit address register.
5.3.2 Prefetchable Memory Base Limit Address Registers
Locations accessed prefetchable memory address range must have true memory-like behavior must exhibit side effects when read. This means that extra reads prefetchable memory location must have side effects. PI7C7100 pre-fetches types memory read commands this address space. prefetchable memory base address prefetchable memory limit address registers define address range that PI7C7100 uses determine when forward memory commands. PI7C7100 forwards memory transaction from primary secondary interface transaction address falls within prefetchable memory address range. PI7C7100 ignores memory transactions initiated secondary interface that fall into this address range. PI7C7100 does respond transactions that fall outside this address range primary interface forwards those transactions upstream from secondary interface (provided that they fall into memory-mapped range forwarded mechanism). prefetchable memory range supports 64-bit addressing provides additional registers define upper bits memory address range, prefetchable memory base address upper bits register, prefetchable memory limit address upper bits register. address comparison, single address cycle (32-bit address) prefetchable memory transaction treated like 64-bit address transaction where upper bits address equal This upper
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32-bit value compared prefetchable memory base address upper bits register prefetchable memory limit address upper bits register. prefetchable memory base address upper bits register must pass single address cycle transactions downstream. Prefetchable memory address range granularity alignment 1MB. Maximum memory address range when 32-bit addressing being used. Prefetchable memory address range defined 16-bit prefetchable memory base address register configuration offset 16-bit prefetchable memory limit address register offset 26h. bits each these registers correspond bits [31:20] memory address. lowest bits hardwired lowest bits prefetchable memory base address assumed 0000h, which results natural alignment boundary. lowest bits prefetchable memory limit address assumed FFFFFh, which results alignment block. Note: initial state prefetchable memory base address register 0000 0000h. initial state prefetchable memory limit address register 000F FFFFh. Note that initial states these registers define prefetchable memory range bottom block memory. Write these registers with their appropriate values before setting either memory enable master enable command register configuration space. turn prefetchable memory address range, write prefetchable memory base address register with value greater than that prefetchable memory limit address register. entire base value must greater than entire limit value, meaning that upper bits must considered. Therefore, disable address range, upper bits registers both same value, while lower base register greater than lower limit register. Otherwise, upper 32-bit base must greater than upper 32-bit limit.
Support
PI7C7100 provides modes support: mode, supporting VGA-compatible addressing snoop mode, supporting palette forwarding
5.4.1 Mode
When VGA-compatible device exists downstream from PI7C7100, mode bridge control register configuration space enable mode. When PI7C7100 operating mode, forwards downstream those transactions addressing frame buffer memory registers, regardless values base limit address registers. PI7C7100 ignores transactions initiated secondary interface addressing these locations. frame buffer consists following memory address range: 000A 0000h000B FFFFh Read transactions frame buffer memory treated non-prefetchable. PI7C7100 requests only single data transfer from target, read byte enable bits forwarded target bus. addresses range 3B0h3BBh 3C0h3DFh I/O. These addresses aliases every throughout first 64KB space. This means that address bits <15:10> decoded value, while address bits [31:16] must BIOS addresses starting C0000h decoded mode.
5.4.2 Snoop Mode
PI7C7100 provides snoop mode, allowing palette write transactions forwarded downstream. This mode used when graphics device downstream from PI7C7100 needs snoop respond palette write transactions. enable mode, snoop command register configuration space. Note that PI7C7100 claims palette write transactions asserting DEVSEL# snoop mode. When snoop set, PI7C7100 forwards downstream transactions within 3C6h, 3C8h 3C9h addresses space. Note that these addresses also forwarded part compatibility mode previously described. Again, address bits <15:10> decoded, while address bits <31:16> must equal which means that these addresses aliases every throughout first 64KB space. Note: both mode snoop set, PI7C7100 behaves same only mode were set.
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Transaction Ordering
maintain data coherency consistency, PI7C7100 complies with ordering rules forth Local Specification, Revision 2.1, transactions crossing bridge. This chapter describes ordering rules that control transaction forwarding across PI7C7100.
Transactions Governed Ordering Rules
Ordering relationships established following classes transactions crossing PI7C7100: Posted write transactions, comprised memory write memory write invalidate transactions. Posted write transactions complete source before they complete destination; that data written into intermediate data buffers before reaches target. Delayed write request transactions, comprised write configuration write transactions. Delayed write requests terminated target retry initiator queued delayed transaction queue. delayed write transaction must complete target before completes initiator bus. Delayed write completion transactions, comprised write configuration write transactions. Delayed write completion transactions complete target bus, target response queued buffers. delayed write completion transaction proceeds direction opposite that original delayed write request; that delayed write completion transaction proceeds from target initiator bus. Delayed read request transactions, comprised memory read, read, configuration read transactions. Delayed read requests terminated target retry initiator queued delayed transaction queue. Delayed read completion transactions, comprised memory read, read, configuration read transactions. Delayed read completion transactions complete target bus, read data queued read data buffers. delayed read completion transaction proceeds direction opposite that original delayed read request; that delayed read completion transaction proceeds from target initiator bus. PI7C7100 does combine merge write transactions: PI7C7100 does combine separate write transactions into single write transactionthis optimization best implemented originating master. PI7C7100 does merge bytes separate masked write transactions same DWORD addressthis optimization also best implemented originating master. PI7C7100 does collapse sequential write transactions same address into single write transactionthe Local Specification does permit this combining transactions.
General Ordering Guidelines
Independent transactions primary secondary buses have relationship only when those transactions cross PI7C7100. following general ordering guidelines govern transactions crossing PI7C7100: ordering relationship transaction with respect other transactions determined when transaction completes, that when transaction ends with termination other than target retry. Requests terminated with target retry accepted completed order with respect other transactions that have been terminated with target retry. order completion delayed requests important, initiator should start second delayed transaction until first been completed. more than delayed transaction initiated, initiator should repeat delayed transaction requests, using some fairness algorithm. Repeating delayed transaction cannot contingent completion another delayed transaction. Otherwise, deadlock occur.
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Write transactions flowing direction have ordering requirements with respect write transactions flowing other direction. PI7C7100 accept posted write transactions both interfaces same time, well initiate posted write transactions both interfaces same time. acceptance posted memory write transaction target never contingent completion non-locked, non-posted transaction master. This true PI7C7100 must also true other agents. Otherwise, deadlock occur. PI7C7100 accepts posted write transactions, regardless state completion delayed transactions being forwarded across PI7C7100.
Ordering Rules
Table shows ordering relationships transactions refers number ordering rules that follow. Table 6-1. Summary Transaction Ordering
Posted elayed read request elayed request elayed read completi elayed completi Posted Write elay elay Write elay ompletion elay Write ompletion
Note: superscript accompanying some table entries refers applicable ordering rule listed this section. Many entries governed these ordering rules; therefore, implementation choose whether transactions pass each other. entries without superscripts reflect PI7C7100s implementation choices. following ordering rules describe transaction relationships. Each ordering rule followed explanation, ordering rules referred number Table These ordering rules apply posted write transactions, delayed write read requests, delayed write read completion transactions crossing PI7C7100 same direction. Note that delayed completion transactions cross PI7C7100 direction opposite that corresponding delayed requests. Posted write transactions must complete target order which they were received initiator bus. subsequent posted write transaction setting flag that covers data first posted write transaction; second transaction were complete before first transaction, device checking flag could subsequently consume stale data. delayed read request traveling same direction previously queued posted write transaction must push posted write data ahead posted write transaction must complete target before delayed read request attempted target bus. read transaction same location write data, read transaction were pass write transaction, would return stale data. delayed read completion must pull ahead previously queued posted write data traveling same direction. this case, read data traveling same direction write data, initiator read transaction same side PI7C7100 target write transaction. posted write transaction must complete target before read data returned initiator. read transaction reading status register initiator posted write data therefore should complete until write transaction complete. Delayed write requests cannot pass previously queued posted write data. posted memory write transactions, delayed write transaction flag that covers data posted write transaction. delayed write request were complete before earlier posted write transaction, device checking flag could subsequently consume stale data.
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Posted write transactions must given opportunities pass delayed read write requests completions. Otherwise, deadlocks occur when some bridges which support delayed transactions other bridges which support delayed transactions being used same system. fairness algorithm used arbitrate between posted write queue delayed transaction queue.
Data Synchronization
Data synchronization refers relationship between interrupt signaling data delivery. Local Specification, Revision 2.1, provides following alternative methods synchronizing data interrupts: device signaling interrupt performs read data just written (software). device driver performs read operation register interrupting device before accessing data written device (software). System hardware guarantees that write buffers flushed before interrupts forwarded. PI7C7100 does have hardware mechanism guarantee data synchronization posted write transactions. Therefore, posted write transactions must followed read operation, either from device location just written some other location along same path), from device driver device registers.
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Error Handling
PI7C7100 checks, forwards, generates parity both primary secondary interfaces. maintain transparency, PI7C7100 always forward existing parity condition other bus, along with address data. PI7C100 always attempts transparent when reporting errors, this always possible, given presence posted data delayed transactions. support error reporting bus, PI7C7100 implements following: PERR# SERR# signals both primary secondary interfaces Primary status secondary status registers device-specific P_SERR# event disable register This chapter provides detailed information about PI7C7100 handles errors. also describes error status reporting error operation disabling.
Address Parity Errors
PI7C7100 checks address parity transactions both buses, address commands. When PI7C7100 detects address parity error primary interface, following events occur: parity error response command register, PI7C7100 does claim transaction with P_DEVSEL#; this allow transaction terminate master abort. parity error response set, PI7C7100 proceeds normally accepts transaction directed across PI7C7100. PI7C7100 sets detected parity error status register. PI7C7100 asserts P_SERR# sets signaled system error status register, both following conditions met: SERR# enable command register. parity error response command register. When PI7C7100 detects address parity error secondary interface, following events occur: parity error response bridge control register, PI7C7100 does claim transaction with S1_DEVSEL# S2_DEVSEL#; this allow transaction terminate master abort. parity error response set, PI7C7100 proceeds normally accepts transaction directed across PI7C7100. PI7C7100 sets detected parity error secondary status register. PI7C7100 asserts P_SERR# sets signaled system error status register, both following conditions met: SERR# enable command register. parity error response bridge control register.
Data Parity Errors
When forwarding transactions, PI7C7100 attempts pass data parity condition from interface other unchanged, whenever possible, allow master target devices handle error condition. following sections describe, each type transaction, sequence events that occurs when parity error detected which parity condition forwarded across PI7C7100.
7.2.1 Configuration Write Transactions Configuration Space
When PI7C7100 detects data parity error during Type configuration write transaction PI7C7100 configuration space, following events occur: parity error response command register, PI7C7100 asserts P_TRDY# writes data configuration register. PI7C7100 also asserts P_PERR#. parity error response set, PI7C7100 does assert P_PERR#. PI7C7100 sets detected parity error status register, regardless state parity error response bit.
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7.2.2 Read Transactions
When PI7C7100 detects parity error during read transaction, target drives data data parity, initiator checks parity conditionally asserts PERR#. downstream transactions, when PI7C7100 detects read data parity error secondary bus, following events occur: PI7C7100 asserts S_PERR# cycles following data transfer, secondary interface parity error response bridge control register. PI7C7100 sets detected parity error secondary status register. PI7C7100 sets data parity detected secondary status register, secondary interface parity error response bridge control register. PI7C7100 forwards parity with data back initiator primary bus. data with parity pre-fetched read initiator primary bus, data discarded data with parity returned initiator. PI7C7100 completes transaction normally. PI7C7100 asserts P_PERR# cycles following data transfer, primary interface parity error response command register. PI7C7100 sets detected parity error primary status register. PI7C7100 sets data parity detected primary status register, primary interface parity-errorresponse command register. PI7C7100 forwards parity with data back initiator secondary bus. data with parity pre-fetched read initiator secondary bus, data discarded data with parity returned initiator. PI7C7100 completes transaction normally. PI7C7100 returns initiator data parity that received from target. When initiator detects parity error this read data enabled report initiator asserts PERR# cycles after data transfer occurs. assumed that initiator takes responsibility handling parity error condition; therefore, when PI7C7100 detects PERR# asserted while returning read data initiator, PI7C7100 does take further action completes transaction normally.
upstream transactions, when PI7C7100 detects read data parity error primary bus, following events occur:
7.2.3 Delayed Write Transactions
When PI7C7100 detects data parity error during delayed write transaction, initiator drives data data parity, target checks parity conditionally asserts PERR#. delayed write transactions, parity error occur following times: During original delayed write request transaction When initiator repeats delayed write request transaction When PI7C7100 completes delayed write transaction target
When delayed write transaction normally queued, address, command, address parity, data, byte enable bits, data parity captured target retry returned initiator. When PI7C7100 detects parity error write data initial delayed write request transaction, following events occur: parity-error-response corresponding initiator set, PI7C7100 asserts TRDY# initiator transaction queued. multiple data phases requested, STOP# also asserted cause target disconnect. cycles after data transfer, PI7C7100 also asserts PERR#. parity-error-response set, PI7C7100 returns target retry. queues transaction usual. PI7C7100 does assert PERR#. this case, initiator repeats transaction. PI7C7100 sets detected-parity-error status register corresponding initiator bus, regardless state parity-error-response bit.
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Note: parity checking turned data parity errors have occurred queued subsequent delayed write transactions initiator bus, possible that initiators re-attempts write transaction match original queued delayed write information contained delayed transaction queue. this case, master timeout condition occur, possibly resulting system error (P_SERR# assertion). downstream transactions, when PI7C7100 delivering data target secondary S_PERR# asserted target, following events occur: PI7C7100 sets secondary interface data parity detected secondary status register, secondary parity error response bridge control register. PI7C7100 captures parity error condition forward back initiator primary bus.
Similarly, upstream transactions, when PI7C7100 delivering data target primary P_PERR# asserted target, following events occur: PI7C7100 sets primary interface data-parity-detected status register, primary parity-errorresponse command register. PI7C7100 captures parity error condition forward back initiator secondary bus.
delayed write transaction completed initiator when initiator repeats write transaction with same address, command, data, byte enable bits delayed write command that head posted data queue. Note that parity compared when determining whether transaction matches those delayed transaction queues. cases must considered: When parity error detected initiator subsequent re-attempt transaction detected target When parity error forwarded back from target
downstream delayed write transactions, when parity error detected initiator PI7C7100 write status return, following events occur: PI7C7100 first asserts P_TRDY# then asserts P_PERR# cycles later, primary interface parityerror-response command register. PI7C7100 sets primary interface parity-error-detected status register. Because there exact data parity match, write status returned transaction remains queue.
Similarly, upstream delayed write transactions, when parity error detected initiator PI7C7100 write status return, following events occur: PI7C7100 first asserts S1_TRDY# S2_TRDY# then asserts S_PERR# cycles later, secondary interface parity-error-response bridge control register (offset 3Ch). PI7C7100 sets secondary interface parity-error-detected secondary status register. Because there exact data parity match, write status returned transaction remains queue.
downstream transactions, where parity error being passed back from target parity error condition originally detected initiator bus, following events occur: PI7C7100 asserts P_PERR# cycles after data transfer, following both true: parity-error-response command register primary interface. parity-error-response bridge control register secondary interface. PI7C7100 completes transaction normally.
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upstream transactions, when parity error being passed back from target parity error condition originally detected initiator bus, following events occur: PI7C7100 asserts S_PERR# cycles after data transfer, following both true: parity error response command register primary interface. parity error response bridge control register secondary interface. PI7C7100 completes transaction normally.
7.2.4 Posted Write Transactions
During downstream posted write transactions, when PI7C7100 responds target, detects data parity error initiator (primary) bus, following events occur: PI7C7100 asserts P_PERR# cycles after data transfer, parity error response command register primary interface. PI7C7100 sets parity error detected status register primary interface. PI7C7100 captures forwards parity condition secondary bus. PI7C7100 completes transaction normally.
Similarly, during upstream posted write transactions, when PI7C7100 responds target, detects data parity error initiator (secondary) bus, following events occur: PI7C7100 asserts S_PERR# cycles after data transfer, parity error response bridge control register secondary interface. PI7C7100 sets parity error detected status register secondary interface. PI7C7100 captures forwards parity condition primary bus. PI7C7100 completes transaction normally.
During downstream write transactions, when data parity error reported target (secondary) targets assertion S_PERR#, following events occur: PI7C7100 sets data parity detected status register secondary interface, parity error response bridge control register secondary interface. PI7C7100 asserts P_SERR# sets signaled system error status register, following conditions met: SERR# enable command register. posted write parity error P_SERR# event disable register set. parity error response bridge control register secondary interface. parity error response command register primary interface. PI7C7100 detected parity error primary (initiator) which parity error forwarded from primary secondary bus. During upstream write transactions, when data parity error reported target (primary) targets assertion P_PERR#, following events occur: PI7C7100 sets data parity detected status register, parity error response command register primary interface. PI7C7100 asserts P_SERR# sets signaled system error status register, following conditions met: SERR# enable command register. parity error response bridge control register secondary interface. parity error response command register primary interface. PI7C7100 detected parity error secondary (initiator) which parity error forwarded from secondary primary bus. Assertion P_SERR# used signal parity error condition when initiator does know that error occurred.
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Because data already been delivered with errors, there other signal this information back initiator. parity error forwarded from initiating target bus, P_SERR# will asserted.
Data Parity Error Reporting Summary
previous sections, responses PI7C7100 data parity errors presented according type transaction progress. This section organizes responses PI7C7100 data parity errors according status bits that PI7C7100 sets signals that asserts. Table shows setting detected parity error status register, corresponding primary interface. This when PI7C7100 detects parity error primary interface. Table Setting Primary Interface Detected Parity Error
Primary detected parity error
Transaction Read Read Read Read Posted Posted Posted Posted elayed elayed elayed elayed
irection ownstream ownstream Upstream Upstream ownstream ownstream Upstream Upstream ownstream ownstream Upstream Upstream
where error detected mary Secondary mary Secondary mary Secondary mary Secondary mary Secondary mary Secondary
Primary /Secondary parity error response bits x/x1
=dont care
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Table shows setting detected parity error secondary status register, corresponding secondary interface. This when PI7C7100 detects parity error secondary interface. Table Setting Secondary Interface Detected Parity Error
Secondary detected parity error Transaction Read Read Read Read Posted Posted Posted Posted elayed elayed elayed elayed irection ownstream ownstream Upstream Upstream ownstream ownstream Upstream Upstream ownstream ownstream Upstream Upstream where error detected mary Secondary mary Secondary mary Secondary mary Secondary mary Secondary mary Secondary Primary /Secondary parity error response bits x/x1
Table shows setting data parity detected primary interfaces status register. This under following conditions: PI7C7100 must master primary bus. parity error response command register, corresponding primary interface, must set. P_PERR# signal detected asserted parity error detected primary bus. Table Setting Primary Interface Data Parity Detected
Primary data parity
Transaction Read Read Read Read Posted Posted Posted Posted elayed elayed elayed elayed
irection ownstream ownstream Upstream Upstream ownstream ownstream Upstream Upstream ownstream ownstream Upstream Upstream
where error detected mary Secondary mary Secondary mary Secondary mary Secondary mary Secondary mary Secondary
Primary /Secondary parity error response bits x/x1
=dont care
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Table shows setting data parity detected status register secondary interface. This under following conditions: PI7C7100 must master secondary bus. parity error response must bridge control register secondary interface. S_PERR# signal detected asserted parity error detected secondary bus. Table Setting Secondary Interface Data Parity Detected
Secondary data parity detected
Transaction Read Read Read Read Posted Posted Posted Posted elayed elayed elayed elayed
irection ownstream ownstream Upstream Upstream ownstream ownstream Upstream Upstream ownstream ownstream Upstream Upstream
where error detected mary Secondary mary Secondary mary Secondary mary Secondary mary Secondary mary Secondary
Primary /Secondary parity error response bits x/x1
=dont care
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Table shows assertion P_PERR#. This signal under following conditions: PI7C7100 either target write transaction initiator read transaction primary bus. parity-error-response must command register primary interface. PI7C7100 detects data parity error primary detects S_PERR# asserted during completion phase downstream delayed write transaction target (secondary) bus. Table Assertion P_PERR#
(de-asserted) (asserted)
Transaction Read Read Read Read Posted Posted Posted Posted elayed elayed elayed elayed
irection ownstream ownstream Upstream Upstream ownstream ownstream Upstream Upstream ownstream ownstream Upstream Upstream
where error detected mary Secondary mary Secondary mary Secondary mary Secondary mary Secondary mary Secondary
Primary /Secondary parity error response bits x/x1
=dont care parity error detected target (secondary) initiator (primary) bus.
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Table shows assertion S_PERR# that under following conditions: PI7C7100 either target write transaction initiator read transaction secondary bus. parity error response must bridge control register secondary interface. PI7C7100 detects data parity error secondary detects P_PERR# asserted during completion phase upstream delayed write transaction target (primary) bus. Table Assertion S_PERR#
(de-asserted) (asserted)
Transaction Read Read Read Read Posted Posted Posted Posted elayed elayed elayed elayed
irection ownstream ownstream Upstream Upstream ownstream ownstream Upstream Upstream ownstream ownstream Upstream Upstream
where error detected mary Secondary mary Secondary mary Secondary mary Secondary mary Secondary mary Secondary
Primary /Secondary parity error response bits x/x1
=dont care parity error detected target (secondary) initiator (primary) bus.
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Table shows assertion P_SERR#. This signal under following conditions: PI7C7100 detected P_PERR# asserted upstream posted write transaction S_PERR# asserted downstream posted write transaction. PI7C7100 detect parity error target posted write transaction. parity error response command register parity error response bridge control register must both set. SERR# enable must command register. Table Assertion P_SERR# Data Parity Errors
(de-asserted) (asserted)
Transaction Read Read Read Read Posted Posted Posted Posted elayed elayed elayed elayed
irection ownstream ownstream Upstream Upstream ownstream ownstream Upstream Upstream ownstream ownstream Upstream Upstream
where error detected mary Secondary mary Secondary mary Secondary mary Secondary mary Secondary mary Secondary
Primary /Secondary parity error response bits x/x1
=dont care parity error detected target (secondary) initiator (primary) bus. parity error detected target (primary) initiator (secondary) bus.
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System Error (SERR#) Reporting
PI7C7100 uses P_SERR# signal report conditionally number system error conditions addition special case parity error conditions described Section 7.2.3. Whenever assertion P_SERR# discussed this document, assumed that following conditions apply: PI7C7100 assert P_SERR# reason, SERR# enable must command register. Whenever PI7C7100 asserts P_SERR#, PI7C7100 must also signaled system error status register. compliance with PCI-to-PCI Bridge Architecture Specification, PI7C7100 asserts P_SERR# when detects secondary SERR# input, S_SERR#, asserted SERR# forward enable bridge control register. addition, PI7C7100 also sets received system error secondary status register. PI7C7100 also conditionally asserts P_SERR# following reasons: Target abort detected during posted write transaction Master abort detected during posted write transaction Posted write data discarded after 224(default) attempts deliver (224 target re3es received) Parity error reported target during posted write transaction (see previous section) Delayed write data discarded after 224(default) attempts deliver (224 target re3es received) Delayed read data cannot transferred from target after 224(default) attempts (224 target re3es received) Master timeout delayed transaction device-specific P_SERR# status register reports reason assertion P_SERR#. Most these events have additional device-specific disable bits P_SERR# event disable register that make possible mask P_SERR# assertion specific events. master timeout condition SERR# enable that event bridge control register therefore does have device-specific disable bit.
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Exclusive Access
This chapter describes LOCK# signal implement exclusive access target transactions that cross PI7C7100.
Concurrent Locks
primary secondary lock mechanisms operate concurrently except when locked transaction crosses PI7C7100. primary master lock primary target without affecting status lock secondary bus, vice versa. This means that primary master lock primary target same time that secondary master locks secondary target.
Acquiring Exclusive Access across PI7C7100
bus, before acquiring access LOCK# signal starting series locked transactions, initiator must first check that both following conditions met: must idle. LOCK# signal must de-asserted. initiator leaves LOCK# signal de-asserted during address phase asserts LOCK# clock cycle later. Once data transfer completed from target, target lock been achieved. Locked transactions cross PI7C7100 downstream upstream directions, from primary secondary vice versa. When target resides another bus, master must acquire only lock also lock every between targets bus. When PI7C7100 detects primary bus, initial locked transaction intended target secondary bus, PI7C7100 samples address, transaction type, byte enable bits, parity, described Section 4.6.4. also samples lock signal. there lock established between ports target already locked another master, then current lock cycle re3ed without forward. Because target retry signaled initiator, initiator must relinquish lock primary bus, therefore lock established. first locked transaction must read transaction. Subsequent locked transactions read write transactions. Posted memory write transactions that part locked transaction sequence still posted. Memory read transactions that part locked transaction sequence pre-fetched. When locked delayed read request queued, PI7C7100 does queue more transactions until locked sequence finished. PI7C7100 signals target retry transactions initiated subsequent locked read transaction that intended targets other side PI7C7100. PI7C7100 allows transactions queued before locked transaction complete before initiating locked transaction. When locked delayed read request transaction moves head delayed transaction queue, PI7C7100 initiates transaction locked read transaction de-asserting LOCK# target during first address phase, asserting LOCK# cycle later. LOCK# already asserted (used another initiator), PI7C7100 waits request access secondary until LOCK# de-asserted when
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