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COM/SEG Driver APR. 2002 Version SUNPLUS TECHNOLOGY reserves


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SPLC560C
COM/SEG Driver
APR. 2002 Version
SUNPLUS TECHNOLOGY reserves right change this documentation without prior notice. Information provided SUNPLUS TECHNOLOGY believed accurate reliable. However, SUNPLUS TECHNOLOGY makes warranty errors which appear this document. responsibility assumed Contact SUNPLUS TECHNOLOGY obtain latest version device specifications before placing your order.
SUNPLUS TECHNOLOGY infringement patent other rights third parties which result from use. addition, SUNPLUS products authorized critical components life support devices/ systems aviation devices/systems, where malfunction failure product reasonably expected result significant injury user, without express written approval Sunplus.
SPLC560C
Table Contents
PAGE
GENERAL DESCRIPTION. FEATURES. BLOCK DIAGRAM 3.1. BLOCK FUNCTIONS 3.2. INPUT/OUTPUT CIRCUITS SIGNAL DESCRIPTIONS 4.1. CONNECTION FUNCTIONAL DESCRIPTIONS. 5.1. FUNCTIONS 5.2. FUNCTION OPERATIONS 5.3. RELATIONSHIP BETWEEN DISPLAY DATA DRIVER OUTPUT PINS 5.4. PRECAUTIONS ELECTRICAL SPECIFICATIONS 6.1. ABSOLUTE MAXIMUM RATINGS 6.2. RECOMMENDED OPERATING CONDITIONS 6.3. CHARACTERISTICS. 6.4. CHARACTERISTICS 6.5. TIMING CHARACTERISTICS SEGMENT MODE. PACKAGE/PAD LOCATIONS 7.1. ASSIGNMENT 7.2. ORDERING INFORMATION 7.3. ALIGN COORDINATE 7.4. LOCATIONS DISCLAIMER. REVISION HISTORY
Sunplus Technology Co., Ltd. Proprietary Confidential
APR. 2002 Preliminary Version:
SPLC560C
COM/SEG DRIVER
GENERAL DESCRIPTION
SPLC560C 160-output segment/common driver suitable driving large/medium scale matrix panels, used personal computers/work-stations. Through (Super Slim TCP) technology, ideal substantially decreasing size frame section module. SPLC560C good both segment driver common driver, create power consuming, high-resolution LCD. Segment Mode Shift clock frequency: 14MHz (Max.) (VDD +5.0V±10%) 8.0MHz (Max.) (VDD +2.5V +4.5V) Adopts data system 4-bit/8-bit parallel input modes selectable with mode (MD) Automatic transfer function enable signal Automatic counting function which, chip select mode,
FEATURES
Both Segment Mode Common Mode Number drive outputs: Supply voltage drive: +15V +30V Supply voltage logic system: +2.5V +5.5V power consumption output impedance CMOS silicon gate process (P-type silicon substrate) Package: 188-pin (Tape Carrier Package) bump chip Common Mode Built-in bits bi-directional shift register
causes internal clock stopped automatically counting input data Line latch circuits reset when DISPOFF active
BLOCK DIAGRAM
V12R V43R Y159 Y160 LEVEL SHIFTER BITS 4-LEVEL DRIVER V43L V12L EI01 EI02 ACTIVE CONTROL BITS LEVEL SHIFTER
DISPOFF
BITS LINE LATCH/SHIFT REGISTER
(divisible into bits Shift clock frequency: 4.0MHz (Max.) (VDD +2.5V +5.5V) Available single mode (160 bits shift register) dual mode bits shift register Y160 Y160 Y80, Y160 Y160 Y81, Single mode Single mode Dual mode Dual mode
CONTROL LOGIC
8BITS*2 DATA LATCH
DATA LATCH CONTROL
CONVERSION DATA CONTROL
TEST CIRCUIT
TEST1 TEST2
above shift directions pin-selectable Shift register circuit reset function when DISPOFF active
Remark: TCP's external shape customized. order your TCP's external shape, please contact SUNPLUS salesperson.
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3.1. Block Functions 3.1.1. Active control
case segment mode, controls selection non-selection chip. Following signal, after chip select signal Once data input been completed, input, select signal generated internally until bits data have been read non-selected. select signal cascade connection output, chip case common mode, controls input/output data bidirectional pins.
3.1.5. Line latch/shift register
case segment mode, bits which have been read into data latch simultaneously latched falling edge signal, output level shifter block. case common mode, shifts data from data input falling edge signal.
3.1.6. Level shifter
logic voltage signal level-shifted driver voltage level, output driver block.
3.1.2. conversion data control
case segment mode, keep input data which clocks 4-bit parallel mode into latch circuit, keep input data which clock 8-bits parallel mode into latch circuit, after that they internal data bits time.
3.1.7. 4-level driver
Drives driver output pins from line latch/shift register data, selecting levels (V0, V12, V43, based S/C, DISPOFF signals.
3.1.3. Data latch control
case segment mode, selects state data latch which reads data signals. shift direction controlled control logic, every bits data read selection signal shifts based state control circuit.
3.1.8. Control logic
Controls operation each block. case segment mode, when signal been input, blocks reset control logic waits selection signal output from active control block.
3.1.4. Data latch
case segment mode, latches data data bus. latched state each driver output controlled control logic data latch control, bits data read sets bits.
3.2. Input/Output Circuits
Internal Circuit Applicable pins L/R, S/C, DI6-DI0, DISPOFF,
Figure Input Circuit
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SPLC560C
Control Signal
Internal Circuit
Applicable pins DI7,
VSS(0 VSS(0
Figure Input Circuit
Internal Circuit Control Signal
Output Signal Control Signal Applicable pins
Figure Input/Output Circuit
Control Signal
Control Signal
Control Signal
Internal Circuit
Control Signal
Applicable pins Y160
Figure Drive Output Circuit
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SPLC560C
SIGNAL DESCRIPTIONS
Mnemonic Y160 V0L, V12L, V12R V43L, V43R V5L, EIO1 EIO2 Type driver output Power supply driver Power supply driver Power supply driver Power supply driver Input selecting reading direction display data segment mode/Input selecting shift direction shift register common mode Power supply logic system (+2.5V +5.5V) Segment mode/common mode selection Input/output chip selection segment mode/Shift data input/output shift register common mode Display data input segment mode Display data input segment mode/Dual mode data input common mode Clock input taking display data segment mode Control input output non-select level Latch pulse input display data segment mode/Shift clock input shift register common mode AC-converting signal input driver waveform Mode selection input Ground (0V) Description
DISPOFF
4.1. Connection
Y160 Y159 Y158
CHIP SURFACE
Note: Doesn't prescribe outline.
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V12L V43L EIO2 DISPOFF EIO1 V43R V12R
APR. 2002 Preliminary Version:
SPLC560C
FUNCTIONAL DESCRIPTIONS
5.1. Functions 5.1.1. Segment mode
Mnemonic V0R, V12R, V12L V43R, V43L V5L, Description Logic system power supply connects +2.5V +5.5V Ground connects Bias Power supply driver voltage Normally, bias voltage used resistor divider. Ensure that voltage such that VSSV5
must connect external power supply, supply regular voltage which
assigned specification each power pin. applications, even though have same voltage level, layout should shorted directly panel. That should have individual path connect-pin. Input pins display data 4-bit parallel input mode, input data into pins, DI0. 8-bit parallel input mode, input data into pins, DI0. Refer "RELATIONSHIP BETWEEN DISPLAY DATA DRIVE OUTPUT PINS" Functional Operations. Clock input taking display data Data read falling edge clock pulse. Latch pulse input display data Data latched falling edge clock pulse. Input selecting reading direction display data When level "L", data read sequentially from Y160 When level "H", data read sequentially from Y160. Refer "REALATIONSHIP BETWEEN DISPLAY DATA DRIVE OUTPUT PINS" Functional Operations. Control input output non-select level input signal level-shifted from logic voltage level drive voltage level, controls drive circuit. When level "L", drive output pins (Y160 level While "L", contents line latch reset, display data read data latch regardless condition DISPOFF When DISPOFF function canceled, driver outputs non-select level (V12 V43), then outputs contents data latch next falling edge that time, DISPOFF removal time does correspond what shown characteristics, cannot output reading data correctly. Table truth values shown "TRUTH TABLE" Function Operations. Segment mode/common mode selection When level "H", segment mode set. signal input driving waveform input signal level-shifted from logic voltage level drive voltage level, controls drive circuit. Normally, inputs frame inversion signal. driver output pin's output voltage level using line latch output signal signal. Table truth values shown "TRUTH TABLE" Function Operations. Connect VDD.
DISPOFF
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Mnemonic Mode selection When level "L", 4-bit parallel input mode set. When level "H", 8-bit parallel input mode set. Refer "RELATIONSHIP BETWEEN DISPLAY DATA DRIVE OUTPUT PINS" Functional Operations. EIO1 EIO2 Input/output pins chip selection When input Level "L", EIO1 output EIO2 input. When input Level "H", EIO1 input EIO2 output. During output, while after bits data have been read, cycle (from falling edge falling edge XCK), after which returns "H". Description
During input, chip selected while after signal input. chip non-selected after bits data have been read. Y160 driver output pins Corresponding directly each shift register, level (V0, V12, V43, selected output. Table truth values shown "TRUTH TABLE" Function Operations.
5.1.2. Common mode
Mnemonic V0R, V12R, V12L V43R, V43L V5L, EIO1 Description Logic system power supply connects +2.5V +5.5V. Ground connects Bias Power supply driver voltage Normally, bias voltage used resistor divider. Ensure that voltage such that VSSV5 <V43<V12<V0. must connect external power supply, supply regular voltage, which assigned specification each power pin. Shift clock pulse input bi-directional shift register Data shifted falling edge clock pulse. Shift data input/output bi-directional shift register Output when level "L", input when level "H". When EIO1 used input pin, will pull-down. When EIO1 used output pin, won't pull-down. Refer "RELATIONSHIP BETWEEN DISPLAY DATA DRIVE OUTPUT PINS" Functional Operations. EIO2 Shift data input/output bi-directional shift register Input when level "L", output when level "H". When EIO2 used input pin, will pull-down. When EIO2 used output pin, won't pull-down. Refer "RELATIONSHIP BETWEEN DISPLAY DATA DRIVE OUTPUT PINS" Functional Operations. Input selecting shift direction bi-directional shift register Data shifted from Y160 when level "L", data shifted from Y160 when level "H". Refer "RELATIONSHIP BETWEEN DISPLAY DATA DRIVE OUTPUT PINS" Functional Operations.
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Mnemonic signal input driving waveform input signal level-shifted from logic voltage level drive voltage level, controls drive circuit. Normally, input frame inversion signal. driver output pin's output voltage level using shift register output signal signal. Table truth values shown "TRUTH TABLE" Functional Operations. Segment mode/common mode selection When level "L", common mode set. Control input output non-select level input signal level-shifted from logic voltage level drive voltage level, controls drive circuit. When level "L", drive output pins (Y160 level While "L", contents shift register reset reading data. When DISPOFF function canceled, driver outputs non-select level (V12 V43), shift data reading next falling edge that time, DISPOFF removal time does correspond what shown characteristics, shift data reading correctly. Table truth values shown "TRUTH TABLE" Functional Operations. Mode selection When level "L", single mode operation selected. When level "H", dual mode operation selected. Refer "RELATIONSHIP BETWEEN DISPLAY DATA DRIVE OUTPUT PINS" Functional Operations. Dual mode data input According data shift direction data shift register, data input starting from 81st bit. When chip used dual mode, will pull-down. When chip used single mode, won't pull-down. Refer "RELATIONSHIP BETWEEN DISPLAY DATA DRIVE OUTPUT PINS" Functional Operations. Y160 used Connect VDD, avoiding floating. used pull-down common mode, connect open. driver output pins Corresponding directly each shift register, level (V0, V12, V43, selected output. Table truth values shown "TRUTH TABLE" Functional Operations. Description
DISPOFF
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5.2. Function Operations 5.2.1. Truth table 5.2.1.1. Segment mode
Latch data DISPOFF Driver output voltage level (Y160
5.2.1.2. Common mode
Latch data DISPOFF
Don't care Note2: "Don't care" should fixed "L", avoiding floating. There kinds power supply (logic level voltage drive voltage) driver. Supply regular voltage which assigned specification each power pin.
Driver output voltage level (Y160
Note1: (0V), (+2.5V +5.5V),
5.3. Relationship between Display Data Driver Output Pins 5.3.1. Segment mode 5.3.1.1. 4-bit parallel mode
EIO1 EIO2 Data Input Output Input Input Output Clock Y160 Y159 Y158 Y157 Clock Y156 Y155 Y154 Y153 Figure clock Clock Y152 Y151 Y150 Y149 Clock Y149 Y150 Y151 Y152 Clock Y153 Y154 Y155 Y156 Clock Y157 Y158 Y159 Y160
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5.3.1.2. 8-bit parallel mode
EIO1 EIO2 Data Input Output Input Input Output Clock Y160 Y159 Y158 Y157 Y156 Y155 Y154 Y153 Clock Y152 Y151 Y150 Y149 Y148 Y147 Y146 Y145 Figure clock Clock Y144 Y143 Y142 Y141 Y140 Y139 Y138 Y137 Clock Y137 Y138 Y139 Y140 Y141 Y142 Y143 Y144 Clock Y145 Y146 Y147 Y148 Y149 Y150 Y151 Y152 Clock Y153 Y154 Y155 Y156 Y157 Y158 Y159 Y160
5.3.2. Common mode
(Single) L(shift left) H(shift right) L(shift left) Data transfer direction Y160 Y160 Y160 Y160 EIO1 Output Input Output EIO2 Input Output Input Input
(Dual)
H(shift right)
Input
Output
Input
Note1: (0V), (+2.5V +5.5V), Don't care Note2: "Don't care" should fixed "L", avoiding floating.
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5.3.3. Connection examples plural segment drivers
CASE data Y160 EIO2 EIO1 Y160 EIO2 EIO1 Y160 EIO2 last data EIO1
CASE
data
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EIO1
EIO2 Y160 EIO1
EIO2 Y160 EIO1
EIO2 Y160 last data
APR. 2002 Preliminary Version:
SPLC560C
5.3.4. Timing characteristics 4-device casecade connection segment drivers
DATA LAST DATA
device
device
device
device
(device (device
(device
(device
n=40 4-bit parallel input mode. n=20 8-bit parallel input mode.
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5.3.5. Connection examples plural common drivers
SINGLE MODE (SHIFTING TOWARD LEFT) first Y160 EIO2 EIO1 DISPOFF Y160 EIO2 EIO1 DISPOFF Y160 EIO2 last EIO1 DISPOFF
VSS(VDD)
DISPOFF
SINGLE MODE (SHIFTING TOWARD RIGHT)
DISPOFF
VSS(VDD)
first EIO2 EIO1 Y160 EIO2
DISPOFF
EIO1 Y160 EIO2
DISPOFF
EIO1 Y160 last
DISPOFF
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5.4. Precautions 5.4.1. Precaution when connecting disconnecting power
This high-voltage driver, permanently damaged high current which flow voltage supplied driver power supply while logic system power supply floating. when connecting logic power supply, logic condition this inside insecurity. Therefore connect driver power supply after resetting logic condition this inside
DISPOFF function.
After that, cancel DISPOFF function
after driver power supply become stable. detail follows: When connecting power supply, connect drive power after connecting logic system power. Furthermore, when disconnecting power, disconnect logic system power after disconnecting driver power. recommend connecting serial resistor (50~100) fuse drive power system current limiter. suitable value resistor consideration display grade. Furthermore, when disconnecting power, drive output pins level DISPOFF function. After that,
disconnect logic system power after disconnecting drive power.
When connecting power supply, follow recommended sequence shown here.
DISPOFF
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ELECTRICAL SPECIFICATIONS
6.1. Absolute Maximum Ratings
Parameter Supply voltage Symbol Supply voltage Input voltage Storage temperature
Note1: Note2: maximum applicable voltage with respect (0V). Note3: Stresses beyond those given Absolute Maximum Rating table cause operational errors damage device. conditions AC/DC Electrical Characteristics. normal operational
Conditions
Applicable Pins V0L,
Ratings -0.3 +6.5 -0.3 -0.3 V0+0.3 -0.3 V0+0.3 -0.3 V0+0.3 -0.3 VDD+0.3 +125
Unit
Referenced (0V)
V12L, V12R V43L, V43R V5L, XCK, L/R, S/C, EIO1, EIO2, DISPOFF
TSTG
6.2. Recommended Operating Conditions
Parameter Supply voltage Supply voltage Operating temperature Symbol TOPR Conditions Referenced (0V) Applicable Pins V0L, Min. +2.5 Typ. Max. +5.5 Unit
Note1: applicable voltage with respect (0V). Note2: Ensure that voltage such that VSSV5V43V12V0
6.3. Characteristics 6.3.1. Segment mode
(VSS +2.5V +5.5V, +15V +30V, +25) Parameter Input voltage Symbol ILIH ILIL ISTB IDD1 IDD2 Conditions -0.4mA +0.4mA |VON| 0.5V +30V +20V Applicable Pins XCK, L/R, S/C, EIO1, EIO2, DISPOFF EIO1, EIO2 XCK, L/R, S/C, EIO1, EIO2, DISPOFF Y160 V0L, Min. 0.8VDD VDD-0.4 Typ. Max. 0.2VDD +0.4 Unit
Output voltage
Input leakage current
Output resistance Stand-by current Supply current (Deselection) Supply current (Selection) Supply current
Note1: +5.0V, +30V, Note2: +5.0V, +30V, fXCK 14.0MHz, No-load, VDD. input data turned over data taking clock (4-bit parallel input mode) Note3: +5.0V, +30V, fXCK 14.0MHz, No-load, VSS. mode. input data turned over data taking clock (4-bit parallel input mode) Note4: +5.0V, +30V, fXCK 14.0MHz, 41.6KHz, 80Hz, No-load. input data turned over data taking clock (4-bit parallel input
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6.3.2. Common mode
(VSS +2.5V +5.5V, +15V +30V, +25) Parameter Input voltage Symbol ILIH ILIL ISTB Conditions -0.4mA +0.4mA |VON| 0.5V +30V +20V Applicable Pins XCK, L/R, S/C, EIO1, EIO2, DISPOFF EIO1, EIO2 XCK, L/R, S/C, EIO1, EIO2, DISPOFF Y160 XCK, EIO1, EIO2, V0L, Min. 0.8VDD VDD-0.4 Typ. Max. 0.2VDD +0.4 Unit
Output voltage
Input leakage current
Output resistance Input pull-down current Stand-by current Supply current Supply current
Note1: +5.0V, +30V, Note2: +5.0V, +30V, 41.6KHz, 80Hz case 1/320 duty operation, no-load.
6.4. Characteristics 6.4.1. Segment mode
(VSS +4.5V +5.5V, +15V +30V, +25) Parameter Shift clock period Shift clock pulse width Shift clock pulse width Data setup time Data hold time Latch pulse pulse width Shift clock rise latch pulse rise time Shift clock fall latch pulse fall time Latch pulse rise shift clock rise time Latch pulse fall shift clock fall time Input signal rise time Input signal fall time Enable setup time Symbol TWCK TWCKH TWCKL TWLPH TWDL TPD1, TPD2 TPD3 Conditions TF10ns 15pF 15pF 15pF Min. Typ. Max. Unit
DISPOFF removal time DISPOFF pulse width
Output delay time Output delay time Output delay time
Note1: Take cascade connection into consideration.
Note2: (TWCK TWCKH TWCKL) maximum case high speed operation.
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6.4.2. Segment mode
(VSS +2.5V +4.5V, +15V +30V, +25) Parameter Shift clock period Shift clock pulse width Shift clock pulse width Data setup time Data hold time Latch pulse pulse width Shift clock rise latch pulse rise time Shift clock fall latch pulse fall time Latch pulse rise shift clock rise time Latch pulse fall shift clock fall time Input signal rise time Input signal fall time Enable setup time Symbol TWCK TWCKH TWCKL TWLPH TWDL TPD1, TPD2 TPD3 Conditions TF11ns 15pF 15pF 15pF Min. Typ. Max. Unit
DISPOFF removal time DISPOFF pulse width
Output delay time Output delay time Output delay time
Note1: Take cascade connection into consideration.
Note2: (TWCK TWCKH TWCKL) maximum case high speed operation.
6.5. Timing Characteristics Segment Mode
TWLPH
TWCKH
TWCKL
TWCK DATA
LAST DATA
TWDL
DISPOFF
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*n=40 4-bit parallel input mode. n=20 8-bit parallel input mode.
TPD1 TPD2
DISPOFF
TPD3 Y160
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6.5.1. Common mode
(VSS +2.5V +5.5V, +15V +30V, +25) Parameter Shift clock period Shift pulse width Data setup time Data hold time Input signal rise time Input signal fall time Symbol TWLP TWLPH TWDL TPD1, TPD2 TPD3 Conditions TF20ns +5.0V±10% +2.5V +4.5V 15pF 15pF 15pF Min. Typ. Max. Unit
DISPOFF removal time DISPOFF pulse width
Output delay time Output delay time Output delay time
6.5.2. Timing characteristics common mode
TWLP
TWLPH
EIO2 (DI7) EIO1 TWDL
DISPOFF
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TPD1 TPD2
DISPOFF
TPD3 Y160 [L/R "L"]
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PACKAGE/PAD LOCATIONS
7.1. Assignment
DISPOFF DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY EIO1 EIO2 Y160 Y159 Y158 Y157 Y156 Y155 Y154 Y153 Y152
(0,0)
Y141 Y142 Y143 Y144 Y145 Y146 Y147
Item Chip size pitch
150; 162; 170; 210; 151; 164; 171;
Size 7980 67.5 (Typ.)
Unit
Bumped size
162; 150; 170; Corner 151, 163,
Bumped height
Note1: Chip size included scribe line. Note2: ensure that functions properly, please bond pins. Note3: 0.1µF capacitor between should placed close possible.
7.2. Ordering Information
Product Number SPLC560C-C SPLC560C-P* Package Type Chip form Package form
Note: *The TCP's external shape customized. order your TCP's external shape, please contact SUNPLUS salesperson.
7.3. Align Coordinate
67.5 7980
Y153
r=29
Y147 Y148
r=29
Y149
Y152 Y150 Y151 67.5
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Y148 Y149 Y150 Y151
SPLC560C
7.4. Locations
Name -3923.11 -3923.11 -3923.11 -3923.11 -3923.11 -3923.11 -3923.11 -3923.11 -3923.11 -3890.00 -3822.50 -3767.50 -3712.50 -3657.50 -3602.50 -3547.50 -3492.50 -3437.50 -3382.50 -3327.50 -3272.50 -3217.50 -3162.50 -3107.50 -3052.50 -2997.50 -2942.50 -2887.50 -2832.50 -2777.50 -2722.50 -2667.50 -2612.50 -2557.50 -2502.50 -2447.50 -2392.50 -2337.50 -2282.50 -2227.50 -2172.50 -2117.50 -2062.50 -2007.50 159.00 104.00 49.00 -6.00 -61.00 -116.00 -171.00 -226.00 -281.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 Name -1952.50 -1897.50 -1842.50 -1787.50 -1732.50 -1677.50 -1622.50 -1567.50 -1512.50 -1457.50 -1402.50 -1347.50 -1292.50 -1237.50 -1182.50 -1127.50 -1072.50 -1017.50 -962.50 -907.50 -852.50 -797.50 -742.50 -687.50 -632.50 -577.50 -522.50 -467.50 -412.50 -357.50 -302.50 -247.50 -192.50 -137.50 -82.50 -27.50 27.50 82.50 137.50 192.50 247.50 302.50 357.50 412.50 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 APR. 2002 Preliminary Version:
Sunplus Technology Co., Ltd. Proprietary Confidential
SPLC560C
Name Y100 Y101 Y102 Y103 Y104 Y105 Y106 Y107 Y108 Y109 Y110 Y111 Y112 Y113 Y114 Y115 Y116 Y117 Y118 Y119 Y120 Y121 Y122 Y123 Y124 Y125 Y126 Y127 Y128 Y129 Y130 Y131 Y132 Y133 467.50 522.50 577.50 632.50 687.50 742.50 797.50 852.50 907.50 962.50 1017.50 1072.50 1127.50 1182.50 1237.50 1292.50 1347.50 1402.50 1457.50 1512.50 1567.50 1622.50 1677.50 1732.50 1787.50 1842.50 1897.50 1952.50 2007.50 2062.50 2117.50 2172.50 2227.50 2282.50 2337.50 2392.50 2447.50 2502.50 2557.50 2612.50 2667.50 2722.50 2777.50 2832.50 2887.50 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 Name Y134 Y135 Y136 Y137 Y138 Y139 Y140 Y141 Y142 Y143 Y144 Y145 Y146 Y147 Y148 Y149 Y150 Y151 Y152 Y153 Y154 Y155 Y156 Y157 Y158 Y159 Y160 EIO2 DUMMY DUMMY 2942.50 2997.50 3052.50 3107.50 3162.50 3217.50 3272.50 3327.50 3382.50 3437.50 3492.50 3547.50 3602.50 3657.50 3712.50 3767.50 3822.50 3890.00 3923.11 3923.11 3923.11 3923.11 3923.11 3923.11 3923.11 3923.11 3923.11 3923.11 3923.11 3913.55 3846.05 3791.05 3736.05 3681.05 3626.05 3571.05 3516.05 3287.12 3131.77 3051.77 2852.27 2672.27 2470.00 2290.00 2110.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -421.00 -281.00 -226.00 -171.00 -116.00 -61.00 -6.00 49.00 104.00 159.00 214.00 269.00 415.00 415.00 415.00 415.00 415.00 415.00 415.00 415.00 394.33 394.33 394.33 394.33 394.33 394.33 394.33 394.33 APR. 2002 Preliminary Version:
Sunplus Technology Co., Ltd. Proprietary Confidential
SPLC560C
Name DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY 1907.60 1711.20 1477.60 1281.20 1047.60 851.20 617.60 421.20 175.00 -175.00 -440.40 -607.07 -787.07 -967.07 -1152.07 -1332.07 -1605.60 -1879.12 394.33 394.33 394.33 394.33 394.33 394.33 394.33 394.33 394.33 394.33 394.33 394.33 394.33 394.33 394.33 394.33 394.33 394.33 Name DUMMY DUMMY EIO1 DUMMY -2164.12 -2344.12 -2524.12 -2768.00 -2948.00 -3134.82 -3314.82 -3515.50 -3570.50 -3625.50 -3680.50 -3735.50 -3790.50 -3845.50 -3913.00 -3923.11 -3923.11 394.33 394.33 394.33 394.33 394.33 394.33 394.33 415.00 415.00 415.00 415.00 415.00 415.00 415.00 415.00 269.00 214.00
DISPOFF
DUMMY
Sunplus Technology Co., Ltd. Proprietary Confidential
APR. 2002 Preliminary Version:
SPLC560C
DISCLAIMER
information appearing this publication believed accurate. Integrated circuits sold Sunplus Technology covered warranty patent indemnification provisions stipulated terms sale only. SUNPLUS makes warranty, express, statutory implied description regarding information this publication FURTHERMORE, SUNPLUS MAKES WARRANTY SUNPLUS reserves right halt production alter specifications regarding freedom described chip(s) from patent infringement. MERCHANTABILITY FITNESS PURPOSE. prices time without notice. publication current before placing orders.
Accordingly, reader cautioned verify that data sheets other information this Products described herein intended normal commercial applications. Please note that application circuits
Applications involving unusual environmental reliability requirements, e.g. military equipment medical life support equipment, specifically recommended without additional processing SUNPLUS such applications. illustrated this document reference purposes only.
Sunplus Technology Co., Ltd. Proprietary Confidential
APR. 2002 Preliminary Version:
SPLC560C
REVISION HISTORY
Date APR. 2002 Revision Original Description Page
Sunplus Technology Co., Ltd. Proprietary Confidential
APR. 2002 Preliminary Version:

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