Grey Level 80-Channel SEG/COM Driver FEB. 2002 Version SUNPL

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

Grey Level 80-Channel SEG/COM Driver FEB. 2002 Version SUNPL

Datasheet Thumbnail

Top Searches for this datasheet

SPLD801B
Grey Level 80-Channel SEG/COM Driver
FEB. 2002 Version
SUNPLUS TECHNOLOGY infringement patent other rights third parties which result from use. addition, SUNPLUS products authorized critical components life support devices/ systems aviation devices/systems, where malfunction failure product reasonably expected result significant injury user, without express written approval Sunplus.
SPLD801B
Table Contents
PAGE
GENERAL DESCRIPTION. BLOCK DIAGRAM FEATURES. SIGNAL DESCRIPTIONS FUNCTIONAL DESCRIPTIONS. 5.1. COMMAND/NORMAL MODE 5.2. GRAY LEVEL/BW (BLACK WHITE) MODE 5.3. INTERNAL BOOSTER CONTROL 5.4. GRAY SCALE CLOCK GENERATOR 5.5. BIAS/BRIGHTNESS CONTROL 5.6. BI-DIRECTION NUMBER COMMONS/ SEGMENTS CONTROL 5.7. TRIPLE/DOUBLE NATIVE VOLTAGE BOOSTER ELECTRICAL SPECIFICATIONS 6.1. ABSOLUTE MAXIMUM RATINGS 6.2. CHARACTERISTICS.11 6.3. CHARACTERISTICS APPLICATION CIRCUITS. 7.1. APPLICATION CIRCUIT (1). 7.2. APPLICATION CIRCUIT (2). 7.3. APPLICATION CIRCUIT (3). 7.4. APPLICATION CIRCUIT (4). PACKAGE/PAD LOCATIONS 8.1. ASSIGNMENT 8.2. ORDERING INFORMATION 8.3. LOCATIONS DISCLAIMER. REVISION HISTORY
Sunplus Technology Co., Ltd. Proprietary Confidential
FEB. 2002 Version:
SPLD801B
GREY LEVEL 80-CHANNEL SEG/COM DRIVER
GENERAL DESCRIPTION
SPLD801B, 4-gray level matrix driver with high voltage CMOS technology from SUNPLUS, able provide varieties common/segment combinations application. Four types combinations provided: segments, SEG, SEG, SEG. operating voltage SPLD801B from 2.4V through 5.5V with maximum 3.0MHz operating frequency rate 3.3V). addition, this includes 160-bit shift register, 160-bit data latch, 80-bit 4-level driver, built voltage buffer resisters bias charge pump VLCD voltage.
FEATURES
Gray Level driver: gray level selected from gray scale Operation voltage 2.4V 5.5V Maximum working frequency: 3.0MHz 3.3V driver voltage 12V(VDD VOUT) Built-in voltage converter (Double /Triple Negative Voltage generator) BIAS voltage supplied externally Serial data input Interface compatible with series controller Provide 1-bit Mode display mode Built bias control (1/5 bias 1/12.5 bias)
BLOCK DIAGRAM
Built level brightness control 4-type combination: Segments, SEG,
SEG, Chain function both Segment driver Common driver
Command mode Data Latch bits
Shifter register bits bits
Command Latch bits
DOUT
Common/Segment Data Latch bits bits
Command mode
Decoder
Gray scale control
Level shifter selector
Oscillator
driver bits (segment/common)
Bias Voltage Generator
VOUT
Y1-Y80
Sunplus Technology Co., Ltd. Proprietary Confidential
FEB. 2002 Version:
SPLD801B
SIGNAL DESCRIPTIONS
Mnemonic O[1:4] O[5:80] DOUT VOUT data shift clock, selected timebase gray scale clock. data shifted latch falling edge "CP" Line pulse. Data shifted into 160-bit shift register would latched line buffer falling edge Frame pulse. used common data input command mode selection. alternate signal Data input. command/display data would shift into SPLD801B through Serial data output. next driver. Digital power Ground reference voltage VOUT Coupling capacitor charge pump Coupling capacitor charge pump Coupling capacitor charge pump Coupling capacitor charge pump Triple Double voltage output Programming mode. some functions Gray clock input. clock. When would input generate gray scale pulled internally. When SPLD801B programmed When segment number larger than 80,DO cascade with Type Initial state Segment /Common output Description
Common/Segment Bi-direction selection
Sunplus Technology Co., Ltd. Proprietary Confidential
FEB. 2002 Version:
SPLD801B
FUNCTIONAL DESCRIPTIONS
5.1. Command/Normal Mode
controlled controller through I/O. command/segment data shifted serially When from latched simultaneously next When '0', SPLD801B enters normal operating mode, segment data shifted from segment register through shift clock '1', SPLD801B enters command mode. command/segment register through shift clock
Action SPLD801B Command mode: Normal mode: Shift command/segment data from command/segment register Shift segment data from segment register
Status data from controller, which include command data (the last bits) segment data (the rests) segment data from controller
timing diagram (Line pulse), (Programming mode), (Frame pulse), (Data shown follows:
Address COM0 COM1
Display DATA
bits
Command
Common Data
Command
Common Data
command data should placed address N+M, where address first common (COM Display Data RAM. When falling edge next would latch this command data into command registers. necessary make sure that pulse width wide enough cover period Moreover, SPLD801B supports
cascade function more dots application. necessary program SPLD801B times when SPLD801B cascaded shown following diagram. command1 data would program first SPLD801B, command2 data would program second SPLD801B.
Address COM0 COM1 Command2
Command1
first SPLD801B
second SPLD801B
Display DATA
Frame
Common Data(2)
Command2
Frame
Common Data(1)
Command1
Common Data(2)
Common Data(1)
Common Data(2)
Command2
Common Data(1)
Command1
Common Data(2)
Common Data(1)
Sunplus Technology Co., Ltd. Proprietary Confidential
FEB. 2002 Version:
SPLD801B
5.1.1. Command/Display data
last bits segment data COM0 defined command data when '1'. Note that only bits (all command except LUT23, LUT22, LUT21, LUT20) supported segments commons mode. Therefore, user should skip these bits (LUT23, LUT22, LUT21, LUT20) command when segments commons mode segments commons mode (two SPLD801B cascaded) selected.
Address $0XN $0X(N+1) -$0X(N+M-4) $0X(N+M-3) $0X(N+M-2) $0X(N+M-1) $0X(N+M) Data Data Data Data BIASEN LUT13 LUT33
Common0 COMMAND DISPLAY Data Data Data Data Data MEN1 LUT12 LUT32 Data Data Data Data LUT11 LUT31 Data Data Data Data GCP4 LUT10 LUT30 Data Data Data LUT23 GCP3 LUT03 Data Data Data LUT22 GCP2 LUT02 Data Data Data LUT21 GCP1 LUT01 Data Data Data LUT20 GCP0 LUT00 BIT1
following diagram corresponds data stored Display Data Panel. Data that first shift from Display Data (AddressN would shift SEGN Panel.
Note: SEG1 means first segment, take mode segments example, SEG1 would output when output when
Command Display Data Command Display Data
Address Address Address Address Address Address Address Address
SEG1 SEG2
Address Address Address Address Address
SEGN
Address Address Address
COM0 COM1
(D7-0) (D7-0) (D7-0)
N+M-4 N+M-3 N+M-2 N+M-1 (D7-0) (D7-0) (D7-0) (D7-0) (D7-0)
COM0 COM1
N+M-1 N+M-2 N+M-3 N+M-4 (D0-7) (D0-7) (D0-7) (D0-7) (D0-7)
(D0-7) (D0-7)
(D0-7)
DISPLAY DATA
COMX COMX
Memory Mapping
Panel
5.2. Gray Level/BW (Black White) Mode
SPLD801B supports display modes setting BIT1 command. BIT1 register: Gray Level Mode Mode Gray Level Mode, users able select 4-level gray scale from levels acquire best display quality setting register. Each gray scale ranges from levels) that indicates level gray color, from light dark, shown following table. Sunplus Technology Co., Ltd. Proprietary Confidential
5.2.1. register: 4-level gray scale selection
Symbol LUT03 LUT13 LUT23 LUT33 Data (MSB, LSB) Description gray scale gray scale gray scale gray scale
bits display data decide segment output Gray Level Mode. Thus, amount data Gray Level Mode double than Mode. Please refer following example details.
FEB. 2002 Version:
SPLD801B
Example: LUT03 0000, gray scale Gray Level LUT13 0110, gray scale Gray Level LUT23 1010, gray scale Gray Level LUT33 1111, gray scale Gray Level
Note1: recommended that only first four gray scales
then gray color would display output. Level16 Level7 Level1 Level11
display data
(1/16,2/16,3/16 4/16 scale) generate lightest gray color acquire better display quality. Note2: necessary register mode.
5.2.2. Gray scale timing chart
frame COM0
Selected period (one horizontal period)
SEG0
Gray level Gray level Gray level Gray level Gray level Gray level Gray level Gray level Gray level Gray level Gray level Gray level Gray level Gray level Gray level Gray level
1/16 2/16 3/16 4/16 5/16 Active pulse width= 6/16 period 7/16 8/16 9/16 10/16 11/16 12/16 13/16 14/16 15/16 15/16
LUT:<0000> LUT:<0001> LUT:<0010> LUT:<0011> LUT:<0100> LUT:<0101> LUT:<0110> LUT:<0111> LUT:<1000> LUT:<1001> LUT:<1010> LUT:<1011> LUT:<1100> LUT:<1101> LUT:<1110> LUT:<1111>
D148 D149 D150 D151 D152 D153 D154 D155 D156 D157 D158 D159 seg3 seg2 seg1
seg80
seg79
seg78
seg77
Sunplus Technology Co., Ltd. Proprietary Confidential
FEB. 2002 Version:
SPLD801B
5.3. Internal Booster Control
SPLD801B supports internal Booster generate Bias voltage. Both Booster shut down save power. SPLD801B enter standby mode MEN1 BIASEN Moreover, output booster will pulled VSS. When MEN1 output booster TRI-state. Users external native voltage replace output internal booster. controlled BIASEN. keep TRI-state. BIAS When BIASEN would output
stable bias voltage, when BIASEN would
BIASEN
MEN1
Booster
Output Booster TRI-state Triple double voltage Triple double voltage TRI-state TRI-state
Bias
Output Ground Bias voltage TRI-state Bias voltage TRI-state Bias voltage
5.4. Gray Scale Clock Generator
SPLD801B method (Pulse Width Modulation) generate waveform segment. necessary register register correctly acquire right waveform segment. register: select clock source CK1) generate gray level scale. (CPF2 registers must series) (When number segment larger than 512. external input selected generate gray level scale.) clock signal used generate Gray Scale clock. recommended that should number segment less than 512. GCP[4:0] register: formula shown follows: Gray Level mode: Divider Total number segment(A) number gray level(2)÷32 (number scale) preset value GCP[4:0] (Divider mode, please refer value listed following table. table show value GCP[4:0] register: Segment Common 32x48 48x32 64x16 80x0 112x48 128x32 144x16 160x0 00000 00000 00001 00001 00010 00011 00011 00100 Gray Level 00001 00010 00011 00100 00110 00111 01000 01001
Note1: When gray level driver used, Register from series must ensure clock source truly duty cycle square wave. gray level clock source isn't exactly pulse width defined Therefore, sure duty cycle square wave, will appropriate gray level pulse width signals. Register will skip some combinations miss some colors because Register `0'. Register when using gray level driver. Note2: register should correctly only Gray Level mode also mode prevent incorrect action SPLD801B.
Sunplus Technology Co., Ltd. Proprietary Confidential
FEB. 2002 Version:
SPLD801B
5.4.1.1. Example1:
Segments Commons panel, total segment number Therefore, (Divider GCP[4:0] should [00010] Frame Rate: 60Hz Clock 184.32KHz Clock (for series) 1.47456MHz (For example Frame Rate: 80Hz Clock 245.76KHz Clock (for series) 1.96608MHz (For example Clock selected between 1.47456MHz register: bits bias selection BS[3:0] 0000 0001 0010 0011 Bias 0100 0101 0110 1100 1/10 1101 1/11 1110 0111 1/12 1111
5.5. Bias/Brightness Control
SPLD801B supports bias selection panel.
BS[3:0] 1000 1001 1010 1011 Bias
1/5.5 1/6.5 1/7.5 1/8.5 1/9.5 1/10.5 1/11.5 1/12.5
register: levels brightness selections SPLD801B support levels adjustment voltage.
reference value VLCD (=VDD voltage listed
table follows. formula: VLCD= (The value listed table) equal triple voltage mode, equal double voltage mode.
BRIGHTNESS CONTROL 10.5 11.5 12.5 BIAS CONTROL 0.903 0.911 0.917 0.923 0.928 0.933 0.937 0.940 0.943 0.946 0.949 0.951 0.953 0.955 0.957 0.959 0.861 0.872 0.881 0.889 0.896 0.903 0.908 0.913 0.917 0.921 0.925 0.928 0.931 0.934 0.937 0.939 0.822 0.836 0.847 0.858 0.866 0.874 0.881 0.887 0.893 0.898 0.903 0.907 0.911 0.914 0.917 0.920 0.787 0.803 0.816 0.828 0.838 0.847 0.856 0.863 0.870 0.876 0.881 0.886 0.891 0.895 0.899 0.903 0.755 0.772 0.787 0.800 0.812 0.822 0.832 0.840 0.847 0.854 0.861 0.866 0.872 0.877 0.881 0.885 0.726 0.744 0.760 0.775 0.787 0.799 0.809 0.818 0.826 0.834 0.841 0.847 0.853 0.859 0.864 0.869 0.698 0.718 0.735 0.751 0.764 0.776 0.787 0.797 0.806 0.815 0.822 0.829 0.836 0.842 0.847 0.853 0.673 0.694 0.712 0.728 0.742 0.755 0.767 0.778 0.787 0.796 0.805 0.812 0.819 0.826 0.832 0.837
1.96608MHz, Frame Rate panel will between 60Hz 80Hz.
5.4.1.2. Example
Segment Common panel, total segment number Therefore, 160, (Divider (160 10-1 GCP[4:0] should [01001] Frame Rate: 60Hz Clock (160 1.536MHz Clock (for series) 3.072MHz (For example 6.144MHz (For example Frame Rate: 80Hz Clock (160 2.048MHz Clock (for series) 4.096MHz (For example 8.192MHz (For example Clock selected between 3.072MHz 4.096MHz (6.144MHz 8.192MHz), Frame Rate panel will between 60Hz 80Hz.
value listed table calculated without loading effect, have some decrease panel loading.
Sunplus Technology Co., Ltd. Proprietary Confidential
FEB. 2002 Version:
SPLD801B
5.6. Bi-Direction Number Commons/ Segments Control
register: 2-bit register programming number Commons Segments DIR: SPLD801B support bi-direction output segment common driver which listed following table. Take panel with segments commons example, when output segment segment common1, common should O49, respectively. Moreover, should value capacitance would range from 0.1µF 4.7µF stable output voltage. O80, O33, O32, when
5.7. Triple/Double Native Voltage Booster
SPLD801B supports internal booster generate native voltage bias voltage. When three capacitors placed between C1N, C2N, VOUT respectively, internal booster output triple native voltage. Moreover, when capacitors placed between C1N, VOUT respectively, internal booster output double native voltage. Note that should shorted VOUT double native voltage mode.
Segment Common
Segment Common
Segment Common
Internal Booster
Internal Booster
VOUT
VOUT
Sunplus Technology Co., Ltd. Proprietary Confidential
FEB. 2002 Version:
SPLD801B
ELECTRICAL SPECIFICATIONS
6.1. Absolute Maximum Ratings
Characteristics Supply Voltage Input Voltage Range Operating Temperature Storage Temperature
conditions AC/DC Electrical Characteristics.
Symbol Tsto
Ratings 7.0V -0.5V 0.5V +150
normal operational
Note: Stresses beyond those given Absolute Maximum Rating table cause operational errors damage device.
6.2. Characteristics
Characteristics Operation Voltage Voltage Operation Current Leakage Current Leakage Current Leakage Current Operation Frequency Input Level Level Level Level Symbol VLCD ILEAK1 ILEAK2 ILEAK3 Limit Min. VDD-0.4 Typ. Max. PGM, DOUT Applicable PINs Unit VLCD 1.0MHz VLCD VLCD 3.3V, 3.3V 5.0V, 5.0V 3.3V 3.3V 3.3V, 0.2mA, 0.2mA, VLCD 10V, Load current 100µA Test Condition
Output
Driver Resistance
Sunplus Technology Co., Ltd. Proprietary Confidential
FEB. 2002 Version:
SPLD801B
6.3. Characteristics
Parameter Clock pulse width rising falling time Line Pulse width rising falling time falling edge rising edge falling edge rising edge Data setup time Data hold time falling edge rising edge falling edge falling edge Symbol TW(CP) Tr(CP) Tf(CP) TW(LP) Tr(LP) Tf(LP) Tdsetup Tdhold TLFR TLFF Limit Min. Typ. Max. Unit
TLFF
TW(LP)
r(CP)
W(CP)
r(LP)
f(LP)
f(CP) Tdsetup Tdhold
Sunplus Technology Co., Ltd. Proprietary Confidential
FEB. 2002 Version:
FEB. 2002
O[80:49] COM1 COM2
SPLD801B
Common Segment
PANEL
SPLD801B
O[80:1] VOUT O[80:1]
COM31 COM32
O[48:1]
0.1µF DOUT
0.1µF
0.1µF 0.1µF
APPLICATION CIRCUITS
7.1. Application Circuit
Fig(1): SPLD801B Double Negative Voltage With
Proprietary Confidential
0.1µF
0.1µF
Sunplus Technology Co., Ltd.
SPL130A
0.1µF
SEG47 SEG48
SEG1 SEG2
Version:
FEB. 2002
COM1 COM2 O[32:1] COM31 COM32
SPLD801B
Common Segment
PANEL
SPLD801B
VOUT O[80:1] O[80:1]
O[80:33]
0.1µF DOUT
0.1µF
0.1µF 0.1µF
7.2. Application Circuit
Fig(2): SPLD801B Double Negative Voltage With High
Proprietary Confidential
0.1µF
0.1µF
Sunplus Technology Co., Ltd.
SPL130A
0.1µF
SEG47 SEG48
SEG1 SEG2
Version:
FEB. 2002
SEG80 SEG81
SEG[80:1]
SPLD801B
COM1 COM2
C[80:1]
Common Segment
O[80:1] CUP2 0.1µ DO80
SPLD802
PANEL
COM79 COM80 SEG1
VSS2
SEG160
S160 0.1µ CUP1
SEG[160:81]
O[80:1]
O[80:1]
LCDEN
SPLD801B
VOUT
0.1µF
SPL130A
0.1µF 0.1µF 0.1µF
0.1µF
SPLD801B
VOUT
0.1µF
0.1µF
DOUT
DOUT
7.3. Application Circuit
Sunplus Technology Co., Ltd.
0.1µF
Fig(3): SPLD802 SPLD801BX2 Common*160 Segment Panel With Triple Native Voltage(VEE) Dir=Low
Proprietary Confidential
Version:
FEB. 2002
SEG80 SEG81 S160
SEG[80:1]
SPLD801B
COM1 COM2
C[80:1]
Common Segment
O[80:1] DO80 CUP2 0.1µ
SPLD802
PANEL
COM79 COM80 SEG1
VSS2
SEG160
0.1µ CUP1
SEG[160:81]
O[80:1]
O[80:1]
LCDEN
SPLD801B
0.1µF
SPL130A
7.4. Application Circuit
Fig(4): SPLD802 SPLD801BX2 Common*160 Segment Panel With Triple Native Voltage(VEE) Dir=High
Proprietary Confidential
Sunplus Technology Co., Ltd.
VOUT
0.1µF 0.1µF 0.1µF
0.1µF
SPLD801B
VOUT
0.1µF
0.1µF
DOUT
DOUT
0.1µF
Version:
SPLD801B
PACKAGE/PAD LOCATIONS
8.1. Assignment
Chip Size: 4730µm 4320µm This substrate should connected
Note1: Chip size included scribe line. Note2: 0.1µF capacitor between should placed close possible.
8.2. Ordering Information
Product Number SPLD801B-nnnnV-C
Note1: Code number (nnnnV) assigned customer. Note2: Code number (nnnn 0000 9999); version
Package Type Chip form
Sunplus Technology Co., Ltd. Proprietary Confidential
FEB. 2002 Version:
SPLD801B
8.3. Locations
Name DOUT VOUT -2161 -2161 -2161 -2161 -2166 -2166 -2166 -2166 -2166 -2166 -2166 -2166 -2166 -2166 -2166 -2166 -2166 -2166 -2166 -2166 -2166 -2166 -2166 -2166 -2166 -808 -652 -492 -348 -204 1092 1236 1380 1524 1668 1812 1746 1590 1440 1296 1146 1008 -248 -386 -524 -662 -800 -938 -1076 -1214 -1371 -1527 -1689 -1970 -1970 -1970 -1970 -1970 -1970 -1970 -1970 -1970 -1970 -1970 -1970 -1970 -1970 -1970 -1970 -1970 -1970 -1970 Name 1968 2136 2173 2173 2173 2173 2173 2173 2173 2173 2173 2173 2173 2173 2173 2173 2173 2173 2173 2173 2173 2173 2173 2173 2173 2173 2173 2173 1956 1803 1651 1507 1363 1219 1075 -220 -1970 -1970 -1746 -1566 -1406 -1262 -1118 -974 -830 -686 -542 -398 -254 -110 1041 1185 1329 1473 1617 1773 1935 1968 1968 1968 1968 1968 1968 1968 1968 1968 1968 1968 1968 1968 1968 1968 1968
Sunplus Technology Co., Ltd. Proprietary Confidential
FEB. 2002 Version:
SPLD801B
Name -364 -508 -652 -796 -940 -1084 -1228 1968 1968 1968 1968 1968 1968 1968 Name -1372 -1516 -1660 -1804 -1959 -2115 1968 1968 1968 1968 1968 1968
Sunplus Technology Co., Ltd. Proprietary Confidential
FEB. 2002 Version:
SPLD801B
DISCLAIMER
information appearing this publication believed accurate. Integrated circuits sold Sunplus Technology covered warranty patent indemnification provisions stipulated terms sale only. SUNPLUS makes warranty, express, statutory implied description regarding information this publication FURTHERMORE, SUNPLUS MAKES WARRANTY SUNPLUS reserves right halt production alter specifications regarding freedom described chip(s) from patent infringement. MERCHANTABILITY FITNESS PURPOSE. prices time without notice. publication current before placing orders.
Accordingly, reader cautioned verify that data sheets other information this Products described herein intended normal commercial applications. Please note that application circuits
Applications involving unusual environmental reliability requirements, e.g. military equipment medical life support equipment, specifically recommended without additional processing SUNPLUS such applications. illustrated this document reference purposes only.
Sunplus Technology Co., Ltd. Proprietary Confidential
FEB. 2002 Version:
SPLD801B
REVISION HISTORY
Date MAY. 2001 JUL. 2001 Revision Original Revise working voltage range from 2.4V 5.5V 2.4V 4.0V Revise maximum clock rate from 4.0MHz 3.0MHz Correct chip size Note1 "9.1 Assignment" Renew document format OCT. 2001 Delete "PRELIMINARY" Revise working voltage range from 2.4V 4.0V 2.4V 5.5V FEB. 2002 C1N, PIN23 Description Page
Sunplus Technology Co., Ltd. Proprietary Confidential
FEB. 2002 Version:

Grey Level 80-Channel SEG/COM Driver FEB. 2002 Version SUNPL

Top Searches for this datasheet

Other recent searches