PCF2104x controller/driver Product specification Supersedes data

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PCF2104x controller/driver Product specification Supersedes data

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PCF2104x controller/driver
Product specification Supersedes data 1997 File under Integrated Circuits, IC12 1997
Philips Semiconductors
Product specification
controller/driver
CONTENTS 7.10 7.11 7.12 8.10 8.11 8.12 8.13 8.14 8.15 8.16 9.3.1 9.3.2 FEATURES APPLICATIONS GENERAL DESCRIPTION Packages Available types ORDERING INFORMATION BLOCK DIAGRAM PINNING FUNCTIONS register select (parallel control) R/W: read/write (parallel control) data clock (parallel control) DB7: data (parallel control) C60: column driver outputs R32: driver outputs VLCD: power supply OSC: oscillator SCL: serial clock line SDA: serial data line SA0: address test FUNCTIONAL DESCRIPTION bias voltage generator Oscillator External clock Power-on reset Registers Busy Flag Address Counter (AC) Display data (DDRAM) Character generator (CGROM) Character generator (CGRAM) Cursor control circuit Timing generator column drivers Programming displays with PCF2104x Programming displays with PCF2104x Reset function INSTRUCTIONS Clear display Return home Entry mode 9.4.1 9.4.2 9.4.3 9.6.1 9.6.2 9.10 9.11 11.1 11.2 11.3 11.4 11.5 11.6 17.1 17.2 17.3 17.4 17.5
PCF2104x
Display on/off control Cursor/display shift Function (parallel mode only) CGRAM address DDRAM address Read busy flag address Write data CGRAM DDRAM Read data from CGRAM DDRAM INTERFACE MICROCONTROLLER (PARALLEL INTERFACE) INTERFACE MICROCONTROLLER (I2C-BUS INTERFACE) Characteristics I2C-bus transfer Start stop conditions System configuration Acknowledge I2C-bus protocol LIMITING VALUES HANDLING CHARACTERISTICS CHARACTERISTICS TIMING DIAGRAMS APPLICATION INFORMATION 8-bit operation, display using internal reset 4-bit operation, display using internal reset 8-bit operation, display operation, display Initializing instruction BONDING LOCATIONS DEFINITIONS LIFE SUPPORT APPLICATIONS PURCHASE PHILIPS COMPONENTS
1997
Philips Semiconductors
Product specification
controller/driver
FEATURES
PCF2104x
does contain high voltage generator that device. PCF2104x optimized chip-on-glass applications. `PCF2104x' represents specific letter code character character generator (CGROM). standard character sets currently available, specified letters (see Figs Other character sets available request. PCF2104x low-power CMOS controller driver, designed drive split screen matrix display lines characters lines characters with format. necessary functions display provided single chip, including on-chip generation bias voltages which results minimum external components lower system power consumption. allow partial shutdown protection system pins does diode connected VDD. chip contains character generator displays alphanumeric kana characters. PCF2104x interfaces most microcontrollers 8-bit bus, 2-wire I2C-bus. Packages
Single chip controller/driver 2-line display characters line, lines characters line character format plus cursor; kana (Japanese syllabary) user-defined symbols On-chip: generation intermediate bias voltages oscillator requires external components (external clock also possible) Display data RAM: characters Character generator ROM: characters Character generator RAM: characters 8-bit parallel 2-wire I2C-bus interface CMOS/TTL compatible row, column outputs rates Uses common code instruction Logic supply voltage range, VSS: Display supply voltage range, VLCD: power consumption. I2C-bus address: 011101 SA0. APPLICATIONS
PCF2104xU/2; chip with bumps tray PCF2104xU/7; chip with bumps tape. further details Chapter Available types
Telecom equipment Portable instruments Point-of-sale terminals. GENERAL DESCRIPTION
PCF2104CU/x: character CGROM PCF2104LU/x: character CGROM PCF2104NU/x: character CGROM.
PCF2104x integrated circuit similar PCF2114x (described "PCF2116 family" data sheet) ORDERING INFORMATION PACKAGE TYPE NUMBER NAME PCF2104CU/2 PCF2104CU/7 PCF2104LU/2 PCF2104LU/7 PCF2104NU/2 PCF2104NU/7 1997 chip with bumps tray chip with bumps tape chip with bumps tray chip with bumps tape chip with bumps tray chip with bumps tape DESCRIPTION VERSION
Philips Semiconductors
Product specification
controller/driver
BLOCK DIAGRAM
PCF2104x
handbook, full pagewidth
5-20 81-96 DRIVERS SHIFT REGISTER 32-BIT
80-21 BIAS VOLTAGE GENERATOR COLUMN DRIVERS
DATA LATCHES SHIFT REGISTER 12-bit CURSOR DATA CONTROL CHARACTER GENERATOR (CGRAM) CHARACTERS CHARACTER GENERATOR (CGROM) CHARACTERS
PCF2104x
OSCILLATOR
DISPLAY DATA (DDRAM) CHARACTERS ADDRESS COUNTER (AC) INSTRUCTION DECODER DATA REGISTER (DR) BUSY FLAG INSTRUCTION REGISTER (IR) BUFFER 109-106 105-102
TIMING GENERATOR
DISPLAY ADDRESS COUNTER
POWER RESET
MGC627
Fig.1 Block diagram.
1997
Philips Semiconductors
Product specification
controller/driver
PINNING SYMBOL VLCD FUNCTIONS register select (parallel control) to12 TYPE
PCF2104x
DESCRIPTION oscillator/external clock input logic supply voltage I2C-bus address input ground driver outputs driver outputs driver outputs column driver outputs driver outputs driver outputs driver outputs I2C-bus serial clock input data clock input register select input read/write input test input 8-bit bidirectional data input/output I2C-bus serial data input/output supply voltage input DB7: data (parallel control)
selects register accessed read write when device controlled parallel interface. logic selects instruction register write Busy Flag Address Counter read. logic selects data register both read write. There internal pull-up R/W: read/write (parallel control)
bidirectional, 3-state data transfers data between system controller PCF2104x. used Busy Flag, signalling that internal operations completed. 4-bit operations higher order lines used; must left open circuit. There internal pull-up each data lines. Note that these pins must left open circuit when I2C-bus control used. C60: column driver outputs
selects either read (R/W logic write (R/W logic operation when control parallel interface. There internal pull-up this pin. data clock (parallel control)
These pins output data pairs columns. This arrangement permits optimized chip-on-glass (COG) layout 4-line characters. R32: driver outputs
HIGH signal start read write operation when device controlled parallel interface. Data clocked chip negative edge clock. Note that this must tied logic (VSS) when I2C-bus control used.
These pins output select waveforms left right halves display. VLCD: power supply
Negative power supply liquid crystal display.
1997
Philips Semiconductors
Product specification
controller/driver
OSC: oscillator Oscillator
PCF2104x
When on-chip oscillator used, this must connected VDD. external clock signal, used, input this pin. SCL: serial clock line
on-chip oscillator provides clock signal display system. external components required. must connected VDD. External clock
Input I2C-bus clock signal. 7.10 SDA: serial data line
Input/output I2C-bus data line. 7.11 SA0: address
external clock used, must input OSC. resulting display frame frequency given fframe 1/2304fosc. clock signal must always present, otherwise frozen state. Power-on reset
hardware sub-address line used program device sub-address different PCF2104xs same I2C-bus. 7.12 test
Power-on reset block initializes chip after power-on power failure. Registers
Must connected VSS. user accessible. FUNCTIONAL DESCRIPTION (see Fig.1) bias voltage generator
PCF2104x 8-bit registers, instruction register (IR) data register (DR). register select signal (RS) determines which register will accessed. instruction register stores instruction codes such display clear cursor shift, address information Display Data (DDRAM) Character Generator (CGRAM). instruction register written read from, system controller. data register temporarily stores data read from DDRAM CGRAM. When reading, data from DDRAM CGRAM (corresponding address Address Counter) written data register prior being read `Read data' instruction. Busy Flag
intermediate bias voltages display also generated on-chip. This removes need external resistive bias chain significantly reduces system power consumption. optimum levels depend multiplex rate selected automatically when number lines display defined. optimum value depends multiplex rate, threshold voltage (Vth) number bias levels. relationships given Table Using 5-level bias scheme rate allows most liquids. effect display contrast negligible. Table RATE Optimum values NUMBER BIAS LEVELS VOP/Vth 3.67 5.19 DISCRIMINATION Von/Voff 1.277 1.196
Busy Flag indicates free/busy status PCF2104x. Logic indicates that chip busy further instructions will accepted. Busy Flag output when logic logic Instructions should only written after checking that Busy Flag logic waiting required number clock cycles.
1997
Philips Semiconductors
Product specification
controller/driver
Address Counter (AC) 8.10
PCF2104x
Character generator (CGRAM)
Address Counter assigns addresses DDRAM CGRAM reading writing instructions `Set CGRAM address' `Set DDRAM address'. After read/write operation Address Counter automatically incremented decremented Address Counter contents output (DB0 DB6) when logic logic Display data (DDRAM)
user-defined characters stored character generator RAM. CGROM CGRAM common address space, which first column reserved CGRAM (see Fig.5). Figure shows addressing principle CGRAM. 8.11 Cursor control circuit
DDRAM stores characters display data, represented 8-bit character codes. DDRAM locations used storing display data used general purpose RAM. basic DDRAM-to-display mapping scheme shown Fig.2. With display shift, characters represented codes first locations, starting address line displayed. Subsequent lines display data starting addresses Hex. Figures show DDRAM-to-display mapping scheme when display shifted. address range 1-line display 2-line display from (line (line 4-line display from lines respectively. 4-line displays address line start address next line consecutive. When display shifted each line wraps around independently others (see Figs When data written DDRAM wrap-around occurs from 1-line mode from 2-line mode; from 4-line mode. Character generator (CGROM)
cursor control circuit generates cursor (underline and/or character blink shown Fig.9) DDRAM address contained Address Counter. When Address Counter contains CGRAM address cursor will inhibited. 8.12 Timing generator
timing generator produces various signals required drive internal circuitry. Internal chip operation disturbed operations data buses. 8.13 column drivers
PCF2104x contains column drivers, which connect appropriate bias voltages sequence display, accordance with data displayed. bias voltages timing selected automatically when number lines display selected. Figures show typical waveforms. 1-line mode outputs driven pairs: R1/R17, R2/R18 example. This allows output pairs connected parallel, thereby providing greater drive capability. Unused outputs should left unconnected.
character generator generates character patterns format from 8-bit character codes. Figures show character sets currently available.
1997
Philips Semiconductors
Product specification
controller/driver
PCF2104x
Display handbook, columns Position (decimal)
non-displayed DDRAM addresses
DDRAM Address (hex)
1-line display non-displayed DDRAM address
DDRAM Address (hex)
line
MLA792
line
2-line display
handbook, columns
non-displayed DDRAM addresses line
line
DDRAM Address (hex)
line
line
line display
MLA793
Fig.2 DDRAM-to-display mapping; shift (PCF2104x).
1997
Philips Semiconductors
Product specification
controller/driver
PCF2104x
Display Position (decimal) DDRAM Address (hex)
Display Position (decimal) DDRAM Address (hex)
line
1-line display
1-line display
line
DDRAM Address (hex)
MLA802
line
DDRAM Address (hex)
MLA815
line
2-line display
2-line display
line
line
line DDRAM Address (hex)
line
DDRAM Address (hex)
line
line
line
line
MLA816
4-line display
MLA803
4-line display
Fig.3
DDRAM-to-display mapping; right shift (PCF2104x).
Fig.4
DDRAM-to-display mapping; left shift (PCF2104x).
1997
Philips Semiconductors
Product specification
controller/driver
PCF2104x
handbook, full pagewidth upper
lower bits xxxx
bits
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
xxxx
0001
xxxx
0010
xxxx
0011
xxxx
0100
xxxx
0101
xxxx
0110
xxxx
0111
xxxx
1000
xxxx
1001
xxxx
1010
xxxx
1011
xxxx
1100
xxxx
1101
xxxx
1110
xxxx
1111
MLB895
Fig.5 Character CGROM; PCF2104C.
1997
Philips Semiconductors
Product specification
controller/driver
PCF2104x
handbook, full pagewidth upper
lower bits xxxx
bits
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
xxxx
0001
xxxx
0010
xxxx
0011
xxxx
0100
xxxx
0101
xxxx
0110
xxxx
0111
xxxx
1000
xxxx
1001
xxxx
1010
xxxx
1011
xxxx
1100
xxxx
1101
xxxx
1110
xxxx
1111
MGC629
Fig.6 Character CGROM; PCF2104L.
1997
Philips Semiconductors
Product specification
controller/driver
PCF2104x
handbook, full pagewidth upper
lower bits xxxx
bits
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
xxxx
0001
xxxx
0010
xxxx
0011
xxxx
0100
xxxx
0101
xxxx
0110
xxxx
0111
xxxx
1000
xxxx
1001
xxxx
1010
xxxx
1011
xxxx
1100
xxxx
1101
xxxx
1110
xxxx
1111
MGM134
Fig.7 Character CGROM; PCF2104N.
1997
Philips Semiconductors
Product specification
controller/driver
PCF2104x
handbook, full pagewidth
character codes (DDRAM data) lower order bits
CGRAM address lower order bits higher order bits
character patterns (CGRAM data)
higher order bits
higher order bits
lower order bits character pattern example character pattern example cursor position
MGA800
Character code bits correspond CGRAM address bits CGRAM address bits designate character pattern line position. line cursor position display performed logical with cursor. Data line will appear cursor position. Character pattern column positions correspond CGRAM data bits being left end, shown figure. CGRAM character patterns selected when character code bits logic CGRAM data logic corresponds selection display. Only bits CGRAM address `Set CGRAM address' instruction. using `Set DDRAM address' instruction using auto-increment feature during CGRAM write. bits read using `Read Busy Flag address' instruction.
Fig.8 Relationship between CGRAM addresses, data display patterns.
1997
Philips Semiconductors
Product specification
controller/driver
PCF2104x
cursor character font alternating display
MGA801
cursor display example
blink display example
Fig.9 Cursor blink display examples.
1997
Philips Semiconductors
Product specification
controller/driver
PCF2104x
handbook, full pagewidth
frame
frame
state (ON) state (ON)
1-line display (1:16)
0.25 state 0.25
0.25 state 0.25
MGA802
Fig.10 Typical waveforms; 1-line mode.
1997
Philips Semiconductors
Product specification
controller/driver
PCF2104x
handbook, full pagewidth
frame
frame
state (ON) state (ON)
2-line display (1:32)
state
0.15 0.15
state
0.15 0.15
MGA803
Fig.11 Typical waveforms; 2-line mode.
1997
Philips Semiconductors
Product specification
controller/driver
8.14 Programming displays with PCF2104x
PCF2104x
Using `Function set' instruction, (respectively). Figures show DDRAM addresses display characters. second each table corresponds either right half 1-line display second line 2-line display. Wrap around data during display shift when writing data non-standard.
PCF2104x used following ways: 1-line mode drive 2-line display characters with rate resulting better contrast. internal data flow chip optimized this purpose.
handbook, full pagewidth
display position DDRAM address
display position DDRAM address
MLB899
Fig.12 DDRAM-to-display mapping; shift (PCF2104x).
handbook, full pagewidth
display position DDRAM address
display position DDRAM address
MLB900
Fig.13 DDRAM-to-display mapping; right shift (PCF2104x).
handbook, full pagewidth
display position DDRAM address
display position DDRAM address
MLB901
Fig.14 DDRAM-to-display mapping; left shift (PCF2104x).
1997
Philips Semiconductors
Product specification
controller/driver
8.15 Programming displays with PCF2104x INSTRUCTIONS
PCF2104x
drive 2-line characters display, instruction `Function set' (respectively). drive 4-line characters 1:32 display, instruction `Function set' (respectively). 8.16 Reset function
PCF2104 automatically initializes (resets) when power turned state after reset given Table Table STEP Display clear. Function set: 8-bit interface 1-line display used Display on/off control: display cursor off; blink off; Entry mode set: (increment) used Default address pointer DDRAM. Busy Flag (BF) indicates busy state logic until initialization ends. busy state lasts chip also initialized software. Tables I2C-bus interface reset. State after reset DESCRIPTION
Only PCF2104x registers, instruction register (IR) data register (DR) directly controlled microcontroller. Before internal operation, control information stored temporarily these registers allow interface various types microcontrollers which operate different speeds allow interfacing peripheral control ICs. PCF2104x operation controlled instructions shown Table together with their execution time. Details explained subsequent sections. Instructions categories, those that: Designate PCF2104x functions such display format, data length, etc. internal addresses Perform data transfer with internal Others. normal use, category instructions used most frequently. However, automatic incrementing decrementing internal addresses after each data write lessens microcontroller program load. display shift particular performed concurrently with display data write, thus enabling designer develop systems minimum time with maximum programming efficiency. During internal operation, instruction other than Busy Flag/address read instruction will executed. Because Busy Flag logic while instruction being executed, advisable ensure that flag logic before sending next instruction wait maximum instruction execution time, given Table instruction sent while Busy Flag HIGH will executed.
1997
1997
Philips Semiconductors
Table
Instructions (note
controller/driver
INSTRUCTION Clear display Return home
operation.
DESCRIPTION
REQUIRED CLOCK CYCLES(2)
Clears entire display sets DDRAM address Address Counter. Sets DDRAM address Address Counter Also returns shifted display original position DDRAM contents remain unchanged. Sets cursor move direction specifies shift display. These operations performed during data write read. Sets entire display on/off (D), cursor on/off blink cursor position character (B). Moves cursor shifts display without changing DDRAM contents. Sets interface data length (DL), number display lines voltage generator control (G). Sets CGRAM address. Sets DDRAM address. Reads Busy Flag (BF) indicating internal operation being performed reads Address Counter contents. Reads data from CGRAM DDRAM. Writes data CGRAM DDRAM.
Entry mode
Display control Cursor/display shift Function
CGRAM address DDRAM address Read busy flag address Read data Write data Notes
read data write data
Product specification
I2C-bus mode don't care. 8-bit mode assumed. I2C-bus mode control byte required when changed; control byte: R/W, command byte: DB0. Example: fosc kHz, 6.67 cycles cycles
PCF2104x
Philips Semiconductors
Product specification
controller/driver
Table decrement display freeze display cursor character cursor position does blink cursor move left shift bits line characters; reserved internal operation last control byte, only data bytes follow Command identities LOGIC increment display shift display cursor character cursor position blinks display shift right shift bits lines characters; lines characters; internal operation progress LOGIC
PCF2104x
next bytes data byte another control byte
instruction write
busy flag address counter read
data register read
MGA804
Fig.15 4-bit transfer example.
1997
Philips Semiconductors
Product specification
controller/driver
PCF2104x
internal
internal operation
busy
busy
instruction write
busy flag check
busy flag check
instruction write
MGA805
IR7, IR3: instruction bit, bit. AC3: Address Counter bit.
Fig.16 example 4-bit data transfer timing sequence.
internal
internal operation
data instruction write
busy busy flag check
busy busy flag check
busy busy flag check
data instruction write
MGA806
Fig.17 Example Busy Flag check timing sequence.
1997
Philips Semiconductors
Product specification
controller/driver
Clear display 9.4.2
PCF2104x
`Clear display' writes space code (hexadecimal) into DDRAM addresses (the character pattern character code must blank pattern), sets DDRAM Address Counter logic returns display original position shifted. Consequently, display disappears cursor blink position goes left edge display (the first line lines displayed) sets entry mode logic (increment mode). entry mode does change. instruction `Clear display' requires extra execution time. This allowed checking Busy Flag (BF) waiting until elapsed. latter must applied where read-back options foreseen, some chip-on-glass (COG) applications. Return home
cursor displayed when logic inhibited when logic Even cursor disappears, display functions I/D, etc. remain operation during display data write. cursor displayed using dots line (see Fig.9). 9.4.3
character indicated cursor blinks when logic blink displayed switching between display characters dots with period second when fosc (see Fig.9). other clock frequencies blink period equal kHz/fosc. cursor blink display simultaneously. Cursor/display shift
`Return home' sets DDRAM Address Counter logic returns display original position shifted. DDRAM contents change. cursor blink position goes left display (the first line lines displayed). entry mode change. 9.3.1 Entry mode
When logic DDRAM CGRAM address increments (decrements) when data written read from DDRAM CGRAM. cursor blink position moves right when incremented left when decremented. cursor blink inhibited when CGRAM accessed. 9.3.2
`Cursor/display shift' moves cursor position display right left without writing reading display data. This function used correct character move cursor through display. 4-line displays, cursor moves next line when passes last position line decimal). When displayed data shifted repeatedly lines shift same time; displayed characters shift into next line. Address Counter (AC) content does change only action performed shift display, increments decrements with cursor shift. 9.6.1 Function (PARALLEL MODE ONLY)
When logic entire display shifts either right (I/D logic left (I/D logic during DDRAM write. Consequently, looks cursor stands still display moves. display does shift when reading from DDRAM, when writing reading from CGRAM. When logic display does shift. 9.4.1 Display on/off control
Sets interface data width. Data sent received bytes (DB7 DB0) when logic nibbles (DB7 DB4) when logic When 4-bit width selected, data transmitted cycles using parallel bus(1). Function from I2C-bus interface: logic from I2C-bus interface. been logic parallel bus, programming I2C-bus interface complicated. 9.6.2
Sets number display lines.
4-bit application left open (internal pull-ups). Hence first function instruction after power-on second function must then sent nibbles) their required values.
display when logic when logic Display data DDRAM affected displayed immediately setting logic
1997
Philips Semiconductors
Product specification
controller/driver
CGRAM address 9.11
PCF2104x
Read data from CGRAM DDRAM
`Set CGRAM address' sets bits CGRAM address (ACG Table into Address Counter (binary A[5] A[0]). Data then written read from CGRAM. Only bits CGRAM address `Set CGRAM address' instruction. using `Set DDRAM address' instruction using auto-increment feature during CGRAM write. bits read using `Read busy flag address' instruction. DDRAM address
Reads binary 8-bit data D[7] D[0] from CGRAM DDRAM. most recent `Set address' instruction determines whether CGRAM DDRAM read. `Read data' instruction gates content data register (DR) while HIGH. After goes again, internal operation increments decrements) stores data corresponding into Remark: only three instructions that update data register (DR) are: `Set CGRAM address' `Set DDRAM address' `Read data' from CGRAM DDRAM. Other instructions (e.g. `Write data, `Cursor/display shift', `Clear display', `Return home') will modify data register content. INTERFACE MICROCONTROLLER (PARALLEL INTERFACE) PCF2104x send data either 4-bit operations 8-bit operation thus interface 4-bit 8-bit microcontrollers. 8-bit mode data transferred 8-bit bytes using data lines DB7. Three further control lines required. 4-bit mode data transferred cycles 4-bits each. higher order bits (corresponding 8-bit mode) sent first cycle lower order bits (DB0 8-bit mode) second cycle. Data transfer complete after 4-bit data transfers. should noted that cycles also required Busy Flag check. 4-bit operation selected instruction. Figs examples protocol. 4-bit mode pins must left open-circuit. They pulled internally.
DDRAM address sets DDRAM address (ADD Table into Address Counter (binary A[6] A[0). Data then written read from DDRAM. Table Hexadecimal address ranges ADDRESS FUNCTION 1-line 2-line 2-line
4-line Read busy flag address
`Read busy flag address' reads Busy Flag (BF). When logic indicates that internal operation progress. next instruction will executed until logic should checked before sending another instruction. same time, value Address Counter expressed binary A[6] A[0] read out. Address Counter used both CGRAM DDRAM value determined previous instruction. 9.10 Write data CGRAM DDRAM
Writes binary 8-bit data D[7] D[0] CGRAM DDRAM. Whether CGRAM DDRAM written determined previous specification CGRAM DDRAM address setting. After writing, address automatically increments decrements accordance with entry mode. Only bits CGRAM data valid, bits `don't care'.
1997
Philips Semiconductors
Product specification
controller/driver
INTERFACE MICROCONTROLLER (I2C-BUS INTERFACE) 11.1 Characteristics I2C-bus 11.5 Acknowledge
PCF2104x
I2C-bus bidirectional, two-line communication between different modules. lines serial data line (SDA) serial clock line (SCL). Both lines must connected positive supply pull-up resistor. Data transfer initiated only when busy. 11.2 transfer
data transferred during each clock pulse. data line must remain stable during HIGH period clock pulse changes data line this time will interpreted control signal. 11.3 Start stop conditions
Both data clock lines remain HIGH when busy. HIGH-to-LOW transition data line, while clock HIGH defined START condition (S). LOW-to-HIGH transition data line while clock HIGH defined STOP condition (P). 11.4 System configuration
number data bytes transferred between start stop conditions from transmitter receiver unlimited. Each byte eight bits followed acknowledge bit. acknowledge HIGH level signal transmitter during which time master generates extra acknowledge related clock pulse. slave receiver which addressed must generate acknowledge after reception each byte. Also master receiver must generate acknowledge after reception each byte that been clocked slave transmitter. device that acknowledges must pull-down line during acknowledge clock pulse, that line stable during HIGH period acknowledge related clock pulse (set-up hold times must taken into consideration). master receiver must signal data transmitter generating acknowledge last byte that been clocked slave. this event transmitter must leave data line HIGH enable master generate stop condition. 11.6 I2C-bus protocol
device generating message `transmitter', device receiving message `receiver'. device that controls message `master' devices which controlled master `slaves'.
Before data transmitted I2C-bus, device which should respond addressed first. addressing always carried with first byte transmitted after start procedure. I2C-bus configuration different PCF2104x READ WRITE cycles illustrated Figs
handbook, full pagewidth
data line stable; data valid change data allowed
MBC621
Fig.18 transfer.
1997
Philips Semiconductors
Product specification
controller/driver
PCF2104x
handbook, full pagewidth
START condition STOP condition
MBC622
Fig.19 Definition START STOP conditions.
MASTER TRANSMITTER/ RECEIVER
SLAVE RECEIVER
SLAVE TRANSMITTER/ RECEIVER
MASTER TRANSMITTER
MASTER TRANSMITTER/ RECEIVER
MGA807
Fig.20 System configuration.
handbook, full pagewidth
DATA OUTPUT TRANSMITTER acknowledge DATA OUTPUT RECEIVER acknowledge FROM MASTER START condition clock pulse acknowledgement
MBC602
Fig.21 Acknowledgement
I2C-bus.
1997
Fig.22 Master transmits slave receiver; WRITE mode.
handbook, full pagewidth
1997
acknowledgement from PCF2104x
Philips Semiconductors
controller/driver
CONTROL BYTE
DATA
CONTROL BYTE
DATA
slave address
bytes
byte
bytes
update data pointer
MGC617
PCF2104x slave address
Product specification
PCF2104x
Last data byte dummy byte (may omitted).
Fig.23 Master reads after setting word address; write word address, RS/RW; READ data.
handbook, full pagewidth
1997
acknowledgement from PCF2104x
Philips Semiconductors
controller/driver
CONTROL BYTE
DATA
CONTROL
DATA
slave address
bytes
bytes
acknowledgement from PCF2104x
SLAVE ADDRESS
acknowledgement from master
DATA
DATA
bytes
last byte update data pointer
MGC618
Product specification
PCF2104x
Philips Semiconductors
Product specification
controller/driver
PCF2104x
handbook, full pagewidth
acknowledgement from PCF2104x
acknowledgement from master
acknowledgement from master
SLAVE ADDRESS
DATA
DATA
bytes
last byte update data pointer
MGC619
Fig.24 Master reads slave immediately after first byte; READ mode previously defined).
1997
Fig.25 I2C-bus timing diagram; rise fall times refer VIH.
handbook, full pagewidth
1997
PROTOCOL START CONDITION (A7) (A6) ACKNOWLEDGE STOP CONDITION
Philips Semiconductors
controller/driver
HD;STA HIGH
t/fSCL
MGA811
SU;STO
Product specification
PCF2104x
Philips Semiconductors
Product specification
controller/driver
LIMITING VALUES accordance with Absolute Maximum Rating System (IEC 134). SYMBOL VLCD Ptot Tstg supply voltage supply voltage input voltage OSC, R/W, output voltage R32, VLCD input current output current total power dissipation power dissipation output storage temperature PARAMETER MIN. -0.5 VLCD
PCF2104x
MAX. +8.0 +150
UNIT
IDD, ISS, ILCD VDD, VLCD current
HANDLING Inputs outputs protected against electrostatic discharge normal handling. However, totally safe, desirable take normal precautions appropriate handling devices (see "Handling Devices" CHARACTERISTICS VLCD Tamb unless otherwise specified. SYMBOL Supplies VLCD IDD1 IDD2 supply voltage supply voltage supply current external VLCD supply current supply current fosc kHz; Tamb fosc kHz; Tamb notes note note PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
IDD3
supply current
ILCD VPOR
VLCD input current Power-on reset voltage level
1997
Philips Semiconductors
Product specification
controller/driver
PCF2104x
SYMBOL Logic VIL1 VIH1 VIL(osc) VIH(osc) IOL(DB) IOH(DB) I2C-bus SDA, VIL2 VIH2 IOL(SDA) outputs RROW RCOL Vtol1 Notes
PARAMETER
CONDITIONS
MIN.
TYP. 0.15
MAX.
UNIT
level input voltage pins R/W, HIGH level input voltage pins R/W, level input voltage HIGH level input voltage pull-up current pins DB7, level output current pins HIGH level output current pins leakage current pins OSC, R/W,
0.7VDD 0.04
0.3VDD 1.00
-1.0
level input voltage HIGH level input voltage leakage current input capacitance level output current (SDA)
note note note
0.7VDD
0.3VDD
note note note
output resistance pins column output resistance pins bias voltage tolerance pins
±130
outputs open-circuit; inputs VSS; VDD; inactive; internal external clock with duty cycle (IDD1 only). Resets logic when VPOR. When voltages above below supply voltages VSS, input current flow; this current must exceed ±0.5 Tested sample basis. Resistance output terminals C60) with load current Iload VLCD outputs measured time. outputs open-circuit.
1997
Philips Semiconductors
Product specification
controller/driver
PCF2104x
CHARACTERISTICS VLCD Tamb unless otherwise specified. SYMBOL fosc PARAMETER frame frequency (internal clock) external clock frequency CONDITIONS note MIN. TYP. MAX. UNIT
timing characteristics: Parallel Interface; notes WRITE OPERATION (WRITING DATA FROM MICROCONTROLLER PCF2104X) PWEH tASU tDSW PWEH tASU tDHD enable cycle time enable pulse width address set-up time address hold time data set-up time data hold time
READ OPERATION (READING DATA FROM PCF2104X MICROCONTROLLER) enable cycle time enable pulse width address set-up time address hold time data delay time data hold time
Timing characteristics: I2C-bus interface; note fSCL tBUF tSU;STA tHD;STA tLOW tHIGH tSU;DAT tHD;DAT tSU;STO Notes timing values valid within operating supply voltage ambient temperature range referenced with input voltage swing VDD. clock frequency tolerable spike width free time set-up time repeated START condition start condition hold time time HIGH time rise time fall time data set-up time data hold time set-up time STOP condition
1997
Philips Semiconductors
Product specification
controller/driver
TIMING DIAGRAMS
PCF2104x
handbook, full pagewidth
VIH1
VIH1 VIL1
VIL1 VIL1 VIH1 VIL1
MLA798
VIH1 VIL1
VIH1 VIL1 VIH1 Valid Data VIL1
Fig.26 Parallel write operation sequence; writing data from microcontroller PCF2104x.
handbook, full pagewidth
VIH1
VIH1 VIL1 VIH1
VIH1
VIL1 VIH1 VIH1
VIL1 VIL1
VOH1 VOL1
VOH1 VOL1
MLA799
Fig.27 Parallel read operation sequence; reading data from PCF2104x microcontroller. 1997
Philips Semiconductors
Product specification
controller/driver
APPLICATION INFORMATION
PCF2104x
handbook, columns
P80CL51
PCF2104x
MGC620
Fig.28 Direct connection 8-bit microcontroller; 8-bit bus.
handbook, columns
P80CL51
PCF2104x
MGC621
Fig.29 Direct connection 8-bit microcontroller; 4-bit bus.
handbook, full pagewidth
VLCD
VLCD
PCF2104x
CHARACTER DISPLAY (SPLIT SCREEN)
MGC624
Fig.30 Typical application using parallel interface.
1997
Philips Semiconductors
Product specification
controller/driver
PCF2104x
handbook, full pagewidth
VLCD
VLCD
CHARACTER DISPLAY (SPLIT SCREEN)
PCF2104x
VLCD
VLCD
CHARACTER DISPLAY
PCF2104x
MGC625
MASTER TRANSMITTER PCF84C81
Fig.31 Application using I2C-bus interface.
1997
Philips Semiconductors
Product specification
controller/driver
17.1 8-bit operation, display using internal reset 17.3 8-bit operation, display
PCF2104x
Table shows example 1-line display 8-bit operation. PCF2104x functions must function instruction prior display. Since display data store data characters, used advertising displays when combined with display shift operation. Since display shift operation changes display position only DDRAM contents remain unchanged. Display data entered first displayed when `Return home' instruction performed. 17.2 4-bit operation, display using internal reset
2-line display, cursor automatically moves from first second line after 40th digit first line been written. Thus, there only characters first line, DDRAM address must after eighth character completed (see Table should noted that both lines display always shifted together, data does shift from line other. 17.4 operation, display
control byte required with most instructions (see Table 17.5 Initializing instruction
program must functions prior 4-bit operation. Table shows example. When power turned 8-bit operation automatically selected PCF2104x attempts perform first write 8-bit operation. Since nothing connected DB3, rewrite then required. However, since operation completed accesses 4-bit operation, rewrite required functions (see Table step Thus, function written twice.
power supply conditions correctly operating internal reset circuit met, PCF2104x must initialized instruction. Tables show this performed 8-bit 4-bit operation.
1997
Philips Semiconductors
Product specification
controller/driver
Table STEP 4-bit operation, 1-line display example; using internal reset INSTRUCTION Power supply (PCF2104x initialized internal reset circuit). Function set: Function set: Display on/off control: Entry mode set: Write data CGRAM/DDRAM: Turns display cursor. DISPLAY OPERATION Initialized. display appears.
PCF2104x
Sets 4-bit operation. this instance operation handled 8-bits initialization only this instruction completes with write. Sets 4-bit operation, selects display. 4-bit operation starts from this point resetting needed.
Entire display blank after initialization.
Sets mode increment address shift cursor right time write DD/CGRAM. Display shifted.
Writes `P'. DDRAM already been selected initialization power-on. cursor incremented shifted right.
1997
1997
Philips Semiconductors
Table STEP
8-bit operation, 1-line display example; using internal reset (character `A')
controller/driver
INSTRUCTION Power supply (PCF2104x initialized internal reset function). Function set: Display mode on/off control: Entry mode set: Write data CGRAM/DDRAM: Write data CGRAM/DDRAM:
DISPLAY
OPERATION Initialized. display appears. Sets 8-bit operation, selects display.
Turns display cursor. Entire display blank after initialization. Sets mode increment address shift cursor right time write DD/CGRAM. Display shifted. Writes `P'. DDRAM already been selected initialization power-on. cursor incremented shifted right. Writes `H'.
Write data CGRAM/DDRAM: Entry mode set: Write data CGRAM/DDRAM: Write data CGRAM/DDRAM: PHILIPS_ Writes `S'.
PHILIPS_
Sets mode display shift time write.
HILIPS
Writes space.
ILIPS
Writes `M'.
Product specification
PCF2104x
1997
Philips Semiconductors
STEP
INSTRUCTION Write data CGRAM/DDRAM: Cursor display shift: Cursor display shift: Write data CGRAM/DDRAM: Cursor display shift: Cursor display shift: Write data CGRAM/DDRAM:
DISPLAY MICROKO Writes `O'.
OPERATION
controller/driver
MICROKO
Shifts only cursor position left.
MICROKO
Shifts only cursor position left.
ICROCO
Writes correction. display moves left.
MICROCO
Shifts display cursor right.
MICROCO_
Shifts only cursor right.
ICROCOM_
Writes `M'.
Return home: PHILIPS Returns both display cursor original position (address
Product specification
PCF2104x
1997
Philips Semiconductors
Table STEP
8-bit operation, 2-line display example; using internal reset
controller/driver
INSTRUCTION Power supply (PCF2104x initialized internal reset function). Function set: Display on/off control: Entry mode set: Write data CGRAM/DDRAM:
DISPLAY
OPERATION Initialized. display appears. Sets 8-bit operation, selects display
Turns display cursor. Entire display blank after initialization. Sets mode increment address shift cursor right time write CG/DDRAM. Display shifted. Writes `P'. DDRAM already been selected initialization power-on. cursor incremented shifted right.
Write data CGRAM/DDRAM: DDRAM address: Write data CGRAM/ DDRAM:
PHILIPS_
Writes `S'.
PHILIPS PHILIPS
Sets DDRAM address position cursor head line. Writes `M'.
Product specification
Write data CGRAM/ DDRAM: Write data CGRAM/ DDRAM:
PHILIPS MICROCO_ PHILIPS MICROCO_
Writes `O'.
PCF2104x
Sets mode display shift time write.
1997
Philips Semiconductors
STEP
INSTRUCTION Write data CGRAM/ DDRAM:
DISPLAY HILIPS ICROCOM_
OPERATION Writes `M'. Display shifted left. first second lines shift together.
controller/driver
Return home:
PHILIPS MICROCOM
Returns both display cursor original position (address
Product specification
PCF2104x
1997
Philips Semiconductors
Table STEP
Example I2C-bus operation; 1-line display (using internal reset, assuming VSS; note I2C-BUS BYTE I2C-bus start Slave address write: Send control byte function set: Function set: Display on/off control: Entry mode set: I2C-bus start Slave address write: Send control byte write data: Write data DDRAM: Write data DDRAM: DISPLAY OPERATION Initialized. display appears. During acknowledge cycle will pulled-down PCF2104x. Control byte sets following data bytes. Selects 1-line display; pulse during acknowledge cycle starts execution instruction. Turns display cursor. Entire display shows character (blank ASCII-like character sets). Sets mode increment address shift cursor right time write DDRAM CGRAM. Display shifted. writing data DDRAM, must Therefore control byte needed.
controller/driver
Writes `P'. DDRAM been selected power-up. cursor incremented shifted right. Writes `H'.
Write data DDRAM: PHILIPS_ Writes `S'.
Product specification
PCF2104x
1997
Philips Semiconductors
STEP (optional step I2C-bus stop)
I2C-BUS BYTE I2C-bus
DISPLAY
OPERATION
controller/driver
start slave address write PHILIPS_ PHILIPS_ PHILIPS Sets DDRAM address Address Counter. (Also returns shifted display original position. DDRAM contents unchanged). This instruction does update Data Register (DR). DDRAM content will read from following instructions. while still I2C-bus write mode. During acknowledge cycle content loaded into internal I2C-bus interface shifted out. previous instruction neither `Set address' `Read data' been performed. Therefore content unknown. SCL; content loaded into interface during previous acknowledge cycle shifted over SDA. DB7. During master acknowledge content DDRAM address loaded into I2C-bus interface. SCL; code letter read first. During master acknowledge code loaded into I2C-bus interface. master acknowledge; After content I2C-bus interface register shifted internal action performed. data loaded interface register, Data Register (DR) updated, Address Counter (AC) incremented cursor shifted.
Control byte: Return home: Control byte read: I2C-bus start Slave address read:
PHILIPS
PHILIPS PHILIPS
Read data: master acknowledge; note Read data: master acknowledge; note Read data: master acknowledge; note
PHILIPS
PHILIPS
PHILIPS
Notes
stop
PHILIPS Product specification
PCF2104x
don't care. left high-impedance microcontroller during READ acknowledge.
1997
Philips Semiconductors
Table Initialization instruction, 8-bit interface (note
controller/driver
STEP Power-on unknown state Wait after rises above VPOR Wait Wait more than I/D; Initialization ends Note don't care.
DESCRIPTION
cannot checked before this instruction. `Function set' (interface 8-bits long).
cannot checked before this instruction.`Function set' (interface 8-bits long).
cannot checked before this instruction. `Function set' (interface 8-bits long). checked after following instructions. When checked, waiting time between instructions specified instruction time (see Table `Function set' (interface 8-bits long). Specify number display lines. `Display off'. `Clear display'. `Entry mode set'.
Product specification
PCF2104x
1997
Philips Semiconductors
Table Initialization instruction, 4-bit interface. applicable I2C-bus operation
controller/driver
STEP Power-on unknown state Wait after rises above VPOR Wait Wait I/D; Initialization ends
DESCRIPTION
cannot checked before this instruction. `Function set' (interface 8-bits long).
cannot checked before this instruction. `Function set' (interface 8-bits long).
cannot checked before this instruction. `Function set' (interface 8-bits long). checked after following instructions. When checked, waiting time between instructions specified instruction time (see Table `Function set' (set interface 4-bits long). Interface 8-bits long. `Function set' (interface 4-bits long). Specify number display lines voltage generator characteristic. `Display off'. `Clear display'. `Entry mode set'.
Product specification
PCF2104x
Philips Semiconductors
Product specification
controller/driver
PCF2104x
handbook, full pagewidth
DISPLAY LAYOUT: COLUMNS PCF2104x column output numbers
MATRIX
column numbers
PCF2104x column output numbers
DISPLAY LAYOUT: ROWS
MGC623
Fig.32 Example display layout (PCF2104x). 1997
Philips Semiconductors
Product specification
controller/driver
PCF2104x
handbook, full pagewidth
display glass
matrix
COLUMN LAYOUT
LAYOUT
MLB898
lines characters display
Fig.33 Display example (PCF2104x); lines characters.
1997
Philips Semiconductors
Product specification
controller/driver
PCF2104x
handbook, full pagewidth
PCF2104x CHIP-ON-GLASS
LINE CHARACTER
2104
MGC626
VLCD
Fig.34 Chip-on-glass application.
1997
Philips Semiconductors
Product specification
controller/driver
BONDING LOCATIONS
PCF2104x
handbook, full pagewidth
5.63
PCF2104x
VLCD
5.10
MGC628
Chip dimensions: approximately 5.10 5.63 Gold bump dimensions: approximately
Fig.35 Bonding locations.
1997
Philips Semiconductors
Product specification
controller/driver
Table Bonding locations (dimensions µm). coordinates referenced centre chip, Fig.35 SYMBOL 1997 -2184.5 -2024.5 -1864.5 -1704.5 -1339 -1179 -1019 -859 -699 -539 -379 -219 1061 1221 1381 1541 1701 1861 2021 2181 2350 2350 2350 2350 2350 2350 2350 2350 2350 2350 2350 -2637 -2637 -2637 -2637 -2637 -2637 -2637 -2637 -2637 -2637 -2637 -2637 -2637 -2637 -2637 -2637 -2637 -2637 -2637 -2637 -2637 -2637 -2637 -2637 -2637 -2637 -2637 -2445 -2285 -2125 -1965 -1805 -1645 -1485 -1325 -1165 -1005 -845 SYMBOL 2350 2350 2350 2350 2350 2350 2350 2350 2350 2350 2350 2350 2350 2350 2350 2350 2350 2350 2350 2350 2185 2025 1865 1705 1545 1385 1225 1065 -215 -375 -535
PCF2104x
-685 -525 -365 -205 1075 1235 1395 1555 1715 1875 2035 2195 2355 2637.5 2637.5 2637.5 2637.5 2637.5 2637.5 2637.5 2637.5 2637.5 2637.5 2637.5 2637.5 2637.5 2637.5 2637.5 2637.5 2637.5 2637.5
Philips Semiconductors
Product specification
controller/driver
PCF2104x
SYMBOL VLCD RECPAT RECPAT RECPAT
-695 -855 -1015 -1175 -1385 -1545 -1705 -1865 -2025 -2185 -2349 -2349 -2349 -2349 -2349 -2349 -2349 -2349 -2349 -2349 -2349 -2349 -2349 -2349 -2349 -2349 -2349 -2349 -2349 -2349 -2349 -2349 -2349 -2349 -2349 -2327.5 -2027.5 1982.5
2637.5 2637.5 2637.5 2637.5 2637.5 2637.5 2637.5 2637.5 2637.5 2637.5 2308 2148 1988 1828 1668 1508 1348 1188 1028 -233 -393 -668 -828 -1103 -1263 -1538 -1698 -1933 -2453 2427.5 -2512.5 2297.5
1997
Philips Semiconductors
Product specification
controller/driver
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
PCF2104x
This data sheet contains target goal specifications product development. This data sheet contains preliminary data; supplementary data published later. This data sheet contains final product specifications.
Limiting values given accordance with Absolute Maximum Rating System (IEC 134). Stress above more limiting values cause permanent damage device. These stress ratings only operation device these other conditions above those given Characteristics sections specification implied. Exposure limiting values extended periods affect device reliability. Application information Where application information given, advisory does form part specification. LIFE SUPPORT APPLICATIONS These products designed life support appliances, devices, systems where malfunction these products reasonably expected result personal injury. Philips customers using selling these products such applications their risk agree fully indemnify Philips damages resulting from such improper sale. PURCHASE PHILIPS COMPONENTS
Purchase Philips components conveys license under Philips' patent components system provided system conforms specification defined Philips. This specification ordered using code 9398 40011.
1997
Philips Semiconductors
Product specification
controller/driver
NOTES
PCF2104x
1997
Philips Semiconductors
Product specification
controller/driver
NOTES
PCF2104x
1997
Philips Semiconductors
Product specification
controller/driver
NOTES
PCF2104x
1997
Philips Semiconductors worldwide company
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other countries apply Philips Semiconductors, Marketing Sales Communications, Building BE-p, P.O. 218, 5600 EINDHOVEN, Netherlands, Fax. 24825 Philips Electronics N.V. 1997
Internet:
SCA53
rights reserved. Reproduction whole part prohibited without prior written consent copyright owner. information presented this document does form part quotation contract, believed accurate reliable changed without notice. liability will accepted publisher consequence use. Publication thereof does convey imply license under patent- other industrial intellectual property rights.
Printed Netherlands
417067/1200/04/pp56
Date release: 1997
Document order number:
9397 02924

PCF2104x controller/driver Product specification Supersedes data

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