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JEDEC PC133 Unbuffered DIMM Timing Margin Review
DRAM
Loads Loads Loads Loads Loads Loads Loads Loads Load Load
SRAS,SCAS,SWE,MA MD/DQM
DRAM Cycle
Case (Hold)
tCNTL, Input *****delay 1.0ns *****delay 1.5ns tFLIGHT* SDRAM Clock skew Other Margin 133MHz Hold Hold Hold -0.18ns 0.82ns 1.32ns 1.0ns 2.7ns 0.25ns 0.5ns 3.13ns 2.0ns 1.0ns
Case (Setup)
setup setup setup 0.82ns -0.18ns -0.68ns 1.9ns 4.6ns 0.25ns 0.5ns -0.57ns* 0.43ns 0.93ns
DRAM Write Cycle DQMs
DQMs
Case(Hold) Case(Setup)
tCNTL, Input Hold 0.90ns setup 1.30ns tFLIGHT* min* 1.55ns max* 3.50ns tIH/IS SDRAM 0.8ns 1.5ns Clock skew 0.25ns 0.45ns Other* 1.0ns 0.80ns Margin 133MHz 0.60ns -0.05ns* "Oth itic tFLIGHT MIN: DIMM, tFLIGHT MAX: DIMM, DIMM DRAM
DRAM Cycle
CTL/ MAB# CTL/
Case(Hold) Case(Setup)
tCNTL, Output tFLIGHT* tIH/IS SDRAM Clock skew Other* Margin 133MHz Hold min* 1.00ns 2.80ns 0.8ns 0.25ns 1.0ns 0.60ns setup max* 2.00ns 5.00ns 1.5ns 0.45ns 1.00ns 5.05ns
DRAM Cycle
CSA[7 CSB[7
Case(Hold) Case(Setup)
tCNTL, Output tFLIGHT* tIH/IS SDRAM Clock skew Other* Margin 133MHz hold min* 0.90ns 2.10ns 0.8ns 0.25ns 1.0ns 0.95ns setup max* 1.70ns 2.74ns 1.5ns 0.45ns 1.00ns 0.11ns
citive DIMM. rivin ttin lty/ itics
Typical SDRAM citive DIMM. Stro rivin ttin lty/ itic
Socket Slot
$SROOR $SROOR 3OXV (QKDQFHG $SROOR 3OXV $SROOR ,QWHJUDWHG
(QKDQFHG $SROOR 3OXV
Performance
$SROOR
5'98
$SROOR ,QWHJUDWHG
11'98
Super
Integration
1H'99
2H'99
"PC1
&RPSDWLEOH $SROOR 3UR3OXVµ
FSB@1 AGP1 SDRAM CPU/ DRAM/
133/ 100/ 100/ 100/ 133/ 133/ "PC133" Enhanced VT82C693
with
FSB@6 DRAM
VT82C596B
"AGP4
0RGLILFDWLRQ $SROOR 3OXV
AGP2 tica
CPU/ DRAM/ 133/ 133/ 133/ 100/ 100/ 100/ Apollo AGP4X
VT82C596B
AGP4
Brid

DRAM Loads Loads Loads Loads Loads Loads Loads Loads Load Load

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