OC-48 SONET/SDH Ethernet Mapper TXC-06710 TECHNICAL OVERVIEW PRODUCT P

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OC-48 SONET/SDH Ethernet Mapper TXC-06710 TECHNICAL OVERVIEW PRODUCT P

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EtherMapTM-48 Device
OC-48 SONET/SDH Ethernet Mapper TXC-06710 TECHNICAL OVERVIEW PRODUCT PREVIEW FEATURES
Single STS-48/STM-16 4xSTS-12/STM-4 line-side interfaces On-chip clock synthesis 4xSTS-12/STM-4 STS-48/STM-16 Framing Transport Overhead Termination Processing Supports contiguous Concatenation STS-1 granularity Pointer tracking AU-4-16c/AU-4-4c/AU4/AU3/TU3 levels Full Duplex cross connect both STS-1-VC-3 TU-3VC-3 granularity, with facility Line Terminal side STS-1 Path level loopbacks Full Path Overhead Processing Termination, HO/LO Path Level. Retiming Path Level (STS-1 through STS-48/48c level) Ring ports, K1/K2 ports, ports TOH/POH Bytes Full support Virtual Concatenation ANSI T1.105/ITU-T G.707/G.783 with without LCAS (ITU-T G.7042) Terminal-side interfaces GMII interfaces (Gigabit Ethernet with MAC) SMII Interfaces (100 Mbit/s Ethernet) Terminal-side Serial Data Reference clock interfaces 4x1.25 SerDes 8B/10B block encoded clients Provides Ethernet 100/1000 Mbit/s Framed mapping over (ITU-T G.7041) LAPS (ITU-T X.86) Provides transparent mapping standard 8B/10B block coded clients, such Gigabit Ethernet, Fibre Channel (ANSI X3.230), ESCON (ANSI X3.296), FICON. Provides configuration Flow Control support oversubscribed operation Gigabit Ethernet (4xGigE into single OC-48) Fast Ethernet clients Mailbox interface with device configuration with higher level messages V/3.3 I/O, core 676-lead Ball Grid Array package
EtherMapTM-48 Device highly integrated, STS-48/STM-16 rate SONET/SDH VLSI device, mapping Gigabit/100BaseT Ethernet 8B/10B block encoded traffic like Gigabit Ethernet, Fibre Channel, FICON, ESCON into SONET/SDH Transport. EtherMap-48 addresses Metro applications such transport switched Ethernet point-to-point connections aggregated Ethernet Packet traffic, Storage Area Networks (SAN). EtherMap-48 SONET/SDH interface consists full duplex STS-48/STM-16 channels, which also operate 4xSTS12/STM-4 rate. EtherMap-48 provides single OC-48 Quad OC-12 framing. There full TOH/POH processing monitoring, along with full Virtual Concatenation LCAS support. EtherMap-48 Ethernet interface consists four 1.25GHz SerDes 8B/10B clients, including Gigabit Ethernet, 4xGMII interfaces Gigabit Ethernet, lead-multiplexed with 24xSMII Fast Ethernet interface. Over-subscription mapping four Gigabit Ethernet streams into single STS-48/STM-16 statistical multiplexing supported configuration built-in flow control mechanisms.
APPLICATIONS
SONET/SDH add/drop terminal multiplexers Multi-service access platforms Next generation Ethernet switches Storage Area Network Equipment Transparent services Ethernet Private Line Services
TERMINAL SIDE
Control Clock EEPROM Serial Interface Signals
HO/LO Path Port Ring Port
Regen/Multiplex Port Ring Port, Port
LINE SIDE
4x1.25 8B/10B Ser. Interfaces
EtherMap-48
OC-48 SONET/SDH Ethernet Mapper
SONET/SDH Line Interface: 1xOC-48/ 4xOC-12
4xGbE GMII MHz/ 4x10B/24xSMII Interfaces
TXC-06710
Microprocessor Interface
External SDRAM
Boundary Scan
Copyright 2002 TranSwitch Corporation EtherMap trademark TranSwitch Corporation TranSwitch registered trademarks TranSwitch Corporation
Document Number: PRODUCT PREVIEW TXC-06710-MA 2002
TranSwitch Corporation Enterprise Drive Shelton, Connecticut 06484 Tel: 203-929-8810 Fax: 203-926-9453 www.transwitch.com
PRODUCT PREVIEW information documents contain information products their formative design phase development. Features, characteristic data other specifications subject change. Contact TranSwitch Applications Engineering current information this product.
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TECHNICAL OVERVIEW
EtherMap-48 TXC-06710
TABLE CONTENTS
Section Page
List Figures Application Examples Functional Description Selected Parameter Values Absolute Maximum Ratings Environmental Limitations Thermal Characteristics. Power Requirements Package Information. Ordering Information. Related Products Documentation Update Registration Form*
Please note that TranSwitch provides documentation products. Current editions many documents available from Products page TranSwitch site www.transwitch.com. Customers using TranSwitch Product, planning should register with TranSwitch Marketing Department receive relevant updated supplemental documentation issued. They should also contact Applications Engineering Department ensure that they provided with latest available information about product, especially before undertaking development designs incorporating product.
LIST FIGURES
Figure
Page
Typical Application using EtherMap-48 Devices Typical Application Over-Subscription. Flexible Add/Drop Multiplex Application EtherMap-48 TXC-06710 Block Diagram EtherMap-48 TXC-06710 Package Diagram
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EtherMap-48 TXC-06710
APPLICATION EXAMPLES
EtherMap-48 used wide range telecommunications applications, such
SONET/SDH add/drop terminal multiplexers
Storage Area Network Applications Multi-service access platforms services Next generation Ethernet switches
Ethernet/Fiber Channel Over SONET Application
Ring Network OC-48/4xOC-12
Ring
OC-48/4xOC-12
EtherMap-48
TXC-06710
4xGMII+ Nx100
EtherMap-48
TXC-06710
4xGMII+ Nx100
GMII
GMII
ROUTER
FIBRE CHNL
FIBRE CHNL
ROUTER
Figure Typical Application using EtherMap-48 Devices Figure shows EtherMap-48 devices being used Router Application (with IEEE 802.3z Gigabit Ethernet over SONET/SDH Transport), Storage Area Network Application, based ANSI X3.230 Fibre Channel.
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TECHNICAL OVERVIEW
EtherMap-48 TXC-06710
Multiple Gigabit Ethernet Mapping with Over-Subscription Application
Ring
Ring
Network OC-48/4xOC-12 OC-48/4xOC-12
EtherMap-48
TXC-06710
4xGMII+ Nx100
EtherMap-48
TXC-06710
4xGMII+ Nx100
LOCAL FLOW CONTROL
GMII
GMII
ETH.
ETH.
LOCAL FLOW CONTROL
END-TO-END FLOW CONTROL
Figure Typical Application Over-Subscription
PRODUCT PREVIEW TXC-06710-MA 2002
PRODUCT PREVIEW
Figure below, possible four Gigabit Ethernet interfaces into single OC-48 line, over-subscribed mode. full-duplex PAUSE frame flow control mechanism provided on-chip MACs supports this application. scaled version this application, i.e., single port into single OC-12 application also possible. application shown below with multiple ports being used.
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EtherMap-48 TXC-06710
Flexible Add/Drop Multiplex Application
OC-12, Mbit/s Dual Counter Rotating Ring OC-12, Mbit/s Dual Counter Rotating Ring WEST EAST
Mbit/s
Mbit/s
Mbit/s
Mbit/s
OC-12
EtherMap-48
Ethernet I/Fs OC-3/12 DS3/E3/STS1
PHAST-12E
UTOPIA2+4xCB
EtherMap-48
Ethernet I/Fs
Ethernet Switches
Add/Drop Applications
DS3/E3/STS-1/STM-0
Applications
Routers
Figure Flexible Add/Drop Multiplex Application
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4xOC-12 Front provides flexibility Add/Drop Multiplexer Applications, inter device operability. following diagram, most devices that shown working together daisy chained manner, with dual line interfaces, either OC-48 OC-12. Note that necessary devices pictured below, working full capacity; flexibility that emphasized.
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EtherMap-48 TXC-06710
FUNCTIONAL block diagram EtherMap-48 shown Figure below:
LINE SIDE
SONET/SDH LINE INTF. 4xDATA+4xCLK RX/TX 4x622 DIFFERENTIAL FULL DUPLEX LVDS INPUTS
CONTROL REFS.
LINE INTERFACE OC-48 4xOC-12
PORT PORT RING PORT OC48 FRMR+TOH TERM/PROC.+ AU-3/4/N RETIMING
96x96 STS-1 GRANULARITY CROSS-CONNECT WITH LINE TERMINAL SIDE PATH LEVEL LOOPBACKS
POP-48 T/P/M
TU-3 PROC;
RING PORT HO/LO PATH PORT HO/LO PATH RISC CORE MEMORY Host Interface MCS; OA&M INTEG, APS/BER ALGO SUPPORT IRAM DRAM
VIRTUAL CONCAT DESKEW+SEQ
EXT. SDRAM VIRTUAL CONCAT.
96x96 VC-3 GRANULARITY CROSS-CONNECT WITH LINE TERMINAL SIDE PATH LEVEL LOOPBACKS
POP-48 VC4/VC3 TERM/PROC/MON
MAPPING LAPS X.86, TRANSPARENT/ FRAMED MAPPINGS STS-1 GRAN, UPTO STS-48c (STM-16c).
HOST INTERFACE
JTAG I/F, TEST CTRLS CHIP RESETS, INTERFACE CTRLS, SYSCLK
EEPROM SERIAL (Upto separate devices)
IEEE 802.3/802.3Z ETHERNET/GigE CONTROLLERS; WITH OVER-SUBSCRIBE BUFFERS RMON. 4x1.2 Serdes 4xGigE GMII I/Fs with 8B/10B EnDec (Alternately, SMII I/F)
ETHERNET SMII HIGH WATERMARK IND. ETHERNET GMII/SMII/8B10B SELECTION
CLIENT SIDE
1.25 INTFs, Data Clk, with side Ref.
GMII INTFs, Multiplexed with SMII I/Fs Mbit/s Ethnet, parallel 8B/10B encoded clients
Figure EtherMap-48 TXC-06710 Block Diagram
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EtherMap-48 TXC-06710
Line Interface (refer functional block number Line Interface configurable Full Duplex 1xOC-48, quad independent 4xOC-12 operation. OC-48/4xOC-12 Line 4x622 Differential LVDS data/clock interface each Receive Transmit sides, with independent differential clock input 4xOC-12 mode. interface SFI-4 standard. Each OC-12 line single Mbit/s LVDS Data. On-chip Clock Synthesis Transmit side provided. Reference input clock 19.44 required. Receive Side Data Clock input assumed. Scrambled Unscrambled Data input. monitoring; Automatic Laser Shutdown, OC-12 basis. (Per ITU-T G.775, ITU-T G.958) Framing Processing (refer functional block number Framing Processing provides OC-48/4xOC-12 SONET/SDH framing functionality corresponding section line overhead processing termination. general features framing block follows. Framer block configured operate either OC-48 OC-12 modes. Receive side serial input interface internal data flow comprising: A1x/A2x Frame detection configurable OC-12/48, optional De-scrambling. Byte BIP-8 Calculation/Comparison, option fixed error interpretation, configurable OC-12/48. ANSI/ETSI options detection. H1x/H2x/H3x Pointer Byte processing AU's/VC's, ANSI/ETSI options bits transitions. Pointer Tracking handles contiguous concatenations order; STS-Mc, where B2x, Byte, BIP-384 Calculation/Comparison, option bit/block error interpretation, configurable OC-12/48. MDB1-6, D1-D12 Bytes extracted from appropriate byte time slots, forwarded external interface comprising byte wide data, clock frame reference, with programmable marker pulse that programmed identifying selected bytes. other bytes, A1/A2, C1/J0, H1/H2/H3, K1/K2 also forwarded, unmarked. Dedicated K1/K2 Port addition Buffer Port. Internal Buffer provided microprocessor access. ANSI byte processing/ ITU-T Trail Message Comparison OC-12/48. Path Detection. Received Positive Negative Pointer justification Performance Counters Transmit side serial output interface internal data flow comprising: Test Line insertion input side faults Transmit input Loss Clock. Path Insertion. MDB1-6, D1-D12 Bytes inserted into appropriate byte time slots, read from internal buffer, writable Message Interface, that programmed marking particular bytes. other bytes, A1/A2, C1/J0, H1/H2/H3 K1/K2 also read from byte wide buffer, unmarked. Dedicated K1/K2 Port addition Buffer Port. bits transmission Receive side LOS, LOF, Line detect. B2x, Byte, BIP-384 Calculation insertion.
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TranSwitch EtherMap-48 provides following features (Refer Block Diagram Figure above functional blocks, which referenced number following sections):
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EtherMap-48 TXC-06710
H1x/H2x/H3x Pointer Recalculation (for VC's) Insertion (Pass through AU's) with Concatenation Bytes support arbitrary contiguous concatenations. Higher Order Path Retiming Pointer Generation. Byte BIP-8 Calculation (with option fixed error interpretation) Insertion. Optional Scrambling data stream excepting A1x/A2x/C1(J0) bytes. A1x/A2x Frame insertion. Also provided are: Performance Counters BIP-8 errors, Positive Negative Justification Counters Pointer Tracking Pointer Generation state machines. Control options disable TOH/DCC byte extraction insertion sides respectively. external Section Line Level Ring Port, with Serial Clock, Data Frame Reference, that serve both Framer Processing blocks. types Line Side Loopbacks involving full payload: With Serial Transmit output looped back towards Serial Receive input, along with Transmit side active clock; With Received Line Side data clock looped back towards Transmit Line. possible engage both (ii) simultaneously, that bidirectional loopback. Independent Retiming FIFO's independent STS-1s. Pointer Generating State Machines STS-1s. Retiming concatenated AUGs, arbitrary concatenated SPEs, with concatenation indicator generation. Optional Path insertion FIFO Error. byte detectors, Block error counting, measurement with programmable error thresholds detection times. Synchronization status byte, debounced made available readout. STS-1_VC-3/4 TU-3_VC-3 Cross Connects (refer functional block number There separate 96x96 Cross Connects provided, HO/LO Receive Transmit paths, basically organized Time-Space-Time Switches. Serves switch Frame aligned AU-3/AU-4 terminated STS-1 columns, Frame aligned TU-3 terminated VC3_SPE columns. Input supports HO/LO path level loopbacks, respective Cross-Connect blocks, completely general manner. There restrictions number STS-1/VC-3 path level loopbacks that engaged given time. Cross-Connect minimum VC-3 (STS-1) granularity case path switching, preserves generalized contiguous concatenated group through switching operation). Supports Broadcasting Multicasting. Output End: Automatic HO/LO VC-3 level Unequipped Insertion output VC-3 corresponding block bandwidth) unassigned, requirements ITU-T G.783 GR-253, TelCordia, September 2000. Output End: Path insertion control (Squelching Functionality). Processing Features (refer functional block numbers block actually comprises parts, processing channels each, handle maximum possible Path processing, channels Path (TU-3) path processing. Handles processing STS-1/VC-3 basis, OC-48/4xOC-12 modes. Each channel processing block programmed total STS-1 timeslots that available; same true order VC-3 timeslots. concatenation types generated recognized Framing block, understood processing block.
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EtherMap-48 TXC-06710
Microprocessor access nine bytes with read write override capability byte storage with ITU/ETSI message comparison, CRC-7 check optional Path generation Trace Identification Mismatch. Byte ANSI message comparison, with CRC-7 option LF/CR option. byte insertion from microprocessor written Reference. error checking bit/ block error counting. calculation insertion with optional error insertion. Path Signal Label mismatch, unequipped detection with optional Path generation mismatch. insertion under microprocessor control. byte processing Virtual Concatenation, based [G.707], [G.783], [G.803] [G.805] along with Link Capacity Adjustment Scheme (LCAS), based [G.7042] document. processing chip includes Virtual Concatenation Multi Frame processing, along with LCAS state machine achieve hitless capacity adjustment. LCAS packets uses Bits Byte, separate embedded Multi-frame structure. LCAS operation compatible with LCAS systems. There adequate memory on-chip achieve 125us Differential Delay Compensation (for total single OC-48 worth payload). higher needs with external SDRAM. important note that when processing channel applies TU-3_VC-3, byte processing Virtual Concatenation still applies, across different TUG-3 structures. external buffer memory required EtherMap-48 device Virtual Concatenation Processing. on-chip memory controller provides 'glueless' interface high speed synchronous 64-bit wide SDRAM, incoming OC-48 line. external timing control logic required. SDRAM memory controller directly addresses Mbytes external buffer memory offering significant buffering capacity. Thus capacity external SDRAM interface enough compensate milliseconds differential delay. processing single RDI, three with counter. inserted either calculated from received errors selectable single three RDI. Supervisory unequipped generation. Path Overhead Byte Insertion From RAM, interfaces, terminal, ring (mate device) Receive side (eg., RDI). byte processing chip, byte access. Single Alarm Indication Port (AIP) Ring Port) combined High Order Order Path Ring operation USHR/P support. external Port supports both AU-3/4 TU-3 Ring port information. There Level AIP/POH Port combiner block. Data Links from OC-48/4xOC-12 lines, made available external port, external processing needed. external Port supports both AU-3/4 TU-3 bytes. TU-3 Pointer tracking constituent TU-3_VC-3s. TU-3 Pointer Tracking Pointer Regeneration features similar what provided pointer tracking regeneration. processing features similar processing there TU-3 Pointer Tracking applicable, then same bypassed. Main Mapper Features (refer functional block number main Ethernet over SONET Mapper Block supports following Mapping modes: Generic Framing Procedure ITU-T G.7041 (January 2002) Transparent Mode that assumes following types 8B/10B encoded clients: ESCON (Enterprise System Connectivity), FICON (Fibre Channel 1GHz), Gigabit Ethernet (Transparently Mapped), DVB-ASI.
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EtherMap-48 TXC-06710
Framed Mapping Features (ITU-T G.7041) (refer functional block number Core Header Framing, with Core Header scrambling. Frame Delineation Algorithm used achieve Frame Sync. User (client data management) frames support with separate Payload Header optional Payload FCS. Payload uses ITU-T CRC-32 polynomial. Message Length programmable. User Frame Payload Header, addition mandatory Type tHEC fields, variable extension header also supported, together with extension (eHEC). Extension Header configurable bytes. Also, mandatory Type fields configurable options (PTI, PFI, UPI). Null, Linear type Extension Headers fully supported. Payload Area scrambler Receive Side DeScrambler activated only SYNC state. Loss Synchronization Alarm Loss Signal Alarm generation frames. Transparent Mapping Features (ITU-T G.7041) (refer functional block number Section [G.7041]. chip 1.25 Serial /DeSerializer (Serdes) with 8B/10B Encoder/Decoder Multiplexing clients possible, frame basis, port addresses User Payload Header Common Section. Adaptation 8B/10B Client signals Frame 64B/65B Block codes, section [G.7041] document, with support 10B_ERR code. 65B_PAD code. Adaptation payload within SONET/SDH container/Virtually Concatenated container based 64B/65B code block multiframe, with leading bits each 64B/65B code, along with CRC-16 computation trailing octets. Special rules running disparity initialization boundaries ordered sets various 8B/10B clients, supported. Rate Adaptation follows: Minimum rules 8B/10B clients followed that, when rate adapting local reference clock demapping end, even worst case input-output clock differentials (clock offset requirements significantly relaxed, ppm, supported frequency range 8B/10B clients), after deleting idles, sufficient min) remains ensure frame delineation. Jitter Wander characteristics depends quality Local clock. After 8B/10B encoding, Fibre Channel FICON full rate 1062.5 ppm; ESCON 0.04 MHz; Gigabit Ethernet 1250 ppm.
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Framed Mode that assumes following types clients: Mbit/s Ethernet, Gigabit Ethernet. Link Access Procedure SONET/SDH, ITU-T X.86 (Draft Documents): LAPS (Link Access Procedure SONET/SDH), ITU-T X.86: Mbit/s Gigabit Ethernet mapping. Granularity STS-1. Each Mapping modes independently configurable, variable proportions, terms STS-1 granularity. variety data paths exist simultaneously. blocks configurable allow mixed mode operation different channels.
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EtherMap-48 TXC-06710
Gigabit Ethernet Features (refer functional block number Ethernet Block comprises four Ethernet Sub-Blocks, 1-4, comprises following components (note that first three bullets below, form common parallel multiplexed interface): 4xGMII Gigabit Ethernet Interface. 24xSMII Fast Ethernet interfaces. 4x8B/10B Parallel Ten-bit Interface 4xMACs Gigabit Ethernet Interfaces 4xFrame/Flow Control Buffers, with Buffer Management Logic Client Signal Rate Adaptation (This block common both Gigabit Ethernet 8B/10B block encoded clients (with EOF/SOF Idle seq. recognition); each buffer block configurable 6xFast Ethernet signals. Buffer Overflow/Underflow alarms apply uniformly both based Block encoded clients. Flow control watermarks apply only based clients. 24xSMII interface processing block. 4x8B/10B Block Encoder/Decoder 4x8B/10B decoded character stream GMII Frame conversion block 4x8B/10B Client SerDes Alarm Processing Block that includes Disparity Error Checking. Loss Clock Monitoring Parallel multiplexed interface. There four 8B/10B Encoders/Decoders that does following: Compliant with IEEE 802.3z 1998 Gigabit Ethernet standard, Fibre Channel ANSI X3.230-1994, ESCON ANSI X3.296-1997. This implies 8B/10B Decoder/Encoder interprets control characters based superset three standards, fully supports Ordered Sets Fibre-Channel, Gigabit Ethernet ESCON. 8B/10B Block Encoder/Decoder independently usable 8B/10B clients requiring on-chip SerDes. 8B/10B Decoder/Encoder with Lookup tables. complete data control codes based IEEE 802.3z, 1998 standard, Clause Table 36-1b. Gigabit Ethernet specific ordered sets control characters fully supported. Client side loopbacks diagnostic capability. Verifies frame integrity (FCS Length checks). Errored frames either filtered, passed higher layer. Egress Ethernet frame encapsulation, such padding achieve minimum length, preamble, Inter packet (IPG), generation. Programmable IPG. Minimum frame size bytes, maximum frame size: bytes. Transparent IEEE 802.3-1998 VLAN (Virtual LAN) byte. Automatic Base page Autonegotiation optimal operating conditions, mechanism IEEE 802.3. Optional Extended Page negotiation supported. Supports IEEE 802.3 mandatory Control Management Registers. Over Subscription support Device Configuration Flow Control. PRODUCT PREVIEW TXC-06710-MA 2002
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Alarms failure Indications: alarms Fibre Channel, ANSI X3.230-1994: Loss Light (LOL) LOS; 8B/10B Loss Synchronization. Transport ingress failure, Fibre channel output does report CSF, continuously outputs 10B_ERR. alarms ESCON, ANSI X3.296 -1997: LOS, Loss 8B/10B sync, output failure Transport Ingress fault. alarms Gigabit Ethernet, IEEE 802.3z-1998: LOS, Loss 8B/10B Sync, output Failure Transport Ingress fault.
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EtherMap-48 TXC-06710
Option support IEEE 802.3-1998 Flow Control each Ethernet Port. Programmable watermarks FIFO full/empty conditions. Automatic generation Pause frames based FIFO fill levels. Note that Full Duplex mode alone supported. Loss-less flow control valid frames bytes. Adequate buffering achieve this included -device RX/TX directions. Provides port side-band Pause state indication upstream devices. Control option disable receiving Ethernet Pause frames, that enables transparent transmission Ethernet Pause frame. Control Statistics IEEE 802.3z-1998) that includes: Detection device, initialization, Device Standard Control Status Registers grouped function: Receive Transmit Control Registers, Receive Transmit Status Registers, Address Recognition Control Registers, RMON registers (for Network Management), Flow Control Registers Performance counters ensure roll-over compliance with standards Provides statistic counters support RMON implementations. group, counters provided TX/RX frames, errors, alignment errors, iii) Multicast frames transmitted received, Broadcast frames transmitted received, Frame length Errors, count valid frames, among others. 8B/10B 1.25 SerDes Features (refer functional block number There four 1.0/1.25 SerDes blocks having following features: Compliant with IEEE 802.3z 1998/ ANSI X3.230 1994. each four SerDes blocks, Receive side Clock Recovery Transmit side PLLs either software programmable hardware selectable, example change reference frequency supplied) serve range clients Fibre Channel Encoded) Gigabit Ethernet (1.250 GHz). Serial loopback. Current Mode Logic (CML) pads. External differential reference clock input Clock Recovery Synthesis Blocks. Loss Signal Detection. Internal Termination resistors. GigE GMII Interface Features (refer functional block number Each four Gigabit Ethernet ports have GMII interface, IEEE 802.3z 1998. signal definitions follows: Receive Side: GMII interface comprises byte data, clock, data valid error indication. Transmit Side: GMII interface comprises byte data, clock (for both Gigabit fast Ethernet options), transmit enable transmit error indication. GMII Management Interface comprises Management Clock Management Serial data I/O.
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Host Interface Processor Features (refer functional block number Provides message based communication with external Host device configuration/statusretrieval. external dependency boot exchange simple read/write/goto messages immediately after reset complete. Support complete firmware download from external SEEPROM. Requires simple message from Host initiate download. Optionally, firmware download from SEEPROM through user downloaded program. Alternatively complete firmware download from Host, requiring external SEEPROM. Instructions/Data memories available on-chip. Writing external SEEPROM supported firmware updates. 16-bit Host interface, lead selectable between Motorola/Intel modes. Serial Boot/Application PROM Memory Feature: EtherMap-48 uses on-chip Primary Secondary boot with external SEEPROM Application memory, which initializes device performs bootstrap startup application load autonomously from this interface requiring minimal intervention from host processor. After EtherMap-48 loaded itself, will ready host communication initialization configuration. Firmware upgrades field downloaded external SEEPROM through EtherMap-48 host mailbox interface. shall possible over-write Boot section PROM. Test Features: Standard 5-lead, IEEE 1149.1 compliant boundary scan. Separate 5-lead JTAG port debug access embedded processor. Scan memBist testability High-Z output leads option Test Enable features
General Device Level Features: Control Management Unified Messaging Interface wide external host interface Standardized Interrupt, Alarm Handling Reset schemes Internal Performance Counters (One second/ minutes) second Performance Fault Monitoring registers, with Alarm Performance Statistics Generation TelCordia GR-253. chip Ethernet RMON capability IEEE 802.1q Test Access Port IEEE 1149.1 boundary scan V/3.3 I/O, core 676-lead ball grid array package
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EtherMap-48 TXC-06710
SELECTED PARAMETER VALUES
ABSOLUTE MAXIMUM RATINGS ENVIRONMENTAL LIMITATIONS Parameter Core Supply Voltage, +1.3V nominal Supply Voltage, +2.5V nominal input voltage Storage temperature range Ambient operating temperature Moisture Exposure Level Relative humidity, during assembly Relative humidity, in-circuit Classification Latch-up Symbol VDD13 VDD25 Unit Level Conditions Notes Notes Notes Note ft/min. linear airflow EIA/JEDEC JESD22-A112-A Note non-condensing Note Meets JEDEC STD-78
absolute value 2000
Notes: Conditions exceeding values cause permanent failure. Exposure conditions near values extended periods impair device reliability. Pre-assembly storage non-drypack conditions recommended. Please refer instructions "CAUTION" label drypack which devices supplied. Test method MIL-STD-883D, Method 3015.7. Device core 1.3V only.
THERMAL CHARACTERISTICS Parameter Thermal resistance: junction ambient POWER REQUIREMENTS Parameter VDD25 IDD25 PDD25 VDD13 IDD13 PDD13
Notes: Typical values based measurements made with nominal voltages values dependent upon VDD.
Unit
oC/W
Test Conditions ft/min linear airflow
Unit
Test Conditions Notes Notes Notes Notes
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PACKAGE INFORMATION
EtherMap-48 device packaged 676-lead (Super Flip Chip) Ball Grid Array package suitable surface mounting, illustrated Figure
Bottom View
TRANSWITCH
TXC-06710AISB
E1/4 Note
D1/4
(A3)
Dimension (Note Notes: dimensions millimeters. Values shown reference only. Identification solder ball corner contained within this shaded zone. This package corner angle, chamfered identification. Size array: TBD, JEDEC code TBD. (Ref.) (Ref.) (BSC) (BSC) (BSC)
Nominal 3.20 0.50 2.54 1.20 0.64 31.0 29.0 31.0 29.0 1.00
Figure EtherMap-48 TXC-06710 Package Diagram
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EtherMap-48 TXC-06710
ORDERING INFORMATION
Part Number: TXC-06710AISB 676-lead ball grid array package
RELATED PRODUCTS
TXC-04226, EtherMap-3 Device (Ethernet into STS-3/STM-1 SONET/SDH Mapper). EtherMap-3 highly integrated device that provides mapping 10/100/1000 Mbit/s Ethernet into SONET/SDH STS-3/STM-1 Transport payloads. device supports connection eight 10/100 Mbit/s Ethernet ports, using SMII interfaces, single 1000 Mbit/s Ethernet port, using GMII interface. transmit direction, each port, received Ethernet frames encapsulated using either LAPS LAPF protocol. TXC-06212, PHAST-12E VLSI Device (Programmable, High Performance ATM/PPP/TDM SONET/SDH Terminator Level with Enhanced Features). PHAST-12E highly integrated SONET/SDH terminator device designed Acell, frame, higher order multiplexing, transmission applications. single PHAST-12E device terminate four individual STS-3c STM-1 lines single STS-12/12c STM-4/4c line.
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NOTES
TranSwitch reserves right make changes product(s) circuit(s) described herein without notice. liability assumed result their application. TranSwitch assumes liability TranSwitch applications assistance, customer product design, software performance, infringement patents services described herein. does TranSwitch warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right TranSwitch covering relating combination, machine, process which such semiconductor products services might used.
PRODUCT PREVIEW information documents contain information products their formative design phase development. Features, characteristic data other specifications subject change. Contact TranSwitch Applications Engineering current information this product.
PRODUCT PREVIEW TXC-06710-MA 2002
PRODUCT PREVIEW
TranSwitch Corporation
Enterprise Drive
Shelton, 06484
Tel: 203-929-8810
Fax: 203-926-9453
www.transwitch.com
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TECHNICAL OVERVIEW
EtherMap-48 TXC-06710
DOCUMENTATION UPDATE REGISTRATION FORM
would like receive updated documentation selected devices becomes available, please provide information requested below (print clearly type) then tear this page, fold mail Marketing Communications Department TranSwitch. Marketing Communications will ensure that relevant Product Information Sheets, Data Sheets, Application Notes, Technical Bulletins other publications sent you. also choose provide same information (203.926.9453), e-mail (info@txc.com), telephone (203.929.8810). Most these documents will also made immediately available direct download Adobe files from TranSwitch World Wide Site (www.transwitch.com). Name: Company: Title: Dept./Mailstop: Street: City/State/Zip: located outside U.S.A., please Country: Postal Code: Telephone: Ext.: Fax:
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PRODUCT PREVIEW TXC-06710-MA 2002
PRODUCT PREVIEW
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www.transwitch.com

OC-48 SONET/SDH Ethernet Mapper TXC-06710 TECHNICAL OVERVIEW PRODUCT P

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