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PDI1394L41 1394 content protection link layer controller
Preliminary specification Supersedes data 2000 2000
Philips Semiconductors
Philips Semiconductors
Preliminary specification
1394 content protection link layer controller
PDI1394L41
FEATURES DESCRIPTION restrictions QUICK REFERENCE DATA ORDERING INFORMATION CONFIGURATION FUNCTIONAL DIAGRAM INTERNAL BLOCK DIAGRAM APPLICATION DIAGRAM DESCRIPTION Host Interface Interface Interface Interface Other Pins 10.0 RECOMMENDED OPERATING CONDITIONS 11.0 ABSOLUTE MAXIMUM RATINGS 12.0 FUNCTIONAL DESCRIPTION 12.1 Overview 12.2 interface layer 12.2.1 61883 International Standard 12.2.2 Headers 12.2.3 Interface 12.2.4 Content Protection 12.2.5 Audio Support 12.2.6 Sync Support 12.2.7 Programmable Buffer Memory 12.3 Bushold Link/PHY single capacitor galvanic isolation 12.3.1 Bushold 12.3.2 Single capacitor isolation 12.4 Power Management 12.5 host interface 12.5.1 Read accesses 12.5.2 Write accesses 12.5.3 Accessing register (Power-down, Power-up) 12.5.4 little endianness, data invariance, data width 12.5.5 Accessing asynchronous packet queues 12.5.6 interface signals 12.6 Asynchronous Packet Interface 12.6.1 Reading Asynchronous Packet 12.6.2 Link Packet Data Formats 12.7 Interrupts 13.0 REGISTER 13.1 Link Control Registers 13.1.1 Register (IDREG) Base Address: 0x000 13.1.2 General Link Control (LNKCTL) Base Address: 0x004 13.1.3 Link /Phy Interrupt Acknowledge (LNKPHYINTACK) Base Address: 0x008 13.1.4 Link Interrupt Enable (LNKPHYINTE) Base Address: 0x00C 13.1.5 Cycle Timer Register (CYCTM) Base Address: 0x010 13.1.6 Register Access (PHYACS) Base Address: 0x014 13.1.7 Global Interrupt Status Control (GLOBCSR) Base Address: 0x018 13.1.8 Timer (TIMER) Base Address: 0x01C 13.2 (Isochronous) Transmitter Receiver Registers 13.2.1 Isochronous Transmit Packing Control Status (ITXPKCTL) Base Address: 0x020
2000
Philips Semiconductors
Preliminary specification
1394 content protection link layer controller
PDI1394L41
13.2.2 Common Isochronous Transmit Packet Header Quadlet (ITXHQ1) Base Address: 0x024 13.2.3 Common Isochronous Transmit Packet Header Quadlet (ITXHQ2) Base Address: 0x028 13.2.4 Isochronous Transmitter Interrupt Acknowledge (ITXINTACK) Base Address: 0x02C 13.2.5 Isochronous Transmitter Interrupt Enable (ITXINTE) Base Address: 0x030 13.2.6 Isochronous Transmitter Control Register (ITXCTL) Base Address: 0x34 13.2.7 Isochronous Transmitter Memory Status (ITXMEM) Base Address: 0x038 13.2.8 Isochronous Receiver Unpacking Control (IRXPKCTL) Base Address: 0x040 13.2.9 Common Isochronous Receiver Packet Header Quadlet (IRXHQ1) Base Address: 0x044 13.2.10 Common Isochronous Receiver Packet Header Quadlet (IRXHQ2) Base Address: 0x048 13.2.11 Isochronous Receiver Interrupt Acknowledge (IRXINTACK) Base Address: 0x04C 13.2.12 Isochronous Receiver Interrupt Enable (IRXINTE) Base Address: 0x050 13.2.13 Isochronous Receiver Control Register (IRXCTL) Base Address: 0x054 13.2.14 Isochronous Receiver Memory Status (IRXMEM) Base Address: 0x058 13.3 Asynchronous Control Status Interface 13.3.1 Asynchronous RX/TX Control (ASYCTL) Base Address: 0x080 13.3.2 Asynchronous RX/TX Memory Status (ASYMEM) Base Address: 0x084 13.3.3 Asynchronous Transmit Request Next (TX_RQ_NEXT) Base Address: 0x088 13.3.4 Asynchronous Transmit Request Last (TX_RQ_LAST) Base Address: 0x08C 13.3.5 Asynchronous Transmit Response Next (TX_RP_NEXT) Base Address: 0x090 13.3.6 Asynchronous Transmit Response Last (TX_RP_LAST) Base Address: 0x094 13.3.7 Asynchronous Receive Request (RREQ) Base Address: 0x098 13.3.8 Asynchronous Receive Response (RRSP) Base Address: 0x09C 13.3.9 Asynchronous RX/TX Interrupt Acknowledge (ASYINTACK) Base Address: 0x0A0 13.3.10 Asynchronous RX/TX Interrupt Enable (ASYINTE) Base Address: 0x0A4 13.3.11 Register Base Address: 0x0B0 13.3.12 Shadow Register (SHADOW_REG) Base Address: 0x0F4 13.4 Indirect Address Registers 13.4.1 13.4.2 Indirect Address Register (INDADDR) Base Address: 0x0F8 13.4.3 Indirect Data Register (INDDATA) Base Address: 0x0FC 13.5 Indirect Address Registers 13.5.1 Registers FIFO Size Programming 14.0 ELECTRICAL CHARACTERISTICS 14.1 Categories 15.0 CHARACTERISTICS 16.0 TIMING DIAGRAMS 16.1 Interface Operation 16.2 Interface Critical Timings 16.3 PHY-Link Interface Critical Timings 16.4 Host Interface Critical Timings 16.5 CYCLEIN/CYCLEOUT Timings 16.6 RESET Timings
2000
Philips Semiconductors
Preliminary specification
1394 content protection link layer controller
PDI1394L41
FEATURES
IEEE1394.a IEEE1394-1995 Standard Link Layer Controller Hardware Support IEC61883 International Standard
Digital Interface Consumer Electronics
DESCRIPTION
PDI1394L41, Philips Semiconductors Full Duplex 1394 Audio/Video (AV) Link Layer Controller, IEEE 1394-1995 compliant link layer controller featuring embedded layer interfaces. layers designed encrypt pack, unpack decrypt application data packets transmission over IEEE1394 using isochronous data transfers "5C" content protection method. application data packetized according 61883 International Standard Interface Consumer Electronic Audio/Video Equipment. Both layer interfaces byte-wide ports capable accommodating various MPEG-2 codecs. flexible host interface provided internal register configuration well performing asynchronous data transfers. Both wide data paths, well multiplexed/non-multiplexed access modes supported. PDI1394L41 powered single power supply inputs outputs tolerant. available LQFP144 package.
Interface IEEE 1394-1995 1394.a Physical Layer
Interface
Tolerant I/Os Single supply voltage Full-duplex isochronous operation Operates with 400/200/100 Mbps physical layer devices byte fully programmable FIFO pool isochronous
asynchronous data
Supports single capacitor isolation mode IEEE 1394-1995,
Annex isolation
6-field deep buffer added enhance real-time isochronous
synchronization using AVFSYNC
restrictions
rules forth Digital Transmission Licensing Administrator (DTLA) information concerning some features subject license issued DTLA. That information been omitted from this data sheet available only DTLA licensees restricted distribution basis. order obtain copy information, licensed parties should contact Philips Semiconductors 1394@philips.com request data sheet addendum AL41-1. Upon verification requestor's DTLA license status, paper copy addendum will sent DTLA listed responsible person within requesting company. Distribution samples sales chip likewise restricted DTLA licensees. information pertaining procurement DTLA license please consult DTLA website http://www.dtcp.com.
Generates port clocks under software control. Select
three frequencies: 24.576, 12.288, 6.144
Hardware support "5C" content protection method chip timer resources Flexible 8/16 multiplexed/non-multiplexed host interface Parallel interface Fast 56-bit cipher/decipher blocks capable operating
Mbps
Hardware authentication acceleration reduce software
processor loading
QUICK REFERENCE DATA
Tamb SYMBOL SCLK PARAMETER Functional supply voltage range Supply current Device clock Operating 49.147 CONDITIONS 49.152 49.157 UNIT
ORDERING INFORMATION
PACKAGES 144-pin LQFP144 TEMPERATURE RANGE OUTSIDE NORTH AMERICA PDI1394L41BE NORTH AMERICA PDI1394L41BE PKG. DWG. SOT486-1
NOTE: This datasheet subject change. Please visit internet website latest changes.
2000
Philips Semiconductors
Preliminary specification
1394 content protection link layer controller
PDI1394L41
CONFIGURATION
LQFP
Function Function INTN WAIT RESETN 16BIT 1394 MODE RESERVED RESERVED RESERVED RESERVED CLK50 CYCLEIN CYCLEOUT RESERVED RESERVED TESTPIN TESTPIN TESTPIN RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
Function CTL1* CTL0* LREQ SCLK* LPS* LINKON ISON AV1ERR0 AV1ERR1 AV1ENDPCK AV1CLK AV1FSYNC AV1VALID AV1SYNC AV1EMIO AV1EMI1 AV1D0 Function AV1D1 AV1D2 AV1D3 AV1D4 AV1D5 AV1D6 AV1D7 AV1READY AV2ERR0/LTLEND AV2ERR1/DATINV AV2ENDPCK AV2CLK AV2FSYNC AV2VALID AV2SYNC AV2EMI0 AV2EMI1 AV2D0 AV2D1 AV2D2 AV2D3 AV2D4 AV2D5 AV2D6 AV2D7 AV2READY RESERVED
Indicates equipped with internal hold circuit activated state ISON pin.
SV01020
2000
Philips Semiconductors
Preliminary specification
1394 content protection link layer controller
PDI1394L41
FUNCTIONAL DIAGRAM
A[7:0] D[15:8] AD[7:0] 16BIT RESETN WAIT INTN CYCLEIN CYCLEOUT CLK50 D[7:0] AV1CLK AV1VALID AV1SYNC AV1FSYNC AV1READY AV1EMI[1:0] AV1ENDPCK AV1ERR0 AV1ERR1 D[0:7] CTL[0:1] LREQ ISON LinkOn SCLK 1394MODE
HOST
PDI1394L41 IEEE 1394 CONTENT PROTECTION LINK LAYER CONTROLLER
LAYER
AV2D[7:0] AV2CLK AV2VALID AV2SYNC AV2FSYNC AV2READY AV2EMI[1:0] AV2ENDPCK AV2ERR0/LTLEND AV2ERR1/DATAINV
LAYER
SV01021
INTERNAL BLOCK DIAGRAM
D[7:0] AV1READY AV1EMI[1:0] AV1CLK AV1SYNC AV1VALID AV1FSYNC AV1ENDPCK AV1ERR0 AV1ERR1 AV1SY
LAYER1
LAYER ISOCHRONOUS TRANSMITTER/ RECEIVER
CYCLEOUT CYCLEIN D[0:7] 12KB BUFFER MEMORY (ISOCH ASYNC PACKETS) LINK CORE CTL[0:1] LREQ LinkOn ISON SCLK 1394MODE
D[7:0] AV2READY AV2EMI[1:0] AV2CLK AV2SYNC AV2VALID AV2FSYNC AV2ENDPCK AV2ERR0/LTLEND AV2ERR1/DATAINV AV2SY
LAYER2
LAYER ISOCHRONOUS TRANSMITTER/ RECEIVER
NOTE: THERE ISOCHRONOUS RECEIVER ISOCHRONOUS TRANSMITTER-THEREFORE, WHEN EITHER AVPORT TRANSMIT, OTHER AVPORT AUTOMATICALLY RECEIVE ASYNC TRANSMITTER RECEIVER
A[7:0] D[15:8] AD[7:0] 16BIT WAIT INTN
HOST
8-BIT INTERFACE
CONTROL STATUS REGISTERS
RESETN
SV01022
2000
Philips Semiconductors
Preliminary specification
1394 content protection link layer controller
PDI1394L41
APPLICATION DIAGRAM
MPEG DECODER INTERFACE PDI1394L41 LINK MPEG DECODER INTERFACE
PHY-LINK INTERFACE
PDI1394Pxx
1394 CABLE INTERFACE
DATA ADDRESS INTERRUPT CONTROL
HOST CONTROLLER
SV01023
DESCRIPTION Host Interface
SYMBOL AD[7:0] D[15:8] A[7:0] NAME FUNCTION Host Interface Data (MSB) through Byte wide data path internal registers. Host Interface Data (MSB) through Only used access mode (HIF 16BIT HIGH). Host Interface Address through Provides host with byte wide interface internal registers. description Host Interface addressing rules (Section 12.5). Control used indicate first byte/word read function last byte/word write function that data quadlet fetched stored. Section 12.5 more information regarding host interface. Chip Select (active LOW). Host control signal enable access FIFO control status registers. Write enable. When asserted (LOW) conjunction with CSN, write PDI1394L41 internal registers requested. (NOTE: these both conjunction with CSN, then write cycle takes place. This used connect CPUs that R/W_N line rather than separate RD_N WR_N lines. that case, connect R/W_N line LOW.) Interrupt (active LOW). Indicates interrupt internal PDI1394L41. Read General Interrupt Register more information. This open drain requires pull-up resistor. Address latch enable. Used multiplex mode only. Read enable. When asserted (LOW) conjunction with CSN, read PDI1394L41 internal registers requested. Wait signal. Signals Host interface WAIT condition when Section 12.5. Reset (active LOW). asynchronous master reset PDI1394L41. Host interface mode pin. When operates mode. When HIGH operates mode. Host interface mode pin. When operates non-multiplex mode, when HIGH operates multiplex mode. When HIGH, low-order eight address bits multiplexed with data AD[7:0], otherwise they non-multiplexed supplied A[7:0].
INTN WAIT RESETN 16BIT
2000
Philips Semiconductors
Preliminary specification
1394 content protection link layer controller
PDI1394L41
Interface
NOTE: This interface configured transmit receive according condition "DIRAV1" GLOBCSR register (0X018)-default transmit. SYMBOL AV1ERR0 AV1ERR1 AV1ENDPCK NAME FUNCTION error. Indicates packet delivered D[7:0] error; current packet unreliable. Sequence Error. Indicates least source packet lost before current [7:0] data. application packet indication from data source. Required only input packet multiple bytes. tied data packets that size. External application clock. Rising edge active. This programmed output application clock. Depending configuration Port transmitter receiver, output enable located ITXPKCTL register (address 0x020) IRXPKCTL register (address 0x040). Programmable frame sync, input when interface transmitter output when interface configured receiver. When input, used designate frame data Digital Video (DV). signal time stamped transmitted field ITXHQ2. When output, signal derived from field IRXHQ2. Value. When port configured transmitter, this input. When port configured receiver, output. description ITXCTL (0x034) IRXCTL (0x054) registers. Indicates data [7:0] valid. Indicates that data currently being clocked source under condition AV1VALID start application packet. interface configured receiver, then will assert AV1SYNC when application packet becomes available persist until first data packet clocked out. Thus, AV1VALID last more than cycle, exactly cycle which AV1VALID asserted. Encryption Mode Indication pins. Outputs encryption mode when this port receive state with decipher enabled. Audio/Video Data (MSB) through Part byte-wide interface layer When port configured receiver, this input. This flow control signal that allows application indicate whether able accept data flowing across Interface interface responds inactive AV1READY asserting AV1VALID, thereby withholding data from application. AV1READY signal processed through level pipelining, which means that Link will accept data cycle which AV1READY de-asserted will accept data cycle which AV1READY asserted. AV1READY When port configured transmit, this output. This flow control signal that allows link chip indicate whether able accept data flowing across Interface source data, external entity, responds inactive AV1READY asserting AV1VALID, thereby withholding data. AV1READY signal should processed sink through level pipelining, which means that receiver must able accept data cycle which AV1READY de-asserted. receiving interface does have accept data cycle which AV1READY asserted.
AV1CLK
AV1FSYNC
AV1VALID
AV1SYNC
105, 117, 116, 115, 114, 111, 110, 109,
AV1EMI[1:0] D[7:0]
2000
Philips Semiconductors
Preliminary specification
1394 content protection link layer controller
PDI1394L41
Interface
NOTE: This interface configured transmit receive according condition "DIRAV1" GLOBCSR register-default receive. SYMBOL AV2ERR0/ LTLEND NAME FUNCTION error, indicates packet containing [7:0] error, current packet unreliable. This also used input mode LTLEND (Little Endian) after chip reset. appropriate pull-up pull-down resistor recommended) should connected place desired state during reset. Please details related LTLEND "Host Interface" section datasheet (Section 12.5). Sequence Error. Indicates least source packet lost before current [7:0] data. This also used input mode DATINV (Data Invariant) after chip reset. appropriate pull-up pull-down resistor recommended) should connected place desired state during reset. Please details related DATINV "Host Interface" section datasheet (Section 12.5). application packet indication from data source. Required only input packet multiple bytes. tied data packets that size. External application clock. Rising edge active. This programmed output application clock. Depending configuration Port transmitter receiver, output enable located ITXPKCTL register (address 0x020) IRXPKCTL register (address 0x040). Programmable frame sync, input when interface transmitter, output when interface configures receiver. When input, used designate frame data Digital Video (DV). signal time stamped transmitted field ITXHQ2. When output, signal derived from field IRXHQ2. Value: When port configured transmitter, this input. When port configured receiver, output. description ITXCTL (0x034) IRXCTL (0x054) registers. Indicates data [7:0] valid. Indicates that data currently being clocked source under condition AV2VALID start application packet. interface configured receiver, then will assert AV2SYNC when application packet becomes available persist until first data packet clocked out. Thus, AV2VALID last more than cycle, exactly cycle which AV2VALID asserted. Encryption Mode Indication pins. Outputs encryption mode when this port receive state with decipher enabled. Audio/Video Data (MSB) through Part byte-wide interface layer When port configured receiver, this input. This flow control signal that allows application indicate whether able accept data flowing across Interface interface responds inactive AV2READY asserting AV2VALID, thereby withholding data from application. AV2READY signal processed through level pipelining, which means that Link will accept data cycle which AV2READY de-asserted will accept data cycle which AV2READY asserted. AV2READY When port configured transmit, this output. This flow control signal that allows link chip indicate whether able accept data flowing across Interface source data, external entity, responds inactive AV2READY asserting AV2VALID, thereby withholding data. AV2READY signal should processed sink through level pipelining, which means that receiver must able accept data cycle which AV2READY de-asserted. receiving interface does have accept data cycle which AV2READY asserted.
AV2ERR1/ DATINV
AV2ENDPCK
AV2CLK
AV2FSYNC
AV2VALID
AV2SYNC
130, 142, 141, 140, 139, 136, 135, 134,
AV2EMI[1:0] D[7:0]
2000
Philips Semiconductors
Preliminary specification
1394 content protection link layer controller
PDI1394L41
Interface
SYMBOL D[0:7] CTL[0:1] 1394 MODE LREQ SCLK LINKON NAME FUNCTION Data (MSB) through (NOTE: preserve compatibility specified Link-Phy interface IEEE 1394-1995 standard, Annex most significant bit). Data expected D[0:1] 100Mb/s, D[0:3] 200Mb/s, D[0:7] 400Mb/s. IEEE 1394-1995 standard, Annex more information. Control Lines between Link Phy. 1394 Specification more information. 1394-1995 Annex (HIGH), 1394.a (LOW) Link Request. request access PHY. IEEE 1394-1995 standard, Annex more information. (Used request arbitration read/write registers). System clock. 49.152MHz input from (the PHY-LINK interface operates this frequency). Link power status. generates host interrupt when this receives link signal from PHY. Interrupt request from another node powered (see pin). Isolation mode. This asserted (LOW) when Annex type isolation barrier used. IEEE 1394-1995 Annex more information. When tied HIGH, this enables internal bushold circuitry affected interface pins (see below). Active bushold circuits allow either direct connection pins single capacitor isolation mode.
ISON
Other Pins
106, 112, 119, 131, 107, 113, 120, 132, SYMBOL NAME FUNCTION
Ground reference
power supply
PD1,2,3,4
Power Down. When asserted (high), Link goes into power mode de-asserts pin. When this state, reads writes registers allowed. Link will resume operation when de-asserted (low), register settings configurations restored their power down values. These pins reserved factory testing. normal operation they should connected ground. Auxiliary clock, value SCLK (usually 49.152 MHz) Provides capability supply external cycle timer signal beginning 1394 cycles. Reproduces 8kHz cycle clock cycle master. Test pins. These signals must connected ground.
RESERVED CLK50 CYCLEIN CYCLEOUT TESTPIN
NOTES: Before asserting bit, SWPD setting high, user should assure that link chip following state operation: isochronous transmit FIFO receiving data transmission isochronous transmitter disabled asynchronous packets being generated transmission Both ASYNC request response queues empty
2000
Philips Semiconductors
Preliminary specification
1394 content protection link layer controller
PDI1394L41
10.0 RECOMMENDED OPERATING CONDITIONS
LIMITS SYMBOL dT/dV Tamb SCLK AVCLK PARAMETER supply voltage Input voltage High-level input voltage Low-level input voltage High-level output current Low-level output current Input transition rise fall time Operating ambient temperature range System clock interface clock Input rise time input fall time 49.147 CONDITIONS MIN. 49.157 MAX. UNIT ns/V
11.0 ABSOLUTE MAXIMUM RATINGS1,
accordance with Absolute Maximum Rating System (IEC 134). Voltages referenced (ground LIMITS SYMBOL IGND, Tstg Tamb Ptot PARAMETER supply voltage input diode current input voltage output diode current output voltage output source sink current current Storage temperature range Operating ambient temperature Power dissipation package CONDITIONS -0.5 -0.5 -0.5 +4.6 +5.5 +0.5 ±150 UNIT
NOTES: Stresses beyond those listed cause permanent damage device. These stress ratings only functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. performance capability high-performance integrated circuit conjunction with thermal environment create junction temperatures which detrimental reliability. maximum junction temperature this integrated circuit should exceed
2000
Philips Semiconductors
Preliminary specification
1394 content protection link layer controller
PDI1394L41
12.0 FUNCTIONAL DESCRIPTION 12.1 Overview
PDI1394L41 IEEE1394-1995 IEEE1394.a compliant link layer controller. provides direct interface between 1394 various MPEG-2 codecs. Link maps unmaps data streams similar data onto 1394 isochronous packets. Data ciphered deciphered according `5C' standard method content protection. Link also provides wide host interface attached microcontroller. Through host interface port, host controller configure layer transmission reception datastreams. host interface port also allows host controller transmit receive 1394 asynchronous data packets.
12.2 interface layer
interface layer format "application packets" according 61883 specification isochronous transport over 1394 network. transmitter receiver within layer perform functions required pack unpack packet data transfer over 1394 network. Once layer properly configured operation, further host controller service should required. operation layer full-duplex, i.e., layer receive transmit packets same cycle. 12.2.1 61883 International Standard PDI1394L41 specifically designed support IEC61883 International Standard Digital Interface Consumer Electronic Audio/Video Equipment. specification defines scheme mapping various types datastreams onto 1394 isochronous data packets. standard also defines software protocol managing isochronous connections 1394 called Connection Management Protocol (CMP). also provides framework transfer functional commands, called Function Control Protocol (FCP). 12.2.2 Headers feature IEC61883 International Standard definition Common Isochronous Packet (CIP) headers. These headers contain information about source type datastream mapped onto isochronous packets. Layer supports headers. headers added transmitted isochronous data packets data source. When receiving isochronous data packets, layer automatically analyzes their headers. analysis headers determines method layer uses unpack data from isochronous data packets. information contained headers accessible registers host interface. (See IEC61883 International Standard Digital Interface Consumer Electronic Audio/Video Equipment more details headers). 12.2.3 Interface link's 8-bit parallel interface synchronous with AVxCLK, designed interface with various MPEG-2 codecs. interface port buffer, programmed, time stamp incoming packets. packet data stored embedded memory buffer, along with time stamp information. After packet been written into layer, layer creates isochronous packet with appropriate header. packet along with header transferred over appropriate isochronous channel/packet. size configuration isochronous data packet payload transmitted determined layer's configuration registers accessible through host interface. interface port waits assertion AVxVALID AVxSYNC. AVxSYNC aligned with rising edge AVxCLK first byte data AVxDATA[7:0]. duration AVxSYNC AVxCLK cycle. AVxSYNC signals layer that transfer packet begun. time AVxSYNC asserted, layer creates time stamp buffer memory. (This only happens configured. format does require these time stamps). time stamp then transmitted part source packet header. This allows receiver provide packet output appropriate time. Only AVSYNC pulse allowed application packet; additional sync pulses presented before full packet inputted, packet will started previously inputted packet data will discarded (and transmitted) conjunction with input error interrupt (INPERR, register 0x02C) being flag error. additional synchronization mechanism defined 61883 specification, called frame sync. frame synchronization signal AVxFSYNC time stamped placed field header. default delay value frame sync cycle times (duration each) future, transmitted very next isochronous cycle regardless available data. PDI1394L41 allows this value programmable from cycle times (see Section 13.2.1). Additionally, some audio applications, value programmed appended only isochronous cycles that have application data attached them. This mode enabled AUDIO (again, Section 13.2.1). When AUDIO mode enabled, additional cycle delays automatically added SYT_DELAY value (bits ITXPKCLT register). receiver side, when stamp matches cycle timer register, pulse generated AVxFSYNC output. timing AVxFSYNC independent AVxCLK. maximum repetition rate application-presented AVFSYNC pulses limited 8,000 pulses second (the cycle rate). rare instance queue overflow with possible loss AVFSYNC pulses, "SYTOVF" interrupt (bit register 0x04C) will occur. SYTOVF interrupt occurs, contents queue automatically flushed normal operation automatically resumes. Some applications would like create their transmit timestamps independent Layer. receive, these applications would like process embedded time stamps instead allowing Layer process these time stamps. This accommodated ENXTMSTMP ITXPKCTL register transmit DIS_TSC IRXPKCTL register receive. conjunction with this mode, additional means flow control enabled AVxREADY signal.
2000
Philips Semiconductors
Preliminary specification
1394 content protection link layer controller
PDI1394L41
Port Transmit Receive
AVxREADY
Description prepared receive byte. attached device will assert AVVALID cycle which AVxRDY false. attached device prepared receive byte. will assert AVxVALID cycle which AVxREADY false.
When port configured receiver, AVxSYNC signal will asserted soon PDI1394L41 port application packet available delivery (independent AVxREADY) will remain asserted until first byte application packet clocked from port. 12.2.4 Content Protection Layer incorporates features implement Digital Transmission Copy Protection (DTCP) scheme that specified Digital Transmission Licensing Authority (DTLA). DTCP specification consists primary functions: stream ciphering authentication. Refer Digital Transmission Content Protection Specification Volume more details about DTCP scheme. Link stream ciphering accomplished internal content cipher decipher blocks. ease software development effort reduce loading controlling processor, link chip also includes cryptographic accelerator capable doing elliptic curve multiplications Sign Verify operations. size number operands cryptographic accelerator blocks, host interface register been extended provide additional control data registers. These extensions have been implemented indirect addressing mechanism. This mechanism allows software written previous versions Link (PDI1394L21 PDI1394L11) operate PDI1394L41. Note, however, that some extensions interrupt registers were made accommodate interrupts originating from content protection block. full description L41's content protection features please data sheet addendum AL41-1. AL41-1 addendum requested from Philips DTLA licensees e-mailing 1394@philips.com. paper copy this addendum available each DTLA licensee after verification license status. Please Section this data sheet further information. DTLA license information available http://www.dtcp.com.
2000
Philips Semiconductors
Preliminary specification
1394 content protection link layer controller
PDI1394L41
12.2.5 Audio Support transmitter some additional features support some types audio transport. These enabled setting (AUDIO) ITXPKCTL (0x020) logic rising edge AVxFSYNC, time stamp will generated written into queue isochronous transmitter. This stamp will point time future dictated following formula: SYT[15:12] CYCTM[15:12] programmed SYT_DELAY value SYT[11:0] CYCTM[11:0] additional delay cycles specific this AUDIO mode. oldest time stamp queue will sent first, only when accompanied data payload. pending time stamp will held until next non-empty packet sent. moment transmission, time stamp should least point cycle future. points time that less than cycle future, will discarded. queue isochronous transmitter store entries, queue isochronous receiver store entries. This supports case where signal applied AVxFSYNC, AUDIO SYT_Delay Assuming there data every cycle, receiver will receive time stamp each cycle with first time stamp pointing just less than cycles future. When queue isochronous receiver full, then most recently received time stamp overwritten with next arriving time stamp. queue should become full contain corrupted time stamp, queue will automatically clear indicate setting "SYTOVF" interrupt. 12.2.6 Sync Support This feature supports 1394 digital camera specification. state this will reflected (ITXCTL register 0x034) will transmitted along with isochronous data block that entered with intended this signal start frame video isochronous header section data payload. Similarly, isochronous receiver will assert AVxSY simultaneously with first byte isochronous packet which value received. NOTE: functionality only intended used when cipher de-cipher enabled.
DATA SYNC
SV01787
Figure Behavior "SY" signal AVport receiver
12.2.7 Programmable Buffer Memory PDI1394L41 maintains distinct buffers that highly configurable optimize bandwidth capabilities. Buffers increased decreased from default value accessing indirect address range 0x100 through 0x1FC (INDADDR, 0x0F8). Layer configured transmit receive compliant MPEG-2 type data, default Isochronous (AV) buffer sizes recommended. FIFO sizes cannot changed dynamically; after FIFO size change, transmitters receivers must reset. Buffers programmed with quadlet (256 Byte) granularity. Minimum buffer size quadlets, maximum buffer size limited buffers cannot exceed Bytes, Quadlets.
DEFAULT BUFFER SIZE
BUFFER MEMORY Asynchronous Receive Response FIFO Asynchronous Receive Request FIFO Asynchronous Transmit Response FIFO Asynchronous Transmit Request FIFO Isochronous (AV) Transmit Buffer Isochronous (AV) Receive Buffer SIZE (Quadlets) 1024 1024
2000
Philips Semiconductors
Preliminary specification
1394 content protection link layer controller
PDI1394L41
12.3 Bushold Link/PHY single capacitor galvanic isolation
12.3.1 Bushold PDI1394L41 uses internal bushold circuit each indicated pins keep these CMOS inputs from "floating" while being driven 3-Stated device input coupling capacitor. Unterminated high impedance inputs react ambient electrical noise which cause internal oscillation excess power supply current draw. following pins have bushold circuitry enabled when ISON logic state: Name CTL0 CTL1 SYSCLK Function control line control line data data data data data data data data System clock input link
Philips bushold circuitry designed provide high resistance pull-up pull-down input pin. This high resistance easily overcome driving device when state switched. Figure shows typical bushold circuit applied CMOS input stage. weak transistors connected input. inverter also connected input supplies gate drive both transistors. When input LOW, inverter output drives lower transistor turns This re-enforces input pin. logic device which normally drives input were 3-Stated, input would remain "pulled-down" weak transistor. driving logic device drives input HIGH, inverter will turn upper transistor re-enforcing HIGH input pin. driving logic device then 3-Stated, upper transistor will weakly hold input HIGH. PHY's outputs 3-Stated single capacitor isolation used with Link; both situations will allow Link inputs float. With bushold circuitry enabled, these pins provided with paths ground, power means bushold transistors; this arrangement keeps inputs known logical states.
INPUT
INTERNAL CIRCUITS
SV00911
Figure Bushold circuit
2000
Philips Semiconductors
Preliminary specification
1394 content protection link layer controller
PDI1394L41
12.3.2 Single capacitor isolation circuit example (Figure shows connections required implement basic single capacitor Link/PHY isolation. NOTE: isolation enablement pins both devices their states, activating bushold circuits each part. bushold circuits provide local ground references each side isolating/coupling capacitors. Also note that ground isolation/signal-coupling must provided form parallel combination resistance capacitance indicated IEEE 1394 standard.
APPLICATION/LINK +3.3V
ISOLATED/PHY +3.3V
LINK PDI1394L41
ISON SCLK PHYCTL0 PHYCTL1 LREQ LINKON
ISO- SYSCLK PDI1394P2x PHYCTL0 PHYCTL1 LREQ LINKON
APPLICATION LINK GROUND
LINK 3.3V
3.3V
ISOLATED GROUND
VALUES THESE RESISTORS DEPEND USED. DATASHEET.
9.1K ALSO APPLICATION NOTE AN2452 MORE DETAILS 1MEG 3.3nF
SV01816
Figure Single capacitor Link/PHY isolation
12.4 Power Management
PDI1394L41 implements several features power management noted 1394a-2000 standard. These features include: Reset Phy/Link interface setting LNKCTL register. Disable Phy/Link interface caused either setting SWPD register -OR- asserting (high) pin. Initialization Phy/Link interface after disabled reset. application power Phy/Link interface deasserting -OR- clearing (low) SWPD register. This will cause produce pulsing signal pin. When power down mode, reads writes host interface will restricted those addressing only register (0x0B0). Please Section 13.3.11 further details. There ways power L41. When application wants 1394 node resume operation, simply needs de-assert pin, clear SWPD register. link also awakened another node sending link-on packet application's node. attached will activate LinkOn line will signal register. Assuming that ELOA enabled, "1", state, will generate interrupt host processor. will then host processor decide whether honor link-on request other node. Then host processor will de-assert -OR- clear SWPD register. This activity will power causing send pulsing signal which notifies PHYchip link activity allows discontinue directing link signal L41. Subsequently, host processor must acknowledge interrupt writing position register after link signal from stopped.
2000
Philips Semiconductors
Preliminary specification
1394 content protection link layer controller
PDI1394L41
12.5 host interface
host interface allows access registers asynchronous packet queues. designed easy with wide range processors, including 8051, MIPS1900, ST20, PowerPC etc. host interface work with wide data paths, offers multiplexed non-multiplexed access. There register addresses (for quadlet wide registers). access bytes rather than quadlets address space bytes, requiring address lines. interface introduces inherent problem that must solved: register fields more than bits wide used (control) changed (status) every internal clock tick. such field accessed through interface requires more than read write cycle, value should change between maintain consistency. overcome this problem accesses chip's internal register space always bits, host interface must converter between internal accesses external accesses. This where shadow register (0x0F4) used. 12.5.1 Read accesses read internal register host interface make snapshot (copy) that specific register which then made available bits time. register that holds snapshot copy real register value inside host interface called shadow register. During 8-bit read cycle address lines used select which bytes currently stored shadow register output onto data bus. This selection done combinatorial logic only, enabling external hardware toggle these lines through values while keeping chip read access mode bytes very fast single extended read cycle), example into external quadlet register. During read cycle address line used select which pair bytes currently stored shadow register output bus. Again selection combinatorial logic, enabling external hardware toggle while keeping chip read access mode both words very quickly. This solution requires control line direct host interface make snapshot internal register when needed, well internal address target register. register address connected input address lines A2.HIF update control line input address line host interface take snapshot target address must presented A2.HIF must raised while executing read access. value will stored shadow register selected byte (HIF mode) word (HIF mode) appears output. registers accessed Direct Address Space. Some registers indirect address space, these registers control FIFO size content protection system. correct internal register space selected through host interface, using directly addressable registers INDADDR (0x0F8) INDDATA (0x0FC).
SHADOW REGISTER
8/16
REGISTERS A0.1 MODE) MODE) A2.7 UPDATE/COPY CONTROL
SV01034
NOTES: required read bytes register before reading another register. example, mode, only byte register 0x54 required read byte address 0x100 0x156 sufficient. update control line does necessarily have connected address line This input could also controlled other means, example combinatorial circuit that activates update control line whenever read access done byte This makes internal updating automatic quadlet reading. Reading bytes shadow register done order often needed. possible read/modify/write register using shadow register (0x0F4) without rewriting bytes. example, modify enable fourth byte Asynchronous Interrupt Enable (0x0A4), read location 0x100+0x0A0+3=0x1A3, followed write modified byte same location 0x100+0x0A0+3=0x1A3 sufficient. other bytes remain unchanged.
2000
Philips Semiconductors
Preliminary specification
1394 content protection link layer controller
PDI1394L41
12.5.2 Write accesses write internal register host interface must collect byte values mode) word values mode) into value then write result target register single clock tick. This requires register hold value being compiled until ready written actual target register. This temporary register inside host interface called shadow register. mode, address lines used select which bytes shadow register written with value data bus. mode, used select which half shadow register written with value data bus. Only byte mode) word mode) written single write access cycle. registers accessed Direct Address Space. Some registers indirect address space, these registers control FIFO size content protection system. correct internal register space selected through host interface, using directly addressable registers INDADDR (0x0F8) INDDATA (0x0FC).
SHADOW REGISTER
8/16
REGISTERS A0.1 MODE) MODE) A2.7 UPDATE/COPY CONTROL
SV01035
NOTES: required write bytes, both words register: those bytes that either reserved (undefined) don't care have written which case they will assigned value that left corresponding byte shadow register from previous write access. example, acknowledge interrupt isochronous receiver mode, single byte write location 0x100+(0x4C)+3 0x14F sufficient. value represents setting A8=1. host interface cannot directly access FIFOs, instead reads from/writes into transfer register (shown Figures above). Data moved between FIFO internal logic soon possible without intervention. update control line does necessarily have connected address line This input could also controlled other means, example combinatorial circuit that activates update control line whenever write access done byte upper bits. This makes internal updating automatic quadlet writing. Writing bytes words shadow register done order often needed (new writes simply overwrite value). possible read/modify/write register using shadow register (0x0F4) without rewriting bytes. example, modify enable fourth byte Asynchronous Interrupt Enable (0x0A4), read location 0x100+0x0A0+3=0x1A3, followed write modified byte same location 0x100+0x0A0+3=0x1A3 sufficient. other bytes remain unchanged.
2000
Philips Semiconductors
Preliminary specification
1394 content protection link layer controller
PDI1394L41
12.5.3 Accessing register (Power-down, Power-up) Accessing register special situation, software written access other link base registers still used. This register read written with link chip power-down mode; this means that there system clock present within link chip. system clock required access other link registers fact that multiple clock cycles required fetch data shadow register write data from shadow register targeted internal register. Reading writing register done through purely combinatoral logic, there access through shadow register. register accessed directly through host interface using same method access required other link base registers. register contains control, status interrupt bits. Operation status interrupt bits register differs slightly from these types bits other registers. Operation falls into four categories: pure status bit, interrupt/status bit, control bit, interrupt control bit. LPSTAT pure status bit; this means that LPSTAT continually reflects status signal link-phy interface. LPSTAT signal active. LPSTAT signal chip inactive. should noted here that LPSTAT should used indicator link chip activity because signal inactive short periods time link chip performing phy-link interface reset function. also pure status when enabled interrupt. will reflect INVERSE status system clock times. When system clock (SCLK) active, When SCLK inactive, also used interrupt setting ESCI this mode operation when interrupt will generated indicate that SCLK become inactive. This interrupt serviced same manner other link register interrupts. write back position order acknowledge interrupt. PLI, interrupt/status bits. These bits enabled interrupts setting corresponding interrupt control EPLI, ELOA, ESCA =1). These bits ALSO status bits when corresponding interrupt enabling However, these bits sets (=1) while status mode, must written with reset. similar operation interrupt operation elsewhere link registers. Also, like other interrupt bits link registers, order acknowledge interrupt these bits, necessary write back position acknowledge interrupt; this resets "0". [Please bear mind that functions represented these bits continuous; recommend that before interrupt acknowledged, corresponding enable should "0", else interrupt will immediately happen again.] SWPD control bit. There ways affect power-down link chip. Setting SWPD will stop link chip from transmitting signal chip thus cause withhold SCLK, thus powering-down link chip. Raising link high level will also accomplish power-down similar manner. BOTH METHODS affect power-down. SWPD bit, being control bit, will reflect state pin. SWPD it's good that active chip operating. this case MUST reset before link will power-up. EPLI, ELOA, ESCA, ESCI interrupt enable bits. Setting these bits will cause corresponding interrupt become active interrupt when that sets. these bits corresponding PLI, LOA, SCA, interrupt/status mode described above. (Also individual descriptions register section this data sheet. Section 13.3.1)
2000
Philips Semiconductors
Preliminary specification
1394 content protection link layer controller
PDI1394L41
12.5.4 little endianness, data invariance, data width host interface offers programmable endianness, data invariance, selectable data widths. LTLEND (pin 121) DATINV (pin 122) multiplexed configuration pins that will sampled trailing edge RESET; states these pins established connecting each proper logic state, ground VDD, through resistor, recommended. verify configuration, shadow register (0x0F4) will preset value 0x0F0A0500 after power reset. Table describes configurations.
Table Configuration possible combinations
LTLEND (Little Endian) DATINV (Data Invariant) 16BIT Table Result Byte/Word address reversed Bytes swapped within word 16-bit data bus, address PDI1394L21 8-bit data bus, address PDI1394L21
Table Explanation mode LittleEnd DataInvariant
HIF16 Outside Address (A1, Inside Address (A1, HIF16 Outside Address (A1, Inside Address (A1,
important note that some operands indirect address space consist more than quadlet. these operands, lowest address always contains most significant quadlet. Endian mode DATAINV bytes each quadlet numbered from left (most significant) right (least significant) shwon Figure access register mode, address should addresses access upper bits register. access upper middle bits register. access lower middle bits register. access lower bits register. access register mode, internal address should addresses access upper bits register access lower bits register
3130
BYTE
BYTE
BYTE
BYTE
SV00656
Figure Byte order quadlets implemented host interface, LTLEND
2000
Philips Semiconductors
Preliminary specification
1394 content protection link layer controller
PDI1394L41
Little Endian mode DATAINV bytes each quadlet numbered from left (most significant) right (least significant) shown Figure access register mode, address should addresses access upper bits register access upper middle bits register access lower middle bits register access lower bits register access register mode, internal address should used addresses access lower bits register access upper bits register
3130
BYTE
BYTE
BYTE
BYTE
SV01079
Figure Byte order quadlets implemented host interface, LTLEND HIGH
12.5.5 Accessing asynchronous packet queues Although entire incoming packets stored receiver buffer memory they randomly accessible. These buffers like FIFOs only frontmost (oldest) data quadlet entry accessible reading. Therefore only location (register address) allocated each receiver queues. Reading this location returns head entry queue, same time removes from queue, making next stored data quadlet accessible. With current host interface such read fact move operation data quadlet from queue shadow register. Once data copied into shadow register longer available queue itself should always read bytes, both words, before attempting other read access careful with interrupt handlers PDI1394L41!).
2000
Philips Semiconductors
Preliminary specification
1394 content protection link layer controller
PDI1394L41
12.5.6 interface signals interface directly compatible with wide range microcontrollers, supports both multiplexed non-multiplex access. uses separate RDN, WRN, ALE, chip select lines. There address inputs (HIF A0.HIF data in/out lines D[7:0] [15:0]. upper bits data in/out lines only used when 8/16 mode (HIF16BIT) held HIGH. required clock that synchronous 1394 base clock. control signals will resampled host interface before being used internally. non-multiplex mode (HIF LOW), access through host interface starts when either Typically chip select signal derived from upper address lines (address decode stage), could also connected port avoid need external address decoder very simple systems. When both host interface will start read access cycle, cycle triggered falling edge either RDN, whichever later. multiplex mode (HIF HIGH), access through host interface starts when either RD_N address must presented [7:0] lines, will latched falling edge ALE. data will offered after falling edge ALE. data presented microcontroller. both multiplexed non-multiplexed mode, WAIT used signal controlling that extension current access cycle needed. This allows PDI1394L41 work same address space peripherals with shorter access time. WAIT will remain HIGH minimum duration access cycle. A[8] HIGH, WAIT will extend access cycle 120ns allow shadow register transfer take place. Subsequent access same register which does required A[8] raised, executed much faster. connecting WAIT appropriate input controlling processor, PDI1394L41 mapped memory space with faster devices. PDI1394L41 should mapped memory space with devices that require access faster than A[7:0] used simple demultiplexer. multiplex mode, address AD[7:0] will appear A[7:0] immediately, will remain there until next rising edge ALE.
CS_N
RD_N
WR_N
HIFA7-A0
HIFD15-D8
HIFAD7-AD0
HIF_WAIT
HIF_MUX
HIF16BIT
SV01868
NOTES: line held LOW. extended read cycle implemented holding CS_N RD_N (active) changing only A7-A0 address. After each address stabilizes, wait least tACC read data. extended read cycle used only following read first byte shadow register using transfer mechanism. section Read Accesses (Section 12.5.1). Figure Read Cycle Non-multiplexed
2000
Philips Semiconductors
Preliminary specification
1394 content protection link layer controller
PDI1394L41
CS_N
RD_N
WR_N
HIFA7-A0
HIFD15-D8
HIFAD7-AD0
HIF_WAIT
HIF_MUX
HIF16BIT
SV01867
NOTE: line held LOW. Figure Write Cycle Non-multiplexed
2000
Philips Semiconductors
Preliminary specification
1394 content protection link layer controller
PDI1394L41
tALEH
CS_N
tPWALE tALES
AD7-AD0
ADDR
DATA
ADDR
DATA
A7-A0
LATCHED
LATCHED
HIFD15-D8
DATA
DATA
RD_N
WR_N
HIF_WAIT
HIF_MUX
HIF16BIT
SV01854
NOTE: Second write cycle elongated WAIT signal. Figure Write Cycle Multiplexed
2000
Philips Semiconductors
Preliminary specification
1394 content protection link layer controller
PDI1394L41
tALEH
CS_N
tPWALE tALES
AD7-AD0
ADDR
ADDR
A7-A0
LATCHED
LATCHED
HIFD15-D8
DATA
DATA
RD_N
WR_N HIF_WAIT
HIF_MUX
HIF16BIT
SV01855
Figure Read Cycle Multiplexed
2000
Philips Semiconductors
Preliminary specification
1394 content protection link layer controller
PDI1394L41
tALEH
CS_N
tPWALE tALES
AD7-AD0
ADDR
DATA
ADDR
DATA
A7-A0
LATCHED
LATCHED
RD_N
WR_N
HIF_WAIT
HIF_MUX
HIF16BIT
SV01856
Figure Write Cycle Multiplexed
2000
Philips Semiconductors
Preliminary specification
1394 content protection link layer controller
PDI1394L41
tALEH
CS_N
tPWALE tALES
AD7-AD0
ADDR
ADDR
A7-A0
LATCHED
LATCHED
RD_N
WR_N HIF_WAIT
HIF_MUX
HIF16BIT
SV01857
Figure Read Cycle Multiplexed
2000
Philips Semiconductors
Preliminary specification
1394 content protection link layer controller
PDI1394L41
CS_N
RD_N
WR_N
HIFA7-A0
HIFAD7-AD0
HIF_WAIT
HIF_MUX
HIF16BIT
SV01866
NOTE: line held LOW. Figure Write Cycle Non-multiplexed
2000
Philips Semiconductors
Preliminary specification
1394 content protection link layer controller
PDI1394L41
CS_N
RD_N
WR_N
HIFA7-A0
HIFAD7-AD0
HIF_WAIT
HIF_MUX
HIF16BIT
SV01865
NOTE: line held LOW. Figure Read Cycle Non-multiplexed
2000
Philips Semiconductors
Preliminary specification
1394 content protection link layer controller
PDI1394L41
12.6 Asynchronous Packet Interface
PDI1394L41 provides interface asynchronous data packets through registers host interface. format asynchronous packets specified following sections. 12.6.1 Reading Asynchronous Packet Upon reception packet, packet data stored appropriate receive FIFO, either Request Response FIFO. location packet indicated either RREQQQAV RRSPQAV status being Asynchronous Interrupt Acknowledge (ASYINTACK) register. packet transferred FIFO successive reads Asynchronous Receive Request (RREQ) Asynchronous Receive Response (RRSP) register. packet (the last quadlet) indicated either RREQQLASTQ RRSPQLASTQ ASYINTACK. Attempting read FIFO when either RREQQQAV RRSPQQAV Asynchronous RX/TX interrupt acknowledge, ASYINTACK, register) will result queue read error. 12.6.2 Link Packet Data Formats data formats transmission reception data shown below. transmit format describes expected organization data presented link asynchronous transmit, physical response, isochronous transmit FIFO interfaces. 12.6.2.1 Asynchronous Transmit Packet Formats These sections describe formats which packets need delivered queues (FIFOs) transmission. There four basic formats follows: ITEM FORMAT No-packet packet data USAGE Quadlet read requests Quadlet/block write responses Quadlet write requests Quadlet packet Quadlet read responses Block read requests Block write requests Block read responses Block Packet Lock requests Lock responses Asynchronous streams Unformatted transmit Concatenated self-ID packets TRANSACTION CODE (tCode) Bhex Ahex Ehex
Each packet format uses several fields (see names descriptions below). More information about these fields (not format) found 1394 specification. Grey fields reserved should zero values.
2000
Philips Semiconductors
Preliminary specification
1394 content protection link layer controller
PDI1394L41
Table Asynchronous Transmit Fields
Field Name tLabel Description This field indicates speed which this packet sent. 00=100 Mbs, 01=200 Mbs, 10=400 Mbs. undefined This field transaction label, which used pair response packet with corresponding request packet. tLabels also used identifiers associate Link data confirmation (see 12.6.2.13) with corresponding request, response, asynchronous stream packet. Only value retryX supported. transaction code this packet. Contains node value. concatenation these field addresses quadlet destination node's address space. Response code write response packet. rCode Meaning Node successfully completed requested operation. Reserved Resource conflict detected responding agent. Request retried. Hardware error. Data available. Field within request packet header contains unsupported invalid value. Address location within specified node accessible. 8-Fh Reserved channel allocated from isochronous manager register CHANNELS_AVAILABLE. Used only Asynchronous stream transmit fields. Values supplied, appropriate user fields supplied appropriate, user. responses, priority 0000 fair arbitration used 0001 priority arbitration used, allowed 1394a supplement IEEE 1394-1995. quadlet write requests quadlet read responses, this field holds data transferred. number bytes requested block read request. number bytes data transmitted this packet tCode indicates lock transaction, this specifies actual lock action performed with data this packet. data sent. dataLength=0, data should written into FIFO this field. Regardless destination source alignment data, first byte block must appear high order byte first quadlet. dataLength zero, then zero-value bytes added onto packet guarantee that whole number quadlets sent.
tCode DestinationID DestinationOffsetHigh DestinationOffsetLow rCode
channel priority Quadlet data Data length dataLength extendedTcode block data
padding
2000
Philips Semiconductors
Preliminary specification
1394 content protection link layer controller
PDI1394L41
12.6.2.2 No-data Transmit no-data transmit formats shown Figures first quadlet contains packet control information. second third quadlets contain 16-bit destination either 48-bit, quadlet aligned destination offset (for requests) response code (for responses).
tLabel
tCode
priority
destinationID
destinationOffsetHigh
destinationOffsetLow
SV01080
Figure Quadlet Read Request Transmit Format
tLabel tCode priority
destinationID
rCode
SV01081
Figure Quadlet/Block Write Response Packet Transmit Format
2000
Philips Semiconductors
Preliminary specification
1394 content protection link layer controller
PDI1394L41
12.6.2.3 Quadlet Transmit Three quadlet transmit formats shown below. these figures: first quadlet contains packet control information. second third quadlets contain 16-bit destination either 48-bit quadlet-aligned destination offset (for requests) response code (for responses). fourth quadlet contains quadlet data read response write quadlet request formats, upper bits contain data length block read request format.
tLabel
tCode
priority
destinationID
destinationOffsetHigh
destinationOffsetLow
quadlet data
SV01082
Figure Quadlet Write Request Transmit Format
tLabel
tCode
priority
destinationID
rCode
quadlet data
SV01083
Figure Quadlet Read Response Transmit Format
2000
Philips Semiconductors
Preliminary specification
1394 content protection link layer controller
PDI1394L41
tLabel
tCode
priority
destinationID
destinationOffsetHigh
destinationOffsetLow
data length
SV01084
Figure Block Read Request Transmit Format
2000
Philips Semiconductors
Preliminary specification
1394 content protection link layer controller
PDI1394L41
12.6.2.4 Block Transmit block transmit format shown below, this generic format reads writes. first quadlet contains packet control information. second third quadlets contain 16-bit destination node either 48-bit destination offset (for requests) response code reserved data (for responses). fourth quadlet contains length data field extended transaction code (all zeros except lock transaction). block data, any, follows extended transaction code.
tLabel
tCode
priority
destinationID destinationOffsetLow dataLength
destinationOffsetHigh
extendedTcode
Block data
padding needed)
SV01085
Figure Block Packet Transmit Format
tLabel tCode priority
destinationID
rCode
dataLength
extendedTcode
Block data
padding needed)
SV01086
Figure Block Read Lock Response Transmit Format
2000
Philips Semiconductors
Preliminary specification
1394 content protection link layer controller
PDI1394L41
12.6.2.5 Unformatted Transmit unformatted transmit format shown Figure first quadlet contains packet control information. remaining quadlets contain data that transmitted without formatting bus. appended packet, data first quadlet sent. This used send configuration Link-on packets. Note that bit-inverted check quadlet must included FIFO since Link core will generate
tLabel
1110
priority
unformatted packet data
SV01087
Figure Unformatted Transmit Format 12.6.2.6 Asynchronous Stream Transmit PDI1394L41 supports asynchronous stream specified IEEE1394.a. asynchronous stream packet format shown below. first quadlet contains packet control information. second quadlet contains datalength, tag, channel number, synchronization code. third quadlet contains datalength quadlets. datalength zero empty asynchronous stream packets.
dataLength tLabel channel 1110 1010 priority
Block data
padding needed)
SV01050
Figure Asynchronous Stream Packet Transmit Format When packet conforming this format written either asynchronous transmit FIFO, asynchronous stream packet (identical cable isochronous packet) will transmitted during asynchronous phase cycle.
2000
Philips Semiconductors
Preliminary specification
1394 content protection link layer controller
PDI1394L41
12.6.2.7 Asynchronous Receive Packet Formats This section describes asynchronous receive packet formats. Four basic asynchronous data packet formats confirmation format exist:
Table Asynchronous Data Packet Formats
ITEM FORMAT No-packet packet data USAGE Quadlet read requests Quadlet/block write responses Quadlet write requests Quadlet packet Quadlet read responses Block read requests Block write requests Block Packet Block read responses Lock requests Lock responses Self-ID packet Confirmation packet Concatenated self-ID packets Confirmation packet transmission TRANSACTION CODE Bhex Ehex
Each packet format uses several fields. More information about most these fields found 1394 specification.
Table Asynchronous Receive Fields
Field Name destinationID tLabel Description This field concatenation busNumbers ones "local bus") nodeNumbers ones broadcast) this node. This field transaction label, which used pair response packet with corresponding request packet. tLables also used identifiers associate Link data confirmation (see 12.6.2.13) with corresponding request, response, asynchronous stream packet. retry code received packet; 1394 specification. transaction code this packet. priority level this packet (0000 cable environment). This node sender this packet. concatenation these field addresses quadlet this node's address space. Response code received packet; 1394 specification. quadlet write requests quadlet read responses, this field holds data received. number bytes data received block packet. tCode indicates lock transaction, this specifies actual lock action performed with data this packet. data received. dataLength=0, data will written into FIFO this field. Regardless destination source alignment data, first byte block will appear high order byte first quadlet. dataLength zero, then zero-value bytes added onto packet guarantee that whole number quadlets sent. Unsolicited response bit. This received response unsolicited. This field contains acknowledge code that link layer returned sender received packet. packets that need acknowledged (such broadcasts) field contains acknowledge value that would have been sent acknowledge been required. values this field listed Table (they also found IEEE 1394 standard). This field used asynchronous streams. 0000 Reserved. 0001 packet 0010-1100 Reserved. 1101 Data error and/or block size mismatch have been detected. 1110-1111 Reserved.
tCode priority sourceID destinationOffsetHigh, destinationOffsetLow rCode quadlet data dataLength extendedTcode block data padding ackSent
status
2000
Philips Semiconductors
Preliminary specification
1394 content protection link layer controller
PDI1394L41
Table Acknowledge codes
Code 0001 0010 0100 0101 0110 1101 Name ack_complete ack_pending ack_busy_X ack_busy_A ack_busy_B ack_data_error Description node successfully accepted packet. packet request subaction, destination node successfully completed transaction response subaction shall follow. node successfully accepted packet. packet request subaction, response subaction will follow later time. This code shall returned response subaction. packet could accepted. destination transaction layer accept packet retry subaction. packet could accepted. destination transaction layer will accept packet when node busy during next occurrence retry phase packet could accepted. destination transaction layer will accept packet when node busy during next occurrence retry phase node could accept block packet because data field failed check, because length data block payload match length contained dataLength field. This code shall returned packet that does have data block payload. field request packet header unsupported incorrect value, invalid transaction attempted (e.g., write read-only address). This revision Link will generate other acknowledge codes, receive them from newer (1394 links. that case, these values will show here.
1110 0000, 0011, 0111 1100, 1111
ack_type_error reserved
2000
Philips Semiconductors
Preliminary specification
1394 content protection link layer controller
PDI1394L41
12.6.2.8 No-data Receive no-data receive formats shown below. first quadlet contains destination node rest packet header. second third quadlet contain 16-bit source either 48-bit, quadlet-aligned destination offset (for requests) response code (for responses). last quadlet contains packet reception status.
3130
destinationID
tLabel
tCode
priority
sourceID
destinationOffsetHigh
destinationOffsetLow
ackSent
SV00257
Figure Quadlet Read Request Receive Format
destinationID tLabel tCode priority
sourceID
rCode
ackSent
SV00258
Figure Write Response Receive Format
2000
Philips Semiconductors
Preliminary specification
1394 content protection link layer controller
PDI1394L41
12.6.2.9 Quadlet Receive quadlet receive formats shown below. first quadlet contains destination node rest packet header. second third quadlets contain 16-bit source either 48-bit, quadlet-aligned destination offset (for requests) response code (for responses). fourth quadlet quadlet data read responses write quadlet requests, data length reserved block read requests. last quadlet contains packet reception status.
destinationID
tLabel
tCode
priority
sourceID
destinationOffsetHigh
destinationOffsetLow
quadlet data
ackSent
SV00259
Figure Quadlet Write Request Receive Format
destinationID
tLabel
tCode
priority
sourceID
rCode
quadlet data
ackSent
SV00260
Figure Quadlet Read Response Receive Format
2000
Philips Semiconductors
Preliminary specification
1394 content protection link layer controller
PDI1394L41
destinationID
tLabel
tCode
priority
sourceID
destinationOffsetHigh
destinationOffsetLow
data length
ackSent
SV00261
Figure Block Read Request Receive Format
2000
Philips Semiconductors
Preliminary specification
1394 content protection link layer controller
PDI1394L41
12.6.2.10 Block receive block receive format shown below. first quadlet contains destination node rest packet header. second third quadlets contain 16-bit sourceID either 48-bit destination offset (for requests) response code reserved data (for responses). fourth quadlet contains length data field extended transaction code (all zeros except lock transactions). block data, any, follows extended code. last quadlet contains packet reception status.
destinationID
tLabel
tCode
priority
sourceID
destinationOffsetHigh
destinationOffsetLow
dataLength
extendedTcode
Block data
padding needed)
ackSent
SV00262
Figure Block Write Lock Request Receive Format
destinationID
tLabel
tCode
priority
sourceID
rCode
dataLength
extendedTcode
Block data
padding needed)
ackSent
SV00263
Figure Block Read Lock Response Receive Format
2000
Philips Semiconductors
Preliminary specification
1394 content protection link layer controller
PDI1394L41
12.6.2.11 Asynchronous Stream Receive Asynchronous streaming receive packet format shown below. first quadlet contains dataLength, tag, Channel number source identification, synchronization information. following quadlets contain (possibly zero) quadlets block information. last quadlet contains transmission speed status information. Asynchronous stream packets placed Receive Response FIFO. Note: fact that asynchronous stream packet type isochronous packet, STRICTISOCH (bit register 0x004) must correct operation.
dataLength chanNum 10102
Block data (possibly zero)
status
SV01052
12.6.2.12 Self-ID packets receive self-ID packet receive formats shown below. first quadlet contains synthesized packet header with tCode (hex). self-ID information, remaining quadlets contain data that received from time reset ends first subaction gap. This concatenation self-ID packets received. Note that bit-inverted check quadlet included Read Request FIFO application must check
3130 11102 00002
self packet data
ackSent
SV00264
Figure Self-ID Receive Format "ackSent" field will either "ACK_DATA_ERROR" non-quadlet-aligned packet received there data overrun, "ACK_COMPLETE" entire string self-ID packets received.
11102 00002
packet first quadlet
SV00265
Figure Packet Receive Format packets, there single following quadlet which first quadlet packet. check quadlet already been verified included.
2000
Philips Semiconductors
Preliminary specification
1394 content protection link layer controller
PDI1394L41
12.6.2.13 Link data confirmation formats After request, response, asynchronous stream packet transmitted, asynchronous transmitter assembles Link data confirmation (see Figure which used confirm transmission higher layers. Packets transmitted from Transmit Request FIFO confirmed confirmation written into Receive Request FIFO packets transmitted from Transmit Response FIFO confirmed confirmation written into Receive Response FIFO. Outgoing packets their confirmations associated their tLabels. user's responsibility assure uniqueness active tLabels.
3130
tLabel
1000
conf
SV01051
Figure Request response confirmation format
Table Confirmation codes
CODE1 DESCRIPTION Non-broadcast packet transmitted; addressed node returned acknowledge (transaction complete). Broadcast packet transmitted non-broadcast packet transmitted; addressed node returned acknowledge complete (transaction complete). Non-broadcast packet transmitted; addressed node returned acknowledge pending. Retry limit exceeded; destination node hasn't accepted non-broadcast packet within maximum number retries (transaction complete). Acknowledge data error received (transaction complete).
Acknowledge type error received (transaction complete). NOTE: other codes reserved.
12.7 Interrupts
PDI1394L41 provides single interrupt line (HIF INTN) connection host controller. Status indications from five major areas device collected ORed together activate INTN. Status from four major areas device collected five status registers; LNKPHYINTACK, ITXINTACK, IRXINTACK, ASYINTACK RDI. this level, each individual status enabled generate chip-level interrupt activating INTN. determining source chip-level interrupt, major area device generating interrupt indicated lower bits GLOBCSR register. These bits non-latching Read-Only status bits need acknowledged. acknowledge clear standing interrupt, LNKPHYINTACK, ITXINTACK, IRXINTACK, ASYINTACK causing interrupt status written logic `1'; Note: Writing value effect. 12.7.1 Determining Clearing Interrupts When responding interrupt event generated PDI1394L41, operating polled mode, first register examined register. Since addition register 0x0b0), will necessary first interrogate register independent GLOBCSR register order locate source interrupt. Embedded software should built perform this function. recommended that this interrogation take place BEFORE read GLOBCSR register accomplished. reason this added step stems from fact that none other link registers accurately read link power-down mode. attempt read GLOBCSR made during link power-down, quadlet will read, quadlet data will contents GLOBCSR. Once been determined that interrupt result setting register, GLOBCSR register should tested next. least significant nibble contains interrupt status bits from general sections device; link layer controller, transmitter, receiver, asynchronous transceiver. bits GLOBCSR[3:0] self clearing status bits. They represent logical enabled interrupt status bits their section Link Layer Controller. Once interrupt, status detected GLOBCSR, appropriate interrupt status register needs read, Interrupt Hierarchy diagram more detail. After interrupt indications dealt with appropriate interrupt status register, interrupt status indication will automatically clear GLOBCSR. interrupt status bits various interrupt status registers latching unless otherwise noted.
2000
Philips Semiconductors
Preliminary specification
1394 content protection link layer controller
PDI1394L41
12.7.1.1 Interrupt Hierarchy
INT_N
ASYTX/RX
ITXINT IRXINT
LNKPHYINT GLOBCSR (0x018)
PHYRST ITBADFMT ATBADFMT SNT_REJ HDRERR TCERR CYTMOUT CYSEC CYSTART AUTH TIMER CMDRST FAIRGAP ARBGAP CYDONE CYPEND CYLOST PHYINT PHYRRX LNKPHYINTACK (0x008)
CRCERR CIPTAGFLT RCVBP SQOV ITXFULL ITXEMPTY SYTOVF IRO/E IREMI IR100LFT IR256LFT IR512LFT IRXFULL IRXEMPTY FSYNC SEQERR
IRXINTACK (0x04C)
ERROR ITO/E TRMBP DBCERR INPERR DISCARD ITEMI IT100LFT IT256LFT IT512LFT TRMSYT ITXINTACK (0x02C)
RREQQFULL SIDQAV RRSPQLASTQ RREQQLASTQ RRSPQRDERR RREQQRDERR RRSPQQAV RREQQQAV TIMEOUT RCVDRSP TRSPQFULL TREQQFULL TRSPQWRERR TREQQWRERR TRSPQWR TREQQWR RRSPQFULL
ASYINTACK (0x0A0)
SV01858
NOTE: read register (0xB0) should done before looking interrupt GLOBCSR register. Figure Interrupt Hierarchy
13.0 REGISTER
Registers bits (quadlet) wide accesses always done quadlet basis. This means that possible write just lower bits, leave other bits unaffected (see Section 12.5.2 more information). values written undefined fields/bits ignored thus DON'T CARE. full bitmap registers listed Table meaning shading cell values follows: bit/field with name written dark shading reserved used. bit/field with name light shading READ ONLY (status) bit/field. value written bottom writable (control) default value after power-on-reset.
Table Full Bitmap Registers (consists four tables shown following pages)
2000
2000
REGISTER ADDRESS 0x008 0x020 0x018 0x014 0x010 0x000 0x00C 0x024 IDREG CYCTIMER 0x01C LNKCTL 0x004 ITXHQ2 ITXHQ1 PHYACS GLOBCSR ITXPKCTL LNKPHYINTACK LNKPHYINTE TMGOSTOP TMCONT TMBRE BSYCTRL WRPHY RCVSELFID RDPHY IDVALID AUDIO TXAP_CLK CYCLE_SECONDS TxENABLE RxENABLE PHYRGAD DATAINV LTLEND AUTH TIMER TRDEL EAUTH ETIMER PHYRGDATA NODE ENOUTAV2 ENOUTAV1 DIRAV1 ECMDRST EFAIRGAP EARBGAP EPHYINT EPHYRRX EPHYRST CMDRST FAIRGAP ARBGAP PHYINT PHYRRX PHYRST STRICTISOCH CYMASTER EITBADFMT EATBADFMT ESNT_REJ EHDRERR ETCERR ECYTMOUT ECYSEC ASYTX/RX ITXINT IRXINT LNKIPHYINT ECYSTART ECYDONE ECYPEND ECYLOST ITBADFMT ATBADFMT SNT_REJ HDRERR TCERR CYTMOUT CYSEC CYSTART CYDONE CYPEND CYLOST TxRDY ROOT BUSYFLAG CYSOURCE CYTMREN CYCLE_NUMBER
0x028
0x02C
Philips Semiconductors
ITXINTACK
ITXINTE
0x030
1394 content protection link layer controller
PRELOAD MAXBL EASYTX/RX EITXINT EIRXINT ELNKPHYINT PHYRXAD ENXTMSTP SYT_DELAY EN_ITX CYCLE_OFFSET PHYRXDATA EN_FS RST_ITX
ERROR
ERROR
PART CODE
EITO/E
ITO/E
EITEMI
ITEMI
EIT100LFT
IT100LFT
EIT256LFT
IT256LFT
EIT512LFT
IT512LFT
ETRMSYT
TRMSYT
ETRMBP
TRMBP
VERSION CODE
EDBCERR
DBCERR
EINPERR
INPERR
ATACK
EDISCARD
DISCARD
EITXFULL
ITXFULL
PDI1394L41
Preliminary specification
SV01859
EITXEMPTY
ITXEMPTY
Philips Semiconductors
Preliminary specification
1394 content protection link layer controller
PDI1394L41
REGISTER ADDRESS ITXCTL 0x034
CPHR_EN
ODD/EVEN ITXM5AV EN_FS RCVBP ERCVBP ODD/EVEN IRXM5AV
CHANNEL
ITXM100LFT
ITXM256LFT
ITXM512LFT
ITXMEM 0x038
ITXMAF
<RESERVED> 0x03C
RXAP_CLK
DIS_TSC
RMVUAP
ITXMF
EN_IRX
IRXPKCTL 0x040 IRXHQ1 0x044
SNDIMM
SPAV
BPAD
IRXHQ2 0x048
IR100LFT
IR256LFT
IR512LFT
SEQERR
CRCERR
IRXFULL
SYTOVF
IRXINTACK 0x04C
IRXEMPTY
CIPTAGFLT
FSYNC
IREMI
IRO/E
ESYTOVF IRXINTE 0x050
EIR100LFT
EIR256LFT
EIR512LFT
EIRXFULL
EIRXEMPTY
ESEQERR
ECRCERR
ECIPTAGFLT
EIREMI
EFSYNC
EIRO/E
IRXCTL 0x054 DECPHR_EN
IRXM100LFT IRXM256LFT IRXM512LFT
IRXMAF
IRXMEM 0x058
<RESERVED> 0x05C <RESERVED> 0x07C
IRXMF
SV01860
2000
IRXME
CHANNEL
ESQOV
SQOV
RST_IRX
ITXME
Philips Semiconductors
Preliminary specification
1394 content protection link layer controller
PDI1394L41
DIS_BCAST
REGISTER ADDRESS ASYCTL 0x080
ARXRST
ATXRST
ARXALL
MAXRC
ASYMEM 0x084
TRSPQIDLE
TREQQIDLE
RRSPQAF
RRSPQ5AV
RREQQAF
RREQQ5AV
TRSPQ5AV
TREQQ5AV TRSPQWR ETRSPQWR
TREQQAF
TRSPQAF
RREQQE
RREQQF
RRSPQE
RRSPQF
TX_RQ_NEXT 0x088
FIRST/MIDDLE QUADLET PACKET TRANSMITTER REQUEST QUEUE (WRITE ONLY)
TX_RQ_LAST 0x08C
LAST QUADLET PACKET TRANSMITTER REQUEST QUEUE (WRITE ONLY)
TX_RP_NEXT 0x090
FIRST/MIDDLE QUADLET PACKET TRANSMITTER RESPONSE QUEUE (WRITE ONLY)
TX_RP_LAST 0x094
LAST QUADLET PACKET TRANSMITTER RESPONSE QUEUE (WRITE ONLY)
RREQ 0x098
QUADLET PACKET FROM RECEIVER REQUEST QUEUE (TRANSFER REGISTER)
RRSP 0x09C
QUADLET PACKET FROM RECEIVER RESPONSE QUEUE (TRANSFER REGISTER)
RREQQRDERR
RRSPQRDERR
RREQQLASTQ
RREQQFULL
RRSPQLASTQ
TREQQWRERR
RRSPQFULL
RREQQQAV
TREQQFULL
TRSPQWRERR
RRSPQQAV
TRSPQFULL
0x0A0
ERRSPQFULL
ERREQQFULL
ERRSPQLASTQ
ERREQQLASTQ
ERRSPQRDERR
ERREQQRDERR
ERRSPQQAV
TIMEOUT
ASYINTACK
ETRSPQFULL
ETREQQFULL
ETRSPQWRERR
ETREQQWRERR
ERREQQQAV
0x0A4
<RESERVED> 0x0A8 0x0AC
ESIDQAV
ASYINTE
ERCVDRSP
LPSTAT
SWPD
0x0B0
ESCA
ELOA
ESCI
EPLI
ETREQQWR
ETIMEOUT
TREQQWR
RCVDRSP
SIDQAV
TREQQE
TREQQF
TRSPQE
TRSPQF
SV01861
2000
Philips Semiconductors
Preliminary specification
1394 content protection link layer controller
PDI1394L41
REGISTER ADDRESS
<RESERVED> 0x0B4 0x0F0
SHADOW_REG 0x0F4
byte
byte
byte
byte
INDADDR 0x0F8
RESERVED
INDADDR
INDDATA 0x0FC
WINDOW INDIRECT QUADLET POINTED INDADDR
SV01033
2000
Philips Semiconductors
Preliminary specification
1394 content protection link layer controller
PDI1394L41
13.1 Link Control Registers
13.1.1 Register (IDREG) Base Address: 0x000 register automatically updated attached with proper Node after completion reset.
3130
NODE
PART CODE
VERSION CODE
SV00915
Reset Value 0xFFFF0202 31.22: 10-bit number that used with Node source address outgoing packets used accept reject incoming packets. This field reverts `1's (0x3FF) upon reset. 21.16: NODE Used conjunction with source address outgoing packets used accept reject incoming packets. This register auto-updates with node assigned after 1394 Tree-ID sequence. 15.8: PART CODE: "02" designates PDI1394L41. 7.0: VERSION CODE: "02" shows this revision level this part.
13.1.2 General Link Control (LNKCTL) Base Address: 0x004 General Link control register used program Link Layer isochronous transceiver, well overall link transceiver. also provides general link status.
STRICTISOCH RCVSELFID CYMASTER CYSOURCE CYTMREN BUSYFLAG TxENABLE RxENABLE
IDVALID
TxRDY ROOT
BSYCTRL
DATAINV LTLEND
ATACK
SV00892
Reset Value 0x46000002 IDValid (IDVALID): When equal one, PDI1394L41 accepts packets addressed this node. This automatically after selfID complete node updated. Receive Self (RCVSELFID): When asserted, self-identification packets, generated each device bus, during initialization received placed into asynchronous request queue single packet. also enables reception configuration packets asynchronous request queue. 29.27: Busy Control (BSYCTRL): These bits control what busy status chip returns incoming packets. field defined below: protocol requested received packet (either dual phase single phase) RESERVED RESERVED single phase retry protocol protocol requested packet, always send busy (for packets) RESERVED RESERVED single phase retry protocol, always send busy Transmitter Enable (TxENABLE): When this set, link layer transmitter will arbitrate send packets. Receiver Enable (RxENABLE): When this set, link layer receiver will receive respond packets. Data Invariant (DATAINV) refers byte ordering data being presented Link through host interface (HIF) port handling address data lines link chip. When DATAINV Link address invariant mode. When DATAINV Link data invariant mode. This only important LTLEND (Little Endian) (1), otherwise ignored. Interpretation address data information varies with settings these bits with data format being presented. section Little Endian Modes more information (Section 12.5.4).
2000
Philips Semiconductors
Preliminary specification
1394 content protection link layer controller
PDI1394L41
3.0:
Little Endian (LTLEND): Refers state endianess data address lines connected 'L41. This reflects state AV2ERR0/LTLEND during power reset. state this read during reset that state latched into this position. When LTLEND chip receive ENDIAN address data host interface (HIF). When LTLEND Link chip will receive LITTLE ENDIAN oriented data address information. this (1), state DATAINV will also become important determination data positions internal link registers. section Little Endian Modes more information (Section 12.5.4). Reset Transmitter (RSTTx): When one, this synchronously resets transmitter within link layer. Reset Receiver (RSTRx): When one, this synchronously resets receiver within link layer. Reset PHY-Link interface (RPL): Resets PHY-Link interface accordance with 1394a requirements. Note: This automatically resets when interface reset operation been completed. PHY-Link reset operation occurs very quickly, reading this accurately usually possible. Before asserting bit, SWPD setting high, user should assure that link chip following state operation: isochronous transmit FIFO receiving data transmission isochronous transmitter disabled asynchronous packets being generated transmission Both ASYNC request response queues empty Strict Isochronous (STRICTISOCH): Used accept reject isochronous packets sent outside specified isochronous cycles (between Cycle Start subaction gap). rejects packets sent outside specified cycles, accepts isochronous packets sent outside specified cycle. Cycle Master (CYMASTER): When asserted PDI1394L41 attached root (ROOT cycle_count field cycle timer register increments, transmitter sends cycle-start packet. Cycle Master function will disabled cycle timeout detected (CYTMOUT LNKPHYINTACK). restart Cycle Master function such case, first reset CYMASTER, then again. Cycle Source (CYSOURCE): When asserted, cycle_count field increments cycle_offset field resets each positive transition CYCLEIN. When deasserted, cycle count field increments when cycle_offset field rolls over. Cycle Timer Enable (CYTIMREN): When asserted, cycle offset field increments. When deasserted, Cycle Timer Register (0x010, CYCTM) used general read write register Host Interface Firmware testing. Transmitter Ready (TxRDY): transmitter idle ready. Root (ROOT): Indicates this device root bus. This automatically updates after self_ID phase. Busy Flag (BUSYFLAG): type busy acknowledge which will sent next time acknowledge required. Busy Busy (only meaningful during dual-phase busy/retry operation). acknowledge received (ATACK): last acknowledge received transmitter response packet sent from transmit-FIFO interface while selected (diagnostic purposes).
2000
Philips Semiconductors
Preliminary specification
1394 content protection link layer controller
PDI1394L41
13.1.3 Link /Phy Interrupt Acknowledge (LNKPHYINTACK) Base Address: 0x008 Link/Phy Interrupt Acknowledge register indicates various status error conditions Link which programmed generate interrupt. interrupt enable register (LNKPHYINTE) mirror this register. Acknowledgment interrupt accomplished writing this register that set. This action reset indication `0'. Writing that already will have effect register.
ITBADFMT ATBADFMT SNT_REJ HDRERR TCERR CYTMOUT CYSEC CYSTART CYDONE CYPEND CYLOST AUTH TIMER CMDRST FAIRGAP ARBGAP PHYINT PHYRRX PHYRST
SV01040
Reset Value 0x00000000 Authentication Acceleration Done (AUTH DN). authentication accelerator finished operation. Check status `Valid' Authentication Accelerator indirect register. Timer (TIMER): When TIMER this indicates that timer counted down zero. This interrupt occur only once occur repeatedly, according setting TMCONT TIMER register. Acknowledge this interrupt writing back into this position. Command Reset Received (CMDRST): write request RESET-START been received. Fair (FAIRGAP): serial been idle fair-gap time (called subaction IEEE 1394 specification). Arbitration Reset (ARBGAP): serial been idle arbitration reset gap. Chip (PHYINT): chip signaled interrupt through interface after reset reset. This becomes active following reasons detected loop bus, cable power fallen below minimum voltage, arbitration state machine timed-out usually indicative loop, cable been disconnected. Typically, recognition notification above events requires between microseconds; therefore, this instantaneously set. Register Information Received (PHYRRX): register been transferred Physical Layer device into Link. Reset Started (PHYRST): Phy-layer reconfiguration started. This interrupt clears valid bit. (Called Reset IEEE 1394 specification). Async queues will flushed during reset. Isochronous Transmitter Stuck (ITBADFMT): transmitter detected invalid data transmit-FIFO interface when isochronous transmit FIFO selected. Reset isochronous transmitter clear. Asynchronous Transmitter Stuck (ATBADFMT): transmitter expected start async packet queue, found other data (out sync with user). Reset asynchronous transmitter clear. Busy Acknowledge Sent Receiver (SNT_REJ): receiver forced send busy acknowledge packet addressed this node because receiver response/request FIFO overflowed. Header Error (HDRERR): receiver detected header error incoming packet that have been addressed this node. Transaction Code Error (TCERR): transmitter detected invalid transaction code data transmit FIFO interface. Cycle Timed (CYTMOUT): ISOCH cycle lasted more than 125µs from Cycle-Start Fair Gap: Disables cycle master function Cycle Second incremented (CYSEC): cycle second field cycle-timer register incremented. This occurs approximately every second when cycle timer enabled. Cycle Started (CYSTART): transmitter sent receiver received cycle start packet. Cycle Done (CYDONE): fair been detected after transmission reception cycle start packet. This indicates that isochronous cycle over; Note: Writing value effect. Cycle Pending (CYPEND): Cycle pending asserted when cycle timer offset zero (rolled over reset) stays asserted until isochronous cycle ended. Cycle Lost (CYLOST): cycle timer rolled over twice without reception cycle start packet. This only occurs when cycle master asserted.
2000
Philips Semiconductors
Preliminary specification
1394 content protection link layer controller
PDI1394L41
13.1.4 Link Interrupt Enable (LNKPHYINTE) Base Address: 0x00C This register mirror Link/Phy Interrupt Acknowledge (LNKPHYINTACK) register. Enabling interrupt accomplished writing corresponding interrupt desired. This register enables interrupts described Link /Phy Interrupt Acknowledge register (LNKPHYINTACK) description. bits enables that function create interrupt. zero disables interrupt, however status readable Link /Phy Interrupt Acknowledge register.
EITBADFMT EATBADFMT ESNT_REJ EHDRERR ETCERR ECYTMOUT ECYSEC ECYSTART ECYDONE ECYPEND ECYLOST EAUTH ECMDRST EFAIRGAP EARBGAP EPHYINT EPHYRRX EPHYRST
ETIMER
SV00894
Reset Value 0x00000000 Bits 21.0 interrupt enable bits Link/Phy Interrupt Acknowledge (LNKPHYINTACK). 13.1.5 Cycle Timer Register (CYCTM) Base Address: 0x010 Cycle Timer Register operation controlled Cycle Timer Enable (CYTMREN) Link Control Register (LNKCTL, 0x004). Cycle Timer Register disabled, used general read write register Host Interface Firmware testing.
3130
CYCLE_SECONDS
CYCLE_NUMBER
CYCLE_OFFSET
SV00276
Reset Value 0x00000000 31.25: Seconds count: 1-Hz cycle timer counter. 24.12: Cycle Number: 8kHz cycle timer counter. 11.0: Cycle Offset: 24.576MHz cycle timer counter.
2000
Philips Semiconductors
Preliminary specification
1394 content protection link layer controller
PDI1394L41
13.1.6 Register Access (PHYACS) Base Address: 0x014 This register provides access internal registers Phy. There special considerations when reading writing this register. When reading register, address register written PHYRGAD field with RDPHY set. data will valid when PHYRRX (LNKPHYINTACK register set. Once this happens register data available PHYRXDATA, address register just read also available PHYRXAD fields. When writing register, address register written PHYRGAD field data written register PHYRGDATA, along with WRPHY being set. Once write complete, WRPHY will cleared. write Read/Write command until previous been completed. After Self-ID phase, register will read automatically.
RDPHY WRPHY PHYRGAD PHYRGDATA PHYRXAD PHYRXDATA
SV00277
Reset Value 0x00000000 Read Chip Register (RDPHY): When asserted, PDI1394L41 sends read register request with address equal interface. This cleared when request sent. Write Chip Register (WRPHY): When asserted, PDI1394L41 sends write register request with address equal interface. This cleared when request sent. 27.24: Chip Register Address (PHYRGAD): This address Phy-chip register that accessed. 23.16: Chip Register Data (PHYRGDATA): This data written Phy-chip register indicated 11.8: Chip Register Received Address (PHYRXAD): Address register from which Data came. 7.0: Chip Register Received Data (PHYRXDATA): Data from register addressed 13.1.7 Global Interrupt Status Control (GLOBCSR) Base Address: 0x018 This register level interrupt status register. external interrupt line set, this register will indicate which major portion Link generated interrupt. There interrupt acknowledge required this level. These bits auto clear when interrupts appropriate section device cleared disabled. Control transceiver also provided this register. Bits used identify which internal modules currently generating interrupt. After identifying module, appropriate register that module must read determine exact cause interrupt. timer available implementation higher level protocols such AV/C HAVi. timer started stopped, automatically reloads with (TIMLOAD 100ms (TIMLOAD When time expired, interrupt will generated through TIMER (Bit LNKPHYINTACK 0x008). normal timer mode (TIMMODE timer will generate interrupt, reload restart every time expires, until TIMRNSTP cleared. reset timer mode (TIMMODE even when already running timer will reload with restart automatically after reset. another reset occurs before timer expires, timer will again reload restart. interrupt will generated until timer expires.
EASYTX/RX ENOUTAV2 ENOUTAV1
ELNKPHYINT
ASYTX/RX
LNKPHYINT
DIRAV1
EIRXINT
EITXINT
SV01024
NOTES There more than interrupt source active same time. INT_N signal (pin remains active long there least more enabled active interrupt status bit. Reset Value 0x00010000 Enable output AVPORT2: enables AVPORT2 output. sets 3-State condition port. 3-State condition port used input unused output according state DIRAV1 (bit 16). Enable output AVPORT1: enables AVPORT1 output. sets 3-State condition port. 3-State condition port used input unused output according state DIRAV1 (bit 16).
2000
IRXINT
ITXINT
Philips Semiconductors
Preliminary specification
1394 content protection link layer controller
PDI1394L41
Direction AVPORT1 (DIRAV1): enables AVPORT1 transmitter, thus AVPORT1 pins inputs. configures AVPORT1 receiver, AVPORT1 pins outputs this configuration. configuration AVPORT2 pins opposite AVPORT1 pins. When AVPORT1 transmit, AVPORT2 receives vice versa. Enables generation external interrupt asynchronous transmitter receiver module (ASYTX/RX, when (1). Disables such interrupts when clear (regardless ASYINTE contents). Enables generation external interrupt isochronous transmitter module (ITXINT, when (1). Disables such interrupts when clear (regardless ITXINTE contents). Enables generation external interrupt isochronous receiver module (IRXINT, when (1). Disables such interrupts when clear (regardless IRXINTE contents). Enables generation external interrupt general link/phy module (LKPHYINT, when (1). Disables such interrupts when clear (regardless LNKPHYINTE contents). Asynchronous Transmitter/Receiver Interrupt (ASYITX/RX): Interrupt source Asynchronous Transmitter/ Receiver Interrupt Acknowledge/Source register. Transmitter Interrupt (ITXINT): Interrupt source Transmitter Interrupt Acknowledge/Source register. Receiver Interrupt (IRXINT): Interrupt source Receiver Interrupt Acknowledge/Source register. Link-Phy Interrupt (LNKPHYINT): Interrupt source Link Interrupt Acknowledge register.
13.1.8 Timer (TIMER) Base Address: 0x01C
TMGOSTOP TMCONT TMBRE
PRELOAD
SV01096
Reset Value 23.0:
TMGOSTOP: Timer Go/Stop, when start timer; when stop timer. TMCONT: Timer Continuous, when continuously operate timer; when operate timer timing cycle, then stop. TMBRE: Timer Reset Enable, when start timer beginning reset; when start timer from TMGOSTOP setting. Timer preload bits. Load number into timer preload bits with most significant higher numbered position; least significant timer preload register basic timing unit 1/(2*CLK25) 80.14 nanoseconds. maximum timer time-out about 1.34 seconds ((2^24)-1 units). timer uses preload value inputted host into bits through this register. preload value placed actual timer/counter (invisible outside world) this value decremented each unit time. timer eventually counts down zero then sets TIMER interrupt flag register 0x008, LINKPHYINTACK (assuming interrupt enabled ETIMER bit). Depending setting TMCONT this register, timer preload value automatically reloaded into timer/counter (when TMCONT with timing cycle automatically re-starting, timer will simply interrupt stop (when TMCONT TMBRE adds mode timer operation which starts timing automatically start 1394 reset. When TMBRE (1), TMGOSTOP function disabled; TMCONT function still available. NOTE: When TMCONT failing acknowledge TIMER interrupt effect starting/restarting timer; interrupt acknowledged (bit reset), timer will continue time restart.
2000
Philips Semiconductors
Preliminary specification
1394 content protection link layer controller
PDI1394L41
13.2 (Isochronous) Transmitter Receiver Registers
13.2.1 Isochronous Transmit Packing Control Status (ITXPKCTL) Base Address: 0x020 This register allows user appropriate packets from data entered into interface. packing control parameters (TRDEL, MAXBL, DBS, QPC, SPH) should never changed while transmitter operating. only exception this MAXBL parameter when MPEG-2 packing mode. NOTE: When reset isochronous transmitter necessary, first disable transmitter (place EN_ITX, LOW), wait FIFO empty, then reset transmitter (place RST_ITX, HIGH). This procedure will ensure that data FIFO transmitted before reset.
SYT_DELAY ENXTMSTP TXAP_CLK EN_FS RST_ITX
AUDIO
TRDEL
MAXBL
EN_ITX
SV01862
Reset Value 0x00000001 AUDIO mode bit: When system AUDIO mode. When AUDIO normal time stamping operation assumed. With AUDIO time stamp FSYNC pulse will appended empty packet. pending stamp will held until next non-empty packet sent. FSYNC pulse input transmitting node's link chip, stamp will made. This stamp will point time future dictated DELAY value register 0x020) added current least significant nibble (lsn) cycle number, plus current cycle offset value. This mode automatically increases SYT_DELAY value additional cycles beyond value programmed SYT_DELAY bits. 29.28: TXAP_CLK: Application Clock, default mode, `00' AVxCLK input. This become application clock isochronous Transmitter (and output) programming `01', `10', `11'. programming values are: Input 24.576MHz 12.288MHz 6.144MHz Note that when enabled `01', `10', `11', port that configured transmitter enabled will output this clock signal AVxCLK pin. 27.16: TRDEL: Transport delay. Value added cycle timer produce time stamps. Lower bits upper bits cycle_offset, (Cycle Timer Register, CYCTM). Remainder adds cycle_count field. 15.8: MAXBL: (maximum) number data blocks payload. ENXTMSTP: Enable External time stamp control. Allows external time stamp (generated application) inserted place link-generated time stamp. Defaults link generated time stamp. application must present first byte quadlet-wide time stamp accompanied AVSYNC pulse (and AVVALID) AVPORT. external time stamp quadlet inputted first, followed application data packet. transmitted packet size quadlet larger than original isochronous data packet-Set isochronous transmitter accordingly with CAUTION: Unless valid 61883 time stamp format (based link cycle timer) used, receiving node link chip must equipped with time stamp check disabling function similar DIS_TSC (register 0X040, Please Section 13.2.8 details. 6.5: SYT_DELAY: Programmable delay AV1FSYNC AV2FSYNC. Each cycle cycle, Reset value "00", cycle delay. cycles cycles cycles Reserved EN_ITX: Enable receipt application packets generation isochronous packets every cycle. This also enables Link Layer arbitrate transmitter each subsequent cycle. When this disabled (0), current packet will transmitted then transmitter will shut down. 3.2: packing mode: variable sized packets, most generic mode. fixed size packets. MPEG-2 packing mode. data, just headers transmitted. EN_FS:enable generation/insertion stamps (Time Stamps) header. Reset Isochronous Transmitter (RST_ITX): causes transmitter reset when `1'. order synchronous reset work properly, AVxCLK (from either internal external source) must present ensure that reset kept (programmed) HIGH least duration AVxCLK period. Failure cause application interface this module improperly reset reset all). When reset enabled, bytes will flushed from FIFO transmission will cease immediately. 2000
Philips Semiconductors
Preliminary specification
1394 content protection link layer controller
PDI1394L41
13.2.2 Common Isochronous Transmit Packet Header Quadlet (ITXHQ1) Base Address: 0x024 Transmit Packing Control register holds specification packing scheme used data stream. This information included Common Isochronous Packet (CIP) header quadlet
SV01747
Reset Value 0x00000000 16.23: DBS: Size data blocks from which payload constructed. value represents length quadlets. 14.15: (Fraction Number) encoding number data blocks into which each source packet shall divided 11.13: QPC: Number dummy quadlets append each source packet before divided into data blocks specified size. value must less than less than 2FN. SPH: Indicates that 25-bit CYCbased time stamp inserted before each application packet. 13.2.3 Common Isochronous Transmit Packet Header Quadlet (ITXHQ2) Base Address: 0x028 contents this register copied second quadlet header transmitted with each isochronous packet.
SV00281
Reset Value 0x00000000 29.24: FMT: Value inserted field header. 23.0: FDF/SYT: Value inserted field. When EN_FS Transmit Control Status Register (ITXPKCTL) (=1), lower bits this register replaced stamp rising edge AVFSYNCIN been detected `1's such edge detected since previous packet. upper bits register sent they appear register. When EN_FS Transmit Control Status Register unset (=0), full bits application specified value.
2000
Philips Semiconductors
Preliminary specification
1394 content protection link layer controller
PDI1394L41
13.2.4 Isochronous Transmitter Interrupt Acknowledge (ITXINTACK) Base Address: 0x02C Transmitter Interrupt Control Status register interrupt register transmitter. Bits "auto repair" themselves, i.e. AVLINK will detect situation attempt recover own. host controller still needs clear these interrupts alerted next time.
ERROR ITO/E ITEMI SYTTI EOTI DBCEI IDDSCI PLDSCI ITXMFI ITXMEI IT100LFT IT256LFT IT512LFT TRMSYT TRMBP DBCERR INPERR DISCARD ITXFULL ITXEMPTY
SV01054
Reset Value 0x00000000 ERROR: cipher block encountered unrecoverable error. Proper operation will resumed disabling resetting ITX. ITO/E: odd/even change occurred cipher, write set. ITEMI: This indicates that value used cipher outgoing transmission changed. Bits interrupt acknowledge bits; defined IT100LFT: Interrupt when transmitter queue reaches quadlets from full. IT256LFT: Interrupt when transmitter queue reaches quadlets from full. IT512LFT: Interrupt when transmitter queue reaches quadlets from full. This disabled 0.5K Byte buffer size set. TRMSYT: Interrupt transmission header quadlet TRMBP: Interrupt payload transmission/discard complete. DBCERR: Acknowledge interrupt Data Block Count (DBC) synchronization loss. INPERR: Acknowledge interrupt input error (input data discarded). DISCARD: Interrupt lost cycle (payload discarded). ITXFULL: Interrupt isochronous memory bank full. This fatal error. transmitter will reset itself automatically when this occurs. ITXEMPTY: Interrupt isochronous memory bank empty. Other bits will always read `0'. 13.2.5 Isochronous Transmitter Interrupt Enable (ITXINTE) Base Address: 0x030 These enabled bits Transmitter Control.
ERROR EIT100LFT EIT256LFT
ETRMBP EDBCERR
EITXFULL
EITXEMPTY
Reset Value 0x00000000 Bits 13.0 interrupt enable bits Isochronous Transmitter Interrupt Acknowledge register (ITXINTACK).
2000
EINPERR EDISCARD
EIT512LFT ETRMSYT
IDDSCI PLDSCI
ITXMFI
ITXMEI
EITEMI
SYTTI EOTI DBCEI
EITO/E
SV01055
Philips Semiconductors
Preliminary specification
1394 content protection link layer controller
PDI1394L41
13.2.6 Isochronous Transmitter Control Register (ITXCTL) Base Address: 0x34
ODD/EVEN CPHR_EN
CHANNEL
SV01016
Reset Value 0x00000000 Cipher Enable: When set, internal cipher will encrypt application packets with associated indirect address space given value assigned. When value changes cipher will automatically change next application packet. Writes ODD/EVEN (bit will automatically swap odd/even cipher. Note: maximum average data rate cipher Mbps. 15.14: Tag: code insert isochronous packet header. Should `01' 61883 International Standard data. 13.8: Channel: Isochronous channel number. 5.4: Speed: Cable transmission speed (S100, S200, S400). 100Mbs 200Mbs 400Mbs reserved Encryption Mode Indication: This pattern specifies level copy control information data stream. field only significance when internal cipher enabled (CPHR_EN Digital Transmission Content Protections Specification, Volume more details about values. even used encryption even, odd). When internal cipher enabled (CPHR_EN write that changes this field will cause cipher swap odd/even key. will changed very next application packet interrupt (ODDEVN) will generated. Digital Transmission Content Protection Specification, Volume more details about odd/even values. When internal cipher enabled (CPHR_EN value current value will transmitted isochronous header. Sync code insert field isochronous packet header. This reflects value synchronized with data payload that associated with 13.2.7 Isochronous Transmitter Memory Status (ITXMEM) Base Address: 0x038 Transmitter Memory Status register reports condition internal memory buffer used store incoming data streams before transmission over 1394 bus. This register used primarily diagnostics; several memory status flags also available ITXINTACK register.
3130 ITXM100LFT ITXM256LFT ITXM512LFT ITXMF ITXMAF ITXM5AV ITXME
SV01056
Reset Value 0x00000003
ITXM100LFT: less quadlets storage available. ITXM256LFT: Memory quadlets space remaining before becoming full. ITXM512LFT: Memory quadlets space remaining before becoming full. ITXMF: memory completely full, storage available. ITXMAF: almost full, exactly quadlet storage available. ITXM5AV: least more quadlets storage available. ITXME: memory bank empty (zero quadlets stored).
2000
Philips Semiconductors
Preliminary specification
1394 content protection link layer controller
PDI1394L41
13.2.8 Isochronous Receiver Unpacking Control (IRXPKCTL) Base Address: 0x040 NOTE: When receiver reset required, first disable receiver (EN_IRX then wait until FIFO emptied, then perform reset. This will allow previously received packets application instead being lost.
RXAP_CLK SNDIMM DIS_TSC RMVUAP SPAV EN_IRX EN_FS RST_IRX
BPAD
SV00887
Reset Value 0x00000041 Receiver Control Bits. 29.28: RXAP_CLK: Receiver Application Clock, default mode, `00' AVxCLK input. This become application clock output isochronous Receiver programming `01', `10', `11'. programming values are: Input 24.576MHz 12.288MHz 6.144MHz Note that when enabled `01', `10', `11', port that configured receiver enabled will output this clock signal AVxCLK pin. SNDIMM: Send immediately; when "1", this will allow received isochronous packet containing error output immediately (without regard time stamp value). This defaults "0". default (reset) mode, packet will output with respect time stamp value, even there error. CAUTION: there error time stamp, packet held into future. This will affect subsequently received packets. DIS_TSC: Disable Time Stamp Checking. Defaults "0", time stamp checking enabled. When time stamp checking disabled, time stamp accompanying packet output before packet application application. This adds extra quadlet data received data stream; application must capable handling this extra bytes. RMVUAP: Remove unreliable packets from memory, attempt delivery SPAV: Source packet available delivery buffer memory. EN_IRX: Enable receiver operation. Value only checked whenever packet arrives, enable/disable while running `graceful', meaning transfers process will completed before this asserted. 2.3: BPAD: Value indicating amount byte padding removed from last data quadlet each source packet, from bytes. This addition quadlet padding defined 61883 International Standard. EN_FS: Enable processing stamps. RST_IRX: causes receiver reset when `1'. order synchronous reset work properly, application must supply AVCLK ensure that reset kept (programmed) HIGH least duration AVCLK period. Failure cause application interface this module improperly reset reset all).
2000
Philips Semiconductors
Preliminary specification
1394 content protection link layer controller
PDI1394L41
13.2.9 Common Isochronous Receiver Packet Header Quadlet (IRXHQ1) Base Address: 0x044 This quadlet represents last received header value when receiver operating.
SV00286
Reset Value 0x00000000 31.30: 29.24 23.16: 15.14: 13.11:
Header, Format: Always first header quadlet. SID: Source contains node address sender isochronous data. DBS: Size data blocks from which payload constructed. value represents length quadlets. (Fraction Number): encoding number data blocks into which each source packet been divided transmitter packet. QPC: Number dummy quadlets appended each source packet before divided into data blocks specified size. SPH: Indicates that CYCbased time stamp inserted before each application packet bits specified 61883 International Standard).
13.2.10 Common Isochronous Receiver Packet Header Quadlet (IRXHQ2) Base Address: 0x048
SV00287
Reset Value 0x0000FFFF 31.30: Header, Format: Should second header quadlet. 29.24: FMT: Value inserted Format field. 23.0: FDF/SYT: ``EN Register IRXPKCTL (0x040) `1', then lower 16-bits interpreted SYT.
2000
Philips Semiconductors
Preliminary specification
1394 content protection link layer controller
PDI1394L41
13.2.11 Isochronous Receiver Interrupt Acknowledge (IRXINTACK) Base Address: 0x04C
IR100LFT IR256LFT IR512LFT IRXFULL IRXEMPTY FSYNC SEQERR CRCERR CIPTAGFLT RCVBP SQOV SYTOVF IRO/E IREMI
SV01025
Reset Valu
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