16-Bit, Programmable with 6-Bit Latch Features General Descriptio

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

16-Bit, Programmable with 6-Bit Latch Features General Descriptio

Datasheet Thumbnail

Top Searches for this datasheet

CS5529
16-Bit, Programmable with 6-Bit Latch
Features General Description
16-bit CS5529 low-power programmable converter which includes digital filter, self system calibration circuitry. chip designed operate from single analog supply ±2.5 analog supplies with either digital supply. digital filter programmable with output update rates between 1.88 (XIN 32.768 kHz). Output word rates increased approximately using kHz. filter designed settle full accuracy selected output word rate conversion. When operated word rates less (XIN 32.768 kHz), filter rejects both line interference simultaneously. power, single conversion settling time, programmable output rates, ability handle negative input signals make this single dual supply product ideal solution isolated non-isolated applications. ORDERING INFORMATION: PAGE CS5529-AP -40°C +85°C 20-PIN PDIP CS5529-AS -40°C +85°C 20-PIN SSOP
Delta-Sigma Converter
Linearity Error: 0.0015%FS Noise Free Resolution: 16-Bits
Bipolar/Unipolar Input Range 6-Bit Output Latch Simple three-wire serial interface
SPIand MicrowireCompatible Schmitt Trigger SCLK
Selectable Output Word Rates Output Settles Conversion Cycle System Self-Calibration with
Read/Write Registers
Single Dual ±2.5 Analog Supply
+3.0 Digital Supply
Power Consumption:
VAAIN+
DGND Digital Filter Differential order deltasigma modulator
AINVREF+ VREF-
Calibration Register Control Register
Output Register
SCLK
Latch
Calibration Memory
Calibration
Clock Gen.
XOUT
Preliminary Product Information
Cirrus Logic, Inc. Crystal Semiconductor Products Division P.O. 17847, Austin, Texas 78760 (512) 7222 FAX: (512) 7581 http://www.crystal.com
This document contains information product. Cirrus Logic reserves right modify this product without notice.
Copyright Cirrus Logic, Inc. 1997 (All Rights Reserved)
DS246PP1
CS5529
ANALOG CHARACTERISTICS
Parameter 25°C; ±2.5V± VREF+ 2.5V, VREF= 0.0V, FCLK 32.768 kHz, (Output Word Rate) Bipolar Mode, Input Range ±2.5V.) (See Notes (Note (Note (Note (Note ±0.0015 ±0.003 Units Bits LSB16 LSB16 nV/°C ppm/°C
Accuracy Linearity Error Missing Codes
Bipolar Offset Unipolar Offset Offset Drift Bipolar Gain Error Unipolar Gain Error Gain Drift
Noise (Note Output Word Rate (Hz)
1.88 3.76 7.51 15.0 30.0 61.6 84.5 101.1 Notes:
Filter Frequency (Hz) 1.64 3.27 6.55 12.7 25.4 50.4 70.7 84.6
Noise (µV) 10.0 45.0 95.0
Applies after system calibration temperature within -40°C +85°C. Specifications guaranteed design, characterization, and/or test. Specification applies device only does include effects external parasitic thermocouples. Drift over specified temperature range after calibration power-up Wideband noise aliased into baseband. Referred input. Typical values shown 25°C. peak-to-peak noise multiply ranges output rates. Specifications subject change without notice.
DS246PP1
CS5529
ANALOG CHARACTERISTICS (continued)
Parameter Units
Analog Input Common Mode Signal AIN+ AIN(Bipolar/Unipolar Mode) Single Supply Dual Supply Common Mode Rejection 60Hz Input Capacitance Current AIN+, AIN(Note System Calibration Specifications Full Scale Calibration Range (Bipolar/Unipolar Mode)(Note Offset Calibration Range (Bipolar/Unipolar Mode) Voltage Reference Input Range {(VREF+) (VREF-)} Common Mode Rejection Input Capacitance Current (Note Power Supplies Power Supply Currents (Normal Mode)
Power Consumption Normal Mode Power Mode Standby Sleep Positive Supplies Negative Supply (Note
VA1.0
1.25
Power Supply Rejection
section data sheet which discusses input models Page minimum Full Scale Calibration Range (FSCR) limited maximum allowed gain register value (with margin). maximum FSCR limited modulator's density range. "Analog Input" section details. Also "Limitations Calibration Range". outputs unloaded. inputs CMOS levels.
DS246PP1
CS5529
DIGITAL CHARACTERISTICS 25°C; ±2.5V ±5%, 5%.)(See Notes 10.)
Parameter High-Level Input Voltage: Pins Except XIN, SCLK SCLK XIN, SCLK SCLK (Note SDO, Iout -5.0mA SDO, Iout 1.6mA SDO, Iout 5.0mA Symbol Cout 0.6VD+ (VD+)-0.9 (VD+)-0.45 (VD+)-1.0 (VD+)-1.0 Units
Low-Level Input Voltage: Pins Except
High-Level Output Voltage: Pins Except Low-Level Output Voltage: Pins Except Input Leakage Current 3-State Leakage Current Digital Output Capacitance
measurements performed under static conditions. Iout -100 unless stated otherwise. (VOH 2.4V Iout µA).
3.0V DIGITAL CHARACTERISTICS 25°C; ±2.5V± 3.0V 5%.)
(See Notes 10.) Parameter High-Level Input Voltage: Pins Except XIN, SCLK SCLK Low-Level Input Voltage: Pins Except XIN, SCLK SCLK High-Level Output Voltage:All Pins Except SDO, Iout =-400µA SDO, Iout =-5.0mA Low-Level Output Voltage:All Pins Except SDO, Iout 400µA SDO, Iout 5.0mA Input Leakage Current 3-State Leakage Current Digital Output Capacitance Symbol Cout 0.6VD+ (VD+)-0.9 (VD+)-0.45 (VD+)-0.3 (VD+)-1.0 0.16 Units
DYNAMIC CHARACTERISTICS
Parameter Modulator Sampling Frequency Filter Settling Time (Full Scale Step) Symbol Ratio XIN/4 1/fout Units
DS246PP1
CS5529
RECOMMENDED OPERATING CONDITIONS (DGND 0V)(See Note 12.)
Parameter Power Supplies: Positive Digital {(VA+) (VA-)} Positive Analog Negative Analog Symbol VAdiff VAVRefdiff 5.25 5.25 5.25 -2.625 Units 4.75 2.375 -2.375 -2.5
Analog Reference Voltage{(VRef+) (VRef-)}
ABSOLUTE MAXIMUM RATINGS* (DGND 0V)(See Note 12.)
Parameter Power Supplies: Positive Digital Positive Analog Negative Analog (Note Symbol VAIIN IOUT (Note VREF pins VINA VIND Tstg -0.3 -0.3 -6.0 -0.3 -0.3 +6.0 +6.0 +0.3 (VA+)+0.3 (VD+)+0.3 +150 Units
Input Current, Except Supplies Output Current Power Dissipation Analog Input Voltage Digital Input Voltage Ambient Operating Temperature Storage Temperature voltages with respect ground.
(Notes
must satisfy {(VA+) (VA-)} +6V. Applies pins including continuous overvoltage conditions analog input (AIN) pins. Transient current 100mA will cause latch-up. Maximum input current power supply Total power dissipation, including input currents output currents. *WARNING: Operation beyond these limits result permanent damage device. Normal operation guaranteed these extremes.
DS246PP1
CS5529
SWITCHING CHARACTERISTICS 25°C; ±2.5V ±5%,
Input Levels: Logic Logic VD+; 50pF) Parameter Master Clock Frequency: External Clock Internal Oscillator(Note17) Master Clock Duty Cycle Rise Times Digital Input Except SCLK SCLK Digital Output Digital Input Except SCLK SCLK Digital Output XTAL 32.768 (Note trise Symbol 32.768 1002 Units cycles
Fall Times
(Note
tfall
Start-up Oscillator Start-up Time
Power-on Reset Period
(Note
tost tpor
Serial Port Timing Serial Clock Frequency Serial Clock
SCLK Pulse Width High Pulse Width
Write Timing Enable Valid Latch Clock
Data Set-up Time prior SCLK rising Data Hold Time After SCLK Rising SCLK Falling Prior Disable
Read Timing Data Valid
SCLK Falling Data Rising Hi-Z
Device parameters specified with 32.768 clock, however, clocks used increased throughput. Figure details. Specified using points waveform interest. Output loaded with Oscillator start-up time varies with crystal parameters. This specification does apply when using external clock source.
DS246PP1
CS5529
SCLK
Continuous Running SCLK Timing (Not Scale)
MSB-1
SCLK
Write Timing (Not Scale)
MSB-1
SCLK
Read Timing (Not Scale)
DS246PP1
CS5529
GENERAL DESCRIPTION
CS5529 16-bit monolithic CMOS converter optimized measure unipolar bipolar signals industrial applications. CS5529 includes coarse charge buffers, fourth order deltasigma modulator, calibration microcontroller, digital filter with selectable decimation rates, 6bit output latch, serial port. digital filter eight different output conversion word rates when chip operating from 32.768 watch crystal equivalent clock (shown Figure
Theory Operation
CS5529 converter designed operate from single analog supply dual ±2.5 analog supply provide user with input range. Analog Characteristics section page details. Figure illustrates CS5529 connected measure ground referenced bipolar signals. Figure illustrates CS5529 connected measure differential inputs relative common mode
+2.5 Analog Supply
VREF+ VREF-
XOUT
Digital Supply
32.768 Optional Clock Source
CS5529 -2.5 +2.5 (Gain Register 4.0) -1.25 +1.25 (Gain Register 2.0) Logic Outputs: Switch from D0-D3 Switch from DGND -2.5 Analog Supply AIN+ AIND3 SCLK
Serial Data Interface
DGND
Figure CS5529 Configured Ground-Referenced Bipolar Signals.
DS246PP1
CS5529
Analog Supply
XOUT 32.768 Optional Clock Source
2.5V
VREF+ VREFCS5529 AIN+ AIND3
±2.5 Input
SCLK
Serial Data Interface
DGND
Figure CS5529 Operating from
System Initialization
When power CS5529 applied, chip held reset condition until 32.768 oscillator started counter-timer elapses. high 32.768 crystal, oscillator takes 400-600 start. counter-timer counts 1002 oscillator clock cycles make sure oscillator fully stable. During this time-out period serial port logic reset (Reset Valid) configuration register set. reset initiated time writing logic (Reset System) configuration register. This automatically sets until configuration register read. After reset, on-chip registers initialized following states converter ready perform conversions.
configuration register: offset register: gain register: 000040(H) 000000(H) 400000(H)
Command Operation
CS5529 includes microcontroller with five registers used control chip. Each register 24-bits length except 8-bit command register (command, configuration, offset, gain, conversion data). After system initialization reset, serial port initialized command mode converter stays this mode until valid 8-bit command received (the first 8-bits into serial port). Table lists valid commands. Once valid 8-bit command read write command word) received interpreted command register, serial port enters data mode. data mode next serial clock pulses shift data either into serial port serial clock pulses needed setup register selected). Table configuring CS5529.
DS246PP1
CS5529
Reading/Writing On-Chip Registers
CS5529 offset, gain, configuration registers read/writable while conversion data register read only. perform read from specific register, command word must logic PS/R bits must logic (MSB) must logic register written selected with RSB2-RSB0 bits command word. perform write specific register, command word must logic PS/R bits must logic (MSB) must logic register written selected with RSB2-RSB0 bits command word. Figure illustrates serial sequence necessary write read from serial port. Set-up Registers chosen with RSB2RSB0 bits, registers read written following sequence: Offset, Gain Configuration. This accomplished following 8-bit command word with three 24-bit data words total data bits.
Command Register
D7(MSB) NAME Command Bit, RSB2 VALUE D3-D1 Single Conversion, Continuous Conversions, Read/Write, Register Select Bit, RSB2RSB0 RSB1 RSB0 PS/R FUNCTION Null command operation). command bits, including must Logic executable commands. Single Conversion active. Perform conversion. Continuous Conversions active. Perform conversions continuously. Write selected register. Read from selected register. Offset Register Gain Register Configuration Register Conversion Data Register (read only) Set-up Registers (Offset, Gain, Configuration) Reserved Reserved Reserved Power Save
Power Save/Run, PS/R
Table Command
DS246PP1
CS5529
Configuration Register
D23(MSB) NAME FUNCTION Latch Output Pins A1-A0 mimic D23-D22 Register bits. Latch Output Pins D3-D0 mimic D21-D18 Register bits. Must always logic zero. Normal Mode Reduced Power Mode 15.0 (2182 cycles) 30.0 (1090 cycles) 61.6 (546 cycles) 84.45 cycles) 101.1 cycles) 1.88 (4361 cycles) 3.76 (8722 cycles) 7.51 (4362 cycles) Bipolar Measurement mode Unipolar Measurement mode Must always logic Normal Operation Activate Reset cycle reset occurred been cleared (read only). Valid Reset occurred. (Cleared when read.) Port Flag mode inactive Port Flag mode active Standby Mode (Oscillator active, allows quick power-up) Sleep Mode (Oscillator inactive) Done Flag cleared (read only). Calibration Conversion cycle completed (read only). Normal operation calibration) Offset Self-Calibration Gain Self-Calibration Offset self-cal followed Gain self-calibration Used. Offset System Calibration Gain System Calibration Used.
VALUE 0000
D23-D22 Latch Outputs, A1-A0 D21-D18 Latch Outputs, D3-D0 Used, Power Mode,
D15-D13 Word Rate, WR2-0 (Note: Rates valid 32.768 kHz)
D11-D8 D2-D0
Unipolar/Bipolar, Used, Reset System, Reset Valid Port Flag, Power Save Select, Done Flag, Calibration Control Bits, CC2-CC0
indicates value after part reset Table Configuration Register
DS246PP1
CS5529
SCLK
Command Time SCLKs
Data Time SCLKs SCLKs Set-up Registers) Write Cycle
SCLK
Command Time SCLKs
Data Time SCLKs SCLKs Set-up Registers) Read Cycle
SCLK
Command Time SCLKs
XIN/OWR Clock Cycles SCLKs Clear Flag
IN/OWR clock cycles each conversion except first conversion which will take XIN/OWR clock cycles
Continuous Conversion Read
Data Time SCLKs
Figure Command Data Word Timing.
DS246PP1
CS5529
Analog Input
Figure illustrates input models pins. model includes coarse/fine charge buffer which reduces dynamic current demands from signal source. buffer designed accommodate rail rail (common-mode plus signal) input voltages. Application Note "Switched-Capacitor Input Structures", details various input architectures. Three factors limit input span CS5529. They include: reference voltage magnitude, offset gain calibration limits, maximum modulator input voltage. external voltage between VREF+ VREF- pins also limits full scale span converter. example, 1.25 reference used place nominal input, fullscale span half. When smaller reference voltage used, resulting code widths smaller. Since output codes exhibit more changing codes fixed amount noise, converter appears noisier. CS5529 also accommodate full scale ranges other than System calibration used increase decrease full scale span converter long calibration stays within specified limits (refer Analog Characteristics). limit, gain calibrations input signal reduced point which gain register reaches upper limit (decimal) [FFFFFF Hex] (this most likely occur with input signal less than nominal range). input voltage into modulator must cause modulator exceed percent high percent density. nominal full scale input span modulator produces from percent density. example, when +2.5 reference used ((VREF+)-(VREF-) bipolar mode selected, converter does have intrinsic gain error, then +2.5 input ((AIN+)-(AIN-) 2.5V) gives percent density -2.5 input gives percent density. limiting cases, percent, modulator's density sets input span -3.75 +3.75 input less than -3.75 will cause modulator's density less than percent input greater than 3.75V will cause density greater than percent. Either input will trigger modulator's oscillation detect circuitry because density exceeds stable operating limit. case, input voltage reference voltage increased decreased same proportion, modulator's density will remain constant.
Voltage Reference
Figure illustrates input models VREF pins. includes coarse/fine charge buffer which reduces dynamic current demand exter-
1Fine 1Coarse VREF 20pF 25mV fVos
1Fine 2Coarse 10pF 32.768
Figure Input model VREF+ VREF- pins.
25mV fVos
32.768
Figure Input models AIN+ AIN- pins.
DS246PP1
CS5529
reference. dynamic input currents each pins determined from models shown. reference's buffer Figure designed accommodate rail-to-rail (common-mode plus signal) input voltages. single-ended reference voltage, such LT1019-2.5, reference output connected VREF+ CS5529 ground reference LT1019-2.5 connected VREF- pin. termines offset trimmed positive negative positive, negative). converter typically trim percent input span. gain register spans from 2-22). decimal equivalent meaning gain register
+.+b
bi2-i
Calibration
CS5529 offers five different calibration functions including self calibration system calibration. However, after CS5529 reset, converter functional perform measurements without being calibrated. this case, converter will utilize initialized values on-chip registers (Gain 1.0, Offset 0.0) calculate output words. initial offset gain errors internal circuitry chip will remain. gain offset registers, which used both self system calibration, used zero full-scale points converter's transfer function. offset register 2-24 proportion input span (bipolar span times unipolar span). offset register
where binary numbers have value either zero corresponds MSB-1, 22). Refer Table details. offset gain calibration steps each take conversion cycle complete. calibration step, calibration control bits will back logic (Done Flag) will logic combination self-calibration (CC2-CC0= 011; offset followed gain), calibration will take conversion cycles complete will after gain calibration completed. will cleared time data register, offset register, gain register, setup register read. Reading configuration register alone will clear bit.
Offset Register
Register
Reset
Sign
2-20 2-21 2-22 2-23 2-24
2-19
represents 2-24 proportion input span (bipolar span times unipolar span) Offset data word bits align (bit MSB-4 offset register changes MSB-4 data)
Gain Register
Register
Reset
2-18 2-19 2-20 2-21 2-22
2-17
gain register span from (4-2-22). After Reset (MSB-1) other bits Table Offset Gain Registers
DS246PP1
CS5529
Self Calibration
CS5529 offers both self offset self gain calibrations. self-calibration offset, converter internally ties inputs modulator together routes them VREF- shown Figure Also self offset calibration requires that VREF- tied fixed voltage between VA-. self-calibration gain, differential inputs modulator connected VREF+ VREF- shown Figure
OPEN AIN+
External Connections AIN+ AIN-
Figure System Calibration Offset.
External Connections AIN+ Full cale AIN-
AINVREF-
OPEN CLOSED
Figure Self Calibration Offset.
Figure System Calibration Gain.
OPEN AIN+
AINVREF+ Reference VREF-
OPEN
CLOSED CLOSED
system gain calibration performed following conditions must met, density modulator must greater than percent (the input modulator must exceed maximum input), input must cause resulting gain register's content, decoded decimal, exceed 3.9999998. above conditions require full scale input voltage modulator least percent nominal value. converter's input range chosen guarantee gain calibration accuracy when gain calibration performed with reference. This useful when user wants manually scale full scale range converter maintain accuracy. example, gain calibration performed with full scale voltage 1.25 input range desired, user read contents gain register, shift bit, then write results back gain register. Assuming system provide known voltages, following equations allow user manually compute calibration register's values based uncalibrated conversions (see note).
Figure Self Calibration Gain.
System Calibration
system calibration functions, user must supply converter calibration signals which represent ground full scale. When system offset calibration performed ground reference signal must applied converter. Figure shown Figure user must input signal representing positive full scale point when system gain calibration performed. either case, calibration signals must within specified calibration limits each specific calibration step (refer System Calibration Specifications).
DS246PP1
CS5529
offset gain calibration registers used adjust typical conversion follows: Co>>4) 222. Calibration performed using following equations: (Rc0/G Ru0) where (Rc1 Rc0)/(Ru1-Ru0).
Note: Uncalibrated conversions imply that gain offset registers default {gain register 0x400000 (Hex) offset register 0x000000 (Hex)}.
conversion words with more peak-to-peak noise, calibration should performed lower output word rates. Also, minimize digital noise near device, user should wait each calibration step completed before reading writing serial port. Factory calibration performed using system calibration capabilities CS5529, offset gain register contents read system microcontroller recorded EEPROM. These same calibration words then uploaded into offset gain registers converter when power first applied system. final tips include ways determine when calibration complete: wait fall. falls logic (Port Flag) configuration register logic poll (Done Flag) configuration register which completion calibration. Whichever method used, calibration control bits (CC2CC0) will return logic upon completion calibration.
variables defined below.
First calibration voltage Second calibration voltage (greater than Result uncalibrated conversion Result uncalibrated conversion (20-bit integer complement) Result uncalibrated conversion (20-bit integer complement) Result conversion Desired calibrated result converting (20-bit integer complement) Desired calibrated result converting (20-bit integer complement) Offset calibration register value (24-bit complement) Gain calibration register value (24-bit integer)
Limitations Calibration Range
System calibration limited signal headroom analog signal path inside chip discussed under Analog Input section this data sheet. gain calibration full scale input signal reduced point which gain register reaches upper limit (4-2-22 decimal) FFFFFF (hexadecimal). Under nominal conditions, this occurs with full scale input signal equal about nominal full scale. With converter's intrinsic gain error, this full scale input signal higher lower. defining minimum Full Scale Calibration Range (FSCR) under "Analog Characteristics", margin retained accommodate intrinsic gain error. Alternatively input full scale signal increased point which modulator reaches density limit percent, which under nominal condition occurs when full scale input signal
DS246PP1
shift right operator (e.g. shifted right bits) shift left operator (e.g. x<<2 shifted left bits)
Note: shift operators used here align decimal points words various lengths. Data right decimal point used calculations shown.
Calibration Tips
Calibration steps performed output word rate selected WR2-WR0 bits configuration register. Since higher word rates result
CS5529
times nominal full scale. With chip's intrinsic gain error, this input full scale input signal maybe higher lower. defining maximum FSCR, margin again incorporated accommodate intrinsic gain error. converter, when port initialization sequence completed, whenever command byte, data word sequence completed. port initialization sequence involves clocking more) bytes 1's, followed byte with following contents (11111110). This sequence places chip command mode where waits valid command.
Latch Output Pins
D3-D0 pins converter mimic D21D18 bits configuration register. D3-D0 used control multiplexers other digital logic functions outside converter. A1-A0 pins converter mimic D23-D22 bits configuration register used control analog switches. These outputs powered from VA-, hence, their output voltage will either logic logic D0-D3 outputs powered from DGND. Their output voltage will logic DGND logic outputs sink source least recommended limit drive currents less than reduce self-heating chip.
Performing Conversions (With
Setting (Single Conversion) command word logic with other command bits CS5529 will perform conversion. completion conversion (Done Flag) configuration register will logic user read configuration register determine set. been set, command issued read conversion data register obtain conversion data word. configuration register will cleared logic when data register, gain register, offset register, setup registers read. Reading only configuration register will clear flag bit. command issued converter while performing conversion, filter will restart convolution cycle perform conversion.
Serial Port Interface
CS5529 serial interface consist four pins, SCLK, SDO, SDI, must held (logic before SCLK transitions recognized port logic. output will held high impedance time logic tied low, port function three wire interface. SCLK input designed with Schmitt-trigger input allow optoisolator with slower rise fall times directly drive pin. output capable sinking sourcing directly drive optoisolator LED. will have less than loss drive voltage when sinking sourcing
Performing Conversions (With
Setting configuration register logic enables output behave flag signal whenever conversions completed. This eliminates need user read flag configuration register determine conversion data word available. (Single Conversion) command issued other command bits will completion conversion. user would then issue SCLKs (with logic clear flag. Upon falling edge SCLK, will present first (MSB) conversion word. SCLKs
Serial Port Initialization
serial port initialized command mode whenever power-on reset performed inside
DS246PP1
CS5529
(high, then low) required read conversion word from port. user must give explicit command read conversion data register when logic data conversion word must read before command entered command used with (Continuous Conversion) command issued other command bits will completion conversion. user would then issue SCLKs (with logic clear flag. Upon falling edge SCLK, will present first (MSB) conversion word. SCLKs (high, then low) required read conversion word from port. user must give explicit command read conversion data register when logic When operating continuous conversion mode, user need read every conversion. user does nothing after falls, will rise clock cycle before next conversion word available then fall again signal that another conversion word available.
Note: user begins clear flag read conversion data, this action must finished before conversion cycle which occurring background complete user wants able read conversion data.
reset converter operate with output word rate 15.0
Clock Generator
CS5529 includes gate which connected with external crystal provide master clock chip. chip designed operate using low-cost 32.768 "tuning fork" type crystal. lead crystal should connected other XOUT. Lead lengths should minimized reduce stray capacitance. converter will operate with external (CMOS compatible) clock with frequencies three times typical frequency 32.768 kHz. Figure details converter's performance increased clock rates. 32.768 crystal normally specified time-keeping crystal with tight specifications both initial frequency drift over temperature. maintain excellent frequency stability, these crystals specified only over limited operating temperature ranges (i.e. °C). However, applications with CS5529 don't generally require such tight tolerances. When converter powered from digital supply, external resistor necessary shown Figure
exit continuous conversion mode, issue valid command input when flag falls. command issued converter while performing conversion, filter will restart convolution cycle perform conversion.
Output Word Rate Selection
WR2-WR0 bits configuration register output conversion word rate converter shown Table word rates indicated table assume master clock 32.768 kHz. Upon
Figure High Speed Clock Performance
DS246PP1
CS5529
XOUT
increased 64.536 doubles filter's corner frequency moves 25.4
Output Coding
32.768
CS5529
CS5529 outputs data binary format when operating unipolar mode two's complement when operating bipolar mode. output conversion word bits, three bytes long, shown Table output first followed rest data bits descending order. CS5529 last byte composed bits D7-D4, which always logic D3-D2, which always logic bits D1-D0 which flag bits. (Overrange Flag) logic time input signal more positive than positive full scale, more negative than zero (unipolar mode), more negative than negative full scale (bipolar mode). cleared back logic whenever conversion word occurs which overranged. (Oscillation Detect) logic time that oscillatory condition detected modulator. This does occur under normal operating conditions, occur whenever input converter extremely overranged. set, conversion data bits completely erroneous. flag will cleared logic when modulator becomes stable. Table illustrates output coding CS5529.
Figure Digital Connection Diagram
Digital Filter
CS5529 eight different linear phase digital filters which output word rates (OWRs) stated Table These rates assume that 32.768 kHz. Each filters magnitude response similar that shown Figure filters optimized settle full accuracy every conversion yield better than rejection both with output word rates below 15.0 converter's digital filters scale with XIN. example with output word rate filter's corner frequency typically 12.7
Figure Filter Response (Normalized Output Word Rate
Output Conversion Data CS5529 bits flags)
Table Data Conversion Word
DS246PP1
CS5529
CS5529 16-Bit Output Coding Two's Complement 7FFF 7FFF -7FFE 0000 -FFFF 8001 -8000 8000
Unipolar Input Voltage >(VFS-1.5 LSB) VFS-1.5
Offset Binary FFFF FFFF -FFFE 8000 -7FFF 0001 -0000 0000
Bipolar Input Voltage >(VFS-1.5 LSB) VFS-1.5
VFS/2-0.5
-0.5
+0.5 <(+0.5 LSB)
-VFS+0.5 <(-VFS+0.5 LSB)
Note: table equals voltage between ground full scale unipolar gain ranges, voltage between full scale bipolar gain ranges. text about error flags under overrange conditions. Table CS5529 Output Coding
Power Consumption
CS5529 accommodates four power consumption modes: normal, power, standby, sleep. normal mode, default mode, entered after power-on-reset typically consumes power mode alternate mode that reduces consumed power entered setting (the power mode bit) configuration register logic Since converter's noise performance improves with increased power consumption, slightly degraded noise linearity performance should expected power mode. final modes power save modes. They power down most analog portion chip stop filter convolutions. power save modes entered whenever PS/R command word logic particular power save mode entered depends state (the power save select bit) configuration register. logic converter enters standby mode reducing power consumption 1mW. standby mode
leaves oscillator on-chip bias generator running. This allows converter quickly return normal power mode once PS/R back logic configuration register PS/R command word logic sleep mode entered reducing consumed power less than Since sleep mode disables oscillator, approximately 500ms oscillator start-up delay period required before returning normal power mode.
Layout
CS5529 should placed entirely over analog ground plane with both AGND DGND pins device connected analog ground plane. Place analog-digital plane split immediately adjacent digital portion chip CDB5529 data sheet suggested layout details Applications Note more detailed layout guidelines. Before layout, please call Free Schematic Review Service.
DS246PP1
CS5529
DESCRIPTIONS
NEGATIVE ANALOG POWER POSITIVE ANALOG POWER DIFFERENTIAL ANALOG INPUT DIFFERENTIAL ANALOG INPUT ANALOG OUTPUT ANALOG OUTPUT
DIGITAL OUTPUT
VAVA+ AIN+
VREF+ VOLTAGE REFERENCE INPUT
VREFD3
VOLTAGE REFERENCE INPUT DIGITAL OUTPUT DIGITAL OUTPUT DIGITAL OUTPUT SERIAL DATA INPUT
SERIAL DATAT OUTPUT
AINA0 SCLK XOUT
DGND
CHIP SELECT SERIAL CLOCK INPUT CRYSTAL
POSITIVE DIGITAL POWER DIGITAL GROUND CRYSTAL
Clock Generator
XIN; XOUT Crystal Crystal Out, Pins gate inside chip connected these pins used with crystal provide master clock device. Alternatively, external (CMOS compatible) clock supplied into provide master clock device.
Control Pins Serial Data
Chip Select, When active low, port will recognize SCLK. When high will output high impedance state. should changed when SCLK Serial Data Input, input serial input port. Data will input rate determined SCLK. Serial Data Output, serial data output. will output high impedance state SCLK Serial Clock Input, clock signal this determines input/output rate data SDI/SDO pins respectively. This input Schmitt trigger allow slow rise time signals. SCLK will recognize clocks only when low. Analog Outputs, logic states A0-A1 mimic states D22-D23 bits configuration register. Logic Output VA-, Logic Output VA+. Digital Outputs, logic states D0-D3 mimic states D18-D21 bits configuration register. Logic Output DGND, Logic Output VD+.
DS246PP1
CS5529
Measurement Reference Inputs
AIN+, AIN- Differential Analog Input, Pins Differential input pins into device. VREF+, VREF- Voltage Reference Input, Pins Fully differential inputs which establish voltage reference on-chip modulator.
Power Supply Connections
Positive Analog Power, Positive analog supply voltage. Nominally +2.5 Negative Analog Power, Negative analog supply voltage. Nominally -2.5 Positive Digital Power, Positive digital supply voltage. Nominally +3.0 DGND Digital Ground, Digital Ground.
DS246PP1
CS5529
SPECIFICATION DEFINITIONS
Linearity Error deviation code from straight line which connects points Converter transfer function. point located below first code transition other point located beyond code transition ones. Units percent full-scale. Differential Nonlinearity deviation code's width from ideal width. Units LSBs. Full Scale Error deviation last code transition from ideal [{(VREF+) (VREF-)} LSB]. Units LSBs. Unipolar Offset deviation first code transition from ideal (1/2 above voltage AIN- pin). When unipolar mode (U/B Units LSBs. Bipolar Offset deviation mid-scale transition (111.111 000.000) from ideal (1/2 below voltage AIN- pin). When bipolar mode (U/B Units LSBs.
ORDERING GUIDE
Model Number CS5529-AP CS5529-AS Linearity Error (Max) ±0.003% ±0.003% Temperature Range -40°C +85°C -40°C +85°C Package 20-pin 0.3" Plastic 20-pin 0.2" Plastic SSOP
SPIis trademark Motorola Inc., Microwireis trademark National Semiconductor Corp.
DS246PP1
CS5529
Plastic
SEATING PLANE
NOTES: POSITIONAL TOLERANCE LEADS SHALL ITHIN 0.25mm (0.010") MAXIMUM MATERIAL CONDITION, RELATION SEATING PLANE EACH OTHER. DIMENSION CENTER LEADS FORMED PARALLEL. DIMENSION DOES INCLUDE MOLD FLASH.
MILLIMETERS INCHES 3.94 0.180 4.57 0.155 0.80 0.51 1.02 0.020 0.030 0.040 0.38 0.46 0.56 0.015 0.018 0.022 1.52 1.78 0.050 0.060 0.070 1.27 0.20 0.25 0.38 0.008 0.010 0.015 24.38 25.40 26.42 0.960 1.000 1.040 6.10 6.35 6.60 0.240 0.250 0.260 2.41 2.54 2.67 0.095 0.100 0.105 7.62 7.92 8.25 0.300 0.312 0.325 3.18 3.30 3.81 0.125 0.130 0.150
SSOP Package Dimensions
VIEW SIDE VIEW Seating Plane
VIEW
NOTES: DIMENSIONS REFERENCE DATUMS INCLUDE MOLD FLASH PROTRUSIONS, INCLUDE MOLD MISMATCH MEASURED PARTING LINE. MOLD FLASH PROTRUSIONS SHALL EXCEED 0.20mm SIDE. DIMENSION DOES INCLUDE DAMBAR PROTRUSION/INTRUSION. ALLOW ABLE DAMBAR PROTRUSION SHALL 13mm TOTAL EXCESS DIMENSION MAXIMUM MATERIAL CONDITION. DAMBAR INTRUSION SHALL REDUCE DIMENSION MORE THAN 0.07mm LEAST MATERIAL CONDITION. THESE DIMENSIONS APPLY FLAT SECTION LEAD BETW 0.10 0.25mm FROM LEAD TIPS.
MILLIMETERS 2.13 0.05 0.15 0.25 1.62 1.75 1.88 0.22 0.30 0.38 other table 7.40 7.80 8.20 5.00 5.30 5.60 0.61 0.65 0.69 0.63 0.90 1.03 other table
INCHES Note 0.084 0.002 0.006 0.010 0.064 0.070 0.074 0.009 0.012 0.015 other table 0.291 0.307 0.323 0.197 0.209 0.220 0.024 0.026 0.027 0.025 0.035 0.040 other table
MILLIMETERS INCHES Note 5.90 6.20 6.50 0.232 0.244 0.256 6.90 7.20 7.50 0.272 0.283 0.295 9.90 10.20 10.50 0.390 0.402 0.413
DS246PP1
CDB5529
CDB5529 Evaluation Board Software
Features General Description
CDB5529 inexpensive tool designed evaluate performance CS5529 16-bit Analog-toDigital Converter (ADC). evaluation board includes LT1019 voltage reference, 80C51 microcontroller, RS232 driver/receiver, firmware. 8051 controls serial communication between evaluation board firmware, thus, enabling quick easy access CS5529's registers. CDB5529 also includes software Time Domain Analysis, Histogram Analysis, Frequency Domain Analysis.
RS-232 Serial Communication with On-board 80C51 Microcontroller On-board Voltage Reference Windows/CVIEvaluation Software
Register Setup Chip Control Analysis Time Domain Analysis Noise Histogram Analysis
Integrated RS-232 Test Mode
ORDERING INFORMATION: CDB5529
+5/+2.5 ANALOG
-2.5 ANALOG
AGND
DGND
+5/3.3 DIGITAL
DIGITAL RS232 CONNECTOR
VOLTAGE REFERENCE
REF+ AIN+ AINREF-
LEDs
CS5529
AIN+ AINCS SCLK XOUT HDR6
RS232 DRIVER/RECEIVER
80C51 MICROCONTROLLER
CRYSTAL 11.0592MHz
RESET CIRCUITRY
TEST SWITCHES
CRYSTAL 32768Hz
Cirrus Logic, Inc. Crystal Semiconductor Products Division P.O. 17847, Austin, Texas 78760 (512) 7222 FAX: (512) 7581 http://www.crystal.com
Copyright Cirrus Logic, Inc. 1997 (All Rights Reserved)
DS246DB1
CDB5529
PART HARDWARE
evaluation board provides voltage reference options, on-board external. With HDR5's jumpers positions LT1019 provides absolute voltage level volts (the LT1019 chosen drift, typically 5ppm/°C). setting HDR5's jumpers position user supply external voltage reference J1's REF+ REF- inputs (Application Note Crystal Semiconductor's site details various voltage references). serial interface SPIand MICROWIREcompatible. interface control lines (CS, SDI, SDO, SCLK) connected 80C51 microcontroller port one. interface external microcontroller, these control lines also connected HDR6. However accomplish this, evaluation board must modified three ways: interface control traces going microcontroller, remove resistors R1-R8, remove microcontroller. Figure illustrates schematic digital section. contains microcontroller, Motorola MC145407 interface chip, test switches. test switches debugging communication problems between CDB5529 microcontroller derives clock from 11.0592 crystal. From this, controller configured communicate RS-232 9600 baud, parity, 8-bit data, stop bit.
Introduction
CDB5529 evaluation board provides quick means testing CS5529 Analog-to-Digital Converter (ADC). board interfaces CS5529 IBMcompatible RS-232 interface while operating from either single supply dual ±2.5 volt supplies. accomplish this, board comes equipped with 80C51 microcontroller 9-pin RS-232 cable which physically interfaces evaluation board Additionally, analysis software provides easy access internal registers converter, provides means display converter's time domain, frequency domain, noise histogram performance. evaluation board's software includes debug algorithms trouble shoot evaluation board. Refer Trouble Shooting Evaluation Board section more details.
Evaluation Board Overview
board partitioned into sections: analog digital. analog section consists CS5529 precision voltage reference. digital section consists 80C51 microcontroller, hardware test switches, reset circuitry, RS-232 interface. CS5529 designed digitize signals while operating from 32.768 crystal. shown Figure signal connected converter's inputs J1's AIN+ AIN- inputs. Note that simple network filters input reduce broadband noise.
DS246DB1
CDB5529
2.5V Analog 0.1µF HDR8 -2.5V Analog REF+ AIN+ AINREFR17 4700pF
HDR1 AGND
10µF
HDR3 0.1µF 3.3V Digital
CS5529
AIN+ DGND SCLK DGND
10µF
HDR9 SCLK
AIN+
0.68µF
HDR2
0.68µF AIN4 AIN2, AGND HDR5
Figure
4700pF
1,LT1019 2,REF+ 3,REF4,VA-
REF+ REF-
HDR6
2.5V Analog VAC21 0.1µF
LT1019 2.5V
XOUT 0.1µF
32768Hz
Figure Analog Schematic Section
DS246DB1
Digital Digital P3.0 P3.1 P1.4 P1.5 P1.6 P1.7 P3.5 P3.6 P2.1 P2.2 XTAL1 P2.3 33pF C0G+5V Digital Bypass XTAL2 LED_555_5003 OFFSETCAL P2.0 P3.2 P3.3 P3.4 5.11k 5.11k 5.11k RESET COMM GAINCAL Test Switch Test Switch Test Switch Loopback Normal HDR7 From RS-232 47µF 0.1µF 10µF From Figure SCLK 33pF 11.0592MHz HDR10 C2C2+ P1.0 P1.1 P1.2 P1.3 P0.0 RS-232 TP71 TP72 0.1µF 1N4148 0.1µF RESET 80C51 Digital TP65 TP64 TP63 TP62 TP61 SN74HC14N 750k
10µF 10µF MC145407 10µF
C1C1+
CDB5529
Figure Digital Schematic Section
DS246DB1
CDB5529
Register Offset Register Gain Register Configuration Register Conversion Data Register
Read Command Byte 0x90 0x92 0x94 0x96 Table Microcontroller Command RS-232
Write Command Byte 0x80 0x82 0x84
Table lists RS-232 commands used communicate between microcontroller. develop additional code communicate evaluation board RS-232, following applies: write internal register, choose appropriate write command byte (See Table transmit first. Then, transmit three data bytes, lowest order byte (bits 7-0) first, with each byte transmitted first. These three data bytes provide 24-bits information written desired register. read from internal register, choose appropriate read command byte transmit first. Then, microcontroller automatically acquires ADC's register contents returns 24-bits information. returned data transmitted lowest order byte first with each byte transmitted first. CS5529 converter designed operate from single dual ±2.5V analog supply. Figure illustrates power supply connections evaluation board. +2.5/5V Analog supplies positive analog section evaluation board,
+2.5V Analog P6KE6V8P 47µF 0.1µF AGND P6KE6V8P -2.5V Analog P6KE6V8P 47µF 0.1µF
LT1019 ADC. -2.5V Analog supplies negative. HDR8 (see Figure used bypass ground. Digital supplies digital section evaluation board. powers 80C51, reset circuitry, RS-232 interface circuitry.
Using Evaluation Board
CS5529 highly integrated ADC. contains coarse/fine charge buffers programmable output word rates (OWR). buffers provide charge modulator reducing dynamic current demand from signal being digitized from external reference. ADC's digital filter allows user select output word rates (OWR's) from 1.88 101.1 (assuming 32.768 clock). output word rates attained when 100kHz clock source used. Since CS5529 such high degree integration flexibility, CS5529 data sheet should read thoroughly before consulted during CDB5529.
HDR3 0.1µF 47µF DGND 0.1µF 47µF HDR8
3.3V Digital P6KE6V8P
P6KE6V8P
Digital
Figure Power Supplies
DS246DB1
CDB5529
Name HDR1 HDR2 HDR3 Function Description Used switch AIN+ between input AGND. Used switch AIN- between input AGND. Used switch digital power converter (VD+) from positive analog supply header (+5V/2.5V Analog) positive digital supply header (+5V/3.3V Digital). Does exist. Used switch VREF+ VREFpins from external connection header board LT1019 reference. Used connect external micro-controller. Used conjunction with self test modes test UART communication between microcontroller Used switch analog component's (LT1019 converter) negative potential between -2.5V Analog header AGND. Used conjunction with HDR3 switch digital ground converter (DGND) from AGND header DGND header. Used switch output switches converter into microcontroller. These shunts must disconnected when converter powered from bipolar supplies.
Software
evaluation board comes with software RS-232 cable link evaluation board executable software developed with Windows/CVIand meant under Windows3.1 later. After installing software, read readme.txt file last minute changes software. Additionally, Part Software further details install software.
HDR4 HDR5
HDR6 HDR7
HDR8
HDR9
IBM, PS/2 trademarks International Business Machines Corporation. Windows trademark Microsoft Corporation. Windows trademarks National Instruments. trademark Motorola. MICROWIRE trademark National Semiconductor.
HDR10
DS246DB1
CDB5529
PART SOFTWARE
Using Software
start-up, window START-UP CONFIGURATION appears first. This window contains information concerning software's title, revision number, copyright date, etc. Additionally, screen menu which displays user options. Notice, menu item Menu initially disabled. This eliminates conflicts with mouse concurrent modems. Before proceeding further, user prompted select serial communication port. initialize port, pull down option Setup from menu select either COM1 COM2. Next, select appropriate part under Part menu. After port initialized part selected, good idea test RS-232 link between evaluation board. this, pull down Setup menu from menu select option TESTRS232. user then prompted evaluation board's test switches then reset board. Once this done, proceed with test. test fails, check hardware connection repeat again. Otherwise, test switches (normal mode) reset board. option Menu available performance tests executed. evaluation software provides three types analysis tests Time Domain, Frequency Domain, Histogram. Time Domain analysis processes acquired conversions produce plot Conversion Sample Number versus Magnitude. Frequency Domain analysis processes acquired conversions produce magnitude versus frequency plot using Fast-Fourier transform (results Fs/2 calculated plotted). Also, statistical noise calculations calculated displayed. Histogram analysis processes acquired conversions produce histogram plot. Statistical noise calculations also calculated displayed (see figures through figure
Installation Procedure
install software: Turn prompt type Launch Windows 3.1or later. Insert Installation Diskette into From within Windows Program Manager, pull down File from menu select option. prompt type: A:\SETUP.EXE <enter>. program will begin installation. After seconds, user will prompted enter directory which install Run-Time EngineTM. Run-Time Enginemanages executables created with Windows/CVIand takes approximately megabytes hard drive space. default directory acceptable, select Run-Time Enginewill installed there. After Run-Time Engineis installed, user prompted enter directory which install CDB5529 software. Select accept default directory. program takes minutes install. After program installed, double click Eval5529 icon launch After seconds, user should graphical user interface environment.
Note: software written with (standard Windows 3.1TM) resolution; however, will work with 1024 resolution. user interface seems little small, user might consider setting display settings standard (640x480 chosen accommodate variety computers).
DS246DB1
CDB5529
evaluation software developed with Windows/CVITM, software development package from National Instruments. More sophisticated analysis software developed purchasing development package from National Instruments (512-794-0100). Load From Disk: Used load display previously saved data conversions from file. file must comply with CDBCAPTURE file save format. format part number, number bits, number conversions, maximum range, data conversions. user prompted enter path file name previously saved data. prevent hardware conflicts, this option deactivated while Input/Output Window. TESTRS232: This test mode tests ability communicate evaluation board. consists subtests: test link between RS-232 interface circuitry; test RS-232 link between microcontroller. HDR7 distinguishes these subtests. HDR7 Normal test complete communication link. HDR7 Loop Back test link between RS-232 Circuitry Then, test switches reset evaluation board. LED's should indicate binary signifying that hardware ready initiate test. complete test, user must initialize First, SETUP menu select communications port then select TESTRS232 option. From there, prompts navigate user through test. indicates test passes fails. Once either test complete, LED's toggle indicate that test mode complete. QUIT: Allows user exit program.
Menu Bars Overview
menu controls link between windows allows user exit program. also allows user initialize serial port load presaved data conversions from file. five principal windows START CONFIGURATION (also referred Setup Window), Input Output Window, Histogram Window, Power Spectrum Window (also referred window), Time Domain Window. Specifically, menu following control items: Menu: select, click option Menu from menu bar, associated keys. items associated with MENU listed described below. Setup Window (F1) (F2) (F3) Input/Output Window Histogram Window
Power Spectrum Window (F4) Time Domain Window (F5) These five menu items allow user navigate between five windows. They available times menu keys. SETUP: select, click option Setup from menu bar. functions available under Setup are: COM1: When selected, COM1 initialized 9600 baud, parity, data bits, stop bit. COM2: When selected, COM2 initialized 9600 baud, parity, data bits, stop bit.
Input/Output Window Overview
Input/Output Window allows user read write internal register converter either binary hexadecimal, acquire real-time conversions. quick access control icons that quickly reset converter, reset converter's serial port, self-calibrate converter's offset gain. following controls indicators associated with this window. Acquire: This control icon. When pressed, transmits collect single conversion command
DS246DB1
CDB5529
microcontroller. microcontroller turn collects conversion from returns stores conversion collects additional conversions form set. From sample collected, high, low, peak-to-peak, average, standard deviation, computed (the size data Average input) then display icons updated. This process continues until STOP button pressed, until another window selected. Note: quick access control icons disabled once Acquire selected. This eliminates potential hardware conflicts. BINARY: Input icons clear individual bits gain, configuration, offset registers. bits first set, then control icon Write Registers selected update registers converter. CONFIGURATION REGISTER: Text display that displays decoded meaning each configuration register. DECIMAL: Three display icons that display decimal contents gain, configuration, offset registers. DIGITAL OUTPUT: Display icon that displays states output latch. invalid when converter powered from bipolar supplies. GAIN REGISTER: Display icon that displays decimal equivalent bits gain register. HEX: Three input/display icons that allow user bits gain, configuration, offset registers hexadecimal nibbles. upper nibbles registers zero's, then leading zero nibbles need entered. Average: Input icon that sets size data conversion referred when Acquire button pressed. Read Registers: This control icon. When pressed gain, offset, configuration registers contents acquired. Then, configuration text register content icons updated. Reinitialize: This control icon. When pressed, logic followed logic sent ADC's serial port reset port. does reset RS-232 link. Reset A/D: This control icon. When pressed, microcontroller sends appropriate commands return converter initial default state. SELF Calibrate: This control icon. When pressed, appropriate commands sent calibrate offset gain. STOP: Stops collection conversion data. Write Registers: This control icon. When pressed, binary input icons settings acquired. This data then transmitted ADC's gain, offset, configuration registers. Then, PC's display updated reflect registers changes.
DS246DB1
CDB5529
Histogram Window Overview
following description controls indicators associated with Histogram Window. Many control icons usable from Histogram Window, Frequency Domain Window, Time Domain Window. brevity, they only described this section. BIN: Displays x-axis value cursor Histogram. CANCEL: Once selected, allows user exit from COLLECT algorithm. data conversion sample sets larger than being collected CANCEL button selected, recommended that user reset evaluation board. board will eventually recover from continuous collection mode, recovery time could long minutes. COLLECT: Initiates data conversion collection process. COLLECT modes operation: collect from file collect from converter. collect from file appropriate file from SETUP-DISK menu option must selected. Once file selected, content displayed graph. user collecting real-time conversions analyze, appropriate port must selected. user then free collect preset number conversions (preset CONFIG pop-up menu discussed below). Notice, there significant acquisition time difference methods. CONFIG: Opens pop-up panel configure much data collected, process data once collected. following controls indicators associated with CONFIG panel. SAMPLES: User selection 256, 512, 1024, 2048, 4096, 8192 conversions. WINDOW: Used Power Spectrum Window calculate FFT. Windowing algorithms include Blackman, Blackman-Harris, Hanning, 5-term Hodie, 7-term Hodie. 5-term Hod34
7-term Hodie windowing algorithms developed Crystal Semiconductor. information concerning these algorithms needed, call technical support. AVERAGE: Sets number consecutive FFT's perform average. LIMITED NOISE BANDWIDTH: Limits amount noise converters bandwidth. Default Accept change MAGNITUDE: Displays y-axis value cursor Histogram. MAXIMUM: Indicator maximum value collected data set. MEAN: Indicator mean data sample set. MINIMUM: Indicator minimum value collected data set. OUTPUT: Control that calls pop-up menu. This menu controls three options: save current data file with CDBCAPTURE format, print current screen, print current graph. RESTORE: Restores display graph after zoom been entered. STD. DEV.: Indicator Standard Deviation collected data set. TEST: Quick access control icon, similar keys, allow user quickly switch between time domain, frequency domain, histogram display. VARIANCE: Indicates Variance current data set. ZOOM: Control icon that allows operator zoom specific portion current graph. zoom, click ZOOM icon, then click graph select first point (the point left corner zoom box). Then click graph again select second point (the point bottom right corner zoom box). Once area been zoomed OUTPUT functions
DS246DB1
CDB5529
used print hard copy that region. Click RESTORE when done with zoom function. ZOOM: description Histogram Window Overview. AVG: Displays number FFT's averaged current display.
Frequency Domain Window (i.e. FFT)
following describe controls indicators associated with Frequency Domain Window. CANCEL: description Histogram Window Overview. COLLECT: description Histogram Window Overview. CONFIG: description Histogram Window Overview. FREQUENCY: Displays x-axis value cursor display. MAGNITUDE: Displays y-axis value cursor display. OUTPUT: description Histogram Window Overview. S/D: Indicator Signal-to-Distortion Ratio, harmonics used calculations (decibels). S/N+D: Indicator Signal-to-Noise Distortion Ratio (decibels). SNR: Indicator Signal-to-Noise Ratio, first harmonics included (decibels). S/PN: Indicator Signal-to-Peak Noise Ratio (decibels). TEST: description Histogram Window Overview.
Time Domain Window Overview
following controls indicators associated with Time Domain Window. CANCEL: description Histogram Window Overview. COLLECT: description Histogram Window Overview. CONFIG: description Histogram Window Overview. COUNT: Displays current x-position cursor time domain display. MAGNITUDE: Displays current y-position cursor time domain display. MAXIMUM: Indicator maximum value collected data set. MINIMUM: Indicator minimum value collected data set. OUTPUT: description Histogram Window Overview. TEST: description Histogram Window Overview. ZOOM: description Histogram Window Overview.
DS246DB1
CDB5529
Trouble Shooting Evaluation Board
This section describes special test modes incorporated microcontroller software diagnose hardware problems with evaluation board.
Note: enter these modes, test switches appropriate position reset evaluation board. reenter normal operation mode, switches back binary zero reset board again.
Test Mode Reserved future modifications. Test Mode Continuously Read Gain Register: This test mode repetitively acquires gain registers default contents (0x400000 HEX). enter this mode, test switches press reset. LED's should indicate binary five. probing HDR6 using triggering pin, oscilloscope logic analyzer will display realtime microcontroller acquires conversion. Test Mode Microcontroller RS-232 Communication Link Test: This test mode tests ability communicate evaluation board. consists subtests: test link between RS-232 interface circuitry; test RS-232 link between microcontroller. HDR7 distinguishes these subtests. HDR7 Normal test complete communication link. HDR7 Loop Back test link between RS-232 Circuitry Then, test switches reset evaluation board. LED's should indicate binary signifying that hardware ready initiate test. complete test, user must initialize First, SETUP menu select communications port then select TESTRS232 option. From there, user prompts navigate user through test. indicates test passes fails. Once either test complete, LED's toggle indicate that test mode complete. Test Mode Toggle LED's: This test mode tests evaluation board LED's. enter this mode, test switches reset board. mode passes, LED's toggle.
Note: Remember, return normal operating mode, test switches binary zero, return HDR7 Normal, reset evaluation board.
Test Mode Normal Mode: This default mode operation. enter this mode, test switches reset board. evaluation board allows normal read/writes ADC's registers. LED's toggle then after reset, then only when communicating with Test Mode Loop Back Test: This test mode checks microcontroller's on-chip UART. enter this mode, test switches 001, HDR7 loop back, then reset board. communication works, LED's toggle. Otherwise, only LED's toggle indicate communication problem. Test Mode Read/Write ADC: This test mode tests microcontroller's ability read write ADC. enter this mode, switches reset board. this test mode, ADC's configuration, offset, gain registers written then read from. correct data read back, LED's toggle. Otherwise, only half them toggle indicate error. Test Mode Continuously Acquire Single Conversion: This test mode repetitively acquires single conversion. enter this mode, test switches press reset. binary three indicated LED's. probing HDR6 using triggering pin, oscilloscope logic analyzer will display real-time microcontroller reads conversion data.
DS246DB1
CDB5529
Figure Main Menu
Figure Input/Output Window
DS246DB1
CDB5529
Figure Frequency Domain Analysis
Figure Configuration Menu
DS246DB1
CDB5529
Figure Time Domain Analysis
Figure Histogram Analysis
DS246DB1
CDB5529
Figure CDB5529 Component Side Silkscreen
DS246DB1
CDB5529
Figure CDB5529 Component Side (top)
DS246DB1
CDB5529
Figure CDB5529 Solder Side (bottom)
DS246DB1
Notes

16-Bit, Programmable with 6-Bit Latch Features General Descriptio

Top Searches for this datasheet

Other recent searches