EA-208E 8-Port Ethernet Access Controller (XpressFlow2001 Series

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EA-208E 8-Port Ethernet Access Controller (XpressFlow2001 Series

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EA-208E 8-Port Ethernet Access Controller
(XpressFlow2001 Series 10/100 Ethernet Switch Chipset)
DISTINCTIVE CHARACTERISTICS independent 10Mbps Ethernet Access Ports
Direct interface with 10BaseT transceiver
State micron Volt CMOS process 352-BGA package Operating frequency maximum maximum maximum
10BaseT Phyiscal Layer Transceiver LOCAL BUFFER MEMORY XPRESSFLOW
MANAGEMENT
EA-208 8-Port Ethernet Access Controller
Port Port Port Port Port Port Port Port
32-bit Local Buffer Memory Interface Supports 128k bytes Utilize high performance 32-bit Synchronous Burst SRAM
Hardware assisted Buffer Queue Management minimized overhead 16-bit Management Interface Allows host access Control Registers Local Buffer Memory Supports Little Endian CPUs Direct interface with various different standard microprocessors including 386, families Motorola series embedded processors Uses Granule frame transferring between Access Controllers Also detects IEEE 802.3X Control frames Capable forward frames full line-rate Distributed Flow Cachingto reduce frame forwarding latency
10BaseT Ports
Automatically selects optimized mode forwarding Allows manual frame forwarding mode selection override Four frame transmission priority queues Assigns unique Address each port Auto padding necessary after stripping Transmit collision Transmit buffer under-run
Multi-Media ready with supports Complies with IEEE 802.1 Bridge Standard VLAN Tagging Stripping Automatic retry frame transmission
32-bit XpressFlow Interface
Supports unicast, multicast, broadcast frames Works together with SC-201 XpressFlow Engine
Supports both Half Full Duplex operation Programmable Flow Control Collision Half Duplex Mode Transmit Flow Control Frame IEEE 802.3x Full Duplex Mode
Automatic receive filtering frames Store Forward Mode Short events frames under bytes Long events frames over 1518/1522 bytes
Three frame forwarding modes
Automatic statistic collection RMON
Store-&-Forward Safe Cut-Thru (Runt Free) Turbo Cut-Thru
1997 9(57(; 1(7:25.6
Page:
Rev. 4.0- December, 1997
XpressFlow 2001 Series Ethernet Switch Chipset
EA-208E 8-Port Ethernet Access Controller
GENERAL DESCRIPTION:
EA-208E provides eight 10Mbps Ethernet network access interface ports. EA-208E provides Ethernet protocols, handles local buffer memory interface management, arbitrates among multiple priority queues, interfaces with XpressFlow Engine other Access Controllers through XpressFlow message passing protocol.
XPRESSFLOW
MANAGEMENT
EA-208E
Local Buffer Memory Local Buffer Memory Interface
XpressFlow Interafce
Management Interafce
Automatic Buffer Manager
Interface
Port
Related Components:
Port
SC-201 XpressFlow Engine EA208 port Ethernet Access Controller EA-222 2-port 10/100 Fast Ethernet Access Controller EA-224 4-port 10/100 Fast Ethernet Access Controller
Port
8-Port 10BaseT
Block Diagram EA-208E Ports Ethernet Access Controller
Typical Application:
18-port Ethernet Switch with Fast Ethernet Up-Links
Address Mapping Table
RS232 Local Control Console
Buffer
SC201 XpressFlow Engine
Flash
Switch Manager
DRAM
Management XpressFlow
Buffer
EA208E 8-Port Ethernet Access Controller
Buffer
EA208E 8-Port Ethernet Access Controller
Buffer
EA224 4-Port Ethernet Access Controller
Ethernet ports
Ethernet ports
Ethernet 100M Fast Ethernet ports
System Block Diagram 18-Port Ethernet Switch with Fast Ethernet Up-Links
1997 9(57(; 1(7:25.6
Page:
Rev. December, 1997
XpressFlow 2001 Series Ethernet Switch Chipset
EA-208E 8-Port Ethernet Access Controller
INFORMATION
Logic Symbol
EA-208E
Control Buffer Memory Interface
L_D[31:0] L_A[18:2] L_BWE[3:0]# L_WE[3:0]# L_OE[3:0]# L_ADSC# L_CLK P_D[15:0] P_A[11:1] P_CS# P_ADS# P_RWC P_BS16# P_RDY# P_INT P_RST# P_CLK S_D[31:0] S_MSGEN# S_EOF# S_IRDY S_TABT# S_OVLD# S_HPREQ# S_REQ# S_GNT# S_CLK
Test
T_MODE Tm_RXD Tm_RXC Tm_TXC Tm_TXEN Tm_TXD Tm_LPBK Tm_FD Tm_COL Tm_CRS Tm_LNK
1997 9(57(; 1(7:25.6
XpressFlow Interface
Management Interface
Page:
Port [7:0] Serial Interface
Rev. December, 1997
XpressFlow 2001 Series Ethernet Switch Chipset Assignment
Note:
Input In-ST Output Out-OD I/O-TS I/O-OD
EA-208E 8-Port Ethernet Access Controller
Active signal Input signal Input signal with Schmitt-Trigger Output signal (Tri-State driver) Output signal with Open-Drain driver Input Output signal with Tri-State driver Input Output signal with Open-Drain driver Input with Tolerance Output signal with programmable polarity. Input output pins with weak internal pull resistors (50k 100k Ohms each) These pins reserved internal only. They should left unconnected.
Name Functions 16mA Management Data [15:0]
No(s).
Symbol
Type I/O-TS (5VT)
Management Interface P_D[15:0] J25,K26,L24,K25,L26, M24,L25,M26,N24,M25, P24,N26,N25,R24,P26, C26,D24,C25,E24,D26, P_A[11:1] D25,F24,E26,E25,G24, P_ADS# P_RWC P_RDY# P_BS16# P_CS# P_INT P_RST#
P_CLK
(5VT)
Management Address [11:1]
(5VT) (5VT) Out-OD Out-OD (5VT) CMOS Output In-ST (5VT) (5VT) CMOS I/O-TS
16mA 16mA
Management Address Strobe Management Read/Write Control Management Data Ready Management Data Management Chip Select Management Interrupt Request Management Master Reset Management Clock
XpressFlow Interface C23,A23,B22,C22,A22 S_D[31:27] P_C[0:4]
B21,D20,C21,A21,B20, A20,C20,B19,A19,C19, B18,A18,B17,C18,A17, D17,B16,C17,A16,B15, A15,C16,B14,D15,A14, C15,B13 S_D[26:0]
CMOS I/O-TS
XpressFlow Data [31:27] Management Interface Configuration [0:4] 12mA XpressFlow Data [26:0]
S_MSGEN# S_EOF# S_IRDY S_TABT# S_HPREQ# S_REQ# S_GNT# S_OVLD# S_CLK
CMOS I/O-TS CMOS I/O-TS CMOS I/O-TS CMOS I/O-OD CMOS I/O-OD CMOS Output CMOS Input CMOS Input CMOS Input
12mA 12mA
XpressFlow Message Envelope XpressFlow Frame XpressFlow Initiator Ready XpressFlow Target Abort XpressFlow High Priority Request XpressFlow Request SC201 XpressFlow Grant from SC201 XpressFlow Overload XpressFlow Clock
1997 9(57(; 1(7:25.6
Page:
Rev. December, 1997
XpressFlow 2001 Series Ethernet Switch Chipset
EA-208E 8-Port Ethernet Access Controller
Type Name Functions
No(s).
Symbol
Control Buffer Memory Interface M4,N2,L3,M1,M2,L1,K3, L_D[31:0] I/O-TS L2,K4,K1,J3,K2,J1,J2, H3,H1,H2,G3,G1,G2,F1, F3,F2,E1,E3,E2,D1,D3, D2,C1,C2,B1 CMOS Output A6,B6,C8,A7,D8,D7,C9, L_A[18:2] A8,B8,A9,C10,B9,D10, A10,C11,B10,A11 L_A[19] CMOS Output L_OE[3]# D5,A5,A3 L_OE[2:0]# CMOS Output D7,E4,B5,C4 L_WE[3:0]# CMOS Output C6,B4,A4,C5 L_BWE[3:0]# CMOS Output
L_ADSC# L_CLK CMOS Output CMOS Output (5VT) (5VT) (5VT) (5VT) (5VT) CMOS
Local Memory Data [31:0]
Local Memory Address [17:2]
Local Memory Address [19] Memory Read Chip Select Local Memory Read Chip Select [2:0] Local Memory Write Chip Select [3:0] Local Memory Byte Write Enable, Byte [3:0] Local Memory Controller Address Status Local Memory Clock input Receive Data (one each 10Mbps Serial Interface Port) Receive Clock (one each 10Mbps Serial Interface Port) Transmit Clock (one each 10Mbps Serial Interface Port) Transmit Enable (one each 10Mbps Serial Interface Port) Transmit Data (one each 10Mbps Serial Interface Port) Loop Back Enable (one each 10Mbps Serial Interface Port)
Ethernet Access Port cont. [7:0] AF20,AE17,AD12,AD9, T[7:2]_RXD AC2,T25 AC25,AF6 T[1:0]_RXD AD19,AD16,AE14,AF10, T[7:2]_RXC AC21,U24 AC24,AE7 T[1:0]_RXC AF18,AD14,AE12,AF8, T[7:0]_TXC W2,AA25,AE22,AD1 AE19,AF15,AF12,AD8, T[7:2]_TXEN W1,AA24 AF22,AF2 T[1:0]_TXEN AE20,AF16,AF13,AE10, T[7:2]_TXD Y1,W25 AF23,AE4 T[1:0]_TXD AD18,AD15,AE13,AF9, T[7:2]_LPBK Y2,Y26 AE23,AF3 T[1:0]_LPBK
AF19,AE16,AD11,AE9, V3,AA26 AD21,AE3 AD17,AE15,AF11,AE8, V1,AB26 AD20,AC23 AE18,AD13,AD10,AD7, U3,AB24, AF21,AD2 AF17,AF14,AE11,AF7, V2,AB25, AE21,AB3
CMOS Output CMOS CMOS Output CMOS
CMOS Output T[7:2]_FD CMOS T[1:0]_FD CMOS Output T[7:2]_COL (5VT)
T[1:0]_COL T[7:2]_CRS T[1:0]_CRS T[7:2]_LNK (5VT) (5VT) (5VT)
Full Duplex Mode (one each 10Mbps Serial Interface Port) Collision Detected (one each 10Mbps Serial Interface Port) Carrier Sense (one each 10Mbps Serial Interface Port) Link Status (one each 10Mbps Serial Interface Port)
(5VT) T[1:0]_LNK (5VT)
1997 9(57(; 1(7:25.6
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Rev. December, 1997
XpressFlow 2001 Series Ethernet Switch Chipset
EA-208E 8-Port Ethernet Access Controller
Type CMOS I/O-TS Name Functions
No(s).
Symbol T_MODE
Test Facility
N1,M3,P2,P1,N3,R2,P3, T_D[15:10] R1,T2,R3,T1,R4,U2,T3, U1,U4 No(s). Symbol
CMOS Output
Type Power
Test Test Mode upon Reset, provides test status output during test mode Test Pins Reserved internal only
Name Functions +3.3 Volt Supply
Power Pins D6,D11,D16,D21,F4, F23,L4,L23,T4,T23,AA4, AA23,AC6,AC11,AC16, AC21 A1,A2,A26,B2,B25,B26, C3,C24,D4,D9,D14,D19, D23,H4,J23,N4,P23,V4, W23,AC4,AC8,AC13, AC18,AC23,AD3,AD24, AE1,AE2,AE25,AF1, AF25
Power
Ground
1997 9(57(; 1(7:25.6
Page:
Rev. December, 1997
XpressFlow 2001 Series Ethernet Switch Chipset Reference Table: (352 BGA)
Signal Name P_A[1] P_A[2] P_A[3] P_A[4] P_A[5] P_A[6] P_A[7] P_A[8] P_A[9] P_A[10] P_A[11] P_ADS# P_CS# P_RWC P_BS16# P_RDY# P_RST# P_INT P_CLK P_D[0] P_D[1] P_D[2] P_D[3] P_D[4] P_D[5] P_D[6] P_D[7] P_D[8] P_D[9] P_D[10] P_D[11] P_D[12] P_D[13] P_D[14] P_D[15] S_CLK S_OVLD# S_HPREQ# S_REQ# S_GNT# S_MSGEN# S_EOF# S_IRDY S_TABT# S_D[0] S_D[1] S_D[2] S_D[3] S_D[4] S_D[5] S_D[6] S_D[7] S_D[8] S_D[9] S_D[10] S_D[11] S_D[12] Signal Name S_D[13] S_D[14] S_D[15] S_D[16] S_D[17] S_D[18] S_D[19] S_D[20] S_D[21] S_D[22] S_D[23] S_D[24] S_D[25] S_D[26] S_D[27] P_C[4] S_D[28] P_C[3] S_D[29] P_C[2] S_D[30] P_C[1] S_D[31] P_C[0] L_A[2] L_A[3] L_A[4] L_A[5] L_A[6] L_A[7] L_A[8] L_A[9] L_A[10] L_A[11] L_A[12] L_A[13] L_A[14] L_A[15] L_A[16] L_A[17] L_A[18] L_A[19] OE[3]# L_OE[2]# L_OE[1]# L_OE[0] L_WE[3]# L_WE[2]# L_WE[1]# L_WE[0]# L_BWE[3]# L_BWE[2]# L_BWE[1]# L_BWE[0]# L_ADSC# L_CLK L_D[0] L_D[1] L_D[2] L_D[3] L_D[4] L_D[5] L_D[6] AE21 AF21 AD20 AD21 AE23 AF23 AF22 AE22 AC24 AC25 AB25 AB24 AB26 AA26 AA24 AA25
EA-208E 8-Port Ethernet Access Controller
Signal Name L_D[7] L_D[8] L_D[9] L_D[10] L_D[11] L_D[12] L_D[13] L_D[14] L_D[15] L_D[16] L_D[17] L_D[18] L_D[19] L_D[20] L_D[21] L_D[22] L_D[23] L_D[24] L_D[25] L_D[26] L_D[27] L_D[28] L_D[29] L_D[30] L_D[31] T0_LNK T0_CRS T0_COL T0_FD T0_LPBK T0_TXD T0_TXEN T0_TXC T0_RXC T0_RXD T1_LNK T1_CRS T1_COL T1_FD T1_LPBK T1_TXD T1_TXEN T1_TXC T1_RXC T1_RXD T2_LNK T2_CRS T2_COL T2_FD T2_LPBK T2_TXD T2_TXEN T2_TXC T2_RXC T2_RXD T3_LNK T3_CRS
Note:
Output signals with programmable polarity. Input output pins with weak internal pull resistors (50k 100k Ohms each) These pins reserved internal only. They should left unconnected.
AE10 AF10 AE11 AD10 AF11 AD11 AE13 AF13 AF12 AE12 AE14 AD12 AF14 AD13 AE15 AE16 AD15 AF16 AF15 AD14 AD16 AE17 AF17 AE18 AD17 AF19 AD18 AE20 AE19 AF18 AD19 AF20
Signal Name T3_COL T3_FD T3_LPBK T3_TXD T3_TXEN T3_TXC T3_RXC T3_RXD T4_LNK T4_CRS T4_COL T4_FD T4_LPBK T4_TXD T4_TXEN T4_TXC T4_RXC T4_RXD T5_LNK T5_CRS T5_COL T5_FD T5_LPBK T5_TXD T5_TXEN T5_TXC T5_RXC T5_RXD T6_LNK T6_CRS T6_COL T6_FD T6_LPBK T6_TXD T6_TXEN T6_TXC T6_RXC T6_RXD T7_LNK T7_CRS T7_COL T7_FD T7_LPBK T7_TXD T7_TXEN T7_TXC T7_RXC T7_RXD T_MODE T_D[0] T_D[1] T_D[2] T_D[3] T_D[4] T_D[5] T_D[6]
AA23 AC11 AC16 AC21 AC13 AC18 AC23 AD24 AE25 AF25
Signal Name T_D[7] T_D[8] T_D[9] T_D[10] T_D[11] T_D[12] T_D[13] T_D[14] T_D[15]
1997 9(57(; 1(7:25.6
Page:
Rev. December, 1997
XpressFlow 2001 Series Ethernet Switch Chipset
EA-208E 8-Port Ethernet Access Controller
FUNCTIONAL DESCRIPTION
Local Memory (Local Buffer Memory) Interface
Uses industry standard Synchronous Burst Mode SRAM bytes 128k 256k Provides separate Read Write Chip Selects L_OE[3:0]# L_WE[3:0]# each memory chip Supports back back Read Write operations across memory chips
4.1.1 Description
Symbol L_D[31:0] L_A[18:2] Type Name Functions
I/O-TS
Local Memory Data [31:0] 32-bit synchronous data bus.
L_A[19] L_OE[3]#
L_OE[2:0]# L_WE[3:0]# L_BWE[3:0]# L_ADSC# L_CLK
CMOS Local Memory Address [18:2] [18:2] synchronous Output address bus. memory address sampled when L_CS# enabled L_ADSC# asserted. CMOS Local Memory Address [19] Local Memory Read Chip Output Select Depends memory configuration, this used Local Memory Address [19] Local Memory Read Chip Select [3]. CMOS Local Memory Read Chip Select [2:0] allows read Output banks memory. CMOS Local Memory Write Chip Select [3:0] allows write Output banks memory. CMOS Local Memory Byte Write Enable [3:0] write individual bytes. Output CMOS Local Memory Controller Address Status load address. Output CMOS Local Memory Clock synchronous clock memory devices. Output
Note:
These pins have weak internal pull resistors (50k 100k Ohms each).
1997 9(57(; 1(7:25.6
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Rev. December, 1997
XpressFlow 2001 Series Ethernet Switch Chipset
4.1.2 Supported Memory Configurations
EA-208E 8-Port Ethernet Access Controller
Read/Write Chip Select High Address Bits
Chip Chip Chip Chip
L_A[19] Chip Total Buffer L_WE[2]# L_OE[2]# L_WE[1]# L_OE[1]# L_WE[0]# L_OE[0]# L_WE[3]# L_OE[3]# Size Chips Memory Size 128k 256k 128k bytes 256k bytes 512k bytes 256k bytes 512k bytes bytes 512k bytes bytes bytes -L_WE[0]# L_OE[0]#
L_WE[1]# L_OE[1]# L_WE[0]# L_OE[0]#
L_WE[3]# L_OE[3]# L_WE[2]# L_OE[2]# L_WE[1]# L_OE[1]# L_WE[0]# L_OE[0]# -L_WE[0]# L_OE[0]#
L_WE[1]# L_OE[1]# L_WE[0]# L_OE[0]#
L_WE[3]# L_OE[3]# L_WE[2]# L_OE[2]# L_WE[1]# L_OE[1]# L_WE[0]# L_OE[0]# -L_A[19] -L_WE[0]# L_OE[0]#
L_WE[1]# L_OE[1]# L_WE[0]# L_OE[0]# -L_WE[0]# L_OE[0]#
4.1.3 Cycle Waveforms
L_CLK L_ADSC# L_CS# L_A[19:2] L_WE[3:0]# L_BWE[3:0]# L_OE[3:0]#
A3+1
A3+2
A3+3
A4+1
A4+2
A4+3
L_D[31:0] (Wr)
D3+1
D3+2
D3+3
L_D[31:0] (Rd)
D4+1
D4+2
D4+3
Typical Local Memory Access Operations
1997 9(57(; 1(7:25.6
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Rev. December, 1997
XpressFlow 2001 Series Ethernet Switch Chipset Management Interface
EA-208E 8-Port Ethernet Access Controller
Supports 16-bit Data Supports early cycle Meets timing requirement Intel/AMD family processors Supports Clock Clock family processors Provides single interrupt signal Switch Manager
Supports various industry standard microprocessors including: Intel 186, 386, family equivalent Motorola series embedded processors Easily adapts other industry standard CPUs Provides separate Address Data Supports Little Endian byte ordering
4.2.1 Description
Symbol P_C[4:0] Type Name Functions CMOS Input Processor Configuration [4:0]: During Reset Cycle, P_C[4:0] pins provides processor configuration. using external weak pull-up -down resistors, they define External Management Interface Configuration. These inputs sampled trailing edge Reset cycle.
C[0] Defines Clock input clock C[1] Selects either Little Endian byte ordering C[2] Defines polarity P_RWC (Rd/Wr Control) input C[3] Defines width EA-208, default 16-bit interface, setting this ignored. C[4] Defines timing relationship between P_RDY P_D[15:0] valid. C[4] High, P_D[15:0] valid along same clock period P_RDY asserted. C[4] Low, P_RDY asserted clock period early ahead P_D[15:0] valid. C[0] Clock Clock Clock C[1] Byte Order Little Endian Endian C[2] P_R/W# P_W/R# C[3] Size C[4] Timing Normal Early
P_A[11:1] (5VT) P_D[15:0] I/O-TS (5VT) P_ADS# (5VT) P_RWC Input (5VT)
After RESET, these pins used XpressFlow Data [31:27]. Address [11:1] port address Data [15:0] 16-bit synchronous data bus.
Address Strobe indicates valid address Read/Write Control indicates current cycle read write cycle. C[1] defines polarity this signal during Reset cycle.
C[1]=Low C[1]=High P_R/W# used PowerPC other similar processors. P_W/R# used 386, other similar processors
P_RDY# Out-OD Data Ready timing indicates data valid P_BS16# Out-OD Size response master that EA208 only supports 16bit data width. P_CS# Input Chip Select indicates XpressFlow Engine target cur(5VT) rent operation. P_INT CMOS Out- Interrupt Request Switch Manager polarity this signal output programmable chip configuration register. P_RST# In-ST Reset Synchronous reset Input from Switch Manager (5VT) P_CLK (5VT) Clock Clock family, Clock others
1997 9(57(; 1(7:25.6
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Rev. December, 1997
XpressFlow 2001 Series Ethernet Switch Chipset
EA-208E 8-Port Ethernet Access Controller
4.2.2 Motorola MPC801 Processor Interface
P_CLK {CLKOUT} P_ADS# {TS#} P_A[11:1] {A[20:30]} P_CS# P_RWC {RD/WR#} P_RDY# {TA#} P_D[15:0] {D[0:15]} (in) P_D[15:0] {D[0:15]} (out)
Note: Mnemonics within equivalent signals defined MPC801
Typical Motorola MPC801 Access Operations
4.2.3 Intel Processor Interface
P_CLK P_ADS# P_A[11:1] P_CS# P_W/R# P_RDY# P_D[15:0] (in)
P_D[15:0] (out)
Typical Access Operations
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XpressFlow 2001 Series Ethernet Switch Chipset
4.2.4 Intel Processor Interface
P_CLK
EA-208E 8-Port Ethernet Access Controller
(internal)
P_ADS#
P_A[11:1]
P_CS#
P_W/R#
P_RDY#
P_D[15:0] (in)
P_D15:0] (out)
Typical Access Operations
P_CLK
(internal) P_RST#
Internal Clock Synchronization
Note: Intel Processor Data Book more details
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XpressFlow 2001 Series Ethernet Switch Chipset
4.2.5 Register
Note:
EA-208E 8-Port Ethernet Access Controller
32-bit registers D-word aligned. 16-bit registers also D-word aligned right justified. Little Endian CPUs, register offset [1,0] always Endian CPUs, register offset [1,0] always operation.
This Global Register. allowed write Global Register devices sind These registers reserved system diagnostic usage only.
Offset
Register Description
Little Endian Endian hF00 hF00 hF10 hF20 hF30 hF40 hF70 hF80 hF90 hFA0 hFB0 hE08 hE18 hE28 hE40 hE50 hE68 hE6C hE68 hE6C hD00 hD30 hD90 hDA0 hDB0 hF02 hF02 hF12 hF22 hF32 hF42 hF72 hF82 hF92 hFA2 hFB2 hE08 hE18 hE28 hE42 hE52 hE68 hE6C hE68 hE6C hD02 hD32 hD92 hDA2 hDB2
Reg.
Note:
Size 16-bit 16-bit 16-bit 16-bit 16-bit 16-bit 16-bit 16-bit 16-bit 16-bit 16-bit 32-bit 32-bit 32-bit 16-bit 16-bit 32-bit 32-bit 32-bit 32-bit 16-bit 16-bit 16-bit 16-bit 16-bit W/-/R W/-W/R W/-W/-/R
Device Configuration Registers (DCR) Global Control Register DCR0 Device Status Register DCR1 Signature Revision Register DCR2 Register DCR3 Device Configuration Register DCR4 Interfaces Status Register DTSR Test Register Interrupt Controls Interrupt Status Register Unmasked ISRM Interrupt Status Register Masked IMSK Interrupt Mask Register Interrupt Acknowledgment Register Buffer Memory Interface MWAR Memory Write Address Reg. Single Cycle MRAR Memory Read Address Reg. Single Cycle MBAR Memory Address Register Burst Mode MWBS Memory Write Burst Size D-words) MRBS Memory Read Burst Size D-words) MWDR Memory Write Data Register MWDX Memory Write Data Reg. Byte Swapping MRDR Memory Read Data Register MRDX Memory Read Data Reg. Byte Swapping Buffer Stack Management FCBBA Frame Control Buffer Base Address FCBAG Frame Control Buffer Buffer Aging Status FCBSL Frame Ctrl Buffer Stack Size Limit FCBST Frame Ctrl Buffer Stack Buffer Threshold FCBSS Frame Ctrl Buffer Stack Allocation Status
1997 9(57(; 1(7:25.6
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Rev. December, 1997
XpressFlow 2001 Series Ethernet Switch Chipset
EA-208E 8-Port Ethernet Access Controller
Offset
Register Description
Little Endian Endian hC00 hC10 hC20 hC30 hC70 hC80 hC90 hCA0 hCB0 hCC0 hCD0 hCE0 hC02 hC12 hC22 hC32 hC72 hC82 hC92 hCA2 hCB2 hCC2 hCD2 hCE2
Reg.
Note:
Size 16-bit 16-bit 16-bit 16-bit 16-bit 16-bit 16-bit 16-bit 16-bit 16-bit 16-bit 16-bit W/-W/R
Access Control Function (Chip Level controls) AVXR VLAN Control Table (VCT) Index Register AVDR Data Register AVTC VLAN Type Code AXSC Transmission Scheduling Control Register AFCR Flow Control Register AMAR0 Multicast Address. Control Frames Byte [1,0] AMAR1 Byte [3,2] AMAR2 Byte [5,4] AMCT Control FrameType Code Register ADAR0 Base Address Register Byte [1,0] ADAR1 Base Address Register Byte [3,2] ADAR2 Base Address Register Byte [5,4]
Ethernet Port Control Registers (substitute with Port Number, {0.7} ECR0 Port Control Register hn00 hn02 16-bit ECR1 Port Configuration Register hn10 hn12 16-bit ECR2 Port Interrupt Mask Register hn20 hn22 16-bit ECR3 Port Interrupt Status Register hn30 hn32 16-bit EXSR Status Register hn40 hn42 16-bit EXEC Error Counters hn50 hn52 16-bit ERSR Status Register hn68 hn68 32-bit EREC Error Counters hn78 hn78 32-bit
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Rev. December, 1997
XpressFlow 2001 Series Ethernet Switch Chipset XpressFlow Interface
EA-208E 8-Port Ethernet Access Controller
Vertex's optimized XpressFlow architecture Provides 1.6G switching bandwidth 1.07G 1.28G 1.60G
level request priorities High priority Data Messages forwarding Ethernet frame from receiving port transmission port priority Command Messages passing control information between devices
Full multi master structure Allows Access Controllers communicate with XpressFlow Engine other Access Controllers message passing protocol
4.3.1 Description
Symbol S_D[31:0] Type Name Functions
S_MSGEN#
S_EOF#
S_IRDY
S_TABT# S_HPREQ# S_REQ# S_GNT# S_OVLD#
S_CLK
CMOS Data [31:0] 32-bit synchronous data bus. I/O-TS Note: During system RESET period, Data [31:27] used Processor Interface Configuration [0:3] CMOS Message Envelope encompasses entire period message I/O-TS transfer. Targets leading edge this signal detect beginning message transfer, decode message header intended target(s). CMOS Frame only used frame data transfer messages identify I/O-TS frame condition. This signal synchronous with Frame Status word appended message. CMOS Initiator Ready normal true signal. When negated, indicates I/O-TS initiator asserted wait state(s) between command words. Target should this signal enable signal latching data from bus. CMOS Target Abort when asserted, target aborted reception I/O-OD current message bus. CMOS High Priority Request indicates more Requester reI/O-OD questing high priority message transfer. CMOS Request Request signal from Access Controller AcOutput cess Arbitrator XpressFlow Engine CMOS Grant Grant signal from Arbitrator Requester Input CMOS Over-load when asserted, data forwarding bandwidth Input been allocated. Cannot support additional load data forwarding traffic. CMOS XpressFlow Clock 50MHz system clock Input
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XpressFlow 2001 Series Ethernet Switch Chipset
4.3.2 Cycle Waveforms
S_CLK
EA-208E 8-Port Ethernet Access Controller
S_MSGEN#
S_D[31:0]
S_EOF#
S_IRDY
XpressFlow Data Transfer Cycle
S_CLK
S_MSGEN#
S_D[31:0]
S_EOF#
S_TABT#
Command Cycle
Data Xfer Data
Aborted Command
Other XpressFlow Cycles
S_CLK S_REQ[k]# S_REQ[j]# S_HPREQ#
High Priority Request pre-empts priority request
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Rev. December, 1997
XpressFlow 2001 Series Ethernet Switch Chipset
EA-208E 8-Port Ethernet Access Controller
S_CLK
S_MSGEN#
S_REQ[j]#
S_GNT[j]#
S_HPREQ#
S_REQ[I]#
S_GNT[I]#
XpressFlow arbitration
S_CLK
S_REQ[k]#
S_OVLD#
Overload pre-empts data transfer request
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Rev. December, 1997
XpressFlow 2001 Series Ethernet Switch Chipset
EA-208E 8-Port Ethernet Access Controller
10Mbps Serial Interface Port thru Port
Fully compliant with IEEE 802.3 Serial Interface Standard connecting with external 10Mbps Ethernet Physical Layer Transceiver
Supports 10Mbps 10BaseT serial interface Supports both half full duplex operation
4.4.1 Description
Symbol Tn_RXD Tn_RXC Tn_TXC Tn_TXEN Tn_TXD Tn_LPBK Tn_FD Tn_COL Tn_CRS Tn_LNK Type (5VT) (5VT) (5VT) CMOS Output CMOS Output CMOS Output CMOS Output (5VT) (5VT) (5VT) Name Functions
Receive Data (one each Serial Interface Port) receive data stream. Receive Clock (one each Serial Interface Port) from external sampling receive data from Tn_RXD input Transmit Clock (one each Serial Interface Port) continuous clock input with duty cycles. Transmit Enable (one each Serial Interface Port) Transmit Data (one each Serial Interface Port) transmit data stream. Loop Back Enable (one each Serial Interface Port) polarity this signal programmable Port Configuration Register Full Duplex Mode (one each Serial Interface Port) polarity this signal programmable Port Configuration Register Collision Detected (one each Serial Interface Port) Carrier Sense (one each Serial Interface Port) Link Status (one each Serial Interface Port) polarity this signal programmable Port Configuration Register
Note:
port number [7:0] These signals have programmable output polarity.
nsec
TXEN
Serial Interface Transmit Timing
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Rev. December, 1997
XpressFlow 2001 Series Ethernet Switch Chipset
EA-208E 8-Port Ethernet Access Controller
nsec
Serial Interface Receive Timing
Test Pins
Symbol T_MODE Type Name Functions
CMOS Test Mode Selection Test Output Test Mode upon Reset, I/O-TS provides test status output during test mode
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Rev. December, 1997
XpressFlow 2001 Series Ethernet Switch Chipset
EA-208E 8-Port Ethernet Access Controller
SPECIFICATION
ABSOLUTE MAXIMUM RATINGS
Storage Temperature Operating Temperature Supply Voltage with Respect Voltage Tolerant Input Pins Voltage Other Input Pins -50°C +125°C +70°C +3.0 +3.6 -0.5 (VDD -0.5 10%)
Stresses above those listed cause permanent device failure. Functionality above these limits implied. Exposure Absolute Maximum Ratings extended periods affect device reliability.
CHARACTERISTICS
+3.0 +3.6 TAMBIENT +70°C Preliminary Symbol fosc Parameter Description Frequency Operation -33) Frequency Operation -40) Frequency Operation (-50) Supply Power 33.3333 (VDD =3.3 Supply Power (VDD =3.3 Supply Power (VDD =3.3 Output High Voltage (CMOS) maximum Output Voltage (CMOS) maximum Output High Voltage (TTL) maximum Output Voltage (TTL) maximum Input High Voltage (CMOS) Input Voltage (CMOS) Input High Voltage (TTL) Input Voltage (TTL) Input High Voltage (TTL tolerant) Input Voltage (TTL tolerant) Input Leakage Current (0.1 VDD) (all pins except those with internal pullup/pull-down resistors) Output Leakage Current (0.1 VOUT VDD) Input Leakage Current (pins with internal pull-down resistors) Input Leakage Current (pins with internal pull-up resistors) Input Capacitance Output Capacitance Capacitance 33.3333 40.0000 50.0000 0.45 -0.5 -0.3 -0.3 0.45 +0.8 +0.8 Unit
VOH-CMOS VOL-CMOS VOH-TTL VOL-TTL VIH-CMOS VIL-CMOS VIH-TTL VIL-TTL VIH-5VT VIL-5VT
COUT CI/O
Notes:
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Page:
Rev. December, 1997
XpressFlow 2001 Series Ethernet Switch Chipset
EA-208E 8-Port Ethernet Access Controller
SPECIFICATION
XpressFlow Interface:
S_CLK
S_D[31:0] S2-min S_MSGEN# S3-min S_EOF# S4-min S_IRDY S_CLK S1-min
S_D[31:0]
S_MSGEN#
S_EOF#
S_IRDY
XpressFlow Interface Output float delay timing
S_TABT#
S_CLK S1-max S1-min S_D[31:0] S2-max S2-min S_MSGEN# S3-max S3-min S_EOF# S4-max S4-min S_IRDY S6-max S6-min S_TABT# S7-max S7-min S_HPREQ# S8-max S8-min S_REQ#
S_HPREQ#
S_GNT#
S_OVLD#
XpressFlow Interface Input setup hold timing
XpressFlow Interface Output valid delay timing
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Rev. December, 1997
XpressFlow 2001 Series Ethernet Switch Chipset
Symbol Parameter S_D[31:0] output valid delay S_MSGEN# output valid delay S_EOF# output valid delay S_IRDY output valid delay S_TABT# output valid delay S_HPREQ# output valid delay S_REQ# output valid delay S_D[31:0] output float delay S_MSGEN# output float delay S_EOF# output float delay S_IRDY output float delay S_D[31:0] input set-up time S_D[31:0] input hold time S_MSGEN# input set-up time S_MSGEN# input hold time S_EOF# input set-up time S_EOF# input hold time S_IRDY input set-up time S_IRDY input hold time S_TABT# input set-up time S_TABT# input hold time S_HPREQ# input set-up time S_HPREQ# input hold time S_GNT# input set-up time S_GNT# input hold time S_OVLD# input set-up time S_OVLD# input hold time
EA-208E 8-Port Ethernet Access Controller
Note: 50pf 50pf 50pf 50pf 50pf 50pf 20pf
(ns) (ns) (ns) (ns) (ns) (ns)
Characteristics XpressFlow Interface
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Rev. December, 1997
XpressFlow 2001 Series Ethernet Switch Chipset Interface:
P_CLK
P16-min
EA-208E 8-Port Ethernet Access Controller
P_CLK
P_D[31:0]
P_RST#
Interface Output float delay timing
P_CLK
P_ADS#
P_W/R#
P16-max P16-min
P_CS#
P_D[15:0]
P17-max P17-min
P_A[11:1]
P_RDY#
P18-max P18-min
P_D[15:0]
P_INT
Interface Output valid delay timing
Symbol Parameter P_RST# input setup time P_RST# input hold time P_ADS# input set-up time P_ADS# input hold time P_W/R# input set-up time P_W/R# input hold time P_CS# input set-up time P_CS# input hold time P_A[11:1] input set-up time P_A[11:1] input hold time P_D[31:0]# input set-up time P_D[31:0]# input hold time P_D[31:0]# output float delay P_D[31:0]# output valid delay P_RDY# output valid delay P_INT# output valid delay
Interface Input setup hold timing
Note:
(ns) (ns) (ns) (ns) (ns) (ns)
60pf 60pf 20pf
Characteristics Interface
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Rev. December, 1997
XpressFlow 2001 Series Ethernet Switch Chipset Local Memory Interface:
L_CLK
EA-208E 8-Port Ethernet Access Controller
L_CLK
L3-max L3-min
L_D[31:0]
L_D[31:0]
L4-max L4-min
Local Memory Interface Input setup hold timing
L_A[19:2]
L5-max L5-min
L_CS[3:0]# L_CLK
L3-min L6-max L6-min
L_ADSC#
L7-max L7-min
L_D[31:0] L_BWE[3:0]#
Local Memory Interface Output float delay timing
L_WE#]
L8-max L8-min
L9-max L9-min
L_OE#
Local Memory Interface Output valid delay timing
Symbol Parameter L_D[31:0]# input set-up time L_D[31:0]# input hold time L_D[31:0]# output valid delay L_A[19:2] output valid delay L_CS[3:0]# output valid delay L_ADSC# output valid delay L_BWE[3:0]# output valid delay L_WE[3:0]# output valid delay L_OE[3:0]# output valid delay L_D[31:0]# output float delay
Note:
(ns) (ns) (ns) (ns) (ns) (ns)
30pf 30pf 30pf 30pf 10pf 10pf
Characteristics Local Memory Interface
1997 9(57(; 1(7:25.6
Page:
Rev. December, 1997
XpressFlow 2001 Series Ethernet Switch Chipset
EA-208E 8-Port Ethernet Access Controller
PACKAGING INFORMATION
352-PIN (35x35x2.33mm)
I.D.
0.75 0.15 (352X)
24.00 32.00 1.17 35.00 0.20
1.27 31.75
0.56 2.33 +/-0.13 0.60 +/-0.10
This Document contains advance information product under development. Vertex reserves right make changes without notice. 16842 Karman Ave, Suite Irvine, 92606-4950 Tel. 1-714-252-8880, FAX: 1-714-252-8868 Site: www.vertex-networks.com
Rev. 4.0- December, 1997
1997 9(57(; 1(7:25.6

EA-208E 8-Port Ethernet Access Controller (XpressFlow2001 Series

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