DSP56301 Advance Information 24-bit Digital Signal Processor
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Order Number: DSP56301/D Rev. 2/2000
DSP56301
Advance Information
24-bit Digital Signal Processor
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Memory Expansion Area
Triple Timer Host Interface ESSI Interface Interface Program 4096 (Default) Data 2048 (Default) Data 2048 (Default)
Peripheral Expansion Area
Address Generator Unit Six-Channel Unit Bootstrap
External Address Switch External Interface Cache Control
Address
Control
24-Bit DSP56300 Core
External Data Switch
Data
Internal Data Switch EXTAL XTAL Clock Generator RESET PINIT/NMI Program Interrupt Controller Program Decode Controller MODD/IRQD MODC/IRQC MODB/IRQB MODA/IRQA Program Address Generator
Data 24+5656-bit 56-bit Accumulators 56-bit Barrel Shifter
Power Mngmnt JTAG OnCE6
Figure DSP56301 Block Diagram
This document contains information product. Specifications information herein subject change without notice. Motorola, Inc. 2000
CONTENTS
SECTION SECTION SECTION SECTION SECTION SECTION APPENDIX SIGNAL/CONNECTION DESCRIPTIONS SPECIFICATIONS: UDR2 TECHNOLOGY MASKS 2A-1 SPECIFICATIONS: CDR2 TECHNOLOGY MASKS 2B-1 PACKAGING DESIGN CONSIDERATIONS ORDERING INFORMATION POWER CONSUMPTION BENCHMARK
APPENDIX BOOTSTRAP PROGRAM: UDR2 TECHNOLOGY MASKS B1-1 APPENDIX BOOTSTRAP PROGRAM: CDR2 TECHNOLOGY MASKS B2-1 INDEX .Index-1
TECHNICAL ASSISTANCE:
Telephone: Email: Internet:
1-800-521-6274 dsphelp@dsp.sps.mot.com http://www.mot.com/SPS/DSP
Data Sheet Conventions
This data sheet uses following conventions:
OVERBAR "asserted" "deasserted" Examples: Indicates signal that active when pulled (For example, RESET active when low.) Means that high true (active high) signal high that true (active low) signal Means that high true (active high) signal that true (active low) signal high Signal/Symbol Logic State Signal State Voltage1
Note:
True False True False
Asserted Deasserted Asserted Deasserted
VIL/VOL VIH/VOH VIH/VOH VIL/VOL
Values VIL, VOL, VIH, defined individual product specifications.
DSP56301 Technical Data
Features
FEATURES
High Performance DSP56300 Core
66/80/100 million instructions second (MIPS) with 66/80/100 clock 3.0-3.6 Object code compatible with DSP56000 core Highly parallel instruction Data Arithmetic Logic Unit (Data ALU) Fully pipelined 24-bit parallel Multiplier-Accumulator (MAC) 56-bit parallel barrel shifter (fast shift normalization; stream generation parsing) Conditional instructions 24-bit 16-bit arithmetic support under software control
Program Control Unit (PCU) Position Independent Code (PIC) support Addressing modes optimized applications (including immediate offsets) On-chip instruction cache controller On-chip memory-expandable hardware stack Nested hardware loops Fast auto-return interrupts
Direct Memory Access (DMA) channels supporting internal external accesses One-, two-, three- dimensional transfers (including circular buffering) End-of-block-transfer interrupts Triggering from interrupt lines peripherals
Phase Lock Loop (PLL) Allows change power Divide Factor (DF) without loss lock Output clock with skew elimination
Hardware debugging support On-Chip Emulation module Joint Action Test Group (JTAG) Test Access Port (TAP) port Address Trace mode reflects internal Program accesses external port
DSP56301 Technical Data
Features
On-Chip Memories
Program RAM, instruction cache, data RAM, data sizes programmable:
Program Instruction Data Size Cache Size Size
4096 24-bit 3072 24-bit 2048 24-bit 1024 24-bit Notes: 1024 24-bit 1024 24-bit 2048 24-bit 2048 24-bit 3072 24-bit 3072 24-bit
Data Size
2048 24-bit 2048 24-bit 3072 24-bit 3072 24-bit
Instruction Switch Mode2 Cache1
disabled enabled disabled enabled disabled disabled enabled enabled
Controlled Cache Enable (CE) Status Register (SR) Controlled Memory Select (MS) Operating Mode Register (OMR)
192/3K 24-bit bootstrap
Off-Chip Memory Expansion
Data memory expansion 24-bit word memory spaces 24-Bit mode 16-bit memory spaces 16-Bit Compatibility mode Program memory expansion 24-bit words memory space 24-Bit mode 16-bit 16-Bit Compatibility mode External memory expansion port Chip Select Logic glueless interface SRAMs On-chip DRAM Controller glueless interface DRAMs
DSP56301 Technical Data
Target Applications
On-Chip Peripherals
32-bit parallel PCI/Universal Host Interface (HI32), Rev. compliant with glueless interface other DSP563xx buses interface requires only 74LS45-style buffer Enhanced Synchronous Serial Interfaces (ESSI0 ESSI1) Serial Communications Interface (SCI) with baud rate generator Triple timer module forty-two programmable General-Purpose Input/Output (GPIO) pins, depending which peripherals enabled
Reduced Power Dissipation
Very power CMOS design Wait Stop power stand-by modes Fully static logic, operation frequency down (DC) Optimized power management circuitry (instruction-dependent, peripheral-dependent, mode-dependent)
TARGET APPLICATIONS
DSP56301 intended general-purpose digital signal processing, particularly multimedia telecommunication applications, such video conferencing cellular telephony.
DSP56301 Technical Data
Product Documentation
PRODUCT DOCUMENTATION
three documents listed following table required complete description DSP56301 necessary design properly with part. Documentation available from following sources (see back cover detailed information): local Motorola distributor Motorola semiconductor sales office Motorola Literature Distribution Center World Wide (WWW)
Table DSP56301 Documentation
Name DSP56300 Family Manual DSP56301 User's Manual DSP56301 Technical Data Description Order Number
Detailed description DSP56300 family processor core DSP56300FM/AD instruction Detailed functional description DSP56301 memory configuration, operation, register programming DSP56301 features list physical, electrical, timing, package specifications DSP56301UM/AD DSP56301/D
DSP56301 Technical Data
SECTION
SIGNAL/CONNECTION DESCRIPTIONS
SIGNAL GROUPINGS
Table Figure group DSP56301 input output signals according function. DSP56301 operates from supply; however, some inputs tolerate special notice this feature added signal descriptions those inputs.
Table 1-1. DSP56301 Functional Signal Groupings
Functional Group Power (VCC) Ground (GND) Clock Address Data Control Interrupt Mode Control Host Interface (HI32) Extended Synchronous Serial Interface (ESSI) Serial Communication Interface (SCI) Timer JTAG/OnCE Port Notes: Port Ports Port
Number Signals Port
Detailed Description Table Table Table Table Table Table Table Table Table 1-11 Table 1-12 Table 1-13 Table 1-14 Table 1-15 Table 1-16
Port signals define external memory interface port, including external address bus, data bus, control signals. Port signals HI32 port signals multiplexed with GPIO signals. Port signals ESSI port signals multiplexed with GPIO signals. Port signals port signals multiplexed with GPIO signals.
DSP56301 Technical Data
Signal Groupings
Signal/Connection Descriptions
DSP56301
VCCP VCCQ VCCA VCCD VCCN VCCH VCCS Power Inputs: Internal Logic Address Data Control HI32 ESSI/SCI/Timer Grounds: Internal Logic Address Data Control HI32 ESSI/SCI/Timer Interrupt/ Mode Control
MODA/IRQA MODB/IRQB MODC/IRQC MODD/IRQD RESET
Host Interface (HI32) Port1
Universal
Port GPIO
GNDP GNDP1 GNDQ GNDA GNDD GNDN GNDH GNDS EXTAL XTAL CLKOUT PCAP PINIT/NMI
Figure page listing Host Interface/Port Signals
&ORFN
Extended Synchronous Serial Interface Port (ESSI0)2
SC[00-02] SCK0 SRD0 STD0
Port GPIO PC[0-2] Port GPIO PD[0-2] Port GPIO Timer GPIO TIO0 TIO1 TIO2
Port
A[0-23] D[0-23] AA[0-3] RAS[0-3] BCLK BCLK
External Address External Data External Control
Extended Synchronous Serial Interface Port (ESSI1)2
SC[10-12] SCK1 SRD1 STD1
Serial Communications Interface (SCI) Port2
SCLK
Timers3
TIO0 TIO1 TIO2 TRST
JTAG/ OnCE Port
Note:
HI32 port supports non-PCI configurations. Twenty-four these HI32 signals also configured GPIO signals (PB0-PB23). ESSI0, ESSI1, signals multiplexed with Port GPIO signals (PC0-PC5), Port GPIO signals (PD0-PD5), Port GPIO signals (PE0-PE2), respectively. TIO0-TIO2 configured GPIO signals.
Figure 1-1. Signals Identified Functional Group
DSP56301 Technical Data
Signal/Connection Descriptions
Signal Groupings Host Port (HP) Reference
HP10 HP11 HP12 HP13 HP14 HP15 HP16 HP17 HP18 HP19 HP20 HP21 HP22 HP23 HP24 HP25 HP26 HP27 HP28 HP29 HP30 HP31 HP32 HP33 HP34 HP35 HP36 HP37 HP38 HP39 HP40 HP41 HP42 HP43 HP44 HP45 HP46 HP47 HP48 HP49 HP50 PVCL
DSP56301
HAD0 HAD1 HAD2 HAD3 HAD4 HAD5 HAD6 HAD7 HAD8 HAD9 HAD10 HAD11 HAD12 HAD13 HAD14 HAD15 HC0/HBE0 HC1/HBE1 HC2/HBE2 HC3/HBE3 HTRDY HIRDY HDEVSEL HLOCK HPAR HPERR HGNT HREQ HSERR HSTOP HIDSEL HFRAME HCLK HAD16 HAD17 HAD18 HAD19 HAD20 HAD21 HAD22 HAD23 HAD24 HAD25 HAD26 HAD27 HAD28 HAD29 HAD30 HAD31 HRST HINTA PVCL
Universal
HA10 pull-up HDBEN HDBDR HSAK HDAK HDRQ HAEN HIRQ HWR/HRW HRD/HDS pull-up pull-up HD10 HD11 HD12 HD13 HD14 HD15 HD16 HD17 HD18 HD19 HD20 HD21 HD22 HD23 HRST HINTA Leave unconnected
Port GPIO
PB10 PB11 PB12 PB13 PB14 PB15 PB16 PB17 PB18 PB19 PB20 PB21 PB22 PB23 Internal disconnect Internal disconnect Internal disconnect Internal disconnect Internal disconnect Internal disconnect Internal disconnect Internal disconnect Internal disconnect Internal disconnect Internal disconnect Internal disconnect Internal disconnect Internal disconnect Internal disconnect Internal disconnect Internal disconnect Internal disconnect Internal disconnect Internal disconnect Internal disconnect Internal disconnect Internal disconnect Internal disconnect Internal disconnect Internal disconnect Internal disconnect Leave unconnected
Host Interface (HI32)/ Port Signals
Note:
HPxx reference only signal name. GPIO references formerly designated HIOxx have been renamed PBxx consistency with other Motorola DSPs.
Figure 1-2. Host Interface/Port Detail Signal Diagram
DSP56301 Technical Data
Power
Signal/Connection Descriptions
POWER
Table 1-2. Power Inputs
Power Name VCCP Description Power Isolated power Phase Lock Loop (PLL). voltage should well-regulated input should provided with extremely impedance path power rail. There VCCP input. Quiet Power Isolated power internal processing logic. This input must tied externally other chip power inputs. user must provide adequate external decoupling capacitors. There four VCCQ inputs. Address Power Isolated power sections address drivers. This input must tied externally other chip power inputs. user must provide adequate external decoupling capacitors. There VCCA inputs. Data Power Isolated power sections data drivers. This input must tied externally other chip power inputs. user must provide adequate external decoupling capacitors. There four VCCD inputs. Control Power Isolated power control drivers. This input must tied externally other chip power inputs. user must provide adequate external decoupling capacitors. There VCCN inputs. Host Power Isolated power HI32 drivers. This input must tied externally other chip power inputs. user must provide adequate external decoupling capacitors. There VCCH inputs. ESSI, SCI, Timer Power Isolated power ESSI, SCI, timer drivers. This input must tied externally other chip power inputs. user must provide adequate external decoupling capacitors. There VCCS inputs. These designations package-dependent. Some packages connect inputs except VCCP each other internally. those packages, power input, except VCCP, labeled VCC. numbers connections indicated this table minimum values; total connections package-dependent.
VCCQ
VCCA
VCCD
VCCN
VCCH
VCCS
Note:
DSP56301 Technical Data
Signal/Connection Descriptions
Ground
GROUND
Table 1-3. Grounds
Ground Name GNDP Description Ground Ground dedicated use. connection should provided with extremely lowimpedance path ground. VCCP should bypassed GNDP 0.47 capacitor located close possible chip package. There GNDP connection. Ground Ground dedicated use. connection should provided with extremely lowimpedance path ground. There GNDP1 connection. Quiet Ground Isolated ground internal processing logic. This connection must tied externally other chip ground connections. user must provide adequate external decoupling capacitors. There four GNDQ connections. Address Ground Isolated ground sections address drivers. This connection must tied externally other chip ground connections. user must provide adequate external decoupling capacitors. There GNDA connections. Data Ground Isolated ground sections data drivers. This connection must tied externally other chip ground connections. user must provide adequate external decoupling capacitors. There four GNDD connections. Control Ground Isolated ground control drivers. This connection must tied externally other chip ground connections. user must provide adequate external decoupling capacitors. There GNDN connections. Host Ground Isolated ground HI32 drivers. This connection must tied externally other chip ground connections. user must provide adequate external decoupling capacitors. There GNDH connections. ESSI, SCI, Timer Ground Isolated ground ESSI, SCI, timer drivers. This connection must tied externally other chip ground connections. user must provide adequate external decoupling capacitors. There GNDS connections.
GNDP1
GNDQ
GNDA
GNDD
GNDN
GNDH
GNDS
Note:
These designations package-dependent. Some packages connect inputs except GNDP GNDP1 each other internally. those packages, power input, except GNDP GNDP1, labeled GND. numbers connections indicated this table minimum values; total connections package-dependent.
DSP56301 Technical Data
Clock
Signal/Connection Descriptions
CLOCK
Table 1-4. Clock Signals
Signal Name EXTAL Type Input State During Reset Input Signal Description External Clock/Crystal Input Interfaces internal crystal oscillator input external crystal external clock. Crystal Output Connects internal crystal oscillator output external crystal. external clock used, leave XTAL unconnected.
XTAL
Output
Chip Driven
PHASE LOCK LOOP (PLL)
Table 1-5. Phase Lock Loop Signals
Signal Name PCAP Type Input State During Reset Input Signal Description Capacitor Connects off-chip capacitor filter. Connect capacitor terminal PCAP other terminal VCCP. used, PCAP tied GND, left floating. CLKOUT Output Chip-driven Clock Output Provides output clock synchronized internal core clock phase. enabled both multiplication division factors equal one, then CLKOUT also synchronized EXTAL. disabled, CLKOUT frequency half frequency EXTAL. PINIT/NMI Input Input Initial/Non-Maskable Interrupt During assertion RESET, value PINIT/NMI written into Enable (PEN) control register, determining whether enabled disabled. After RESET deassertion during normal instruction processing, PINIT/NMI Schmitttrigger input negative-edge-triggered Non-Maskable Interrupt (NMI) request internally synchronized CLKOUT. PINIT/NMI tolerate
EXTERNAL MEMORY EXPANSION PORT (PORT
DSP56301 Technical Data
Signal/Connection Descriptions
External Memory Expansion Port (Port
Note: When DSP56301 enters low-power stand-by mode (Stop Wait), releases mastership tri-states relevant Port signals: A0-A23, D0-D23, AA0/RAS0- AA3/RAS3, CAS, BCLK, BCLK. hardware refresh external DRAM enabled, Port exits Wait mode allow refresh occur then returns Wait mode.
EXTERNAL ADDRESS
Table 1-6. External Address Signals
Signal Name A0-A23 Type Output State During Reset Tri-stated Signal Description Address When master, A0-A23 specify address external program data memory accesses. minimize power dissipation, A0-A23 change state when external memory spaces being accessed.
EXTERNAL DATA
Table 1-7. External Data Signals
Signal Name D0-D23 Type Input/Output State During Reset Tri-stated Signal Description Data When master, D0-D23 provide bidirectional data external program data memory accesses.
EXTERNAL CONTROL
Table 1-8. External Control Signals
Signal Name AA0-AA3/ RAS0-RAS3 Type Output State During Reset Tri-stated Signal Description Address Attribute Address Strobe these signals function chip selects additional address lines. RAS, these signals function Dynamic Random Access Memory (DRAM) interface. These signals have programmable polarity. Read Enable When master, asserted read external memory data (D0-D23). Write Enable When master, asserted write external memory data D23).
Output
Tri-stated
Output
Tri-stated
DSP56301 Technical Data
External Memory Expansion Port (Port
Signal/Connection Descriptions
Table 1-8. External Control Signals (Continued)
Signal Name BSBS Type Output State During Reset Tri-stated Signal Description Strobe When master, asserted half clock cycle start cycle provide "early start" signal controller. external used during instruction cycle, remains deasserted until next external cycle. Transfer Acknowledge DSP56301 master there external activity, DSP56301 master, input ignored. input Data Transfer Acknowledge (DTACK) function that extend external cycle indefinitely. number wait states 2,., infinity) added wait states inserted keeping deasserted. typical operation, deasserted start cycle, asserted enable completion cycle, deasserted before next cycle. current cycle completes clock period after asserted synchronous CLKOUT. number wait states determined input Control Register (BCR), whichever longer. used minimum number wait states external cycles. functionality, must programmed least wait state. zero wait state access cannot extended deassertion; otherwise improper operation result. operate synchronously asynchronously depending setting Operating Mode Register (OMR). functionality cannot used while performing DRAM type accesses; otherwise improper operation result. Output Output (deasserted) Request Asserted when requests mastership. deasserted when longer needs bus. asserted deasserted independently whether DSP56301 master slave. "parking" allows deasserted even though DSP56301 master (see description "parking" signal description). Request Hold (BRH) allows asserted under software control even though does need bus. typically sent external arbitrator that controls priority, parking, tenure each master same external bus. affected only requests external bus, never internal bus. During hardware reset, deasserted arbitration reset slave state.
Input
Ignored Input
DSP56301 Technical Data
Signal/Connection Descriptions
External Memory Expansion Port (Port
Table 1-8. External Control Signals (Continued)
Signal Name Type Input State During Reset Ignored Input Signal Description Grant Asserted external arbitration circuit when DSP56301 becomes next master, must asserted/deasserted synchronous CLKOUT proper operation. When asserted, DSP56301 must wait until deasserted before taking mastership. When deasserted, mastership typically given current cycle. This occur middle instruction that requires more than external cycle execution. Busy Indicates that active must asserted deasserted synchronous CLKOUT. Only after deasserted pending master become master (and then assert signal again). master keep asserted after ceasing activity, regardless whether asserted deasserted. This called "bus parking" allows current master reuse without re-arbitration until another device requires bus. deasserted "active pull-up" method (that driven high then released held high external pull-up resistor). requires external pull-up resistor. Output Driven high Lock Asserted start external divisible Read-Modify-Write (RMW) cycle, remains asserted between read write cycles, deasserted write cycle. This provides "early start" signal controller. used "resource lock" external multi-port memory secure semaphore updates. Early deassertion provides "early end" signal useful external control. external used during instruction cycle, remains deasserted until next external indivisible cycle. only instructions that automatically assert BSET, CLR, BCHG when they access external memory. operation also assert setting Control Register. Column Address Strobe When master, DRAM uses strobe column address. Otherwise, Mastership Enable (BME) DRAM Control Register cleared, signal tri-stated. Clock When master, BCLK active when set. When BCLK active synchronized CLKOUT internal PLL, BCLK precedes CLKOUT one-fourth clock cycle. Clock When master, BCLK inverse BCLK signal.
Input/ Output
Input
Output
Tri-stated
BCLK
Output
Tri-stated
BCLK
Output
Tri-stated
DSP56301 Technical Data
Interrupt Mode Control
Signal/Connection Descriptions
INTERRUPT MODE CONTROL
interrupt mode control signals select chip's operating mode comes hardware reset. After RESET deasserted, these inputs hardware interrupt request lines.
Table 1-9. Interrupt Mode Control
Signal Name RESET Type State During Reset Input Signal Description
Input
Reset Deassertion RESET internally synchronized clock (CLKOUT). When asserted, chip placed Reset state internal phase generator reset. Schmitt-trigger input allows slowly rising input (such capacitor charging) reset chip reliably. RESET deasserted synchronous CLKOUT, exact start-up timing guaranteed, allowing multiple processors start synchronously operate together "lock-step." When RESET signal deasserted, initial chip operating mode latched from MODA, MODB, MODC, MODD inputs. RESET signal must asserted after power-up. This input tolerant.
MODA
Input
Input
Mode Select Selects initial chip operating mode during hardware reset becomes levelsensitive negative-edge-triggered, maskable interrupt request input IRQA during normal instruction processing. MODA, MODB, MODC, MODD select sixteen initial chip operating modes, latched into when RESET signal deasserted. External Interrupt Request Internally synchronized CLKOUT. IRQA asserted synchronous CLKOUT, multiple processors re-synchronized using WAIT instruction asserting IRQA exit Wait state. processor Stop stand-by state IRQA asserted, processor exits Stop state. These inputs tolerant.
IRQA
Input
MODB
Input
Input
Mode Select Selects initial chip operating mode during hardware reset becomes levelsensitive negative-edge-triggered, maskable interrupt request input IRQB during normal instruction processing. MODA, MODB, MODC, MODD select sixteen initial chip operating modes, latched into when RESET signal deasserted. External Interrupt Request Internally synchronized CLKOUT. IRQB asserted synchronous CLKOUT, multiple processors re-synchronized using WAIT instruction asserting IRQB exit Wait state. processor Stop stand-by state IRQC asserted, processor will exit Stop state. These inputs tolerant.
IRQB
Input
1-10
DSP56301 Technical Data
Signal/Connection Descriptions
Interrupt Mode Control
Table 1-9. Interrupt Mode Control (Continued)
Signal Name MODC Type State During Reset Input Signal Description
Input
Mode Select Selects initial chip operating mode during hardware reset becomes levelsensitive negative-edge-triggered, maskable interrupt request input IRQC during normal instruction processing. MODA, MODB, MODC, MODD select sixteen initial chip operating modes, latched into when RESET signal deasserted. External Interrupt Request Internally synchronized CLKOUT. IRQC asserted synchronous CLKOUT, multiple processors re-synchronized using WAIT instruction asserting IRQC exit Wait state. processor Stop stand-by state IRQC asserted, processor exits Stop state. These inputs tolerant.
IRQC
Input
MODD
Input
Input
Mode Select Selects initial chip operating mode during hardware reset becomes levelsensitive negative-edge-triggered, maskable interrupt request input IRQD during normal instruction processing. MODA, MODB, MODC, MODD select sixteen initial chip operating modes, latched into when RESET signal deasserted. External Interrupt Request Internally synchronized CLKOUT. IRQD asserted synchronous CLKOUT, multiple processors re-synchronized using WAIT instruction asserting IRQD exit Wait state. processor Stop stand-by state IRQD asserted, processor exits Stop state. These inputs tolerant.
IRQD
Input
DSP56301 Technical Data
1-11
Host Interface (HI32)
Signal/Connection Descriptions
HOST INTERFACE (HI32)
Host Interface (HI32) provides fast parallel data 32-bit port that directly connect host bus. HI32 supports variety standard buses directly connect number industrystandard microcomputers, microprocessors, DSPs, hardware.
Host Port Usage Considerations
Careful synchronization required when system reads multiple-bit registers that written another asynchronous system. This common problem when asynchronous systems connected they Host port). considerations proper operation discussed Table 1-10.
Table 1-10. Host Port Usage Considerations
Action Asynchronous read receive byte registers Description When reading receive byte registers, Receive register High (RXH), Receive register Middle (RXM), Receive register (RXL), host interface programmer should interrupts poll Receive register Data Full (RXDF) flag that indicates data available. This assures that data receive byte registers valid. host interface programmer should write transmit byte registers, Transmit register High (TXH), Transmit register Middle (TXM), Transmit register (TXL), unless Transmit register Data Empty (TXDE) set, indicating that transmit byte registers empty. This guarantees that transmit byte registers transfer valid data Host Receive (HRX) register. host interface programmer must change Host Vector (HV) register only when Host Command (HC) clear. This practice guarantees that interrupt control logic receives stable vector.
Asynchronous write transmit byte registers
Asynchronous write host vector
Host Port Configuration
HI32 signal functions vary according programmed configuration interface determined 24-bit Control Register (DCTR). Refer DSP56301 User's Manual detailed descriptions HI32 configuration registers.
1-12
DSP56301 Technical Data
Signal/Connection Descriptions
Host Interface (HI32)
Table 1-11. Host Interface
Signal Name HAD[0-7] Type Input/Output State During Reset Tri-stated Signal Description Host Address/Data When HI32 programmed interface with function selected, these signals lines Address/ Data bus. Host Address 3-10 When HI32 programmed interface with universal, non-PCI function selected, these signals lines 3-10 Address bus. Port When HI32 configured GPIO through DCTR, these signals individually programmed through HI32 Data Direction Register (DIRH). These inputs tolerant. HAD[8-15] Input/Output Tri-stated Host Address/Data 8-15 When HI32 programmed interface with function selected, these signals lines 8-15 Address/Data bus. Host Data When HI32 programmed interface with universal non-PCI function selected, these signals lines Data bus. Port 8-15 When HI32 configured GPIO through DCTR, these signals individually programmed through HI32 DIRH. These inputs tolerant.
HA[3-10]
Input
PB[0-7]
Input Output
HD[0-7]
Input/Output
PB[8-15]
Input Output
DSP56301 Technical Data
1-13
Host Interface (HI32)
Signal/Connection Descriptions
Table 1-11. Host Interface (Continued)
Signal Name HC0-HC3/ HBE[0-3] Type Input/Output State During Reset Tri-stated Signal Description Command 0-3/Byte Enable When HI32 programmed interface with function selected, these signals lines Address/ Data bus. Host Address When HI32 programmed interface with universal, non-PCI function selected, these signals lines Address bus. Note: fourth signal this should connected pull-up resistor directly when non-PCI used.
HA[0-2]
Input
PB[16-19]
Input Output
Port 16-19 When HI32 configured GPIO through DCTR, these signals individually programmed through HI32 DIRH. These inputs tolerant.
HTRDY
Input/ Output
Tri-stated
Host Target Ready When HI32 programmed interface with function selected, this Host Target Ready signal. Host Data Enable When HI32 programmed interface with universal, non-PCI function selected, this Host Data Enable signal. Port When HI32 configured GPIO through DCTR, this signal individually programmed through HI32 DIRH. This input tolerant.
HDBEN
Output
PB20
Input Output
HIRDY
Input/ Output
Tri-stated
Host Initiator Ready When HI32 programmed interface with function selected, this Host Initiator Ready signal. Host Data Direction When HI32 programmed interface with universal, non-PCI function selected, this Host Data Direction signal. Port When HI32 configured GPIO through DCTR, this signal individually programmed through HI32 DIRH. This input tolerant.
HDBDR
Output
PB21
Input Output
1-14
DSP56301 Technical Data
Signal/Connection Descriptions
Host Interface (HI32)
Table 1-11. Host Interface (Continued)
Signal Name HDEVSEL Type Input/ Output State During Reset Tri-stated Signal Description Host Device Select When HI32 programmed interface with function selected, this Host Device Select signal. Host Select Acknowledge When HI32 programmed interface with universal, non-PCI function selected, this Host Select Acknowledge signal. Port When HI32 configured GPIO through DCTR, this signal individually programmed through HI32 DIRH. This input tolerant. HLOCK Input Tri-stated Host Lock When HI32 programmed interface with function selected, this Host Lock signal. Host Strobe When HI32 programmed interface with universal, non-PCI function selected, this Host Strobe Schmitt-trigger signal. Port When HI32 configured GPIO through DCTR, this signal individually programmed through HI32 DIRH. This input tolerant. HPAR Input/ Output Tri-stated Host Parity When HI32 programmed interface with function selected, this Host Parity signal. Host Acknowledge When HI32 programmed interface with universal, non-PCI function selected, this Host Acknowledge Schmitt-trigger signal. Port When HI32 configured GPIO through DCTR, this signal internally disconnected. This input tolerant.
HSAK
Output
PB22
Input Output
Input
PB23
Input Output
HDAK
Input
DSP56301 Technical Data
1-15
Host Interface (HI32)
Signal/Connection Descriptions
Table 1-11. Host Interface (Continued)
Signal Name HPERR Type Input/ Output State During Reset Tri-stated Signal Description Host Parity Error When HI32 programmed interface with function selected, this Host Parity Error signal. Host Request When HI32 programmed interface with universal, non-PCI function selected, this Host Request output. Port When HI32 configured GPIO through DCTR, this signal internally disconnected. This input tolerant. HGNT Input Input Host Grant When HI32 programmed interface with function selected, this Host Grant signal. Host Address Enable When HI32 programmed interface with universal, non-PCI function selected, this Host Address Enable output signal. Port When HI32 configured GPIO through DCTR, this signal internally disconnected. This input tolerant. HREQ Output Tri-stated Host Request When HI32 programmed interface with function selected, this Host Request signal. Host Transfer Acknowledge-When HI32 programmed interface with universal, non-PCI function selected, this Host Data Enable signal. programmed active high active low. Port When HI32 configured GPIO through DCTR, this signal internally disconnected. This input tolerant.
HDRQ
Output
HAEN
Input
Output
1-16
DSP56301 Technical Data
Signal/Connection Descriptions
Host Interface (HI32)
Table 1-11. Host Interface (Continued)
Signal Name HSERR Type Output, open drain State During Reset Tri-stated Signal Description Host System Error When HI32 programmed interface with function selected, this Host System Error signal. Host Interrupt Request When HI32 programmed interface with universal, non-PCI function selected, this Host Interrupt Request signal. Port When HI32 configured GPIO through DCTR, this signal internally disconnected. This input tolerant. HSTOP Input/ Output Tri-stated Host Stop When HI32 programmed interface with function selected, this Host Stop signal. Host Write/Host Read-Write When HI32 programmed interface with universal, non-PCI function selected, this Host Write/Host Read-Write Schmitt-trigger signal. Port When HI32 configured GPIO through DCTR, this signal internally disconnected. This input tolerant. HIDSEL Input Input Host Initialization Device Select When HI32 programmed interface with function selected, this Host Initialization Device Select signal. Host Read/Host Data Strobe When HI32 programmed interface with universal, non-PCI function selected, this Host Data Read/ Host Data Strobe Schmitt-trigger signal. Port When HI32 configured GPIO through DCTR, this signal internally disconnected. This input tolerant.
HIRQ
Output, open drain
HWR/HRW
Input
HRD/HDS
Input
DSP56301 Technical Data
1-17
Host Interface (HI32)
Signal/Connection Descriptions
Table 1-11. Host Interface (Continued)
Signal Name HFRAME Type Input/ Output State During Reset Tri-stated Signal Description Host Frame When HI32 programmed interface with function selected, this Host cycle Frame signal. Non-PCI When HI32 programmed interface with universal, non-PCI function selected, this signal must connected pull-up resistor directly VCC. Port When HI32 configured GPIO through DCTR, this signal internally disconnected. This input tolerant. HCLK Input Input Host Clock When HI32 programmed interface with function selected, this Host Clock input. Non-PCI When HI32 programmed interface universal non-PCI function selected, this signal must connected pull-up resistor directly VCC. Port When HI32 configured GPIO through DCTR, this signal internally disconnected. This input tolerant. HAD[16-31] Input/Output Tri-stated Host Address/Data 16-31 When HI32 programmed interface with function selected, these signals lines 16-31 Address/Data bus. Host Data 8-23 When HI32 programmed interface with universal, non-PCI function selected, these signals lines 8-23 Data bus. Port When HI32 configured GPIO through DCTR, these signals internally disconnected. These inputs tolerant.
HD[8-23]
Input/Output
1-18
DSP56301 Technical Data
Signal/Connection Descriptions
Host Interface (HI32)
Table 1-11. Host Interface (Continued)
Signal Name HRST Type Input State During Reset Tri-stated Signal Description Hardware Reset When HI32 programmed interface with function selected, this Hardware Reset input. Hardware Reset When HI32 programmed interface with universal, non-PCI function selected, this Hardware Reset Schmitt-trigger signal. Port When HI32 configured GPIO through DCTR, this signal internally disconnected. This input tolerant. HINTA Output, open drain Tri-stated Host Interrupt When function selected, this signal Interrupt open-drain output. Port When HI32 configured GPIO through DCTR, this signal internally disconnected. This input tolerant. PVCL Input Input Voltage Clamp When HI32 programmed interface with function selected uses signal environment, connect this (3.3 enable high voltage clamping required specifications. other cases, including signal environment, leave input unconnected.
HRST
Input
DSP56301 Technical Data
1-19
Enhanced Synchronous Serial Interface (ESSI0)
Signal/Connection Descriptions
ENHANCED SYNCHRONOUS SERIAL INTERFACE (ESSI0)
synchronous serial interfaces (ESSI0 ESSI1) provide full-duplex port serial communication with variety serial devices, including more industry-standard CODECs, other DSPs, microprocessors, peripherals that implement Motorola Serial Peripheral Interface (SPI).
Table 1-12. Enhanced Synchronous Serial Interface (ESSI0)
Signal Name SC00 Type Input Output State During Reset Input Signal Description Serial Control Functions either Synchronous Asynchronous mode. Asynchronous mode, this signal used receive clock (Schmitt-trigger input). Synchronous mode, this signal either Transmitter output Serial Flag Port default configuration following reset GPIO. PC0, signal direction controlled through Port Directions Register (PRR0). signal configured ESSI signal SC00 through Port Control Register (PCR0). This input tolerant. SC01 Input/Output Input Serial Control Functions either Synchronous Asynchronous mode. Asynchronous mode, this signal receiver frame sync I/O. Synchronous mode, this signal either Transmitter output Serial Flag Port default configuration following reset GPIO. PC1, signal direction controlled through PRR0. signal configured ESSI signal SC01 through PCR0. This input tolerant. SC02 Input/Output Input Serial Control Signal Frame sync both transmitter receiver Synchronous mode, transmitter only Asynchronous mode. When configured output, this signal internally generated frame sync signal. When configured input, this signal receives external frame sync signal transmitter (and receiver synchronous operation). Port default configuration following reset GPIO. PC2, signal direction controlled through PRR0. signal configured ESSI signal SC02 through PCR0. This input tolerant.
Input Output
Input Output
1-20
DSP56301 Technical Data
Signal/Connection Descriptions
Enhanced Synchronous Serial Interface (ESSI0)
Table 1-12. Enhanced Synchronous Serial Interface (ESSI0) (Continued)
Signal Name SCK0 Type Input/Output State During Reset Input Signal Description Serial Clock Provides serial rate clock ESSI interface. SCK0 clock input output both transmitter receiver Synchronous modes, transmitter Asynchronous modes. Although external serial clock independent asynchronous system clock, must exceed minimum clock cycle time (that system clock frequency must least three times external ESSI clock frequency). ESSI needs least three phases inside each half serial clock. Input Output Port default configuration following reset GPIO. PC3, signal direction controlled through PRR0. signal configured ESSI signal SCK0 through PCR0. This input tolerant. SRD0 Input/Output Input Serial Receive Data Receives serial data transfers ESSI receive shift register. SRD0 input when data being received. Port default configuration following reset GPIO. PC4, signal direction controlled through PRR0. signal configured ESSI signal SRD0 through PCR0. This input tolerant. STD0 Input/Output Input Serial Transmit Data Transmits data from serial transmit shift register. STD0 output when data being transmitted. Port default configuration following reset GPIO. PC5, signal direction controlled through PRR0. signal configured ESSI signal STD0 through PCR0. This input tolerant.
Input Output
Input Output
DSP56301 Technical Data
1-21
Enhanced Synchronous Serial Interface (ESSI1)
Signal/Connection Descriptions
ENHANCED SYNCHRONOUS SERIAL INTERFACE (ESSI1)
Table 1-13. Enhanced Synchronous Serial Interface (ESSI1)
Signal Name SC10 Type Input Output State During Reset Input Signal Description Serial Control Function determined mode. Asynchronous mode, this signal receive clock (Schmitt-trigger input). Synchronous mode, this signal either Transmitter output Serial Flag Port default configuration following reset GPIO input PD0. When configured PD0, signal direction controlled through Port Directions Register (PRR1). signal configured ESSI signal SC10 through Port Control Register (PCR1). This input tolerant. SC11 Input/Output Input Serial Control Function determined mode. Asynchronous mode, this signal receiver frame sync I/O. Synchronous mode, this signal either Transmitter output Serial Flag Port default configuration following reset GPIO. When configured PD1, signal direction controlled through PRR1. signal configured ESSI signal SC11 through PCR1. This input tolerant. SC12 Input/Output Input Serial Control Signal Frame sync both transmitter receiver Synchronous mode, transmitter Asynchronous mode. When configured output, this signal internally generated frame sync signal. When configured input, this signal receives external frame sync signal transmitter (and receiver Synchronous operation). Port default configuration following reset GPIO. PD2, signal direction controlled through PRR1. signal configured ESSI signal SC12 through PCR1. This input tolerant.
Input Output
Input Output
1-22
DSP56301 Technical Data
Signal/Connection Descriptions
Enhanced Synchronous Serial Interface (ESSI1)
Table 1-13. Enhanced Synchronous Serial Interface (ESSI1) (Continued)
Signal Name SCK1 Type Input/Output State During Reset Input Signal Description Serial Clock ESSI interface serial rate clock transmitter receiver Synchronous modes, transmitter only Asynchronous modes. Although external serial clock independent asynchronous system clock, must exceed minimum clock cycle time (that system clock frequency must least three times external ESSI clock frequency). ESSI needs least three phases inside each half serial clock. Input Output Port default configuration following reset GPIO. PD3, signal direction controlled through PRR1. signal configured ESSI signal SCK1 through PCR1. This input tolerant. SRD1 Input/Output Input Serial Receive Data Receives serial data transfers ESSI receive shift register. SRD1 input when data being received. Port default configuration following reset GPIO. PD4, signal direction controlled through PRR1. signal configured ESSI signal SRD1 through PCR1. This input tolerant. STD1 Input/Output Input Serial Transmit Data Transmits data from serial transmit shift register. STD1 output when data being transmitted. Port default configuration following reset GPIO. PD5, signal direction controlled through PRR1. signal configured ESSI signal STD1 through PCR1. This input tolerant.
Input Output
Input Output
DSP56301 Technical Data
1-23
Serial Communication Interface (SCI)
Signal/Connection Descriptions
SERIAL COMMUNICATION INTERFACE (SCI)
Serial Communication interface (SCI) provides full-duplex port communication with other DSPs, microprocessors, peripherals, such modems.
Table 1-14. Serial Communication Interface (SCI)
Signal Name Input Type State During Reset Input Signal Description Serial Receive Data Receives byte-oriented serial data transfers receive shift register. Port default configuration following reset GPIO. PE0, signal direction controlled through Port Directions Register (PRR). signal configured signal through Port Control Register (PCR). This input tolerant. Output Input Serial Transmit Data Transmits data from transmit data register. Port default configuration following reset GPIO. PE1, signal direction controlled through PRR. signal configured signal through PCR. This input tolerant. SCLK Input/Output Input Serial Clock Provides input output clock transmitter and/or receiver. Port default configuration following reset GPIO. PE2, signal direction controlled through PRR. signal configured signal SCLK through PCR. This input tolerant.
Input Output
Input Output
Input Output
TIMERS
DSP56301 three identical, independent timers. timers internal external clocking, interrupt DSP56301 after specified number events (clocks), signal external device after counting specific number internal events.
1-24
DSP56301 Technical Data
Signal/Connection Descriptions
TimerS
Table 1-15. Triple Timer Signals
Signal Name TIO0 Type Input Output State During Reset Input Signal Description Timer Schmitt-Trigger Input/Output When Timer functions external event counter measurement mode, TIO0 input. When Timer functions watchdog, timer, pulse modulation mode, TIO0 output. default mode after reset GPIO input. This changed output configured Timer Input/Output through Timer Control/Status Register (TCSR0). This input tolerant. TIO1 Input Output Input Timer Schmitt-Trigger Input/Output When Timer functions external event counter measurement mode, TIO1 input. When Timer functions watchdog, timer, pulse modulation mode, TIO1 output. default mode after reset GPIO input. This changed output configured Timer Input/Output through Timer Control/Status Register (TCSR1). This input tolerant. TIO2 Input Output Input Timer Schmitt-Trigger Input/Output When Timer functions external event counter measurement mode, TIO2 input. When Timer functions watchdog, timer, pulse modulation mode, TIO2 output. default mode after reset GPIO input. This changed output configured Timer Input/Output through Timer Control/Status Register (TCSR2). This input tolerant.
DSP56301 Technical Data
1-25
JTAG/OnCE Interface
Signal/Connection Descriptions
JTAG/ONCE INTERFACE
Table 1-16. JTAG/OnCE Interface
Signal Name Input Type State During Reset Input Signal Description Test Clock Synchronizes JTAG test logic. This input tolerant. Input Input Test Data Input Serial signal test instructions data. sampled rising edge internal pull-up resistor. This input tolerant. Output Tri-stated Test Data Output Test data serial signal test instructions data. tri-statable actively driven shift-IR shift-DR controller states. changes falling edge TCK. Test Mode Select Sequences test controller's state machine. sampled rising edge internal pullup resistor. This input tolerant. TRST Input Input Test Reset Asynchronously initializes test controller. TRST internal pull-up resistor. TRST must asserted after power This input tolerant.
Input
Input
1-26
DSP56301 Technical Data
Signal/Connection Descriptions
JTAG/OnCE Interface
Table 1-16. JTAG/OnCE Interface (Continued)
Signal Name Type Input/Output State During Reset Input Signal Description Debug Event Provides enter Debug mode from external command controller input) acknowledge that chip entered Debug mode output). When asserted input, causes DSP56300 core finish current instruction, save instruction pipeline information, enter Debug mode, wait commands from debug serial input line. When debug request breakpoint condition cause chip enter Debug mode asserted output three clock cycles. internal pull-up resistor. standard part JTAG Test Access Port (TAP) Controller. connects OnCE module initiate Debug mode directly provide direct external indication that chip entered Debug mode. other interface with OnCE module must occur through JTAG port. This input tolerant.
DSP56301 Technical Data
1-27
JTAG/OnCE Interface
Signal/Connection Descriptions
1-28
DSP56301 Technical Data
SECTION
SPECIFICATIONS: UDR2 PROCESS TECHNOLOGY MASKS
INTRODUCTION
DSP56301 fabricated high-density CMOS with Transistor-Transistor Logic (TTL) compatible inputs outputs. DSP56301 specifications preliminary from design simulations, fully tested guaranteed. Finalized specifications will published after full characterization device qualifications complete.
DSP56301 Technical Data
CAUTION
This Section contains specifications masks 0F92R, 1F92R, 0F48S, 1F48S, 2F48S, 3F48S DSP56301. These masks Motorola's universal design rules (UDR2) process technology. Section specifications more recent masks DSP56301 that Motorola's communications design rules (CDR2) process technology.
2A-1
Maximum Ratings
Specifications: UDR2 Process Technology Masks
MAXIMUM RATINGS
CAUTION
This device contains circuitry protecting against damage high static voltage electrical fields; however, normal precautions should taken avoid exceeding maximum voltage ratings. Reliability enhanced unused inputs tied appropriate logic voltage level (for example, either VCC).
Note: calculation timing requirements, adding maximum value specification minimum value another specification does yield reasonable sum. maximum specification calculated using worst case variation process parameter values direction. minimum specification calculated using worst case same parameters opposite direction. Therefore, "maximum" value specification never occurs same device that "minimum" value another specification; adding maximum minimum represents condition that never exist.
Table 2A-1. Maximum Ratings
Symbol Rating1 Value1,
Unit
Supply Voltage
-0.3 +4.0
input voltages excluding tolerant" inputs3 tolerant" input voltages
VIN5
3.95
Current drain excluding Operating temperature range Storage temperature Notes:
+100 +150
TSTG
-40C +100C, Absolute maximum ratings stress ratings only, functional operation maximum guaranteed. Stress beyond maximum rating affect device reliability cause permanent damage device. CAUTION: Tolerant" input voltages cannot more than 3.95 greater than supply voltage; this restriction applies "power on," well during normal operation. case, input voltages must higher than 5.75 Tolerant" inputs inputs that tolerate
2A-2
DSP56301 Technical Data
Specifications: UDR2 Process Technology Masks
Thermal Characteristics
THERMAL CHARACTERISTICS
Table 2A-2. Thermal Characteristics
Characteristic Junction-to-ambient thermal resistance1 Junction-to-case thermal resistance
Symbol RqJA RqJC
TQFP Value 49.5
PBGA3 Value 48.4
PBGA4 Value 25.2
Unit
°C/W °C/W °C/W
Thermal characterization parameter Notes:
ELECTRICAL CHARACTERISTICS
Table 2A-3. Electrical Characteristics6
Symbol Characteristics VIHP VIHX VILP VILX ITSI 0.01 DSP56301 Technical Data
Junction-to-ambient thermal resistance based measurements horizontal single-sided printed circuit board SEMI G38-87 natural convection. (SEMI Semiconductor Equipment Materials International, East Middlefield Rd., Mountain View, 94043, 415-964-5111.) Junction-to-case thermal resistance based measurements using cold plate SEMI G30-88, with exception that cold plate temperature used case temperature. These simulated values. Test board 2-ounce copper traces routed outer balls. These simulated values. test board two, 2-ounce signal layers 1-ounce solid ground planes internal test board.
Unit
Supply voltage
Input high voltage D(0-23), MOD1/IRQ1, RESET, PINIT/NMI JTAG/ESSI/SCI/Timer/HI32 pins9 EXTAL8 Input voltage D(0-23), MOD1/IRQ1, RESET, PINIT JTAG/ESSI/SCI/Timer/HI32 pins EXTAL8 Input leakage current
3.95
High impedance (off-state) input current Output high voltage (IOH -0.4 mA)5,7 CMOS (IOH mA)5
2A-3
Electrical Characteristics
Specifications: UDR2 Process Technology Masks
Table 2A-3. Electrical Characteristics6 (Continued)
Characteristics Output voltage (IOL open-drain pins mA)5,7 CMOS (IOL mA)5 Internal supply current2: Normal mode Wait mode3 Stop mode4 supply current Input capacitance5 Notes: Symbol ICCI ICCW ICCS MHz: MHz: MHz: MHz: MHz: MHz: 0.01 Unit
Refers MODA/IRQA, MODB/IRQB, MODC/IRQC, MODD/IRQD pins. Power Consumption Considerations page provides formula compute estimated current requirements Normal mode. order obtain these results, inputs must terminated (that allowed float). Measurements based synthetic intensive benchmarks (see $SSHQGL[ power consumption numbers this specification percent measured results this benchmark. This reflects typical applications. Typical internal supply current measured with 100°C. order obtain these results, inputs must terminated (that allowed float). XTAL signals disabled during Stop state. order obtain these results, inputs that disconnected Stop mode must terminated (that allowed float). Periodically sampled percent tested. -40°C +100 This characteristic does apply XTAL PCAP. Driving EXTAL VIHX high VILX value cause additional power consumption current). minimize power consumption, minimum VIHX should lower than maximum VILX should higher than VCC. CAUTION: Tolerant" input voltages cannot more than 3.95 greater than supply voltage; this restriction applies "power on," well during normal operation. case, input voltages must higher than 5.75 Tolerant" inputs inputs that tolerate
ELECTRICAL CHARACTERISTICS
timing waveforms shown electrical characteristics section tested with maximum minimum pins except EXTAL, which tested using input levels shown Note Table 2A-3. timing specifications, which referenced device input signal, measured production with respect 50-percent point respective input signal's transition. DSP56301 output levels measured with production test machine reference levels respectively. Note: Although minimum value frequency EXTAL MHz, device test conditions rated speed.
2A-4
DSP56301 Technical Data
Specifications: UDR2 Process Technology Masks
Internal Clocks
INTERNAL CLOCKS
Table 2A-4. Internal Clocks, CLKOUT
Expression1, Characteristics Symbol Internal operation frequency CLKOUT with enabled Internal operation frequency CLKOUT with disabled MF)/ (PDF Ef/2
Internal clock CLKOUT high period With disabled With enabled With enabled Internal clock CLKOUT period With disabled With enabled With enabled Internal clock CLKOUT cycle time with enabled
0.49 DF/MF 0.47 DF/MF 0.49 DF/MF 0.47 DF/MF DF/MF ICYC DSP56301 Technical Data
0.51 DF/MF 0.53 DF/MF 0.51 DF/MF 0.53 DF/MF
Internal clock CLKOUT cycle time with disabled Instruction cycle time Notes:
Division Factor External frequency External clock cycle Multiplication Factor Predivision Factor Internal clock cycle &ORFN *HQHUDWRU section )DPLO\ 0DQXDO detailed discussion PLL.
EXTERNAL CLOCK OPERATION
DSP56301 system clock derived from on-chip crystal oscillator, shown Figure cover page, externally supplied. externally supplied square wave voltage source should connected EXTAL, leaving XTAL physically connected board socket (see Figure 2A-2).
2A-5
External Clock Operation (;7$/ ;7$/
Specifications: UDR2 Process Technology Masks (;7$/ ;7$/
;7$/
;7$/
Fundamental Frequency Fork Crystal Oscillator
Fundamental Frequency Crystal Oscillator
fOSC 32.768
Calculations were done 32.768 crystal with following parameters: load capacitance (CL) 12.5 shunt capacitance (C0) series resistance drive level
EXTAL
CLKOUT with disabled
CLKOUT with enabled Note:
2A-6
fOSC
Suggested Component Values:
Suggested Component Values:
fOSC
Calculations were done 4/20 crystal with following parameters: CLof 30/20 series resistance 100/20 drive level
Figure 2A-1. Crystal Oscillator Circuits
VIHC
Midpoint
VILC
midpoint (VIHC VILC).
Figure 2A-2. External Clock Timing
DSP56301 Technical Data
Specifications: UDR2 Process Technology Masks
External Clock Operation
Table 2A-5. Clock Operation
Characteristics Symbol Frequency EXTAL (EXTAL Frequency) rise fall time this external clock should maximum. EXTAL input high1, With disabled (46.7%-53.3% duty cycle6) With enabled (42.5%-57.5% duty cycle6) EXTAL input low1, With disabled (46.7%-53.3% duty cycle6) With enabled (42.5%-57.5% duty cycle6) EXTAL cycle time2 With disabled With enabled 66.0 80.0
6.44 157.0 7.08 6.44 157.0 15.15 15.15 273.1 11.0 ICYC 30.3 15.15 8.53 DSP56301 Technical Data
7.08
5.84 5.31
157.0
5.84 5.31
157.0
12.50 12.50
273.1 11.0
CLKOUT change from EXTAL fall with disabled
CLKOUT rising edge from EXTAL rising edge with enabled MHz)3,5 CLKOUT rising edge from EXTAL rising edge with enabled MHz)3,5 CLKOUT falling edge from EXTAL falling edge with enabled MHz)3,5
Instruction cycle time ICYC (See Table 2A-4 page 2A-5.) (46.7%-53.3% duty cycle) With disabled With enabled
25.0 12.50
8.53
Notes:
Measured percent input transition. maximum value enabled given minimum maximum Periodically sampled percent tested. maximum value enabled given minimum maximum skew guaranteed other value. indicated duty cycle specified maximum frequency which part rated. minimum clock high time required correction operation, however, remains same lower operating frequencies; therefore, when lower clock frequency used, signal symmetry vary from specified duty cycle long minimum high time time requirements met.
2A-7
Phase Lock Loop (PLL) Characteristics
Specifications: UDR2 Process Technology Masks
PHASE LOCK LOOP (PLL) CHARACTERISTICS
Table 2A-6. Characteristics
Characteristics frequency when enabled 2/PDF) external capacitor (PCAP VCCP) (CPCAP1) Unit
Note:
RESET, STOP, MODE SELECT, INTERRUPT TIMING24
Table 2A-7. Reset, Stop, Mode Select, Interrupt Timing6
Expression
Characteristics
425) 590) 425) 590) CPCAP value capacitor (connected between PCAP VCCP). recommended value CPCAP computed from following equations: (500 150, 26.0 760.0 15.2 1.14 1.14 38.0 38.0 625.0 12.5 31.3 31.3 1000 75000 75000 DSP56301 Technical Data
Unit
Delay from RESET assertion pins reset value3
26.0
Required RESET duration4 Power external clock generator, disabled Power external clock generator, enabled Power internal oscillator During STOP, XTAL disabled (PCTL During STOP, XTAL enabled (PCTL During normal operation
2A-8
Specifications: UDR2 Process Technology Masks
Reset, Stop, Mode Select, Interrupt Timing24
Table 2A-7. Reset, Stop, Mode Select, Interrupt Timing6 (Continued)
Characteristics Expression Delay from asynchronous RESET deassertion first external address output (internal reset deassertion)5 Minimum Unit
Maximum
318.0 15.2 3.25 20.25 50.0 312.0 41.6 30.0 30.0 10.0 8.25 10.0 8.25 4.25 7.25 66.0 55.1 112.0 157.0 92.6 130.0 DSP56301 Technical Data
MHz: 3.25 MHz: 3.25 MHz: 20.25 11.0 MHz: 20.25 9.95
51.0
42.6
263.1
Synchronous reset setup time from RESET deassertion CLKOUT Transition Minimum Maximum
12.5
Synchronous reset deasserted, delay time from CLKOUT Transition first external address output Minimum Maximum Mode select setup time Mode select hold time
258.1
Minimum edge-triggered interrupt request assertion width
Minimum edge-triggered interrupt request deassertion width
Delay from IRQA, IRQB, IRQC, IRQD, assertion external memory access address valid Caused first interrupt instruction fetch Caused first interrupt instruction execution Delay from IRQA, IRQB, IRQC, IRQD, assertion general-purpose transfer output valid caused first interrupt instruction execution
2A-9
Reset, Stop, Mode Select, Interrupt Timing24
Specifications: UDR2 Process Technology Masks
Table 2A-7. Reset, Stop, Mode Select, Interrupt Timing6 (Continued)
Characteristics Expression Delay from address output valid caused first interrupt instruction execute interrupt request deassertion level sensitive fast interrupts1 Delay from assertion interrupt request deassertion level sensitive fast interrupts1 MHz8: 3.75 MHz8: 3.75 12.4 MHz8: 3.25 MHz8: 3.25 12.4 Unit
MHz8: 3.5) MHz8: 3.5) 12.4 MHz8: 3.5) MHz8: 3.5) 12.4 MHz8: MHz8: 12.4 MHz8: 2.5) MHz8: 2.5) 12.4 141.0 380.0 116.6 DSP56301 Technical Data
Delay from assertion interrupt request deassertion level sensitive fast interrupts1 DRAM
SRAM
SRAM
SRAM
Synchronous interrupt setup time from IRQA, IRQB, IRQC, IRQD, assertion CLKOUT Transition
Synchronous interrupt delay time from CLKOUT Transition first external address output valid caused first instruction fetch after coming Wait Processing state Minimum 9.25 24.75 Maximum Duration IRQA assertion recover from Stop state
314.4
2A-10
Specifications: UDR2 Process Technology Masks
Reset, Stop, Mode Select, Interrupt Timing24
Table 2A-7. Reset, Stop, Mode Select, Interrupt Timing6 (Continued)
Characteristics Expression Delay from IRQA assertion fetch first instruction (when exiting Stop)2, active during Stop (PCTL Stop delay enabled (OMR active during Stop (PCTL Stop delay enabled (OMR active during Stop (PCTL (Implies Stop Delay) Duration level sensitive IRQA assertion ensure interrupt service (when exiting Stop)2, active during Stop (PCTL Stop delay enabled (OMR active during Stop (PCTL Stop delay enabled (OMR active during Stop (PCTL (implies Stop delay) Interrupt Requests Rate HI32, ESSI, SCI, Timer IRQ, (edge trigger) IRQ, (level trigger) Unit
(128 PLC/2)
64.1
17.0
(8.25 0.5) 117.4 132.6 96.9 (128K PLC/2) (20.5 0.5) 64.1 17.0 62.1 15.4 83.4 68.8 12TC 12TC 4.25 66.0 181.8 121.2 121.2 181.8 90.9 106.1 30.3 45.5 55.1 DSP56301 Technical Data
(23.75 352.3 62.1 290.6 15.4 0.5)
109.4
150.0 100.0 100.0 150.0 75.0 87.5 25.0 37.5
Requests Rate Data read from HI32, ESSI, Data write HI32, ESSI, Timer IRQ, (edge trigger) Delay from IRQA, IRQB, IRQC, IRQD, assertion external memory (DMA source) access address valid
2A-11
Reset, Stop, Mode Select, Interrupt Timing24
Specifications: UDR2 Process Technology Masks
Table 2A-7. Reset, Stop, Mode Select, Interrupt Timing6 (Continued)
Characteristics Expression Notes: Unit
When fast interrupts used with IRQA, IRQB, IRQC, IRQD defined level-sensitive, timings through apply prevent multiple interrupt service. avoid these timing restrictions, deasserted Edge-triggered mode recommended when fast interrupts used. Long interrupts recommended when Level-sensitive mode used. This timing depends several settings: disable, using internal oscillator (PLL Control Register (PCTL) oscillator disabled during Stop (PCTL stabilization delay required assure that oscillator stable before executing programs. that case, resetting Stop delay (OMR provides proper delay. While possible recommended these specifications guarantee timings that case. disable, using internal oscillator (PCTL oscillator enabled during Stop (PCTL 17=1), stabilization delay required recovery time minimal (OMR setting ignored). disable, using external clock (PCTL stabilization delay required recovery time defined PCTL settings. enable, PCTL shutdown during Stop. Recovering from Stop requires locked. lock procedure duration, Lock Cycles (PLC), range 1000 cycles. This procedure occurs parallel with stop delay counter, stop recovery ends when last these events occurs. stop delay counter completes count lock procedure completion. value disable
maximum value 4096 (maximum divided desired internal frequency (that 4096/66 ms). During stabilization period, constant, their width vary, timing vary well. Periodically sampled percent tested. external clock generator, RESET duration measured during time which RESET asserted, valid, EXTAL input active valid. internal oscillator, RESET duration measured during time which RESET asserted valid. specified timing reflects crystal oscillator stabilization time after power-up. This number affected both specifications crystal other components connected oscillator reflects worst case conditions. When valid, other "required RESET duration" conditions specified above) have been met, device circuitry uninitialized state that result significant power consumption heat-up. Designs should minimize this state shortest possible duration. does lose lock. -40°C +100°C, number wait states (measured clock cycles, number TC). expression compute maximum value.
2A-12
DSP56301 Technical Data
Specifications: UDR2 Process Technology Masks
Reset, Stop, Mode Select, Interrupt Timing24
RESET Pins Reset Value
A[0-23]
First Fetch
Figure 2A-3. Reset Timing
CLKOUT
RESET
A[0-23]
Figure 2A-4. Synchronous Reset Timing
DSP56301 Technical Data
2A-13
Reset, Stop, Mode Select, Interrupt Timing24
Specifications: UDR2 Process Technology Masks
A[0-23]
)LUVW ,QWHUUXSW ,QVWUXFWLRQ ([HFXWLRQ)HWFK
IRQA, IRQB, IRQC, IRQD,
GeneralPurpose
IRQA, IRQB, IRQC, IRQD,
IRQA, IRQB, IRQC, IRQD,
IRQA, IRQB, IRQC, IRQD,
2A-14
First Interrupt Instruction Execution General Purpose
Figure 2A-5. External Fast Interrupt Timing
Figure 2A-6. External Interrupt Timing (Negative Edge-Triggered)
DSP56301 Technical Data
Specifications: UDR2 Process Technology Masks
Reset, Stop, Mode Select, Interrupt Timing24
CLKOUT
IRQA, IRQB, IRQC, IRQD,
A[0-23]
MODA, MODB, MODC, MODD, PINIT
Figure 2A-7. Synchronous Interrupt from Wait State Timing
RESET
IRQA, IRQB, IRQC, IRQD,
Figure 2A-8. Operating Mode Select Timing
IRQA
A[0-23]
)LUVW ,QVWUXFWLRQ )HWFK
Figure 2A-9. Recovery from Stop State Using IRQA
DSP56301 Technical Data
2A-15
Reset, Stop, Mode Select, Interrupt Timing24
Specifications: UDR2 Process Technology Masks
IRQA A[0-23] )LUVW ,54$ ,QWHUUXSW ,QVWUXFWLRQ )HWFK
Figure 2A-10. Recovery from Stop State Using IRQA Interrupt Service
A[0-23]
IRQA, IRQB, IRQC, IRQD,
2A-16
6RXUFH $GGUHVV First Interrupt Instruction Execution
Figure 2A-11. External Memory Access (DMA Source) Timing
DSP56301 Technical Data
Specifications: UDR2 Process Technology Masks
External Memory Expansion Port (Port
EXTERNAL MEMORY EXPANSION PORT (PORT
SRAM Timing
Table 2A-8. SRAM Read Write Accesses
Characteristics Symbol Expression1 MHz: 0.25 MHz: 0.25 frequencies: 0.75 1.25 Unit
Address valid assertion pulse width
Address valid assertion
tRC, 26.3 86.9 162.7 14.9 0.5) MHz: 0.25 MHz: 0.25 frequencies: 1.25 2.25 18.2 26.3 49.0 14.9 30.1 DSP56301 Technical Data
21.0 71.0
133.5
11.6
assertion pulse width
14.3 21.0 39.8
deassertion address valid
11.6 24.1
2A-17
External Memory Expansion Port (Port
Specifications: UDR2 Process Technology Masks
Table 2A-8. SRAM Read Write Accesses (Continued)
Characteristics Symbol Expression1 Address valid input data valid tAA, MHz: 0.75) 11.0 MHz: 0.75) MHz: 0.25) 11.0 MHz: 0.25) Unit
15.5
12.4
tOHZ 0.75) MHz: 0.25) MHz: 0.25) MHz: 0.25 MHz: 0.25 frequencies: 1.25 2.25 22.5 17.9 (tDW) 15.2 30.4 -7.5 11.8 24.3 -0.6 -6.8 0.75 0.25 -0.25 DSP56301 Technical Data
assertion input data valid
deassertion data valid (data hold time)
Address valid deassertion Data valid deassertion (data setup time)
Data hold time from deassertion
assertion data active
2A-18
Specifications: UDR2 Process Technology Masks
External Memory Expansion Port (Port
Table 2A-8. SRAM Read Write Accesses (Continued)
Characteristics Symbol Expression1 deassertion data high impedance 0.25 1.25 2.25 1.25 2.25 3.25 0.75 1.75 2.75 14.9 30.1 45.2 19.1 34.3 11.6 24.1 36.6 15.8 28.3 Unit
deassertion time
deassertion time
Address valid assertion assertion pulse width deassertion address valid
Notes:
22.5 37.7 11.7 34.4 49.5 0.25) 0.25 1.25 2.25 15.1 15.9 31.0 number wait states specified BCR. -40°C +100 DSP56301 Technical Data
Previous deassertion data active (write)
17.9 30.4
27.8 40.3
11.8
12.6 25.1
2A-19
External Memory Expansion Port (Port
Specifications: UDR2 Process Technology Masks
$>±@ $$>±@
'>±@
$>±@ $$>±@
'>±@
2A-20
'DWD
Figure 2A-12. SRAM Read Access
'DWD
Figure 2A-13. SRAM Write Access
DSP56301 Technical Data
Specifications: UDR2 Process Technology Masks
External Memory Expansion Port (Port
DRAM Timing
selection guides Figure 2A-14 Figure 2A-17 page 2A-31 primary selection only. Final selection should based timings following tables. example, selection guide suggests that four wait states must used operation when Page Mode DRAM used. However, using information appropriate table, designer evaluate whether fewer wait states determining which timing prevents operation MHz, running chip slightly lower frequency (for example, MHz), using faster DRAM becomes available), control factors such capacitive resistive load improve overall system performance.
'5$0 7\SH WS68
&KLS IUHTXHQF\ :DLW VWDWHV :DLW VWDWHV :DLW VWDWHV :DLW VWDWHV
Note:This figure should used primary selection. exact detailed timings, following tables.
Figure 2A-14. DRAM Page Mode Wait States Selection Guide
DSP56301 Technical Data
2A-21
External Memory Expansion Port (Port
Specifications: UDR2 Process Technology Masks
Table 2A-9. DRAM Page Mode Timings, Wait State (Low-Power Applications)1,
MHz6 Characteristics Symbol Expression Page mode cycle time consecutive accesses same direction Page mode cycle time mixed (read write) accesses assertion data valid (read) tCAC 100.0 66.7 MHz6 Unit
1.25
62.5
41.7
42.5 67.5 tOFF tRSH 0.75 33.5 21.0 tRHCP tCAS 96.0 62.7 0.75 33.5 21.0 tCRP 1.75 3.25 4.25 6.25 81.5 156.5 206.5 306.5 21.0 21.0 52.3 102.2 135.5 202.1 12.7 12.7 tASC tCAH tRAL tRCS tRCH tWCH 0.75 0.75 0.25 33.5 21.0 96.0 33.7 20.8 70.5 62.7 21.2 12.5 45.5 DSP56301 Technical Data
25.8 42.5
Column address valid data valid (read) deassertion data valid (read hold time) Last assertion deassertion
Previous deassertion deassertion assertion pulse width
Last deassertion deassertion4 BRW[1-0] BRW[1-0] BRW[1-0] BRW[1-0] deassertion pulse width
Column address valid assertion assertion column address valid
Last column address valid deassertion deassertion assertion deassertion assertion assertion deassertion assertion pulse width
2A-22
Specifications: UDR2 Process Technology Masks
External Memory Expansion Port (Port
Table 2A-9. DRAM Page Mode Timings, Wait State (Low-Power Applications)1, (Continued)
MHz6 Characteristics Symbol Expression Notes: Last assertion deassertion assertion deassertion Data valid assertion (Write) tRWL tCWL 1.75 1.75 0.25 0.75 83.2 83.2 33.5 54.0 54.0 21.0 25.8 MHz6 Unit
assertion data valid (write)
assertion assertion Last assertion deassertion
assertion data valid
deassertion data valid assertion data active
deassertion data high impedance
tWCS tROH 45.7 29.0 71.0 46.0 42.5 0.75 37.2 24.7 0.25 12.5 Characteristics Symbol Expression 15.2 tCAC 2.75 MHz: MHz: 41.7 DSP56301 Technical Data
number wait states Page mode access specified DCR. refresh period specified DCR. timings calculated worst case. Some timings better specific cases (for example, equals read-after-read write-after-write sequences). BRW[1-0] (DRAM control register bits) defines number wait states that should inserted each DRAM out-of-page access. deassertion always occurs after deassertion; therefore, restricted timing tOFF tGZ. Reduced clock speed allows Page Mode DRAM with Wait state (see Figure 2A-14 page 2A-21).
Table 2A-10. DRAM Page Mode Timings, Wait States1,
Unit 34.4 12.3
Page mode cycle time assertion data valid (read)
2A-23
External Memory Expansion Port (Port
Specifications: UDR2 Process Technology Masks
Table 2A-10. DRAM Page Mode Timings, Wait States1, (Continued)
Characteristics Symbol Expression Column address valid data valid (read) MHz: MHz: Unit
30.4
17.9 36.6
24.8
deassertion data valid (read hold time) Last assertion deassertion
tOFF tRSH 1.75 3.25
Previous deassertion deassertion assertion pulse width
Last deassertion deassertion5 BRW[1-0] BRW[1-0] BRW[1-0] BRW[1-0] deassertion pulse width
22.5 45.2 tRHCP tCAS 18.7 14.8 tCRP 24.4 47.2 62.4 92.8 19.0 37.8 50.3 75.3 1.25 14.9 11.6 tASC 11.2 tCAH tRAL 1.75 22.5 17.9 41.5 33.5 tRCS 1.25 2.75 MHz: 0.25 MHz: 0.25 15.1 11.8 tRCH tWCH tRWL tCWL 18.5 33.4 37.4 33.6 14.6 26.8 30.1 27.0 DSP56301 Technical Data
Column address valid assertion assertion column address valid
Last column address valid deassertion deassertion assertion deassertion assertion assertion deassertion assertion pulse width Last assertion deassertion assertion deassertion Data valid assertion (write)
2A-24
Specifications: UDR2 Process Technology Masks
External Memory Expansion Port (Port
Table 2A-10. DRAM Page Mode Timings, Wait States1, (Continued)
Characteristics Symbol Expression assertion data valid (write) assertion assertion Last assertion deassertion assertion data valid tWCS tROH 1.75 MHz: 1.75 MHz: 1.75 22.5 10.9 33.9 17.9 27.3 Unit
19.0 0.75 11.1 0.25 Characteristics Symbol Expression 22.8 37.9 tCAC MHz: MHz: MHz: MHz: 53.0 DSP56301 Technical Data
15.4
deassertion data valid6
assertion data active
deassertion data high impedance Notes:
number wait states Page mode access specified DCR. refresh period specified DCR. asynchronous delays specified expressions valid DSP56301. timings calculated worst case. Some timings better specific cases (for example, equals read-after-read write-after-write sequences). BRW[1-0] (DRAM Control Register bits) defines number wait states that should inserted each DRAM out-of-page access. deassertion always occurs after deassertion; therefore, restricted timing tOFF tGZ. There DRAMs fast enough wait states Page mode 100MHz (see Figure 2A-14 page 2A-21).
Table 2A-11. DRAM Page Mode Timings, Three Wait States1,
Unit 18.5 31.0
43.8
Page mode cycle time assertion data valid (read)
Column address valid data valid (read)
2A-25
External Memory Expansion Port (Port
Specifications: UDR2 Process Technology Masks
Table 2A-11. DRAM Page Mode Timings, Three Wait States1, (Continued)
Characteristics Symbol Expression deassertion data valid (read hold time) Last assertion deassertion Previous deassertion deassertion assertion pulse width tOFF tRSH tRHCP tCAS 33.9 64.2 26.3 27.3 52.3 21.0 Unit
Last deassertion deassertion5 BRW[1-0] BRW[1-0] BRW[1-0] BRW[1-0] deassertion pulse width
tCRP 2.25 3.75 4.75 6.75 28.2 51.0 66.2 96.6 22.2 40.9 53.4 78.4 18.7 14.8 tASC 11.2 tCAH tRAL 33.9 56.6 27.3 46.0 tRCS 1.25 0.75 15.1 11.8 tRCH tWCH 2.25 29.9 23.9 48.5 39.3 tRWL 3.75 3.25 1.25 MHz: MHz: 52.5 44.9 33.9 14.6 49.0 42.6 36.3 27.3 11.3 39.8 tCWL tWCS tROH 30.4 DSP56301 Technical Data
24.8
Column address valid assertion
assertion column address valid Last column address valid deassertion deassertion assertion deassertion assertion assertion deassertion assertion pulse width
Last assertion deassertion assertion deassertion
Data valid assertion (write) assertion data valid (write) assertion assertion Last assertion deassertion assertion data valid
deassertion data valid6
2A-26
Specifications: UDR2 Process Technology Masks
External Memory Expansion Port (Port
Table 2A-11. DRAM Page Mode Timings, Three Wait States1, (Continued)
Characteristics Symbol Expression assertion data active deassertion data high impedance Notes: 0.75 0.25 11.1 Unit
Characteristics Symbol Expression 68.2 tCAC MHz: 2.75 MHz: 2.75 34.2 MHz: 3.75 MHz: 3.75 49.3 tOFF tRSH tRHCP tCAS tCRP 2.75 4.25 5.25 7.25 35.7 58.6 73.8 103.9 49.0 86.9 33.9 DSP56301 Technical Data
number wait states Page mode access specified DCR. refresh period specified DCR. asynchronous delays specified expressions valid DSP56301. timings calculated worst case. Some timings better specific cases (for example, equals read-after-read write-after-write sequences). BRW[1-0] (DRAM control register bits) defines number wait states that should inserted each DRAM out-of page-access. deassertion always occurs after deassertion; therefore, restricted timing tOFF tGZ.
Table 2A-12. DRAM Page Mode Timings, Four Wait States1,
Unit 27.9 40.4
Page mode cycle time
56.3
assertion data valid (read)
Column address valid data valid (read)
deassertion data valid (read hold time) Last assertion deassertion
39.8 71.0 27.3
Previous deassertion deassertion assertion pulse width Last deassertion deassertion5 BRW[1-0] BRW[1-0] BRW[1-0] BRW[1-0]
28.4 47.2 59.6 84.6
2A-27
External Memory Expansion Port (Port
Specifications: UDR2 Process Technology Masks
Table 2A-12. DRAM Page Mode Timings, Four Wait States1, (Continued)
Characteristics Symbol Expression deassertion pulse width Column address valid assertion assertion column address valid Last column address valid deassertion deassertion assertion deassertion assertion tASC tCAH tRAL 26.3 11.2 49.0 71.8 21.0 39.8 58.5 Unit
assertion deassertion assertion pulse width
Last assertion deassertion
assertion deassertion
Data valid assertion (write) assertion data valid (write)
assertion assertion Last assertion deassertion
assertion data valid
tRCS 1.25 1.25 3.25 15.1 15.2 45.0 11.8 11.9 36.4 tRCH tWCH 63.7 51.8 tRWL tCWL 4.75 67.7 55.1 3.75 52.5 42.6 49.0 39.8 tWCS tROH 1.25 14.6 11.3 64.2 52.3 MHz: 3.25 MHz: 3.25 41.7 valid6 0.75 0.25 11.1 DSP56301 Technical Data
34.1
Notes:
deassertion data
assertion data active deassertion data high impedance
number wait states Page mode access specified DCR. refresh period specified DCR. asynchronous delays specified expressions valid DSP56301. timings calculated worst case. Some timings better specific cases (for example, equals read-after-read write-after-write sequences). BRW[1-0] (DRAM control register bits) defines number wait states that should inserted each DRAM out-of-page access. deassertion always occurs after deassertion; therefore, restricted timing tOFF tGZ.
2A-28
Specifications: UDR2 Process Technology Masks
External Memory Expansion Port (Port
$>±@ &ROXPQ $GGUHVV &ROXPQ $GGUHVV /DVW &ROXPQ $GGUHVV
'>±@
'DWD 'DWD 'DWD
Figure 2A-15. DRAM Page Mode Write Accesses
DSP56301 Technical Data
2A-29
External Memory Expansion Port (Port
Specifications: UDR2 Process Technology Masks
$>±@ &ROXPQ $GGUHVV &ROXPQ $GGUHVV /DVW &ROXPQ $GGUHVV
'>±@
2A-30
'DWD 'DWD
'DWD
Figure 2A-16. DRAM Page Mode Read Accesses
DSP56301 Technical Data
Specifications: UDR2 Process Technology Masks '5$0 7\SH WS68
External Memory Expansion Port (Port
Note:This figure should used primary selection. exact detailed timings, following tables.
Table 2A-13. DRAM Out-of-Page Refresh Timings, Four Wait States1,
MHz4 MHz4 Unit 84.2 34.2 42.5 Characteristics3
Random read write cycle time assertion data valid (read) assertion data valid (read) Column address valid data valid (read) deassertion data valid (read hold time) deassertion assertion
:DLW VWDWHV :DLW VWDWHV :DLW VWDWHV :DLW VWDWHV
&KLS IUHTXHQF\
Figure 2A-17. DRAM Out-of-Page Wait States Selection Guide
Symbol
Expression
250.0
166.7 54.3
tRAC tCAC tOFF
2.75 1.25
130.0 55.0 67.5
1.75
83.5
DSP56301 Technical Data
2A-31
External Memory Expansion Port (Port
Specifications: UDR2 Process Technology Masks
Table 2A-13. DRAM Out-of-Page Refresh Timings, Four Wait States1, (Continued)
MHz4 Characteristics3 Symbol Expression assertion pulse width assertion deassertion assertion deassertion assertion pulse width assertion assertion tRAS tRSH tCSH tCAS 3.25 1.75 2.75 1.25 158.5 83.5 133.5 58.5 104.3 54.3 87.7 37.7 MHz4 Unit
assertion column address valid deassertion assertion deassertion pulse width
address valid assertion assertion address valid
Column address valid assertion
assertion column address valid assertion column address valid Column address valid deassertion deassertion assertion deassertion assertion deassertion assertion assertion deassertion assertion deassertion
2A-32
tRCD tRAD tCRP 73.0 60.5 77.0 64.5 48.0 39.7 1.25 2.25 1.75 1.75 1.25 0.25 108.5 83.5 83.5 58.5 71.0 54.3 54.3 37.7 tASR tRAH tASC tCAH 1.75 83.5 54.3 3.25 158.5 96.0 104.3 62.7 tRAL tRCS tRCH tRRH tWCH tWCR 0.75 0.25 71.2 33.8 70.8 145.8 46.2 21.3 45.8 95.8 DSP56301 Technical Data
52.0 43.7
Specifications: UDR2 Process Technology Masks
External Memory Expansion Port (Port
Table 2A-13. DRAM Out-of-Page Refresh Timings, Four Wait States1, (Continued)
MHz4 Characteristics3 Symbol Expression Notes: assertion pulse width assertion deassertion assertion deassertion Data valid assertion (write) assertion data valid (write) assertion data valid (write) assertion assertion tRWL tCWL 4.75 4.25 2.25 1.75 220.5 233.2 208.2 108.5 83.5 145.5 154.0 137.4 71.0 125.8 MHz4 Unit
assertion assertion (refresh)
deassertion assertion (refresh) assertion deassertion
assertion data valid
deassertion data valid3
assertion data active deassertion data high impedance
54.3 tDHR 3.25 158.5 104.3 95.7 tWCS tCSR tRPC 145.7 21.0 58.5 12.7 37.7 1.25 tROH 221.0 146.0 192.5 0.75 0.25 37.2 24.7 12.5 DSP56301 Technical Data
number wait states page access specified DCR. refresh period specified DCR. deassertion always occurs after deassertion; therefore, restricted timing tOFF tGZ. Reduced clock speed allows DRAM out-of-page access with four Wait states (see Figure 2A-17 page 2A-31).
2A-33
External Memory Expansion Port (Port
Specifications: UDR2 Process Technology Masks
Table 2A-14. DRAM Out-of-Page Refresh Timings, Eight Wait States1,
Characteristics4 Symbol Expression3 Random read write cycle time assertion data valid (read) tRAC MHz: 4.75 MHz: 4.75 MHz: 2.25 MHz: 2.25 136.4 64.5 26.6 112.5 52.9 21.6 31.0 33.3 23.9 Unit
assertion data valid (read)
Column address valid data valid (read)
deassertion data valid (read hold time)
deassertion assertion assertion pulse width
assertion deassertion assertion deassertion assertion pulse width
assertion assertion
assertion column address valid
deassertion assertion deassertion pulse width address valid assertion assertion address valid Column address valid assertion assertion column address valid assertion column address valid
2A-34
tCAC MHz: MHz: 40.0 tOFF 3.25 5.75 3.25 4.75 2.25 45.2 83.1 45.2 68.0 30.1 36.6 67.9 36.6 55.4 24.1 tRAS tRSH tCSH tCAS tRCD tRAD 35.9 39.9 29.3 1.75 24.5 28.5 19.9 49.1 30.4 36.6 17.9 36.6 67.9 tCRP 4.25 2.75 3.25 1.75 0.75 3.25 5.75 59.8 37.7 45.2 22.5 45.2 83.1 tASR tRAH tASC tCAH DSP56301 Technical Data
Specifications: UDR2 Process Technology Masks
External Memory Expansion Port (Port
Table 2A-14. DRAM Out-of-Page Refresh Timings, Eight Wait States1, (Continued)
Characteristics4 Symbol Expression3 Column address valid deassertion deassertion assertion deassertion assertion deassertion assertion tRAL tRCS tRCH tRRH 1.25 MHz: 0.25 MHz: 0.25 56.6 26.5 15.2 46.0 21.2 11.9 87.3 Unit
assertion deassertion assertion deassertion assertion pulse width
assertion deassertion assertion deassertion
Data valid assertion (write) assertion data valid (write) assertion data valid (write)
assertion assertion
assertion assertion (refresh)
deassertion assertion (refresh) assertion deassertion assertion data valid
deassertion data
assertion data active deassertion data high impedance
tWCH tWCR 41.3 79.1 124.3 tRWL tCWL 8.75 7.75 4.75 3.25 5.75 128.3 113.1 68.0 45.2 83.1 tDHR tWCS tCSR tRPC 79.0 18.7 1.75 22.5 tROH 124.8 11.1 MHz: MHz: 0.75 0.25 106.1 valid4 DSP56301 Technical Data
33.3
64.6
101.8 105.1 92.6 55.4 36.6 67.9
64.5 14.8 17.9
102.3
2A-35
External Memory Expansion Port (Port
Specifications: UDR2 Process Technology Masks
Table 2A-14. DRAM Out-of-Page Refresh Timings, Eight Wait States1, (Continued)
Characteristics4 Symbol Expression3 Notes: Unit
number wait states out-of-page access specified DCR. refresh period specified DCR. asynchronous delays specified expressions valid DSP56301. deassertion always occurs after deassertion; therefore, restricted timing tOFF tGZ. Either tRCH tRRH must satisfied read cycles.
Table 2A-15. DRAM Out-of-Page Refresh Timings, Eleven Wait States1,
Unit 71.6 40.4 49.8 33.3 23.9 Characteristics4 Symbol Expression3
Random read write cycle time
assertion data valid (read)
assertion data valid (read)
Column address valid data valid (read)
deassertion data valid (read hold time)
deassertion assertion assertion pulse width
assertion deassertion assertion deassertion assertion pulse width assertion assertion assertion column address valid deassertion assertion deassertion pulse width
2A-36
181.8 150.0 tRAC MHz: 6.25 MHz: 6.25 MHz: 3.75 MHz: 3.75 87.2 tCAC 49.3 MHz: MHz: 60.7 tOFF 4.25 7.75 5.25 6.25 3.75 1.75 5.75 4.25 60.4 49.1 tRAS 113.4 75.5 90.7 52.8 35.9 24.5 83.1 60.4 92.9 tRSH tCSH tCAS tRCD tRAD tCRP 39.9 28.5 61.6 74.1 42.9 29.3 19.9 67.9 49.1 DSP56301 Technical Data
Specifications: UDR2 Process Technology Masks
External Memory Expansion Port (Port
Table 2A-15. DRAM Out-of-Page Refresh Timings, Eleven Wait States1, (Continued)
Characteristics4 Symbol Expression3 address valid assertion assertion address valid Column address valid assertion assertion column address valid assertion column address valid Column address valid deassertion tASR tRAH tASC tCAH 4.25 1.75 0.75 5.25 7.75 60.4 22.5 75.5 49.1 17.9 61.6 92.9 71.0 33.7 Unit
deassertion assertion
deassertion assertion deassertion assertion
assertion deassertion assertion deassertion assertion pulse width
assertion deassertion assertion deassertion
Data valid assertion (write) assertion data valid (write) assertion data valid (write) assertion assertion assertion assertion (refresh)
deassertion assertion (refresh) assertion deassertion
113.4 86.9 41.7 tRAL tRCS tRCH tRRH 1.75 MHz: 0.25 MHz: 0.25 22.8 tWCH tWCR 71.6 109.4 11.5 169.7 tRWL tCWL 11.75 10.25 5.75 5.25 7.75 2.75 11.5 173.7 151.0 83.1 75.5 tDHR tWCS tCSR tRPC tROH 113.4 94.2 18.7 37.7 170.2 DSP56301 Technical Data
18.2
58.3 89.6
139.3
142.7 130.1 67.9 61.6 92.9 77.0 14.8 30.4 139.8
2A-37
External Memory Expansion Port (Port
Specifications: UDR2 Process Technology Masks
Table 2A-15. DRAM Out-of-Page Refresh Timings, Eleven Wait States1, (Continued)
Characteristics4 Symbol Expression3 assertion data valid MHz: MHz: Unit
144.0
118.5
deassertion data valid assertion data active deassertion data high impedance Notes:
0.75 0.25
11.1
number wait states out-of-page access specified DCR. refresh period specified DCR. asynchronous delays specified expressions valid DSP56301. deassertion always occurs after deassertion; therefore, restricted timing tOFF tGZ. Either tRCH tRRH must satisfied read cycles.
Table 2A-16. DRAM Out-of-Page Refresh Timings, Fifteen Wait States1,
Unit 96.6 52.9 62.3 Characteristics3 Symbol Expression
Random read write cycle time
assertion data valid (read)
assertion data valid (read)
Column address valid data valid (read)
deassertion data valid (read hold time) deassertion assertion assertion pulse width assertion deassertion
2A-38
242.4 90.7 143.7 90.7 200.0 MHz: 8.25 MHz: 8.25 MHz: 4.75 MHz: 4.75 117.5 64.5 MHz: MHz: 6.25 9.75 6.25 75.8 74.1 117.9 74.1 tOFF tRAS tRSH DSP56301 Technical Data
Specifications: UDR2 Process Technology Masks
External Memory Expansion Port (Port
Table 2A-16. DRAM Out-of-Page Refresh Timings, Fifteen Wait States1, (Continued)
Characteristics3 Symbol Expression assertion deassertion assertion pulse width assertion assertion assertion column address valid deassertion assertion deassertion pulse width tCSH tCAS tRCD tRAD tCRP 8.25 4.75 2.75 7.75 6.25 6.25 2.75 0.75 121.0 68.0 51.0 39.7 113.4 90.7 90.7 37.7 55.0 43.7 99.1 55.4 41.8 32.4 92.9 45.8 36.4 Unit
address valid assertion assertion address valid Column address valid assertion
assertion column address valid assertion column address valid Column address valid deassertion
deassertion assertion
deassertion assertion deassertion assertion
assertion deassertion assertion deassertion assertion pulse width assertion deassertion assertion deassertion
Data valid assertion (write) assertion data valid (write) assertion data valid (write) assertion assertion
tASR tRAH tASC tCAH 6.25 9.75 90.7 143.7 tRAL 102.1 72.0 tRCS tRCH tRRH 1.75 MHz: 0.25 MHz: 0.25 22.8 tWCH tWCR tRWL tCWL tWCS 86.7 15.5 15.75 14.25 8.75 6.25 9.75 139.7 230.3 234.3 211.6 128.6 90.7 143.7 139.6 DSP56301 Technical Data
74.1 74.1 30.4
74.1
117.9 83.5
58.7
18.2
70.8
114.6 189.3 192.6 180.1 105.4 74.1 117.9 114.5
2A-39
External Memory Expansion Port (Port
Specifications: UDR2 Process Technology Masks
Table 2A-16. DRAM Out-of-Page Refresh Timings, Fifteen Wait States1, (Continued)
Characteristics3 Symbol Expression assertion assertion (refresh) deassertion assertion (refresh) assertion deassertion assertion data valid tCSR tRPC tROH 4.75 15.5 MHz: MHz: 18.7 68.0 230.8 204.6 14.8 55.4 189.8 168.5 Unit
deassertion data valid3 assertion data active
deassertion data high impedance Notes:
number wait states out-of-page access specified DCR. refresh period specified DCR. deassertion always occurs after deassertion; therefore, restricted timing tOFF tGZ. Either tRCH tRRH must satisfied read cycles.
2A-40
0.75 0.25 11.1 DSP56301 Technical Data
Specifications: UDR2 Process Technology Masks
External Memory Expansion Port (Port
$>±@
$GGUHVV &ROXPQ $GGUHVV
'>±@
Figure 2A-18. DRAM Out-of-Page Read Access
DSP56301 Technical Data
2A-41
External Memory Expansion Port (Port
Specifications: UDR2 Process Technology Masks
$>±@
'>±@
2A-42
$GGUHVV &ROXPQ $GGUHVV 'DWD
Figure 2A-19. DRAM Out-of-Page Write Access
DSP56301 Technical Data
Specifications: UDR2 Process Technology Masks
External Memory Expansion Port (Port
Synchronous Timings (SRAM)
Figure 2A-20. DRAM Refresh Access
Table 2A-17. External Synchronous Timings (SRAM Access)4
Unit Characteristics Expression1,
CLKOUT high assertion
MHz: 0.25
13.9
MHz: 0.25 MHz: 0.75 MHz: 0.75
CLKOUT high deassertion
12.4
16.4
10.4
CLKOUT high address valid5
MHz: 0.25 MHz: 0.25
DSP56301 Technical Data
2A-43
External Memory Expansion Port (Port
Specifications: UDR2 Process Technology Masks
Table 2A-17. External Synchronous Timings (SRAM Access)4 (Continued)
Characteristics Expression1, CLKOUT high address invalid5 CLKOUT high invalid valid CLKOUT high (setup time) CLKOUT high invalid (hold time) CLKOUT high data active CLKOUT high data valid 0.25 0.25 13.9 Unit
CLKOUT high data invalid
CLKOUT high data high impedance
Data valid CLKOUT high (setup)
CLKOUT high data invalid (hold) CLKOUT high assertion
CLKOUT high deassertion CLKOUT high assertion3
MHz: 0.25 MHz: 0.25 0.25 MHz: 0.25 MHz: 0.25 MHz: 0.75 MHz: 0.75 12.4 16.4 10.4 MHz: MHz: frequencies: 12.9 DSP56301 Technical Data
11.1
CLKOUT high deassertion Notes:
number wait states specified BCR. asynchronous delays specified expressions valid DSP56301. assertion refers next rising edge CLKOUT. External synchronous timings should used only reference clock relative timings. T198 T199 valid Address Trace mode set. status (See T212) determine whether access referenced A[0-23] internal external, when this mode enabled.
2A-44
Specifications: UDR2 Process Technology Masks
External Memory Expansion Port (Port
&/.287 $>±@ $$>±@
'>±@
'>±@
'DWD 'DWD
DSP56301 Technical Data
Figure 2A-21. Synchronous Timings SRAM (BCR Controlled)
2A-45
External Memory Expansion Port (Port
Specifications: UDR2 Process Technology Masks
&/.287 $>±@ $$>±@
'>±@
'>±@
Figure 2A-22. Synchronous Timings SRAM Controlled)
2A-46
'DWD 'DWD
DSP56301 Technical Data
Specifications: UDR2 Process Technology Masks
External Memory Expansion Port (Port
Arbitration Timings
Table 2A-18. Arbitration Timings1
Characteristics Expression CLKOUT high assertion/deassertion2 asserted/deasserted CLKOUT high (setup) CLKOUT high deasserted/asserted (hold) deassertion CLKOUT high (input setup) CLKOUT high assertion (input hold) CLKOUT high assertion (output) Unit
CLKOUT high deassertion (output) high high impedance (output)
CLKOUT high address controls active CLKOUT high address controls high impedance
CLKOUT high active
CLKOUT high deassertion
CLKOUT high high impedance
Notes:
0.25 MHz: 0.25 MHz: 0.25 0.25 MHz: 0.25 MHz: 0.25 MHz: 0.75 MHz: 0.75 12.4 DSP56301 Technical Data
asynchronous delays specified expressions valid DSP56301. T212 valid Address Trace mode when set. deasserted internal accesses asserted external accesses.
2A-47
External Memory Expansion Port (Port
Specifications: UDR2 Process Technology Masks
&/.287
$>±@
$$>±@
2A-48
Figure 2A-23. Acquisition Timings
DSP56301 Technical Data
Specifications: UDR2 Process Technology Masks
External Memory Expansion Port (Port
&/.287
$>±@
$$>±@
DSP56301 Technical Data
Figure 2A-24. Release Timings Case (BRT Cleared)
2A-49
External Memory Expansion Port (Port
Specifications: UDR2 Process Technology Masks
&/.287
$>±@
$$>±@
2A-50
Figure 2A-25. Release Timings Case (BRT Set)
DSP56301 Technical Data
Specifications: UDR2 Process Technology Masks
Host Interface Timing
HOST INTERFACE TIMING
Table 2A-19. Universal Mode Timing Parameters
Characteristic Expression Access Cycle Time HA[10-0], HAEN Setup Data Strobe Assertion1 HA[10-0], HAEN Valid Hold from Data Strobe Deassertion1 Setup Assertion2 45.5 37.5 18.9 12.0 22.2 Unit
Valid Hold from Deassertion2 Data Strobe Deasserted Width
Data Strobe Asserted Pulse Width1 Asserted Pulse Width
Assertion Data Strobe Assertion1
Assertion Data Strobe Deassertion1
Deassertion Data Strobe Deassertion1 Data Valid Assertion (HBS Used-Tied VCC)2
Data Active from Read Data Strobe Assertion3
Data Valid from Read Data Strobe Assertion Wait States Inserted-HTA Asserted)3 Data Valid Hold from Read Data Strobe Deassertion3 Data High Impedance from Read Data Strobe Deassertion3 Data Valid Setup Write Data Strobe Deassertion4 Data Valid Hold from Write Data Strobe Deassertion4 HSAK Assertion from Data Strobe Assertion1 HSAK Asserted Hold from Data Strobe Deassertion1 Active from Data Strobe Assertion1,2,5
39.9 14.0 41.4 26.7 16.3 21.0 14.5 25.0 10.0 DSP56301 Technical Data
32.9
34.1 22.1 11.0
2A-51
Host Interface Timing
Specifications: UDR2 Process Technology Masks
Table 2A-19. Universal Mode Timing Parameters (Continued)
Characteristic Expression Assertion from Data Strobe Assertion (HBS Used-Tied VCC)1,2,5 Assertion from Assertion2,5 Deasserted from Data Strobe Assertion1,2,5 Assertion Data Strobe Deassertion1,2 High Impedance from Data Strobe Deassertion1,2 HIRQ Asserted Pulse Width (HIRH HIRD 13.8 13.8 44.1 44.1 26.7 18.5 37.8 37.8 23.6 15.3 55.9 55.9 Unit
Data Strobe Deasserted Hold from HIRQ Deassertion (HIRH
HIRQ Asserted Hold from Data Strobe Assertion (HIRH HIRQ Deassertion from Data Strobe Assertion (HIRH HIRD HIRQ High Impedance from Data Strobe Assertion (HIRH HIRD 0)1,6
HIRQ Active from Data Strobe Deassertion (HIRH HIRD HIRQ Deasserted Hold from Data Strobe Deassertion1 HDRQ2 Asserted Hold from Data Strobe Assertion1 HDRQ2 Deassertion from Data Strobe Assertion1
6.07 22.7 18.8 28.0 28.0 65.9 65.9 37.9 37.9 22.7 31.3 31.3 18.8 28.0 65.9 25.0 42.4 35.0 DSP56301 Technical Data
55.9 22.2
HDRQ2 Deasserted Hold from Data Strobe Deassertion1 HDAK Assertion Data Strobe Assertion1 HDAK Asserted Hold from Data Strobe Deassertion1
HDBEN Deasserted Hold from Data Strobe Assertion1 HDBEN Assertion from Data Strobe Assertion1 HDBEN Asserted Hold from Data Strobe Deassertion1
2A-52
Specifications: UDR2 Process Technology Masks
Host Interface Timing
Table 2A-19. Universal Mode Timing Parameters (Continued)
Characteristic Expression HDBEN Deassertion from Data Strobe Deassertion1 HDBDR High Hold from Read Data Strobe Assertion3 HDBDR from Read Data Strobe Assertion3 HDBDR Hold from Read Data Strobe Deassertion3 HDBDR High from Read Data Strobe Deassertion3 25.0 25.0 22.2 22.2 22.2 22.2 Unit
HRST Assertion Host Port Pins High Impedance2 Notes:
25.0 25.0 Characteristic Expression 45.5 DSP56301 Technical Data
Data Strobe Dual Data Strobe mode Single-Data Strobe mode. HTA, HDRQ, HRST programmed active-high active-low. example timing diagrams, HDRQ HRST shown active-high shown active low. Read Data Strobe Dual Data Strobe mode Single-Data Strobe mode. Write Data Strobe Dual Data Strobe mode Single-Data Strobe mode. requires external pull-down resistor programmed active high (HTAP external pull-up resistor programmed active (HTAP resistor value should consistent with specifications. HIRQ requires external pull-up resistor programmed open drain (HIRD resistor value should consistent with specifications. "LT" value latency timer register (CLAT) programmed user during selfconfiguration. Values valid 0.3V Asynchronous delay this expression valid only 66MHz DSP56301/D (DSP56301PW66 DSP56301GC66).
Table 2A-20. Universal Mode, Synchronous Port Type Host Timing
Unit 37.5
Access Cycle Time HA[10-0], HAEN Setup Data Strobe Assertion1 HA[10-0], HAEN Valid Hold from Data Strobe Deassertion1 Data Strobe Deasserted Width1
2A-53
Host Interface Timing
Specifications: UDR2 Process Technology Masks
Table 2A-20. Universal Mode, Synchronous Port Type Host Timing (Continued)
Characteristic Expression Asserted Pulse Width Assertion Data Strobe Assertion1 Assertion Data Strobe Deassertion1 Deassertion Data Strobe Deassertion1 Data Active from Read Data Strobe Assertion3 41.4 26.7 34.1 22.1 18.9 12.0 15.3 55.9 55.9 Unit
Data Valid from Read Data Strobe Assertion Wait States Inserted-HTA Asserted)3 Data Valid Hold from Read Data Strobe Deassertion3 Data High Impedance from Read Data Strobe Deassertion3 Data Valid Setup Write Data Strobe Deassertion4
Data Valid Hold from Write Data Strobe Deassertion4
Assertion Data Strobe Deassertion1,2 High Impedance from Data Strobe Deassertion1,2 HIRQ Asserted Pulse Width (HIRH HIRD
Data Strobe Deasserted Hold from HIRQ Deassertion (HIRH
HIRQ Asserted Hold from Data Strobe Assertion (HIRH HIRQ Deassertion from Data Strobe Assertion (HIRH HIRD HIRQ High Impedance from Data Strobe Assertion (HIRH HIRD 0)1,6 HIRQ Active from Data Strobe Deassertion (HIRH HIRD HIRQ Deasserted Hold from Data Strobe Deassertion1 HRST Assertion Host Port Pins High Impedance2
21.0 14.5 10.0 18.5 6.07 22.7 18.8 28.0 28.0 65.9 65.9 37.9 37.9 25.0 31.3 31.3 DSP56301 Technical Data
22.2
2A-54
Specifications: UDR2 Process Technology Masks
Host Interface Timing
Table 2A-20. Universal Mode, Synchronous Port Type Host Timing (Continued)
Characteristic Expression Assertion CLKOUT Rising Edge Data Strobe Deassertion CLKOUT Rising Edge1 Notes: Unit
+,54
Data Strobe Dual Data Strobe mode Single-Data Strobe mode. HTA, HDRQ, HRST programmed active-high active-low. example timing diagrams, HDRQ HRST shown active-high shown active low. Read Data Strobe Dual Data Strobe mode Single-Data Strobe mode. Write Data Strobe Dual Data Strobe mode Single-data Strobe mode. requires external pull-down resistor programmed active high (HTAP external pull-up resistor programmed active (HTAP resistor value should consistent with specifications. HIRQ requires external pull-up resistor programmed open drain (HIRD resistor value should consistent with specifications. "LT" value latency timer register (CLAT) programmed user during selfconfiguration. Values valid 0.3V Asynchronous delay this expression valid only 66MHz DSP56301/D (DSP56301PW66 DSP56301GC66).
Figure 2A-26. Timing
Figure 2A-27. HIRQ Pulse Width (HIRH
DSP56301 Technical Data
2A-55
Host Interface Timing
Specifications: UDR2 Process Technology Masks
+567 2XWSXWV
Figure 2A-28. HRST Timing
+'>±@
+6$.
9DOLG 2XWSXW
+'%'5
+'%(1
Figure 2A-29. Read Timing
2A-56
DSP56301 Technical Data
Specifications: UDR2 Process Technology Masks
Host Interface Timing
9DOLG ,QSXW
+'>±@
+6$. +'%'5
+'%(1
Figure 2A-30. Write Timing
&/.287
Figure 2A-31. Synchronous Timing
DSP56301 Technical Data
2A-57
Host Interface Timing
Specifications: UDR2 Process Technology Masks
&/.287
Figure 2A-32. Data Strobe Synchronous Timing Table 2A-21. Mode Timing Parameters1
Characteristic10 Symbol tVAL 11.0 12.0 tVAL(ptp) tOFF 28.0 tSU(ptp) 10.0, 12.0 10.0, 12.0 tRST tRST-CLK 100.0 100.0 tRST-OFF tCYC 40.0 30.0 12.0 12.0 30.0 11.0 11.0 tHIGH tLOW DSP56301 Technical Data
Unit
Notes:
HCLK Signal Valid Delay-Bussed Signals HCLK Signal Valid Delay-Point Point Float Active Delay
11.0 12.0
Active Float Delay
28.0
Input Time HCLK-Bussed Signals Input Time HCLK-Point Point Input Hold Time from HCLK
Reset Active Time After Power Stable Reset Active Time After HCLK Stable Reset Active Output Float Delay HCLK Cycle Time HCLK High Time HCLK Time
40.0
standard timing, Local Specification, Rev. 2.0, especially Chapters HI32 supports these timings operating clock frequency above. core operating frequency should greater than frequency maintain proper operation. HGNT setup time
2A-58
Specifications: UDR2 Process Technology Masks
Host Interface Timing
+&/. 287387 '(/$< +LJK ,PSHGDQFH 287387
,1387
32:(5
+&/.
+567
6LJQDOV
Figure 2A-33. Timing
Figure 2A-34. Reset Timing
DSP56301 Technical Data
2A-59
Timing
Specifications: UDR2 Process Technology Masks
TIMING
Table 2A-22. Timing
Characteristics1 Symbol tSCC2 tSCC/2 10.0 tSCC/2 10.0 tSCC/4 -17.0 Expression Synchronous clock cycle Clock period Clock high period Output data setup clock falling edge (internal clock) Output data hold after clock rising edge (internal clock) Input data setup time before clock rising edge (internal clock) 121.0 50.5 50.5 20.5 100.0 40.0 40.0 14.3 Unit
tSCC/4 22.5 18.8 tSCC/4 25.0 63.0 56.3 tSCC/4 32.0 32.0 23.0 20.5 tACC3 tACC/2 10.0 tACC/2 10.0 tACC/2 30.0 969.7 474.8 474.8 458.8 800.0 390.0 390.0 370.0 tACC/2 30.0 458.8 370.0 DSP56301 Technical Data
Input data valid before clock rising edge (internal clock) Clock falling edge output data valid (external clock)
25.8
32.0
Output data hold after clock rising edge (external clock) Input data setup time before clock rising edge (external clock)
Input data hold time after clock rising edge (external clock) Asynchronous clock cycle Clock period Clock high period Output data setup clock rising edge (internal clock) Output data hold after clock rising edge (internal clock)
2A-60
Specifications: UDR2 Process Technology Masks
Timing
Table 2A-22. Timing (Continued)
Characteristics1 Symbol Expression Notes: Unit
-40°C +100 tSCC synchronous clock cycle time. (For internal clock, tSCC determined clock control register TC.) tACC asynchronous clock cycle time; value given Clock mode. (For internal clock, tACC determined clock control register TC.)
SCLK (Output) Data Valid Data Valid Internal Clock SCLK (Input) Data Valid Data Valid External Clock
Figure 2A-35. Synchronous Mode Timing
DSP56301 Technical Data
2A-61
ESSI0/ESSI1 Timing
Specifications: UDR2 Process Technology Masks
SCLK (Output) Data Valid
ESSI0/ESSI1 TIMING
Characteristics4,
Table 2A-23. ESSI Timings
Expression Symbol tSSICC 60.6 45.5 20.3 22.7 20.3 22.7 50.0 37.5 15.0 18.8 15.0 18.8 10.0 10.0 37.0 22.0 37.0 22.0 37.0 22.0 37.0 22.0 19.0 39.0 24.0 39.0 24.0 36.0 21.0 37.0 22.0 19.0 39.0 24.0 39.0 24.0 36.0 21.0 37.0 22.0 DSP56301 Technical Data
Figure 2A-36. Asynchronous Mode Timing
Condition5
Unit
Clock cycle1
Clock high period internal clock external clock Clock period internal clock external clock
rising edge (bl) high rising edge (bl) rising edge (wr) high2 rising edge (wr) low2 rising edge (wl) high rising edge (wl)
Data setup time before (SCK Synchronous mode) falling edge
2A-62
Specifications: UDR2 Process Technology Masks
ESSI0/ESSI1 Timing
Table 2A-23. ESSI Timings (Continued)
Characteristics4, Symbol Expression Data hold time after falling edge input (bl, high before falling edge2 input (wl) high before falling edge input hold time after falling edge Flags input setup before falling edge 23.0 23.0 23.0 23.0 Condition5 Unit
Flags input hold time after falling edge rising edge (bl) high rising edge (bl) rising edge (wr) high2
rising edge (wr) low2 rising edge (wl) high rising edge (wl)
rising edge data enable from high impedance
rising edge Transmitter drive enable assertion rising edge data valid rising edge data high impedance3
rising edge Transmitter drive enable deassertion3 input (bl, setup time before falling edge2
19.0 19.0 29.0 15.0 31.0 17.0 31.0 17.0 33.0 19.0 30.0 16.0 31.0 17.0 31.0 17.0 34.0 20.0 21.0 21.0 42.6 21.0 31.0 16.0 34.0 20.0 21.0 DSP56301 Technical Data
29.0 15.0
31.0 17.0 31.0 17.0
33.0 19.0
30.0 16.0 31.0 17.0 31.0 17.0 34.0 20.0 41.3 21.0 31.0 16.0 34.0 20.0
2A-63
ESSI0/ESSI1 Timing
Specifications: UDR2 Process Technology Masks
Table 2A-23. ESSI Timings (Continued)
Characteristics4, Symbol Expression input (wl) data enable from high impedance input (wl) Transmitter drive enable assertion input (wl) setup time before falling edge input hold time after falling edge Flag output valid after rising edge Notes: 21.0 27.0 31.0 21.0 27.0 31.0 Condition5 Unit
internal clock, external clock cycle defined Icyc ESSI control register. word-relative frame sync signal waveform relative clock operates same manner bit-length frame sync signal waveform, spreads from serial clock before first clock (same Length Frame Sync signal), until before last clock first word frame. Periodically sampled percent tested. -40°C +100 (SCK Pin) Transmit Clock (SC0 Pin) Receive Clock (SC2 Pin) Transmit Frame Sync (SC1 Pin) Receive Frame Sync Internal Clock External Clock Internal Clock, Asynchronous mode (Asynchronous implies that different clocks) Internal Clock, Synchronous mode (Synchronous implies that same clock) length word length word length relative
2A-64
32.0 18.0 32.0 18.0 DSP56301 Technical Data
Specifications: UDR2 Process Technology Masks
ESSI0/ESSI1 Timing
,QSXW 2XWSXW
:RUG
'DWD First Last 7UDQVPLWWHU 'ULYH (QDEOH )ODJV
:RUG
Note
Note:
Network mode, output flag transitions occur start each time slot within frame. Normal mode, output flag state asserted entire frame period.
Figure 2A-37. ESSI Transmitter Timing
DSP56301 Technical Data
2A-65
ESSI0/ESSI1 Timing
Specifications: UDR2 Process Technology Masks
(Input/Output) (Bit) (Word)
Data
(Bit)
(Word)
Flags
2A-66
First Last
Figure 2A-38. ESSI Receiver Timing
DSP56301 Technical Data
Specifications: UDR2 Process Technology Masks
Timer Timing
TIMER TIMING
Table 2A-24. Timer Timing
Characteristics Expression High Timer setup time from (Input) assertion CLKOUT rising edge Synchronous timer delay time from CLKOUT rising edge external memory access address valid caused first interrupt instruction execution 32.5 32.5 10.25 156.0 15.15 27.0 27.0 129.1 12.5 Unit
CLKOUT rising edge (Output) assertion Minimum Maximum 19.8 CLKOUT rising edge (Output) deassertion Minimum Maximum Note:
11.1 28.1 19.8 11.1 28.1
26.1
26.1
-40°C +100
Figure 2A-39. Timer Event Input Restrictions
DSP56301 Technical Data
2A-67
GPIO Timing
Specifications: UDR2 Process Technology Masks
&/.287
,QSXW $GGUHVV
&/.287
2XWSXW
GPIO TIMING
)LUVW ,QWHUUXSW ,
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