Single Supply, 16-Bit Converter CS5509 single supply, 16-bit, ser
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CS5509
Single Supply, 16-Bit Converter
CS5509 single supply, 16-bit, serial-output CMOS converter. CS5509 uses charge-balanced (delta-sigma) techniques provide cost, high resolution measurement output word rates samples second. on-chip digital filter offers superior line rejection when device operated from 32.768 clock (output word rate Hz.). CS5509 on-chip self-calibration circuitry which initiated time temperature ensure minimum offset full-scale errors. power, high resolution small package size make CS5509 ideal solution loop-powered transmitters, panel meters, weigh scales battery powered instruments. ORDERING INFORMATION CS5509-AP -40° +85° 16-pin Plastic CS5509-AS -40° +85° 16-pin SOIC
Delta-Sigma Converter Differential Input
16-bit Missing Codes Linearity Error: ±0.0015%FS Selectable Unipolar/Bipolar Ranges Common Mode Rejection
Either Digital Interface On-chip Self-Calibration Circuitry Output Update Rates 200/second Ultra Power:
VREF+
VREF10
DGND
SCLK SDATA
AIN+
Differential 4th-Order Delta-Sigma Modulator Digital Filter
Serial Interface Logic
AIN-
DRDY
Calibration Calibration SRAM CONV XOUT
BP/UP
Cirrus Logic, Inc. Crystal Semiconductor Products Division P.O. 17847, Austin, Texas 78760 (512) 7222 FAX: (512) 7581 http://www.crystal.com
Copyright Cirrus Logic, Inc. 1997 (All Rights Reserved)
DS125F1
CS5509
ANALOG CHARACTERISTICS 25°C; 10%; 3.3V VREF+ 2.5V, VREF- fCLK 330kHz; Bipolar Mode; Rsource with 10nF AIN; AIN- 2.5V; unless otherwise specified.) (Notes
Parameter* (Note (Note (Note (Note (Note (Note Unipolar Bipolar 50,60 (Note ITotal IAnalog IDigital (Note 0.0015 0.0015 0.0015 0.005 ±0.25 ±0.25 ±0.5 ±0.5 ±0.5 ±0.25 ±0.25 0.16 +2.5 ±2.5 0.003 0.003 0.003 0.0125 ±0.5 2.25 Units ±%FS ±%FS ±%FS ±%FS LSBrms Volts Volts
Accuracy Linearity Error
fCLK fCLK fCLK fCLK
32.768 247.5
Differential Nonlinearity Full Scale Error Full Scale Drift Unipolar Offset Unipolar Offset Drift Bipolar Offset Bipolar Offset Drift Noise (Referred Output)
Analog Input Analog Input Range:
Common Mode Rejection: fCLK 32.768kHz Input Capacitance Bias Current
(Note (Note
Power Supplies Power Supply Currents:
Power Dissipation Power Supply Rejection
Notes: Both source resistance shunt capacitance critical determining CS5509's source impedance requirements. Refer text section Analog Input Impedance Considerations. Specifications guaranteed design, characterization and/or test. Applies after calibration temperature interest. Total drift over specified temperature range since calibration power-up 25°C. input differential. Therefore, Signal Common Mode Voltage VA+. CS5509 accept input voltages analog supply. unipolar mode CS5509 will output input magnitude ((AIN+)-(AIN-)) exceeds ((VREF+)-(VREF-)) will output input becomes more negative than Volts. bipolar mode CS5509 will output input magnitude ((AIN+)-(AIN-)) exceeds ((VREF+)-(VREF-)) will output input becomes more negative magnitude than -((VREF+)-(VREF-)). outputs unloaded. inputs CMOS levels.
Refer Specification Definitions immediately following Description Section. Specifications subject change without notice. DS125F1
CS5509
DYNAMIC CHARACTERISTICS
Parameter Modulator Sampling Frequency Output Update Rate (CONV Filter Corner Frequency Settling Time Step) Symbol fout f-3dB Ratio fclk/2 fclk/1622 fclk/1928 1/fout Units
DIGITAL CHARACTERISTICS
(Notes Parameter
25°C; VA+, 10%;
Symbol Units High-Level Input Voltage: Pins Except Low-Level Input Voltage: Pins Except (VD+)-1.0 High-Level Output Voltage (Note Low-Level Output Voltage Iout 1.6mA Input Leakage Current 3-State Leakage Current Cout Digital Output Capacitance Notes: measurements performed under static conditions. Iout -100 This guarantees ability drive load. (VOH 2.4V Iout µA).
3.3V DIGITAL CHARACTERISTICS 25°C;
(Notes Parameter High-Level Input Voltage: Low-Level Input Voltage: High-Level Output Voltage Low-Level Output Voltage Input Leakage Current 3-State Leakage Current Digital Output Capacitance Pins Except Pins Except Iout -400µA Iout 400µA
10%; 3.3V 0.3VD+ 0.16VD+ Units
Symbol 0.7VD+ 0.6VD+ (VD+)-0.3 Cout
DS125F1
CS5509
SWITCHING CHARACTERISTICS
Logic Logic VD+; pF.) (Note Parameter Master Clock Frequency Internal Oscillator: External Clock:
25°C; VA+, 10%; Input Levels: Symbol fclk 30.0 32.768 53.0 Units
Master Clock Duty Cycle trise Rise Times: Digital Input (Note Digital Output tfall Fall Times: Digital Input (Note Digital Output Start-Up tres Power-On Reset Period (Note tosu Oscillator Start-up Time XTAL=32.768 (Note 1800/fclk Wake-up Period (Note twup Calibration CONV Pulse Width (CAL=1) (Note tccw tscl 2/fclk+200 CONV High Start Calibration 3246/fclk tcal Start Calibration Calibration Conversion tcpw CONV Pulse Width tscn 2/fclk+200 CONV High Start Conversion 82/fclk tbus Time BP/UP stable prior DRDY falling tbuh Hold Time BP/UP stable after DRDY falls tcon 1624/fclk Start Conversion Conversion (Note Notes: Specified using points waveform interest. internal power-on-reset activated whenever power applied device. Oscillator start-up time varies with crystal parameters. This specification does apply when using external clock source. wake-up period begins once oscillator starts; when using external fclk, after power-on reset time elapses. Calibration also initiated pulsing high while CONV=1. Conversion time will 1622/fclk CONV remains high continuously.
DS125F1
CS5509
3.3V SWITCHING CHARACTERISTICS
Parameter Master Clock Frequency Internal Oscillator: External Clock:
25°C; 10%; 3.3V Input Levels: Logic Logic VD+; pF.) (Note Symbol fclk trise tfall 30.0 82/fclk 32.768 1800/fclk 3246/fclk 1624/fclk 53.0 2/fclk+200 2/fclk+200 Units
Master Clock Duty Cycle Rise Times: Digital Input (Note Digital Output Fall Times: Digital Input (Note Digital Output Start-Up Power-On Reset Period (Note Oscillator Start-up Time XTAL=32.768 (Note Wake-up Period (Note Calibration CONV Pulse Width (CAL=1) (Note CONV High Start Calibration Start Calibration Calibration Conversion CONV Pulse Width CONV High Start Conversion Time BP/UP stable prior DRDY falling Hold Time BP/UP stable after DRDY falls Start Conversion Conversion (Note
tres tosu twup tccw tscl tcal tcpw tscn tbus tbuh tcon
DS125F1
CS5509
XIN/2 CONV STATE Standby Calibration Standby
Figure Calibration Timing (Not Scale)
XIN/2 CONV DRDY BP/UP STATE Standby Conversion Standby
Figure Conversion Timing (Not Scale)
DS125F1
CS5509
SWITCHING CHARACTERISTICS 25°C; VA+, 10%; Input Levels: Logic
Logic VD+; pF.) (Note Parameter Pulse Width High Pulse Width Access Time: data valid (Note Maximum Delay Time: SCLK falling SDATA (Note Output Float Delay High output Hi-Z (Note SCLK falling Hi-Z Serial Clock Serial Clock Symbol fsclk tcsd tfd1 tfd2 Units
Notes: activated asynchronously DRDY, will recognized occurs when DRDY high clock cycles. propagation delay time great cycles plus guarantee proper clocking SDATA when using asynchronous SCLK(i) should taken high sooner than fclk after goes low. SDATA transitions falling edge SCLK. Note that rising SCLK must occur enable serial port shifting mechanism before falling edges recognized. returned high before data bits output, SDATA output will complete current data then high impedance.
3.3V SWITCHING CHARACTERISTICS 25°C; 10%, 3.3V
Input Levels Logic Logic VD+; 50pF.) (Note Parameter Pulse Width High Pulse Width Access Time: data valid (Note Maximum Delay Time: SCLK falling SDATA (Note Output Float Delay High output Hi-Z (Note SCLK falling Hi-Z Serial Clock Serial Clock Symbol fsclk tcsd tfd1 tfd2 1.25 Units
DS125F1
CS5509
DRDY SDATA(o) SCLK(i) Hi-Z MSB-1 MSB-2
DRDY SDATA(o) Hi-Z SCLK(i) MSB-1 LSB+2 LSB+1
Figure Timing Relationships (Not Scale)
DS125F1
CS5509
RECOMMENDED OPERATING CONDITIONS
(DGND (Note (VREF+)-(VREF-) (VREF+)-(VREF-) Units
Parameter Symbol Power Supplies: Positive Digital 3.15 Positive Analog Analog Reference Voltage (Note (VREF+)-(VREF-) Analog Input Voltage: (Note Unipolar VAIN Bipolar VAIN -((VREF+)-(VREF-))
Notes: voltages with respect ground. CS5509 operated with reference voltage with corresponding reduction noise-free resolution. common mode voltage voltage reference value long +VREF -VREF remain inside supply values GND.
ABSOLUTE MAXIMUM RATINGS*
Symbol Power Supplies: Ground (Note Positive Digital (Note Positive Analog Input Current, Except Supplies (Notes Iout Output Current Power Dissipation (Total) (Note VINA Analog Input Voltage VREF pins VIND Digital Input Voltage Ambient Operating Temperature Tstg Storage Temperature Notes: Parameter -0.3 -0.3 -0.3 -0.3 -0.3 (VD+)-0.3 (VA+)+0.3 (VD+)+0.3 Units
should more positive than (VA+)+0.3V. must always less than (VA+)+0.3V, never exceed +6.0 Applies pins including continuous overvoltage conditions analog input (AIN) pin. Transient currents 100mA will cause latch-up. Maximum input current power supply Total power dissipation, including input currents output currents.
WARNING: Operation beyond these limits result permanent damage device. Normal operation guaranteed these extremes.
DS125F1
CS5509 GENERAL DESCRIPTION CS5509 power, 16-bit, monolithic CMOS converter designed specifically measurement signals. CS5509 includes delta-sigma charge-balance converter, voltage reference, calibration microcontroller with SRAM, digital filter serial interface. CS5509 optimized operate from 32.768 crystal driven external clock whose frequency between kHz. When digital filter operated with 32.768 clock, filter zeros precisely line frequencies multiples thereof. CS5509 uses "start convert" command start convolution cycle digital filter. Once filter cycle completed, output port updated. When operated with 32.768 clock converts updates output port samples/sec. output port operates synchronous externally-clocked interface format. tion this command will occur until complete wake-up period elapses. command given, device enters standby state. Calibration After initial application power, CS5509 must enter calibration state prior performing accurate conversions. During calibration, chip executes two-step process. device first performs offset calibration then follows this with gain calibration. calibration steps determine zero reference point full scale reference point converter's transfer function. From these points calibrates zero point gain slope used properly scale output digital codes when doing conversions. calibration state entered whenever CONV pins high same time. state CONV pins poweron recognized commands, will executed until 1800 clock cycle wake-up period. CONV become active (high) during 1800 clock cycle wake-up time, converter will wait until wake-up period elapses before executing calibration. wake-up time elapsed, converter will standby mode waiting instruction will enter calibration cycle immediately CONV become active. calibration lasts 3246 clock cycles. Calibration coefficients then retained SRAM (static RAM) during conversion. state BP/UP ignored during calibration should remain stable throughout calibration period minimize noise. When conversions performed unipolar mode bipolar mode, converter uses same calibration factors compute digital
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THEORY OPERATION Basic Converter Operation CS5509 converter three operating states. These stand-by, calibration, conversion. When power first applied, internal power-on reset delay about resets logic device. oscillator must then begin oscillating before device considered functional. After power-on reset applied, device enters wake-up period 1800 clock cycles after clock present. This allows delta-sigma modulator other circuitry (which operating with very currents) reach stable bias condition prior entering into either calibration conversion states. During 1800 cycle wake-up period, device accept input command. Execu10
CS5509 output code. only difference that bipolar mode on-chip microcontroller offsets computed output word code value 8000H. This means that bipolar measurement range calibrated from full scale positive full scale negative. Instead calibrated from bipolar zero scale point full scale positive. slope factor then extended below bipolar zero accommodate negative input signals. converter used convert both unipolar bipolar signals changing BP/UP pin. Recalibration required when switching between unipolar bipolar modes. calibration cycle, on-chip microcontroller checks logic state CONV signal. CONV input device will enter standby mode where waits further instruction. CONV signal high calibration cycle, converter will enter conversion state perform conversion input channel. signal returned time after calibration initiated. CONV also returned low, should never taken then taken back high until calibration period ended converter standby state. CONV taken then high again with high while converter calibrating, device will interrupt current calibration cycle start one. taken CONV taken then high during calibration, calibration cycle will continue conversion command disregarded. state BP/UP important during calibrations. "end calibration" signal desired, pulse signal high while leaving CONV signal high continuously. Once calibration completed, conversion will performed. conversion, DRDY will fall indicate first valid conversion after calibration been completed.
DS125F1
Conversion conversion state entered calibration cycle, whenever converter idle standby mode. CONV taken high initiate calibration cycle also high), remains high until calibration cycle completed (CAL taken after CONV transitions high), converter will begin conversion upon completion calibration period. BP/UP latched input. BP/UP controls output word from digital filter processed. bipolar mode output word computed digital filter offset 8000H (see Understanding Converter Calibration). BP/UP changed after conversion started long stable clock cycles conversion period prior DRDY falling. wishes intermix measurement bipolar unipolar signals various input signals, best switch BP/UP immediately after DRDY falls leave BP/UP stable until DRDY falls again. digital filter CS5509 Finite Impulse Response designed settle full accuracy conversion time. CONV left high, CS5509 will perform continuous conversions. conversion time will 1622 clock cycles. conversion initiated from standby state, there clock cycles uncertainty when conversion actually begins. This because internal logic operates half external clock rate exact phase internal clock 180° phase relative clock. When conversion initiated from standby state, will take clock cycles begin. Actual conversion will 1624 clock cycles before DRDY goes indicate that serial port been updated. Serial Interface Logic section
CS5509 data sheet information reading data from serial port. event conversion command (CONV going positive) issued during conversion state, current conversion will terminated conversion will initiated. Voltage Reference CS5509 uses differential voltage reference input. positive input VREF+ negative input VREF-. voltage between VREF+ VREF- range from volt minimum volts maximum. gain slope will track changes reference without recalibration, accommodating ratiometric applications. Analog Input Range analog input range magnitude voltage between VREF+ VREFpins. unipolar mode input range will equal magnitude voltage reference. bipolar mode input voltage range will equate plus minus magnitude voltage reference. While voltage reference great volts, common mode voltage value long reference inputs VREF+ VREF- stay within supply voltages GND. differential input voltage also have common mode value long maximum signal magnitude stays within supply voltages. converter intended measure frequency inputs. designed yield accurate conversions even with noise exceeding input voltage range long spectral components this noise will filtered digital filter. example, with volt reference unipolar mode, converter will accurately convert input signal volts with overrange noise. volt signal could have
Unipolar Input Voltage >(VREF LSB) VREF VREF/2 +0.5 <(+0.5 LSB) Output Codes FFFF FFFF FFFE 8000 7FFF 0001 0000 0000 Bipolar Input Voltage >(VREF LSB) VREF -0.5 -VREF +0.5 <(-VREF +0.5 LSB)
Note: Table excludes common mode voltage signal reference inputs. Table Output Coding
component which volts above maximum input (3.5 volts peak; volts plus volts peak noise) still accurately convert input signal (XIN 32.768 kHz). This assumes that signal plus noise amplitude stays within supply voltages. CS5509 converters output data binary format when converting unipolar signals offset binary format when converting bipolar signals. Table outlines output coding both unipolar bipolar measurement modes. Converter Performance CS5509 converter excellent linearity performance. Calibration minimizes errors offset gain. CS5509 device missing code performance 16-bits. Figure illustrates CS5509. converter achieves Common Mode Rejection (CMR) typical, typical. CS5509 experience some drift temperature changes CS5509 uses chopper-stabilized techniques minimize drift. Measurement errors offset gain drift eliminated time recalibrating converter.
DS125F1
CS5509
+1/2
(LSB)
-1/2
32,768
65,535
Codes
Figure CS5509 Differential Nonlinearity plot.
Analog Input Impedance Considerations analog input CS5509 modeled illustrated Figure Capacitors each) used dynamically sample each inputs (AIN+ AIN-). Every half cycle switch alternately connects capacitor output buffer then directly pin. Whenever sample capacitor switched from output buffer pin, small packet charge dynamic demand current) required from input source settle voltage sample capacitor final value. voltage output buffer differ from actual input voltage offset voltage buffer. Timing allows half clock cycle voltage sample capacitor settle final value.
equation maximum acceptable source resistance derived.
Rsmax 2XIN (15pF CEXT) 15pF(100mv) (15pF CEXT
This equation assumes that offset voltage buffer which worst case. value maximum error voltage which acceptable. CEXT combination external stray capacitance. maximum error voltage (Ve) CS5509 (1/4LSB 16-bits), above equation indicates that when operating from 32.768 XIN, source resistances acceptable absence external capacitance (CEXT VREF+ VREF- inputs have nearly same structure AIN+ AIN- inputs. Therefore, discussion analog input impedance applies voltage reference inputs well.
AIN+ AINV
Internal Bias Voltage
Figure Analog Input Model
DS125F1
CS5509
32.768kHz 330.00kHz
Frequency (Hz)
Attenuation (dB)
Notch Depth (dB) 125.6 126.7 145.7 136.0 118.4 132.9 102.5 108.4
Frequency (Hz) 50±1% 60±1% 100±1% 120±1% 150±1% 180±1% 200±1% 240±1%
Minimum Attenuation (dB) 55.5 58.4 62.2 68.4 74.9 87.9 94.0 104.4
-100
-120 -140
32.768 -160 402.83 805.66 1208.5 1611.3 2014.2 2416.9 Frequency (Hz)
Figure Filter Magnitude Plot
Flatness Frequency -0.010
-0.093
Table Filter Notch Attenuation (XIN 32.768 kHz)
Phase (Degrees) 32.768 -135 -180
Attenuation (dB)
-0.041
-0.166 -0.259 -0.374 -0.510 -0.667 -0.846 -1.047 -3.093
-100 -120
-140
32.768
Frequency (Hz)
Frequency (Hz)
Figure Filter Magnitude Plot
Figure Filter Phase Plot
Digital Filter Characteristics digital filter CS5509 combination comb filter pass filter. comb filter zeros transfer function which optimally placed reject line interference frequencies their multiples) when CS5509 clocked 32.768 kHz. Figures illustrate magnitude phase characteristics filter.
Figure illustrates filter attenuation from exactly 100, filter provides over rejection. Table indicates filter attenuation each potential line interference frequencies when converter operating with 32.768 clock. converter yields excellent attenuation these interference frequencies even fundamental line frequency should vary from
DS125F1
CS5509 specified frequency. -3dB corner frequency filter when operating from 32.768 clock Figure illustrates that phase characteristics filter precisely linear phase. CS5509 operated clock rate other than 32.768 kHz, filter characteristics, including comb filter zeros, will scale with operating clock frequency. Therefore, optimum rejection line frequency interference will occur with CS5509 running 32.768 kHz. Anti-Alias Considerations Spectral Measurement Applications Input frequencies greater than half output word rate (CONV aliased converter. prevent this, input signals should limited frequency greater than half output word rate converter (when CONV =1). Frequencies close modulator sample rate (XIN/2) multiples thereof also aliased. signal source includes spectral components above half output word rate (when CONV these components should removed means low-pass filtering prior input prevent aliasing. Spectral components greater than half output word rate VREF inputs (VREF+ VREF-) also aliased. Filtering reference voltage remove these spectral components from reference voltage desirable. Crystal Oscillator CS5509 designed operated using 32.768 "tuning fork" type crystal. crystal should connected input. other should attached XOUT. Short lead lengths should used minimize stray capacitance. Over industrial temperature range (-40 on-chip gate oscillator will oscillate with other crystals range kHz. chip will operate with external clock frequencies from over industrial temperature range. 32.768 crystal normally specified time-keeping crystal with tight specifications both initial frequency drift over temperature. maintain excellent frequency stability, these crystals specified only over limited operating temperature ranges (i.e. manufacturers. Applications these crystals with CS5509 does require tight initial tolerance tempco drift. Therefore, lower cost crystal with looser initial tolerance tempco will generally adequate with CS5509. Also check with manufacturer about wide temperature range application their standard crystals. Generally, even those crystals specified limited temperature range will operate over much larger ranges frequency stability over temperature requirement. frequency stability ±3000 over operating temperature range still typically better than line frequency stability over cycle-to-cycle during course day. Serial Interface Logic digital filter CS5509 takes 1624 clock cycles compute output word once conversion begins. conversion cycle, filter will attempt update serial port. clock cycles prior update DRDY will high. When DRDY goes high just prior port update checks port either empty unselected port empty unselected, digital filter will update port with output word. When data into port DRDY will low.
DS125F1
CS5509 Reading Serial Data SDATA output serial data. When goes after data becomes available (DRDY goes low), SDATA comes Hi-Z with data present. SCLK input serial clock. data SDATA pin, first rising edge SCLK enables shifting mechanism. This allows falling edges SCLK shift subsequent data bits port. Note that data output SCLK signal high, first falling edge SCLK will ignored because shifting mechanism become activated. After first rising edge SCLK, each subsequent falling edge will shift serial data. Once present, falling edge SCLK will cause SDATA output Hi-Z DRDY return high. serial port register will updated with data word upon completion another conversion serial port been emptied, inactive (high). operated asynchronously DRDY signal. DRDY signal need monitored long signal taken least clock cycles plus prior SCLK being toggled. This ensures that gained control over serial port. Power Supplies Grounding analog digital supply pins CS5509 brought separate pins minimize noise coupling between analog digital sections chip. digital section chip supply current flows into pin. CMOS device, CS5509 requires that supply voltage always more positive than voltage other device. this requirement met, device latch-up damaged. circumstances voltage must remain more positive than
pins; must remain more positive than pin. Figure illustrates System Connection Diagram CS5509. Note that supply pins bypassed with capacitors that digital supply derived from supply. Figure illustrates CS5509 operating from analog supply +3.3V digital supply. When using separate supplies VD+, must established first. should never become more positive than under operating condition. Remember investigate transient power-up conditions, when power supply have faster rise time.
Schematic Layout Review Service
Confirm Optimum Schematic Layout Before Building Your Board. Free Review Service Call Applications Engineering.
DS125F1
CS5509
Analog Supply Optional Clock Source 32.768
XOUT
SCLK SDATA
Serial Data Interface
CS5509 Analog Signal
AIN+ AINCS CONV Control Logic
Voltage Reference
VREF+ VREFGND
BP/UP
DRDY
Figure System Connection Diagram Using Single Supply
DS125F1
CS5509
Note: must never more positive than Analog Supply Optional Clock Source 32.768 +3.3V Digital Supply
XOUT
SCLK SDATA
Serial Data Interface
CS5509
Analog Signal AIN+ AINCS CONV Voltage Reference VREF+ VREFGND BP/UP DRDY Control Logic
Figure System Connection Diagram Using Split Supplies
DS125F1
CS5509 DESCRIPTIONS*
CHIP SELECT CONVERT CALIBRATE CRYSTAL CRYSTAL BIPOLAR/UNIPOLAR DIFFERENTIAL ANALOG INPUT DIFFERENTIAL ANALOG INPUT *Pinout applies both PDIP SOIC CONV XOUT BP/UP AIN+ AIN-
DRDY SDATA SCLK VREFVREF+
DATA READY SERIAL DATA OUTPUT SERIAL CLOCK INPUT POSITIVE DIGITAL POWER GROUND POSITIVE ANALOG POWER VOLTAGE REFERENCE INPUT VOLTAGE REFERENCE INPUT
Clock Generator XIN; XOUT Crystal Crystal Out, Pins gate inside chip connected these pins used with crystal provide master clock device. Alternatively, external (CMOS compatible) clock supplied into provide master clock device. Loss clock will device into lower powered state (approximately power reduction). Serial Output Chip Select, This input allows external device access serial port. DRDY Data Ready, Data Ready goes digital filter convolution cycle indicate that output word been placed into serial port. DRDY will return high after data bits shifted serial port master clock cycles before data becomes available inactive (high). SDATA Serial Data Output, SDATA output serial output port. Data from this will output rate determined SCLK. Data output first advances next data falling edges SCLK. SDATA will high impedance state when transmitting data. SCLK Serial Clock Input, clock signal this determines output rate data from SDATA pin. This must allowed float.
DS125F1
CS5509 Control Input Pins Calibrate, When taken high same time that CONV taken high converter will perform self-calibration which includes calibration offset gain scale factors converter. CONV Convert, CONV initiates calibration cycle taken from high while high, initiates conversion taken from high with low. CONV held high (CAL low) converter will continuous conversions. BP/UP Bipolar/Unipolar, BP/UP selects conversion mode converter. When high converter will convert bipolar input signals; when will convert unipolar input signals. Measurement Reference Inputs AIN+, AIN- Differential Analog Inputs, Pins Analog differential inputs delta-sigma modulator. VREF+, VREF- Differential Voltage Reference Inputs, Pins differential voltage reference these pins operates voltage reference converter. voltage between these pins voltage between volts. Power Supply Connections Positive Analog Power, Positive analog supply voltage. Nominally volts. Positive Digital Power, Positive digital supply voltage. Nominally volts +3.3 volts. Ground, Ground.
DS125F1
CS5509 SPECIFICATION DEFINITIONS Linearity Error deviation code from straight line which connects endpoints Converter transfer function. endpoint located below first code transition other endpoint located beyond code transition ones. Units percent full-scale. Differential Nonlinearity deviation code's width from ideal width. Units LSBs. Full Scale Error deviation last code transition from ideal [{(VREF+) (VREF-)} LSB]. Units LSBs. Unipolar Offset deviation first code transition from ideal (1/2 above voltage AINpin.) when unipolar mode (BP/UP low). Units LSBs. Bipolar Offset deviation mid-scale transition (011.111 100.000) from ideal (1/2 below voltage AIN- pin.) when bipolar mode (BP/UP high). Units LSBs
DS125F1
CS5509 APPENDIX following companies provide 32.768 crystals many package varieties temperature ranges. Electronics 5570 Enterprise Parkway Fort Meyers, 33905 (813) 693-0099 Micro Crystal Division West Algonquin Road Arlington Heights, 60005 (708) 806-1485 SaRonix 4010 Transport Street Palo Alto, California 94303 (415) 856-6900 Statek North Main Orange, California 92668 (714) 639-7810 Ltd. North Street Crewkerne Somerset TA18 England 01460 77155 Pierre Hersberger Microcrystal/DIV. S.A. Schild-Rust-Strasse Grenchen CH-2540 Switzerland Taiwan X'tal Corp. Chung Yang Reitou, Taipei, Taiwan Tel: 02-894-1202 Fax: 02-895-6207 Interquip Limited 24/F Million Fortune Industrial Centre 34-36 Chai Street, Tsuen Tel: 4135515 Fax: 4137053 Enterprises, Ltd. View Estate North Point, Hong Kong Tel: 5784921 Fax: 8073126 Darren Mcleod Hy-Q International Pty. Ltd. Rosella Road, FRANKSON, 3199 Victoria, Australia Tel: 61-3-783 9611 Fax: 61-3-783 9703
DS125F1
CDB5509
Evaluation Board CS5509 Converter
CDB5509 circuit board designed provide quick evaluation CS5509 converter. board provides buffered digital signals, on-board precision voltage reference, options using external clock, momentary switch initiate calibration. ORDERING INFORMATION CDB5509 Evaluation Board
Operation with on-board 32.768 crystal
off-board clock source Switch Selectable:
BP/UP mode
On-board precision voltage reference Access digital control pins
CS5509
AIN+ AINVREF
CLKIN
Cirrus Logic, Inc. Crystal Semiconductor Products Division P.O. 17847, Austin, Texas 78760 (512) 7222 FAX: (512) 7581 http://www.crystal.com
Copyright Cirrus Logic, Inc. 1998 (All Rights Reserved)
DS125DB1
CDB5509
Introduction CDB5509 evaluation board provides quick means testing CS5509 converter. CS5509 converter requires minimal amount external circuitry. evaluation board comes configured with converter chip operating from 32.768 crystal with off-chip precision volt reference. board provides access digital interface pins CS5509 chip. Most applications will require buffer proper operation. board operation, select either bipolar unipolar mode with switch Then press pushbutton after board powered This initiates calibration converter which required before measurements taken. With CONV high (S2-3 open) converter will convert continuously. Figure illustrates CAB5509 adapter board. CAB5509 translates CS5505 pinout CS5509 pinout. Figures illustrate evaluation board layout while Figure illustrates component placement (silkscreen) evaluation board.
Evaluation Board Overview board provides complete means making CS5509 converter chip function. user must provide means taking output data from board serial format using system. Figure illustrates schematic board. board comes configured converter chip operate from 32.768 watch crystal. connector external clock provided board. connect external source converter chip, circuit trace must cut. Then jumper must inserted proper holes connect converter input line from BNC. input terminated with resistor. Remove this resistor driving from logic gate. schematic Figure board comes with converter VREF+ VREF- pins hard-wired volt bandgap voltage reference board. control pins CS5509 available header connector. Buffer used buffer converter interface off-board circuits. buffers used evaluation board only because exact loading off-board circuitry unknown.
DS125DB1
DS125DB1
6.8V DGND 10nF 10nF TP10 CONV VREF+ VREFCS CS5509 DRDY TP11 TP12 TP13 100k 100k 100k 100k 100k 100k AGND 0.01 100k 0.1µF LT1019 -2.5 External VREF
DRDY SCLK SDATA
CONV
DRDY
SDATA
SDATA
SCLKO SCLKI BP/UP 100k 74HC4050 74HC125
SCLK
TP14 AIN+ 100k AINR12 100k TP15 AINTP6 AIN+ BP/UP
0.01
CLKIN
XOUT 32.768
CONV BP/UP
CDB5509
Note: Buffers required general applications.
Figure Connections
CDB5509
CONV XOUT BP/UP AIN+ AIN-
DRDY SDATA SCLK VREFVREF+
Figure CS5509 Layout
(Top View)
Figure CAB5509 Adapter Board
DS125DB1
CDB5509
Figure Ground Plane Layer (NOT SCALE)
DS125DB1
CDB5509
Figure Bottom Trace Layer (NOT SCALE)
DS125DB1
CDB5509
Figure Silk Screen Layer (NOT SCALE) DS125DB1
CDB5509
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