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ORCA® ORT8850 Field-Programmable System Chip (FPSC) Eight-Channel Mbits/s Backplane Transceiver
Field-programmable system chips (FPSCs) bring whole dimension programmable logic: FPGA logic embedded system solution single device. Lattice developed solution designers need many advantages FPGA-based design implementation, coupled with high-speed serial backplane data transfer. Built Series reconfigurable embedded system-on-chips (SoC) architecture, ORT8850 family made backplane transceivers containing eight channels, each operating Mbits/s (6.8 Gbits/s when eight channels used) full-duplex synchronous interface, with built-in clock data recovery (CDR) standard-cell logic, along with 600K usable FPGA system gates. circuitry proven macrocell available from Lattice's intellectual property library, already been implemented numerous applications including ASICs, standard products, FPSCs create interfaces SONET/SDH STS3/STM-1, STS-12/STM-4, STS-48/STM-16, STS192/STM-64 applications. With addition protocol access logic such protocol-independent framers, asynchronous transfer mode (ATM) framers, packet-over-SONET (POS) interfaces, framers HDLC Internet protocol (IP), designers build configurable interface retaining proven backplane driver/receiver technology. Designers also device drive high-speed data transfer across buses within system that SONET/SDH based. example, designers build Gbits/s PCI-to-PCI half bridge using soft core. ORT8850 family offers clockless high-speed interface interdevice communication, board across backplane. built-in clock recovery ORT8850 allows higher system performance, easier-to-design clock domains multiboard system, fewer signals backplane. Network designers will benefit from backplane transceiver network termination device. backplane transceiver offers SONET scrambling/descrambling data streamlined SONET framing, pointer moving, transport overhead handling, plus programmable logic terminate network into proprietary systems. non-SONET application, SONET functionality hidden from user prior networking knowledge required. 8850 also offers 8B/10B coding addition SONET scrambling. Also included device three full-duplex, highspeed parallel interfaces, consisting 8-bit data, control (such start-of-cell), clock. interface delivers double data rate (DDR) data rates (622 Mbits/s pin), converts this data internal device into 32-bit wide data running half rate clock edge. Functions such centering transmit clock transmit data done automatically interface. Applications delivered this interface include parallel backplane interface similar recently proposed RapidIOpacket-based interface.
Table ORCA ORT8850 Family-Available FPGA Logic
Device ORT8850L ORT8850H Rows Columns Total PFUs 2024 FPGA User LUTs 4,992 16,192 Blocks Bits Usable Gates 260-470 530-970
Note: embedded core interface included above gate counts.The usable gate counts range from logic-only gate count gate count assuming PFUs/SLICs being used RAMs. logic-only gate count includes each PFU/SLIC (counted gates/PFU), including gates LUT/FF pair (eight PFU), gates SLIC/FF pair (one PFU). Each four groups counted gates (three FFs, fast-capture latch, output logic, CLK, buffers). PFUs used counted four gates bit, with each capable implementing gates) PFU. Embedded block (EBR) counted four gates plus each block additional gates. gates used each gates embedded system microprocessor interface logic. Both PLLs conservatively utilized gate calculations.
ORCA ORT8850 FPSC Eight-Channel Mbits/s Backplane Transceiver
Table Contents
Contents Page Contents Page
Introduction.1 Embedded Core Features (Serial).4 Embedded Core Features (Parallel).4 Programmable FPGA Features Programmable Logic System Features Description.7 What FPSC? FPSC Overview FPSC Gate Counting FPGA/Embedded Core Interface ORCA Foundry Development System FPSC Design FPGA Logic Overview Logic Programmable Routing System-Level Features.10 Microprocessor Interface System Phase-Locked Loops Embedded Block Configuration Additional Information ORT8850 Overview Device Layout Backplane Transceiver Interface Interface SMacrocell 8B/10B Encoder/Decoder FPGA Interface Byte-Wide Parallel Interface FPSC Configuration Generic Backplane Transceiver Application.17 Synchronous Transfer Mode (STM) 8B/10B Mode Backplane Transceiver Core Detailed Description Macro STransmitter (FPGA Backplane) SReceiver (Backplane FPGA) 8B/10B Transmitter (FPGA Backplane) 8B/10B Receiver (Backplane FPGA) Pointer Mover Block (Backplane FPGA) Receive Bypass Options FPGA Interface
Powerdown Mode SRedundancy Protection Switching LVDS Protection Switching RapidIO Interface Pi-Sched. Overview Receive Cell Interface Transmit Cell Interface Memory Map. Definition Register Types Absolute Maximum Ratings. Recommended Operating Conditions Power Supply Decoupling Circuit. Electrical Timing Characteristics Parallel RapidIO-like Interface Timing Characteristics. Embedded Core LVDS LVDS Receiver Buffer Requirements Input/Output Buffer Measurement Conditions (on-LVDS Buffer). LVDS Buffer Characteristics. Termination Resistor LVDS Driver Buffer Capabilities Information Package Pinouts Package Thermal Characteristics Summary FPSC Maximum Junction Temperature Package Thermal Characteristics. Package Coplanarity Package Parasitics Package Outline Diagrams. Terms Definitions Package Outline Drawings 352-Pin PBGA 680-Pin PBGAM Hardware Ordering Information Software Ordering Information
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ORCA ORT8850 FPSC Eight-Channel Mbits/s Backplane Transceiver
Table Contents (continued)
List Figures Page List Tables Page
Figure ORCA ORT8850 Block Diagram Figure High-Level Diagram ORT8850 Transceiver Figure 8850 with 8B/10B Coding/Decoding Figure Functional Block Diagram Figure Byte Ordering Input/Output Interface STS-12 Mode Figure C1J1 Functionality Figure Stuff Bytes Figure Interconnect Streams FIFO Figure Example Inter-SAlignment Figure Example Intra-SAlignment Figure Example Twin STS-12 Stream Figure Examples Link Alignment Figure Pointer Mover State Machine Figure RapidIO Receive Cell Interface Figure RapidIO Transmit Cell Interface Figure Sample Power Supply Filter Network Analog Power Supply Pins Figure Receive Parallel Data/Control Timing Figure Transmit Parallel Data/Control Timing Figure Test Loads Figure Output Buffer Delays Figure Input Buffer Delays Figure LVDS Driver Receiver Associated Internal Components Figure LVDS Driver Receiver Figure LVDS Driver Figure Package Parasitics .106
Table ORCA ORT8850 Family- Available FPGA Logic Table Transmitter LVDS Output (Transparent Mode) Table Transmitter LVDS Output (TOH Insert Mode) Table Receiver (Output Parallel Bus) Table C1J1 Functionality Table Valid Special Characters Table Valid Starting Positions STS-Mc Table RapidIO Signals to/from FPGA Table Signals Used Register Bits Table Structural Register Elements Table Memory Table Memory Descriptions Table Absolute Maximum Ratings Table Recommended Operating Conditions Table Absolute Maximum Ratings Table Recommended Operating Conditions Table Receiver Specifications Table Transmitter Specifications Table Synthesizer Specifications Table Parallel Receive Data/Control Timing Table Transmit Parallel Data/Control Timing Table Driver Data Table Driver Data Table Driver Power Consumption Table Receiver Data Table Receiver Power Consumption Table Receiver Data Table LVDS Operating Parameters Table FPGA Common-Function Description Table FPSC Function Description Table Embedded Core/FPGA Interface Signal Description Table ORT8850H Pins That Unused ORT8850L Table ORT8850L 352-Pin PBGA Pinout Table ORT8850L ORT8850H 680-Pin PBGAM Pinout Table ORCA ORT8850 Plastic Package Thermal Guidelines .106 Table ORCA ORT8850 Package Parasitics .106 Table Device Type Options .110 Table Temperature Options .110 Table Package Type Options .110 Table .ORCA FPSC Package Matrix (Speed Grades) .110
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ORCA ORT8850 FPSC Eight-Channel Mbits/s Backplane Transceiver
Embedded Core Features (Serial)
Implemented ORCA Series FPGA. Allows wide range applications SONET network termination application well generic data moving high-speed backplane data transfer. knowledge SONET/SDH needed generic applications. Simply supply data, MHz-106 clock, frame pulse. High-speed interface (HSI) function clock/data recovery serial backplane data transfer without external clocks. Eight-channel function provides Mbits/s serial interface channel total chip bandwidth Gbits/s (full duplex). function uses Lattice's Mbits/s serial interface core. Rates from Mbits/s Mbits/s supported directly (lower rates directly supported through decimation interpolation). LVDS I/Os compliant with EIA®-644 support insertion. embedded LVDS I/Os include both input output on-board termination allow long-haul driving backplanes. Low-power core. Low-power LVDS buffers. Programmable STS-1, STS-3, STS-12 framing. Independent STS-1, STS-3, STS-12 data streams quad channels. data multiplexing/demultiplexing 106.25 byte-wide data processing FPGA logic. On-chip, phase-lock loop (PLL) clock meets jitter tolerance specification ITU-T recommendation G.958. Powerdown option receiver per-channel basis. Selectable 8B/10B coder/decoder SONET scrambler/descrambler. automatically recovers from loss-of-clock once reference clock returns normal operating state. Frame alignment across multiple ORT8850 devices work/protect switching OC-192/STM-64 above rates. In-band management configuration through transport overhead extraction/insertion.
Supports transparent modes where either only insertion A1/A2 framing bytes, bytes inserted. Streamlined pointer processor (pointer mover) frame alignment system clocks. Built-in boundry scan (IEEE ®1149.1 JTAG). FIFOs align incoming data across eight channels (two groups four channels four groups channels) both SONET scrambling 8B/10B modes. Optional ability bypass alignment FIFOs. protection supports STS-12/STS-48 redundancy either software hardware control protection switching applications. STS-192 above rates supported through multiple devices. ORCA FPGA soft intellectual property core support variety applications. Programmable Spointer mover bypass mode. Programmable Sframer bypass mode. Programmable bypass mode (clocked LVDS high-speed interface). Redundant outputs multiplexed redundant inputs I/Os allow implementation eight channels with redundancy single device.
Embedded Core Features (Parallel)
Three full-duplex, double data rate (DDR) groups include 8-bit data, control, clock. Each interface implemented with LVDS I/Os that include on-board termination allow long-haul driving backplanes, such industry-standard RapidIO interface. External speeds interface (622 Mbits/s pin), with internal, singleedge data transferred rate 32-bit plus control. Automatic centering transmit clock data interface. Direct interfaces Pi-Sched (266 LVDS), Pi-X (128 TTL), (100 TTL) ATM/ switch/port controller devices.
Lattice Semiconductor
ORCA ORT8850 FPSC Eight-Channel Mbits/s Backplane Transceiver
dual-port. Create large, fast RAM/ROM blocks (128 only eight PFUs) using SLIC decoders bank drivers. Soft-wired LUTs (SWL) allow fast cascading three levels logic single through fast internal routing, which reduces routing congestion improves speed. Flexible fast access inputs from routing. Fast-carry logic routing four adjacent PFUs nibble-wide, byte-wide, longer arithmetic functions, with option register carry-out.
Programmable FPGA Features
High-performance platform design: 0.13 7-level metal technology. Internal performance >250 MHz. Over 600K usable system gates. Meets multiple interface standards. operation (30% less power than operation) translates greater performance. Traditional selections: LVTTL LVCMOS (3.3 I/Os. pin-selectable clamping diodes provide compliance. Individually programmable drive capability: sink/12 source, sink/6 source, sink/3 source. slew rates supported (fast slew-limited). Fast-capture input latch input flip-flop (FF)/latch reduced input setup time zero hold time. Fast open-drain drive capability. Capability register 3-state enable signal. Off-chip clock drive capability. Two-input function generator output path. programmable high-speed I/O: Single-ended: GTL, GTL+, PECL, SSTL3/2 (class II), HSTL (Class III, IV), ZBT, DDR. Double-ended: LVDS, bused-LVDS, LVPECL. LVDS include optional on-chip termination resistor on-chip reference generation. Customer defined: ability substitute arbitrary standard-cell meet fast-moving standards. capability (de)multiplex signals: both input output rates (266 effective rate). downlink uplink capability (i.e., internal I/O). Enhanced twin-quad programmable function unit (PFU): Eight 16-bit look-up tables (LUTs) PFU. Nine user registers PFU, following each LUT, organized allow nibbles independently, plus extra arithmetic operations. register control each independent programmable clocks, clock enables, local set/reset, data selects. structure allows flexible combinations LUT4, LUT5, LUT6, MUX, MUX, ripple mode arithmetic functions same PFU. PFU, configurable single-
Abundant high-speed buffered nonbuffered routing resources provide average speed improvements over previous architectures. Hierarchical routing optimized both local global routing with dedicated routing resources. This results faster routing times with predictable efficient performance. SLIC provides eight 3-statable buffers, 10-bit decoder, PAL®-like and-or-invert (AOI) each programmable logic cell. Improved built-in clock management with dual-output programmable phase-locked loops (PPLLs) provide optimum clock modification conditioning phase, frequency, duty cycle from MHz. embedded quad-port blocks, read ports, write ports, sets byte lane enables. Each embedded block configured One-512 (quad-port, read/two write) with optional built-in arbitration. One-256 (dual-port, read/one write). One-1K (dual-port, read/one write). Two-512 (dual-port, read/one write each). with arbitrary number words whose less (dual-port, read/one write). Supports joining blocks. 8-bit content addressable memory (CAM) support. FIFO dual Constant multiply Dual variable multiply Embedded 32-bit internal system plus 4-bit parity interconnects FPGA logic, microprocessor interface (MPI), embedded blocks, embedded backplane transceiver blocks with performance. Included built-in system registers that control status center device.
Lattice Semiconductor
ORCA ORT8850 FPSC Eight-Channel Mbits/s Backplane Transceiver
Programmable FPGA Features (continued)
Built-in testability: Full boundary scan (IEEE 1149.1 Draft 1149.2 JTAG). Programming readback through boundary scan port compliant IEEE Draft 1532:D1.7. TS_ALL testability function 3-state pins. temperature-sensing diode. cycle stealing capability allows typical internal speed improvement after final place route. This feature also enables compliance with many setup/hold clock specifications provide reduced ground bounce output buses allowing flexible delays switching output buffers.
Variable size bused readback configuration data capability with built-in microprocessor interface system bus. Internal, 3-state, bidirectional buses with simple control provided SLIC. clock routing structures global local clocking significantly increases speed reduces skew (<200 OR4E4). local clock routing structures allow creation localized clock trees. edge clock routing supports least fast edge clocks side device double-data rate (DDR) zero-bus turnaround (ZBT) memory interfaces support latest high-speed memory interfaces. 2x/4x uplink downlink capabilities interface high-speed external I/Os reduced speed internal logic. ORCA Foundry 2000 development system software. Supported industry-standard tools design entry, synthesis, simulation, timing analysis. Meets universal test operations interface A(UTOPIA) Levels Also meets proposed specifications UTOPIA Level Gbits/s interfaces. edge clock routing structures allow seven high-speed clocks each edge device improved setup/hold clock performance.
Programmable Logic System Features
local compliant FPGA I/Os. Improved PowerPC®860 PowerPC high-speed synchronous microprocessor interface used configuration, readback, device control, device status, well general-purpose interface FPGA logic, RAMs, embedded backplane transceiver blocks. Glueless interface synchronous PowerPC processors with user-configurable address space provided. embedded AMBAspecification system (ARM processor) facilitates communication among microprocessor interface, configuration logic, embedded block RAM, FPGA logic, backplane transceiver logic. network PLLs meet ITU-T G.811 specifications provide clock conditioning DS-1/E-1 STS-3/STM-1 applications. Flexible general-purpose PPLLs offer clock multiply 8x), divide (down 1/8x), phase shift, delay compensation, duty cycle adjustment combined.
Lattice Semiconductor
ORCA ORT8850 FPSC Eight-Channel Mbits/s Backplane Transceiver
Series based FPSCs expand this interface providing link between embedded block multimaster 32-bit system FPGA logic. This system allows core easy access many FPGA logic functions including embedded block RAMs microprocessor interface. Clock spines also pass across FPGA/embedded core boundary. This allows fast, low-skew clocking between FPGA embedded core. Many special signals from FPGA, such DONE global set/reset, also available embedded core, making possible fully integrate embedded core with FPGA system. even greater system flexibility, FPGA configuration RAMs available embedded core. This allows user-programmable options embedded core, turn allowing greater flexibility. Multiple embedded core configurations designed into single device with user-programmable control over which configurations implemented, well capability change core functionality simply reconfiguring device.
Description
What FPSC?
FPSCs, field-programmable system chips, devices that combine field-programmable logic with ASIC mask-programmed logic single device. FPSCs provide time market flexibility FPGAs, design effort savings using soft intellectual property (IP) cores, speed, design density, economy ASICs.
FPSC Overview
Lattice's Series FPSCs created from Series ORCA FPGAs. create Series FPSC, several columns programmable logic cells (see FPGA Logic Overview section FPGA logic details) added embedded logic core. Other than replacing some FPGA gates with ASIC gates, greater than 10:1 efficiency, none FPGA functionality changed-all Series FPGA capability retained: embedded block RAMs, MPI, PCMs, boundary scan, etc. columns programmable logic replaced right device, allowing pins from replaced columns used pins embedded core. remainder device pins retain their FPGA functionality.
ORCA Foundry Development System
ORCA Foundry development system used process design from netlist configured FPGA. This system used design onto ORCA architecture, then place route using ORCA Foundry's timing-driven tools. development system also includes interfaces libraries for, other popular tools design entry, synthesis, simulation, timing analysis. ORCA Foundry development system interfaces front-end design entry tools provides tools produce configured FPGA. design flow, user defines functionality FPGA points design flow: design entry bitstream generation stage. Recent improvements ORCA Foundry allow user provide timing requirement information through logical preferences only; thus, designer required have physical knowledge implementation.
FPSC Gate Counting
total gate count FPSC embedded core (standard-cell/ASIC gates) FPGA gates. Because FPGA gates generally expressed usable range with nominal value, total FPSC gate count sometimes expressed same manner. Standard-cell ASIC gates are, however, times more silicon-area efficient than FPGA gates. Therefore, FPSC with embedded function gate equivalent FPGA with much larger gate count.
FPGA/Embedded Core Interface
interface between FPGA logic embedded core been enhanced allow greater number interface signals than previous FPSC achitectures. Compared bringing embedded core signals off-chip, this on-chip interface much faster requires less power. delays interface precharacterized accounted ORCA Foundry Development System. Lattice Semiconductor
ORCA ORT8850 FPSC Eight-Channel Mbits/s Backplane Transceiver
Description (continued)
Following design entry, development system's map, place, route tools translate netlist into routed FPGA. floorplanner available layout feedback control. static timing analysis tool provided determine device speed back-annotated netlist created allow simulation timing. Timing simulation output files from ORCA Foundry also compatible with many third-party analysis tools. stream generator then used generate configuration data which loaded into FPGAs internal configuration RAM, embedded block RAM, and/or FPSC memory. When using stream generator, user selects options that affect functionality FPGA. Combined with front-end tools, ORCA Foundry produces configuration data that implements various logic routing options discussed this data sheet.
FPSC Design
Development facilitated FPSC design which, together with ORCA Foundry third-party synthesis simulation engines, provides software documentation required design verify FPSC implementation. Included FPSC configuration manager, Synopsys Smart Model complete online documentation. kit's software couples with ORCA Foundry, providing seamless FPSC design environment. More information obtained visiting ORCA website contacting local sales office, both listed last page this document.
architecture consists four basic elements: programmable logic cells (PLCs), programmable cells (PIOs), embedded block RAMs (EBRs), systemlevel features. These elements interconnected with rich routing fabric both global local wires. array PLCs surrounded common interface blocks which provide abundant interface adjacent PLCs system blocks. Routing congestion around these critical blocks eliminated same routing fabric implemented within programmable logic core. Each contains PFU, SLIC, local routing resources, configuration RAM. Most FPGA logic performed PFU, decoders, PAL-like functions, 3-state buffering performed SLIC. PIOs provide device inputs outputs used register signals perform input demultiplexing, output multiplexing, uplink downlink functions, other functions output signals. Large blocks quadport complement existing distributed memory. blocks used implement RAM, ROM, FIFO, multiplier, CAM. Some other system-level functions include MPI, PLLs, embedded system (ESB).
Logic
Each within contains eight 4-input (16-bit) LUTs, eight latches/FFs, additional flip-flop that used independently with arithmetic functions. organized twin-quad fashion; sets four LUTs that controlled independently. Each independent programmable clocks, clock enables, local set/reset, data selects. LUTs also combined arithmetic functions using fast-carry chain logic either 4-bit 8-bit modes. carry-out either mode registered ninth pipelining. Each also configured synchronous single- dual-port ROM. latches) obtain input from outputs directly from invertible inputs, they tied high tied low. also have programmable clock polarity, clock enables, local set/reset.
FPGA Logic Overview
ORCA Series architecture generation SRAM-based programmable devices from Lattice. includes enhancements innovations geared toward today's high-speed systems single chip. Designed with networking applications mind, Series family incorporates system-level features that further reduce logic requirements increase system speed. ORCA Series devices contain many patented enhancements offered variety packages speed grades. hierarchical architecture logic, clocks, routing, RAM, system-level blocks create seamless merge FPGA ASIC designs. Modular hardware software technologies enable system-on-chip integration with true plug-and-play design implementation.
Lattice Semiconductor
ORCA ORT8850 FPSC Eight-Channel Mbits/s Backplane Transceiver
Series logic been enhanced include modes speed uplink downlink capabilities. These modes supported through shift register logic, which divides down incoming data rates multiplies outgoing data rates. This logic block also supports high-speed mode requirements where data clocked into buffers both edges clock. programmable cell allows designers select I/Os which meet many communication standards permitting device hook directly without external interface translation. They support traditional FPGA standards well high-speed, singleended, differential-pair signaling shown Table Based programmable, bank-oriented ring architecture, designs implemented using referenced output levels.
Description (continued)
SLIC connected from routing resources from outputs PFU. contains eight 3state, bidirectional buffers, logic perform 10-bit function decoding, AND-OR with optional INVERT perform PAL-like functions. 3state drivers SLIC their direct connections from outputs make fast, true, 3-state buses possible within FPGA, reducing required routing allowing real-world system performance.
Programmable
Series addresses demand flexibility select I/Os that meet system interface requirements. I/Os programmed same manner previous ORCA devices, with additional features which allow user flexibility select types that support high-speed interfaces. Each contains four programmable pads interfaced through common interface block FPGA array. split into pairs pads with each pair having independent clock enables, local set/reset, global set/reset. input side, each contains programmable latch/flip-flop which enables very fast latching data from pad. combination provides very setup requirements zero hold times signals coming on-chip. also used demultiplex input signal, such multiplexed address/data signal, register signals without explicitly building demultiplexer with PFU. output side each PIO, output from array routed each output flip-flop, logic associated with each pad. output logic associated with each allows multiplexing output signals other functions output signals. output combination with output signal multiplexing, particularly useful registering address signals multiplexed with data, allowing full clock cycle data propagate output. output buffer signal inverted, 3-state control made active-high, active-low, always enabled. addition, this 3-state signal registered nonregistered.
Routing
abundant routing resources Series architecture organized route signals individually buses with related control signals. Both local global signals utilize high-speed buffered nonbuffered routes. segmented (x1), segmented (x6), bused half-chip (xHL) routes patterned together provide high connectivity with fast software routing times high-speed system performance. Eight fully distributed primary clocks routed low-skew, high-speed distribution network sourced from dedicated pads, PLLs, logic. Secondary edge-clock routing available fast regional clock control signal routing both internal regions device edges. Secondary clock routing sourced from pin, PLLs, logic. improved routing resources offer great flexibility moving signals from logic core. This flexibility translates into improved capability route designs required speeds when signals have been locked specific pins.
Lattice Semiconductor
ORCA ORT8850 FPSC Eight-Channel Mbits/s Backplane Transceiver
System-Level Features
Series also provides system-level functionality means microprocessor interface, embedded system bus, quad-port embedded block RAMs, universal programmable phase-locked loops, addition highly tuned networking specific phase-locked loops. These functional blocks allow easy glueless system interfacing capability adjust varying conditions today's high-speed networking systems.
Phase-Locked Loops
eight PLLs provided each Series device, with four PLLs generally provided FPSCs. Programmable PLLs used manipulate frequency, phase, duty cycle clock signal. Each PPLL capable manipulating conditioning clocks from MHz. Frequencies adjusted from 1/8x input clock frequency. Each programmable provides outputs that have different multiplication factors have same phase relationships. Duty cycles phase delays adjusted 12.5% clock period increments. automatic input buffer delay compensation mode available phase delay. Each PPLL provides outputs that have programmable (12.5% steps) phase differences. Additional highly tuned characterized, dedicated phase-locked loops (DPLLs) included ease system designs. These DPLLs meet ITU-T G.811 primaryclocking specifications enable system designers very tightly target specified clock conditioning traditionally available universal PPLLs. Initial DPLLs targeted low-speed networking also high-speed SONET/SDH networking STS-3 STM-1 systems. These DPLLs typically included FPSC devices found ORT8850 family.
Microprocessor Interface
provides glueless interface between FPGA PowerPC microprocessors. Programmable 16-, 32-bit interfaces with optional parity Motorola® PowerPC bus, used configuration readback, well FPGA control monitoring FPGA status. transactions utilize Series embedded system performance. system-level microprocessor interface FPGA user-defined logic following configuration, through system bus, including access embedded block general user-logic, provided MPI. supports burst data read write transfers, allowing short, uneven transmission data through interface including data FIFOs. Transfer accesses single beat 4-bytes less), 4-beat 4bytes), 8-beat 2-bytes), 16-beat 1-bytes).
Embedded Block
quad-port blocks embedded FPGA core significantly increase amount memory complement distributed memories. EBRs include write ports, read ports, byte lane enables which provide four-port operation. Optional arbitration between write ports available, well direct connection high-speed system bus. Additional logic been incorporated allow significant flexibility FIFO, constant multiply, two-variable multiply functions. user configure FIFO blocks with flexible depths 512k, 256k, including asynchronous synchronous modes programmable status error flags. Multiplier capabilities allow multiple 8-bit number with 16-bit fixed coefficient vice versa (24-bit output), multiply 8-bit numbers (16-bit output). On-the-fly coefficient modifications available through second read/ write port. 8-bit CAMs embedded block implemented single match, multiple match, clear modes. EBRs also preloaded device configuration time. Lattice Semiconductor
System
on-chip, multimaster, 8-bit system with 1-bit parity facilitates communication among MPI, configuration logic, FPGA control, status registers, embedded block RAMs, well user logic. Utilizing AMBA specification protocol, embedded system offers arbiter, decoder, master, slave elements. Master slave elements also available user-logic embedded backplane transceiver portion 8850. system control registers provide control FPGA such signaling reprogramming, reset functions, programming. Status registers monitor INIT, DONE, system errors. interrupt controller integrated provide eight possible interrupt resources. clock generation sourced from microprocessor interface clock, configuration clock (for slave configuration modes), internal oscillator, user clock from routing, from port clock (for JTAG configuration modes).
ORCA ORT8850 FPSC Eight-Channel Mbits/s Backplane Transceiver
Other configuration options include initialization embedded-block memories FPSC memory well system options stream error checking. Programming readback through JTAG (IEEE 1149.2) port also available meeting insystem programming (ISP) standards (IEEE 1532 Draft).
System-Level Features (continued)
Configuration
FPGAs functionality determined internal configuration RAM. FPGAs internal initialization/configuration circuitry loads configuration data powerup under system control. configuration data reside externally EEPROM other storage media. Serial EEPROMs provide simple, pin-count method configuring FPGAs. loaded using several configuration modes. Supporting traditional master/slave serial, master/slave parallel, asynchronous peripheral modes, Series also utilizes microprocessor interface embedded system perform both programming readback. Daisy chaining multiple devices partial reconfiguration also permitted.
Additional Information
Contact your local Lattice representative additional information regarding ORCA Series FPGA devices, visit website http://www.latticesemi.com
Lattice Semiconductor
ORCA ORT8850 FPSC Eight-Channel Mbits/s Backplane Transceiver
ORT8850 Overview
Device Layout
ORT8850 FPSC provides high-speed backplane transceiver combined with FPGA logic. device based OR4E2 OR4E6 FPGAs. OR4E2 array programmable logic cells (PLCs) OR4E6 array. ORT8850, several columns PLCs these arrays were replaced with embedded backplane transceiver core. ORT8850 embedded core comprises long-haul interface macro three RapidIO macros intraboard chip-to-chip backplane communication. long-haul interface includes high-speed interface (HSI) macrocell, synchronous transport module (STM) macrocell, 8B/10B encoder/decoder. eight full-duplex channels perform data transfer, scrambling/descrambling encoding/decoding, framing rate Mbits/s. Each RapidIO block transmit receive section that each contain LVDS clock buffer pair, LVDS start-of-cell buffer pair, eight LVDS clock buffer pairs which double edge clocked corresponding clock. Figure shows ORT8850 block diagram.
links. macrocell used clock/data recovery (CDR) serialize/deserialize between 106.25 byte-wide internal data buses Mbits/s serial LVDS links. Mbits/s SONET stream, will perform clock data recovery (CDR) MUX/deMUX between 77.76 byte-wide internal data buses Mbits/s serial LVDS links. Each Mbits/s serial link uses pseudo-SONET protocol. SONET A1/A2 framing used link detect frame location. link also scrambled using standard SONET scrambler definition ensure proper transitions link improved performance. Selectable transport overhead (TOH) bytes insertable transmit direction. selectable bytes inserted from software programmable registers that accessed microprocessor interface. Elastic buffers (FIFOs) used align each incoming STS-12 link 77.76 clock frame. These FIFOs will absorb delay variations between four Mbits/s links timing skews between cards along backplane traces. greater variations, streamlined pointer processor (pointer mover) within Smacro will align frames regardless their incoming frame position. backplane transceiver allows SONET scrambling frame alignment 8-bit/10-bit (8B/10B) encoding/decoding. SONET advantage reduced overhead (3.3% overhead SONET overhead 8B/10B). 8B/10B advantage faster synchronization bytes transferred data 8B/10B four frames data SONET). effective data transfer rate scrambled SONET greater than Mbits/s while effective data transfer rate 8B/10B greater than Mbits/s. Frame synchronization multichannel alignment provided 8B/10B mode through special characters. Figure shows architecture ORT8850 backplane transceiver core.
Backplane Transceiver Interface
advantage ORT8850 FPSC bring specific networking functions early market presence using programmable logic system. Mbits/s backplane transceiver core allows ORT8850 communicate across backplane given board aggregate speed Gbits/s, providing physical medium high-speed asynchronous serial data transfer between system devices. This device intended for, limited connecting terminal equipment SONET/SDH, ATM, systems. backplane transceiver core used support Gbits/s interface backplane connection mate TADM042G5 device other SONET devices such redundant central crossconnect. interface implemented eight-channel Mbits/s LVDS
Lattice Semiconductor
ORCA ORT8850 FPSC Eight-Channel Mbits/s Backplane Transceiver
ORT8850 Overview (continued)
8-bit/10-bit DECODER
Mbits/s DATA FULLDUPLEX SERIAL CHANNELS Mbits/s DATA
LVDS I/Os
CLOCK/DATA RECOVERY
BYTEWIDE DATA
PSEUDOSONET FRAMER
POINTER MOVER SCRAMBLING FIFO ALIGNMENT SELECTED
8-bit/10-bit ENCODER
INTERFACE (RapidIO)
ORCA SERIES FPGA LOGIC
LVDS I/Os
STANDARD FPGA I/Os
INTERFACE (RapidIO)
LVDS I/Os
INTERFACE (RapidIO)
LVDS I/Os
1729(F)
Figure ORCA ORT8850 Block Diagram
Lattice Semiconductor
ORCA ORT8850 FPSC Eight-Channel Mbits/s Backplane Transceiver
ORT8850 Overview (continued)
PWRUPRST FROM FPGA (GOES BLOCKS)
INTERFACE SYSTEM RING
RapidIO YTRISTN_A UTXTRISTN_A RSTN_UTX_A UTXD_A[31:0] UTXSOC_A WUTXCLK_FPGA PFCLK CSYSENB_A RSTN_RX_A ZRXD_A[31:0] ZRXSOC_A ZRXSOCVIOL_A ZRXALNVIOL_A WRXCLK_A_FPGA ZRXCLK_A RapidIO YTRISTN_B UTXTRISTN_B RSTN_UTX_B UTXD_B[31:0] UTXSOC_B WUTXCLK_FPGA PFCLK CSYSENB_B RSTN_RX_B ZRXD_B[31:0] ZRXSOC_B TRANSMIT FIFO TXD[31:0] TXSOC TRANSMIT MODULE SOFT CNTL SOFT CNTL RECEIVE MODULE TRANSMIT FIFO TXD[31:0] TXSOC TRANSMIT MODULE SOFT CNTL
TXD_A[7:0] TXSOC_A TXCLK_A
RXD_A[7:0]
RXSOC_A
RXCLK_A
TXD_B[7:0] TXSOC_B TXCLK_B
RXD_B[7:0]
FPGA
ZRXSOCVIOL_B ZRXALNVIOL_B WRXCLK_B_FPGA ZRXCLK_B 12X8 SYTRISTN_C UTXTRISTN_C RSTN_UTX_C UTXD_C[31:0] UTXSOC_C WUTXCLK_FPGA PFCLK CSYSENB_C RSTN_RX_C ZRXD_C[31:0] ZRXSOC_C ZRXSOCVIOL_C ZRXALNVIOL_C WRXCLK_C_FPGA ZRXCLK_C RapidIO TRANSMIT FIFO TXD[31:0] TXSOC
RECEIVE MODULE
RXSOC_B
RXCLK_B
DATA 8B/10B K-CONTROL INPUTS LINE_FP, SYS_FP SMACRO SYS_CLK CHANNELS) PROT_SW DATA C1J1 RECOVERED CLKS DATA TOH_CK_EN TOH_FP DATA TOH_CK_EN BLOCK TOH_CLK
SOFT CNTL
TXD_C[7:0]
TRANSMIT MODULE SOFT CNTL
TXSOC_C TXCLK_C
RXD_C[7:0]
RECEIVE MODULE
RXSOC_C
RXCLK_C
Figure High-Level Diagram ORT8850 Transceiver Lattice Semiconductor
ORCA ORT8850 FPSC Eight-Channel Mbits/s Backplane Transceiver
8B/10B Encoder/Decoder
ORT8850 facilitates high-speed serial transfer data variety applications including Gigabit Ethernet, fibre channel, serial backplanes, proprietary links. device provides 8B/10B coding/decoding each channel. 8B/10B transmission code includes serial encoding/decoding rules, special characters, error detection. Information transmitted over fibre shall encoded eight bits time into 10-bit transmission character then sent serially. 10-bit transmission characters support eight-bit combinations. Some remaining transmission characters referred special characters, used functions which distinguishable from contents frame.
ORT8850 Overview (continued)
Interface
high-speed interconnect (HSI) macrocell used clock/data recovery MUX/deMUX between 106.25 byte-wide internal data buses Mbits/s external serial links. interface receives eight Mbits/s serial input data streams from LVDS inputs provides eight independent 106.25 byte-wide data streams recovered clock Smacro. There requirement alignment since SONET type framing will take place inside ORT850 core. transmit, converts four byte-wide 106.25 data streams serial streams Mbits/s LVDS outputs.
SMacrocell
Sportion embedded core consists transmitter (Tx) receiver (Rx) sections. receiver receives eight byte-wide data streams 106.25 associated clocks from HSI. section, incoming streams SONET framed descrambled before they written into FIFO, which absorbs phase delay variations allows shift system clock. then extracted sent eight serial ports. pointer mover consists three blocks: pointer interpreter, elastic store, pointer generator. pointer interpreter finds synchronous transport signal (STS) synchronous payload envelopes (SPE) places into small elastic store from which pointer generator will produce eight byte-wide STS-12 streams data that aligned system timing pulse. section, transmitted data each channel received through parallel serial port from FPGA circuit. bytes received from serial input port optionally inserted from programmable registers serial inputs STS-12 frame processor. Each eight parallel input buses synchronized free-running system clock. Then data transferred HSI. Smacrocell also scrambler/descrambler disable feature, allowing user disable scrambler transmitter descrambler receiver. Also, unused channels disabled reduce power dissipation.
FPGA Interface
FPGA logic will receive/transmit frame-aligned (optional 8B/10B mode) streams 106.25 data (maximum eight streams each direction) from/to backplane transceiver embedded core. frames transmitted FPGA will aligned FPGA frame pulse which will provided FPGA user's logic Smacro. receive pointer mover alignment FIFOs bypassed, then each channel will provide receive clock receive frame pulse signals. Otherwise, frames received from FPGA logic will aligned system frame pulse that will supplied Smacro from FPGA user's logic.
Byte-Wide Parallel Interface
Three byte-wide parallel interface provided ORT8850. Each interface provides transmit receive byte-wide data, control signal, clock. Receive data sampled both edges receive clock converted 32-bit data bus, which single-edge clocked half-speed clock transfer FPGA logic. Maximum transmit/receive clock rate internal FPGA clock. This allows Mbits/s link data transfer rate. Other functions provided include check minimum number transferred bytes. first byte-wide interface (RapidIO Figure always available. other interfaces (RapidIO RapidIO available when Mbits/s serial links being used.
Lattice Semiconductor
ORCA ORT8850 FPSC Eight-Channel Mbits/s Backplane Transceiver
ORT8850 Overview (continued)
FPSC Configuration
Configuration ORT8850 occurs stages: FPGA stream configuration embedded core setup. FPGA Configuration Prior becoming operational, FPGA goes through sequence states, including powerup, initialization, configuration, start-up, operation. FPGA logic configured standard FPGA stream configuration means discussed Series FPGA data sheet. options embedded core registers that accessed through FPGA system bus. system driven external compliant microprocessor block user master interface FPGA logic. simple block, that drives system using user interface uses very little FPGA logic, available MPI/System application note (AP01-032NCIP). This block sets embedded core state machine allows ORT8850 work independent system without external microprocessor interface. Embedded Core Setup options operation core configured according device register map, which included with ORT8850 FPSC simulation kit. During powerup sequence, ORT8850 device (FPGA programmable circuit core) held reset. LVDS output buffers other output buffers held 3-state. flip-flops core area reset state, with exception boundry-scan shift registers, which only reset boundaryscan reset. After powerup reset, FPGA start configuration. During FPGA configuration, ORT8850 core will held reset local interface signals forced high, following activehigh signals (PROT_SWITCH_A, PROT_SWITCH_C, TX_TOH_CK_EN, SYS_FP, LINE_FP) will forced
low. CORE_READY signal sent from embedded core FPGA held low, indicating that core ready interact with FPGA logic. FPGA configuration sequence, CORE_READY signal will held SYS_CLK cycles after DONE, TRI_IO RST_N (core global reset) high. Then will active-high, indicating embedded core ready function interact with FPGA programmable circuit. During FPGA reconfiguration when DONE TRI_IO low, CORE_READY signal sent from core FPGA will held again indicate embedded core ready interact with FPGA logic. During FPGA partial configuration, CORE_READY stays active. same FPGA configuration sequence described previously will repeat again. initialization embedded core consists steps: register configuration synchronization alignment FIFO. order configure embedded core, registers need unlocked writing 0x30005 address 0x30004 writing 0x80 address 0x05. Control registers 0x30004 0x30005 lock registers. output data, serial port, clock frame pulse controlled 3-state registers (the registers 3-state output control optional; these output 3state enable signals brought across local interface available FPGA side), next step activate 3-state output signals taking them functional state from high-impedance state. This done writing 0x01 correspond bits channel registers 0x30020, 0x30038, 0x30050, 0x30068, 0x30080, 0x30090, 0x300B0, 0x300C8. addition, synchronization selected streams recommended some networking systems applications. This requires resync alignment FIFO after enabled channels have valid frame pulse 8B/10B control character. sections about SLink Alignment Setup 8B/10B Link Alignment Setup more details.
Lattice Semiconductor
ORCA ORT8850 FPSC Eight-Channel Mbits/s Backplane Transceiver
8B/10B Mode
ORT8850 facilitates high-speed serial transfer data variety applications including Gigabit Ethernet, fibre channel, serial backplanes, proprietary links. place Sinterface, ORT8850 also provides 8B/10B coding/decoding each channel. 8B/10B transmission code includes serial encoding/decoding rules, special characters, error detection. 8B/10B mode, received first transmitted first. 10-bit encoded transmission characters labeled transmitted with first last, where MSB. Transmitter Description data input transmitter each channel 8-bit word K-control input. input used identify data special character. each channel, input data byte clocked into FIFO. When K-control data parallel input mapped into corresponding control character. transmit FIFOs must initialized upon deassertion RST_N signal. Receiver Description Clock recovery performed input data stream each channel ORT8850. recovered data then aligned 10-bit word boundary. Word alignment accomplished detecting aligning 8B/10B comma sequence. will detect align either polarity comma sequence. 10-bit word aligned data then decoded 8-bit output passed alignment FIFOs. Each receive channel provides FIFO order adjust skew between channels ensure that first valid data following comma character transmitted simultaneously from channels that programmed aligned. RESET state, each channel actively searching occurence comma character. Once channel powered comma detect pulse will found doutxx-fp channel FPGA. Receive Channel Sync Block order account skews between channels, necessary align multiple channels comma character boundary. sync algorithm assumes that either eight channels, groups four channels, four groups channels will aligned. ORT8850 powers RESET state which channel alignment done.
Generic Backplane Transceiver Application
Synchronous Transfer Mode (STM)
combination ORT8850 soft cores provides generic data moving solution non-SONET applications. There requirement SONET knowledge users. that needed supply pseudo-SONET framer with data, clock, frame pulse. provision registers also need this done through either FPGA MPI, state machine FPGA section (VHDL code available from Lattice). frame pulse must supplied SYS_FP signal. generic applications, frame pulse created FPGA logic from 77.76 SYS_CLK using simple resettable counter (the frame pulse should only high cycle SYS_CLK). VHDL core that automatically provides frame pulse available from Lattice. Byte-wide data then sent each transmit channels follows: first bytes transferred will invalid data (replaced overhead), where first byte sent rising edge SYS_CLK when SYS_FP high. next 1044 byte positions filled with valid data. This will repeat total nine times invalid bytes followed 1044 valid bytes) which time next frame pulse will found. Thus, (96.7%) data bytes sent valid user data. ORT8850 also supports transparent mode where only first bytes invalid data (A1/A2 frame bytes) followed 9,684 bytes valid user data. receive side, pulse must again supplied LINE_FP. this case, however, only signal DOUT<channel>_SPE (where eight channels labeled must monitored each channel, where high value this signal means valid data. Again, bytes received (96.7%) will valid data. Transparent mode also supported receive data.
Lattice Semiconductor
ORCA ORT8850 FPSC Eight-Channel Mbits/s Backplane Transceiver
Generic Backplane Transceiver Application (continued)
TRANSMIT CHANNEL PARALLEL DINXX DATAIN FIFO SERIALIZER
8B/10B ENCODER
LVDS
ERROR FLAG ALIGNMENT FIFO DOUTXX PARALLEL DATA SYS_CLK COMMA _DET DOUTXX_FP 10b/8b DECODER
DESERIALIZER BYTE ALIGN
DATA
CLOCK RECOVERY
LVDS
LCKRX
CLOCK
RECEIVER CHANNEL 1757(F)
Figure 8850 with 8B/10B Coding/Decoding
Backplane Transceiver Core Detailed Description
Macro
high-speed interface (HSI) provides physical medium high-speed asynchronous serial data transfer between ASIC devices. devices mounted same board mounted different boards connected through shelf backplane. macro eight-channel clockphase select (CPS) data retime function with serial-to-parallel demultiplexing incoming data stream parallel-to-serial multiplexing outgoing data. macrocell used eight-channel 16-channel configuration. ORT8850 uses eightchannel macro cell. macro consists three functionally independent blocks: receiver, transmitter, synthesizer shown Figure synthesizer block generates necessary clock operation from MHz, MHz, reference. synthesizer block common asset shared eight receive transmit channels. reference clock must match interface frequency.
HSI_RX block receives differential Mbits/s subrates Mbits/s, Mbits/s) serial data without clock LVDS receiver input. Based data transitions, receiver selects appropriate clock phase each channel retime data. retimed data clock then passed deMUX (deserializer) module. DeMUX module performs serial-to-parallel conversion provides three possible parallel rates, Mbits/s, Mbits/s, Mbits/s, where Mbits/s data used SONET mode Mbits/s data used 8B/10B mode (212 Mbits/s unused). HSI_TX block receives Mbits/s (SONET mode), Mbits/s (8B/10B mode) parallel data input. (serializer) module performs parallel-toserial conversion using clock provided PLL/synthesizer block. resulting Mbits/s serial data stream then transmitted through LVDS driver. loopback feature built into macro provides looping transmitter data output into receiver input when desired. rate examples described here maximum rates possible. actual internal clock rate determined provided reference clock rate. example, reference clock provided, macro will operate Mbits/s.
Lattice Semiconductor
ORCA ORT8850 FPSC Eight-Channel Mbits/s Backplane Transceiver
Backplane Transceiver Core Detailed Description (continued)
RXPWRDN[(n 1):0] RESETRX (TEST) TSTCLK SERIAL PARRALLEL CREG BYPASS CREG LOOPBKEN LOOPBKCH[(n 1):0] DIN[(n 1):0] Mbits/s Mbits/s Mbits/s DATA CLOCK/DATA ALIGNMENT RETIME SELECT LD[(n 1):0]RX[9:0] LCKRX[(n 1):0] WORD ALIGN RC[1:0]CK[(n-1):0] ENCOMMA[(n-1):0] SYSCLK (850 MHz) SYNTHESIZER COMMADET[(n-1):0] ASIC BLOCK Mbits/s Mbits/s
DEMUX
PARRALLEL SERIAL
LCKPLL Mbits/s Mbits/s
DOUT[(n -1):0] Mbits/s Mbits/s Mbits/s DATA BYPASS TSTCLK
LD[(n 1):0] TX[9:0] Mbits/s Mbits/s
MODE CONTROL
EN10BIT
RESETTX (TEST)
5-8592(F).b
Figure Functional Block Diagram
Lattice Semiconductor
ORCA ORT8850 FPSC Eight-Channel Mbits/s Backplane Transceiver
Backplane Transceiver Core Detailed Description (continued)
STransmitter (FPGA Backplane)
synchronous transport module (STM) portion embedded core consists slices: Each Sslice four STS-12 transmit channels, which treated single STS-48 channel. general, transmitter circuit receives four byte-wide 77.76 data from FPGA, which nominally represents four STS-12 streams This data synchronized system (reference) clock, system frame pulse from FPGA logic. Transport overhead bytes then optionally inserted into these streams, streams forwarded HSI. byte timing pulses required isolate individual overhead bytes (e.g., D1-D3, etc.) generated internally based system frame pulse (SYS_FP) received from FPGA logic. streams operate byte-wide 77.76 modes. processor operates from 77.76 supports following signals: insertion optional corruption; pass transparently; BIP-8 parity calculation (after scrambling) byte insertion optional corruption (before scrambling); optional insert; optional S1/M0 insert; optional E1/F1/E2 insert; optional section data communication channel (DCC,
D1-D3) line data communication channel (DCC, D4-D12) insertion (for intercard communications channel); scrambling outgoing data stream with optional scrambler disabling; optional stream disabling. streams operate byte-wide 77.76 (622 Mbits/s) 106.25 (850 Mbits/s) modes. When ORT8850 used nonnetworking applications generic high-speed backplane data mover, serial ports unused used slow-speed, off-channel communication between devices. optional transparent mode available where only twelve twelve bytes used frame alignment synchronization. Data received parallel optionally scrambled transferred LVDS outputs. Byte Ordering Information Smacro slice (i.e., supports quad STS12, quad STS-3, quad STS-1 modes operation input/output ports. STS-48 also supported, must received quad STS-12 format. When operating quad STS-12 mode, each independent byte streams carries entire STS-12 within Figure reveals byte ordering individual STS-12 streams STS-48 operation. Note that recovered data will always continue same order transmitted.
STS-12 STS-12 STS-12 STS-12
STS-48 QUAD STS-12 FORMAT
QUAD STS-12
STS-12 STS-12 STS-12 STS-12
5-8574
Figure Byte Ordering Input/Output Interface STS-12 Mode Lattice Semiconductor
ORCA ORT8850 FPSC Eight-Channel Mbits/s Backplane Transceiver
addition above hardcoded exceptions, source some bytes further controlled software. When configured pass-through mode, specific bytes must flow transparently from parallel input. Note that blocks STS-1 bytes forming STS-12 controlled whole. There software controls channel, listed below:
Backplane Transceiver Core Detailed Description (continued)
Transport Overhead In-Band Communication byte used in-band configuration, service, management since carried along same channel data. ORT8850, in-band signaling efficiently utilized, since total cost overhead only 3.3%. Transport Overhead Insertion (Serial Link) serial links used insert bytes into transmit data. transmit data TOH_CLK_EN retimed TOH_CLK order meet setup hold specifications device. retimed data shifted into 288-bit (36-byte 8-bit) shift register then multiplexed 8-bit inserted into byte-wide data stream. Insertion from these serial links pass-through from byte-wide data under software control. Transport Overhead Byte Ordering (FPGA Backplane) transparent mode, data received parallel input transferred, unaltered, serial LVDS output. However, byte STS#1 always replaced with calculated value (the bytes following replaced with zeros). Also, bytes STS-1s always regenerated. serial port used transparent mode operation. insert mode, bytes transferred, unaltered, from input parallel serial LVDS output. other hand, bytes received from serial input port inserted STS12 frame before being sent LVDS output. Although bytes from STS-1s transferred into device from each serial port, them inserted frame. There three hardcoded exceptions byte insertion:
Source bytes STS-1s bytes) specified control (per channel control). Source bytes STS-1s bytes) specified control (per channel control). Source bytes STS-1s bytes) specified control (per channel control). Source bytes STS-1s bytes) specified control (per channel control). Source bytes STS-1s bytes) specified control (per channel control). Source bytes STS-1s bytes) specified control (per channel control). Source bytes STS-1s bytes) specified control (per channel control). Source bytes STS-1s bytes) specified control (per channel control). Source bytes STS-1s bytes) specified control (per channel control). Source bytes STS-1s bytes) specified control (per channel control). Source bytes STS-1s bytes) specified control (per channel control). Source bytes STS-1s bytes) specified control (per channel control). Source bytes STS-1s bytes) specified control (per channel control). Source bytes STS-1s bytes) specified control (per channel control). Source bytes STS-1s bytes) specified control (per channel control).
Framing bytes (A1/A2 STS-1s) inserted from serial input bus. Instead, they always regenerated. Parity byte STS#1) inserted from serial input bus. Instead, always recalculated (the bytes following replaced with zeros). Pointer bytes (H1/H2/H3 STS-1s) inserted from serial input bus. Instead, they always flow transparently from parallel input LVDS output.
reconstruction dependent transmitter mode operation. transparent mode, bytes LVDS output shown Table capability ORT8850 allows user choose insert byte following bytes zeros. This option also available bytes.
Lattice Semiconductor
ORCA ORT8850 FPSC Eight-Channel Mbits/s Backplane Transceiver
Backplane Transceiver Core Detailed Description (continued)
Table Transmitter LVDS Output (Transparent Mode)
Regenerated bytes. Transparent bytes from parallel input port.
insert mode operation, bytes LVDS output shown Table This also shows order which data transferred serial interface, starting with most significant first byte. first first byte replaced even parity check over bytes from previous frame. Table Transmitter LVDS Output (TOH Insert Mode)
Regenerated bytes. Inserted transparent bytes. Blocks STS-1 bytes controlled whole. There controls/channel: K1/K2, S1/M0, E1/F1/E2, D10, D11, D12. Transparent bytes (from parallel input port). Inserted bytes from serial input port.
A1/A2 Frame Insert Testing bytes provide special framing pattern that indicates where STS-1 begins stream. bytes each STS-12 0xF6, bytes STS-12 0x28 when overridden with user-specified value testing. latency from transmission first byte device output pins from transmit frame pulse (SYS_FP) FPGA embedded core input between five seven cycles fpga_sysclk. A1/A2 testing (corruption) controlled stream A1/A2 error insert register. When A1/A2 corruption detection particular stream, A1/A2 values corrupted A1/A2 value registers sent number frames defined corrupted A1/A2 frame count register. When corrupted A1/A2 frame count register zero, A1/A2 corruption will continue until A1/A2 error insert register cleared. This also allows alternate values during normal operation. ORT8850, optionally possible insert per-device basis, byte values set, well number frames corruption. Then, insert specified A1/A2 values, each channel enable register. When enable register set, A1/A2 values corrupted number specified number frames corrupt. insert errors again, perchannel fault insert register must cleared, again. Only last first corrupted.
Lattice Semiconductor
ORCA ORT8850 FPSC Eight-Channel Mbits/s Backplane Transceiver
FPGA Swill aligned frame pulse SYS_FP that supplied Smacro. either direction, system frame pulse line frame pulse active system clock cycle, indicating location byte STS#1. They common eight channels except when pointer mover alignment FIFOs bypassed. that case, line frame pulse each receive channel generated Smacro passed FPGA interface. Repeater This block essentially inverse sampler block. receives byte-wide STS-12 rate data from insert block. order support quad STS-1 STS-3 modes operation, (622 Mbits/s) connected slower speed device (e.g., Mbits/s Mbits/s). purpose this block rearrange data being that each transmitted four twelve times, thus simulating Mbits/s 51.84 Mbits/s serial data. example, STS-3 mode, incoming STS-12 stream composed four identical STS-3s only every fourth byte used. expansion process takes single byte stretches take bytes each consisting copies bits from original byte. STS-1 mode, every twelfth byte used four groups bytes form AAAAAAAA, AAAABBBB, BBBBBBBB forwarded HSI. alternate method supplying STS-1 mode 207.36 four times repeater function.
Backplane Transceiver Core Detailed Description (continued)
Calculation Insertion interleaved parity (BIP-8) error check even parity over bits STS-1 frame defined first STS-1 STS-N only, calculation block computes BIP-8 code, using even parity over bits previous STS-12 frame after scrambling inserted byte current STS-12 frame before scrambling. Per-bit corruption controlled force BIP-8 corruption register (register address 0F). this register, corresponding calculated BIP-8 inverted before insertion into byte position. Each stream independent fault insert register that enables inversion bytes. bytes other STS1s stream filled with zeros. ORT8850, optionally possible insert subsequent bytes zeros. Stream Disable When disabled appropriate stream enable register, prescrambled data stream ones, feeding HSI. macro powered down per-stream basis, LVDS outputs. Scrambler data stream scrambled using frame-synchronous scrambler with sequence length 127. scrambling function disabled software. generating polynomial scrambler This polynomial conforms standard SONET STS-12 data format. scrambler reset 1111111 first byte (byte following byte twelfth STS-1). That byte subsequent bytes scrambled exclusive-ORed, with output from byte-wise scrambler. scrambler runs continuously from that byte throughout remainder frame. bytes scrambled. System Frame Pulse Line Frame Pulse System frame pulse (for transmitter) line frame pulse (for receiver) generated FPGA logic. A1/A2 framing used link locating frame location. frames sent FPGA aligned FPGA frame pulse LINE_FP which provided FPGA Smacro. frames sent from
SReceiver (Backplane FPGA)
Each Sslices ORT8850 four receiving channels that treated STS-48 stream, treated independent channels. Incoming data received through LVDS serial ports data rate Mbits/s. receiver handle data streams with frame offsets bytes which would timing skews between cards along backplane traces other transmission medium. order this multichannel alignment capability operate properly, should noted that while skew between channels very large, they must operate exact same frequency frequency deviation), thus requiring that their transmitters driven same clock source. received data streams processed STM, then passed through boundary FPGA logic.
Lattice Semiconductor
ORCA ORT8850 FPSC Eight-Channel Mbits/s Backplane Transceiver
Backplane Transceiver Core Detailed Description (continued)
Framer Block framer block takes byte-wide data from HSI, outputs byte-aligned, byte-wide data stream sync pulse. framer algorithm determines out-of-frame/in-frame status incoming data will cause interrupts both errored frame out-of-frame (OOF) state. framer detects framing pattern generates frame pulse. When framer detects OOF, will generate interrupt. Also, framer detects errored frame increments A1/A2 frame error counter. counter monitored processor compile performance status quality backplane. Because ORT8850 intended between another ORT8850 other devices backplane, there only errored frame state. Thus, after transitions missed, state machine goes into state there severely errored frame (SEF) loss-of-frame (LOF) indication. Calculate Each block receives byte-wide scrambled 77.76 data frame sync from framer. Since each independently clocked, block operates individual streams. Timing signals required locate overhead bytes extracted generated internally based frame sync. block produces byte-wide (optionally) descrambled data output frame sync alignment FIFO block. frame sync signals also sent FPGA logic when alignment FIFO block bypassed. calculation block computes BIP-8 (bit interleaved parity bits) code, using even parity over bits previous STS-12 frame before descrambling; this value checked against byte current frame after descrambling. per-stream error counter incremented each that error. error counter read interface.
Descrambling. streams descrambled using frame synchronous descrambler with sequence length with generating polynomial A1/A2 framing bytes, section trace byte (J0) growth bytes (Z0) descrambled. descrambling function disabled software. Sampler. This block operates byte-wide data directly from macro. external interface always runs Mbits/s (STS-12), Mbits/s, connected directly Mbits/s STS-3 stream 51.84 Mbits/s STS-1 stream. connected either Mbits/s 51.84 Mbits/s stream, each incoming data received either times respectively. This block used return byte stream expected STS-12 format. mode operation controlled register either STS-12 (pass-through), STS-3 (every fourth bit), STS-1 (every twelfth bit). output from this block bitaligned (i.e., 8-bit sample does necessarily contain entire SONET byte), standard SONET STS-12 format (i.e., four STS-3s STS-1s) suitable framing. AIS-L Insertion. Alarm indication signal (AIS) continuous stream unframed sent alert downstream equipment that near-end terminal failed, lost signal source, been temporarily taken service. enabled AIS_L force register, AIS-L inserted into received frame writing ones bytes descrambled stream. AIS-L Insertion Out-of-Frame. enabled register, AIS-L inserted into received frame writing ones bytes descrambled stream when framer indicates that out-of-frame condition exists. Internal Parity Generation Even parity generated data bytes routed parallel with data checked before protection switch parallel output.
Lattice Semiconductor
ORCA ORT8850 FPSC Eight-Channel Mbits/s Backplane Transceiver
Backplane Transceiver Core Detailed Description (continued)
Transport Overhead Extraction Transport overhead extracted from receive data stream extract block. incoming data gets loaded into 36-byte shift register system clock domain. This, turn, clocked onto clock domain start time, where clocked out. During time, receiver frame pulse generated, RX_TOH_FP, which indicates start bytes. This pulse, along with receive clock enable, RX_TOH_CK_EN, well data, launched rising edge clock TOH_CLK. Byte Ordering processor responsible dropping bytes each channel through four corresponding serial ports. four serial ports synchronized clock (the same clock that being used serial ports transmitter side). This free-running clock provided core external circuitry operates minimum frequency maximum frequency 77.76 MHz. Data transferred over serial links bursty fashion controlled clock enable signal, which generated ASIC common four channels. bytes STS-12 streams transferred over appropriate serial link same order which they appear standard STS-12 frame. Data transfer should preformed row-byrow basis such that internal data buffering needs kept minimum. Data transfers serial links will synchronized relative frame signal. Receiver Reconstruction Receiver reconstruction output parallel shown following table pointer mover bypassed). Table Receiver (Output Parallel Bus)
Regenerated bytes. Regenerated bytes (under pointer generator control, bits must transparent, AIS-P must supported). Bytes taken from elastic store buffer, negative stuff opportunity-else, forced zeros. Transparent zeros (K1/K2 either taken from K1/K2 buffer forced zeros-soft, control). transparent mode, AIS-L must supported. zero bytes.
serial port, bytes dropped received LVDS input (MSB first). only exception most significant byte STS#1, which replaced with even parity bit. This parity calculated over previous frame. Also, AIS-L (either resulting from forced through software), bits forced ones with proper parity (parity automatically ends being AIS-L). Special Byte Functions Handling. bytes used automatic protection switch (APS) applications. bytes optionally passed through pointer mover under software control, zero with other bytes. Handling. discussed previously, bytes used framing header. bytes always regenerated hexadecimal respectively. Lattice Semiconductor
ORCA ORT8850 FPSC Eight-Channel Mbits/s Backplane Transceiver
Backplane Transceiver Core Detailed Description (continued)
C1J1 Outputs. These signals each channel passed FPGA logic allow pointer processor other function extract payload without interpreting pointers. ORT8850, each frame STS-1s. region, there pulses each STS-1s. There C1(J0, SONET specifications instead section trace identify each STS-1 STS-N) pulse area frame. Thus, there total pulses C1(J0) pulse frame. C1(J0) pulse coincident with STS1 each frame, flag active when data stream area. behavior dependent pointer movement concatenation. Note that area, also carry valid data. When valid data carried this slot, high this particular time slot. region, there valid data during column, signal will low. allows pointer processor extract payload without interpreting pointers. C1J1 functionality described Table generic data operation, valid data available when C1J1 signal ignored. Table C1J1 Functionality C1J1 Description information excluding C1(J0) STS1 Position C1(J0) STS1 (one frame). Typically used provide unique link identification (256 possible unique links) help ensure cards connected into backplane correctly cables connected correctly. information excluding bytes. Position bytes.
Note:The following rules observed generating C1J1 signals: occurrence AIS-P STS-1, there corresponding pulse. case concatenated payloads STS48c), only head STS-1 group associated pulse. C1J1 signal tracks pointer movements. During negative justification event, high during byte indicate that payload data available. During positive justification event, during positive stuff opportunity byte indicate that payload data available.
STS-12
first BYTES STS-1S
STS-12
PULSE C1J1 PULSE STS-1
5-9330(F)
Note: C1J1 signal behavior shown this figure just illustration purposes: pulse position must always shown; however, position pulses vary based path overhead location each STS-1 within STS-12 stream. C1J1 signal must always active during C1(J0) time slot STS#1. C1J1 signal must also active during twelve time slots. However, C1J1 must active STS-1 which AIS-P generated. Also, concatenated payloads, only head group must have pulse.
Figure C1J1 Functionality Lattice Semiconductor
ORCA ORT8850 FPSC Eight-Channel Mbits/s Backplane Transceiver
Backplane Transceiver Core Detailed Description (continued)
STS-12
NEGATIVE STUFF OPPORTUNITY BYTES
POSITIVE STUFF OPPORTUNITY BYTES
STS-12
SIGNAL SHOWS NEGATIVE STUFFING STS-1, POSITIVE STUFFING STS-1
5-9331
Note: signal behavior shown this figure just illustration purposes: behavior dependent pointer movements concatenation. signal must high during negative stuff opportunity byte time slots (H3) which valid data carried (negative stuffing). signal must during positive stuff opportunity byte time slots which there valid data (positive stuffing).
Figure Stuff Bytes SFIFO Alignment (Backplane FPGA) alignment FIFO allows transfer data system clock. FIFO sync block (Figure allows system configured allow frame alignment multiple slightly varying data streams. This optional alignment ensures that matching STS-12 streams will arrive FPGA perfect data sync. frame alignment configurable allow possibility fully independent (i.e., total frame misalignment) STS-12s.
Lattice Semiconductor
ORCA ORT8850 FPSC Eight-Channel Mbits/s Backplane Transceiver
Backplane Transceiver Core Detailed Description (continued)
four streams correct mode when synchronization takes place, then those streams enabled disabled without affecting synchronization. These streams frame-aligned patterns shown Figure Figure Figure
ALIGNMENT
Stream Stream Stream Stream Stream Stream Stream Stream Stream Stream
STS-12 STREAM STS-12 STREAM STS-12 STREAM STS-12 STREAM FIFO SYNC STS-12 STREAM STS-12 STREAM STS-12 STREAM STS-12 STREAM
SSLICE
Stream Stream Stream Stream Stream Stream
0674
Figure Example Inter-SAlignment
SSLICE
ALIGNMENT
Stream Stream Stream Stream Stream Stream Stream Stream Stream Stream Stream Stream
5-8577
Stream Stream Stream Stream
Figure Interconnect Streams FIFO Alignment incoming data from (also referred CDRM850) separated into four STS-12 channels slice. Thus, there STS-12 channels from slice Sand STS12 channels slice These streams frame-aligned following patterns: STS-48 mode, four STS-12s each Sslice aligned with each other (i.e., AD). Optionally, STS-48 mode, eight STS-12s (STMs aligned allow hitless switching STS-48 level). Multiple devices aligned enable STS192 higher modes. Streams also aligned twin STS-12 basis. There also provision allow certain streams disabled (i.e., producing interrupts affecting synchronization). These streams enabled later time without disrupting other streams. selected stream needs part bigger group (i.e., SA), then either entire group must resynched affected stream must have been correct mode (i.e., align when initial synchronization performed. long
0673(F)
Figure Example Intra-SAlignment
TWINS ALIGNMENT STREAMS
Stream Stream Stream Stream Stream Stream Stream Stream Stream Stream Stream Stream Stream Stream Stream Stream
0675
Figure Example Twin STS-12 Stream Alignment Lattice Semiconductor
ORCA ORT8850 FPSC Eight-Channel Mbits/s Backplane Transceiver
address FIFO block. first every STS12 stream written same location (address FIFO. Also, frame passed through FIFO along with first byte before first STS12. read control block synchronizes reading FIFO streams that aligned. Reading begins when FIFO sync signals that applicable appropriate margin have been written FIFO. read blocks synchronized begin reading same time same location memory (address alignment algorithm takes difference between read address write address indicate relative clock alignments between STS-12 streams. this depth indication exceeds certain limits clocks), then interrupt given microprocessor (alignment overflow). Each STS-12 stream realigned software gets line (this would cause loss data). background applications that have less than 154.3 interlink skew, misalignment will occur. SLink Alignment Setup order ensure proper operation SLink Alignment capability, following setup procedures should followed after enabled channels have valid frame pulse: streams aligned, including disabled streams, into their required alignment mode. Force AIS-L streams synchronized (refer register map, write 0x01 register 0x30020, 0x30038, 0x30050, 0x30068, 0x30080, 0x30098, 0x300B0, 0x300C8). Wait four frames. Write 0x01 FIFO alignment resync register bits required register 0x30017 0x30018. Wait four frames. Release AIS-L streams (write 0x00 register 0x30020, 0x30038, 0x30050, 0x30068, 0x30080, 0x30098, 0x300B0, 0x300C8). This procedure allows normal data flow through embedded core.
Backplane Transceiver Core Detailed Description (continued)
FIFO block consists 24-bit 10-bit FIFO link. This FIFO used align ±154.3 interlink skew transfer system clock. FIFO sync circuit takes metastable hardened frame pulses from write control blocks produces sync signals that indicate when read control blocks should begin reading from first FIFO location. sync signals, this block produces error indicator which indicates that signals aligned apart alignment (i.e., greater than clocks apart). Sync error signals sent read control block alignment. read control block synched only once start-up; further synchronization software controlled. action resynching read control block will always cause loss data. register allows read control block resynched. SLink Alignment general operation link alignment algorithm wait clocks (i.e., half FIFO) from arriving frame pulse then signal read control block begin reading. perfectly aligned frame pulses across links, simply matter counting down then signaling read control block. algorithm down counts until frame pulses have arrived then when they present. example (Figure 12), pulses arrive together, then alignment algorithm would count clocks); however, arriving pulses spread over four clocks, then would count first four pulses then clock afterward, which gives total clocks between first frame pulse first read. This puts center arriving frame pulses halfway point buffer. This extent algorithm, facility actively correcting problems once they occur. write control block receives byte-wide data 77.76 frame pulse clocks before first byte STS-12 frame. generates write
CLOCKS
CLOCKS LAST ARRIVES
ARRIVE TOGETHER (WRITING BEGINS)
24-byte FIFO
SYNC. PULSE (READING BEGINS)
CLOCKS FIRST ARRIVES (WRITING BEGINS)
24-byte FIFO
SYNC PULSE (READING BEGINS)
PERFECTLY ALIGNED FRAMES
4-BYTE SPREAD ARRIVING FRAMES
5-8584
Figure Examples Link Alignment Lattice Semiconductor
ORCA ORT8850 FPSC Eight-Channel Mbits/s Backplane Transceiver
Backplane Transceiver Core Detailed Description (continued)
8B/10B Transmitter (FPGA Backplane)
each channel, 8B/10B encoder enabled place Stransmitter. This block receives 8-bit data from FPGA interface, encodes into 10-bit code, then sends this 10-bit code block serialization transmission from ORT8850. This 8-bit 10-bit encoding provides guaranteed transmission large number transmissions allow easy recovery other backplane transmission medium, also allows insertion control characters. These control characters have many uses, including their ORT8850 align 10-bit word boundries perform multi-channel alignments, will discussed 8B/10B receiver section. data input transmitter each channel from FPGA logic 8-bit word K-control input. Kcontrol input used designate data special character, where logic indicates that data should mapped control character. following table shows this mapping that supported. different codings possible each data value shown encoded word encoded word (-). transmitter selects between positive negative encoded word based calculated disparity present data. Table Valid Special Characters character
K28.0 K28.1 K28.2 K28.3 K28.4 K28.5 K28.6 K28.7 K23.7 K27.7 K29.7 K30.7
EDCBA 43210
11100 11100 11100 11100 11100 11100 11100 11100 10111 11011 11101 11110
control
Encoded Word abcdei fghj
001111 0100 001111 1001 001111 0101 001111 0011 001111 0010 001111 1010 001111 0110 001111 1000 111010 1000 110110 1000 101110 1000 011110 1000
Encoded Word abcdei fghj
110000 1011 110000 0110 110000 1010 110000 1100 110000 1101 110000 0101 110000 1001 110000 0111 000101 0111 001001 0111 010001 0111 100001 0111
should also noted that data serialized reverse order from Sblock, where dinxy[0] transmitted first (the 8B/10B receive block also deserializes reverse order Sreceive block).
8B/10B Receiver (Backplane FPGA)
Instead using Sreceiver block ORT8850, separate decoder block available allow receiving data that been encoded using standard 8B/10B encoder. This encoding/decoding scheme also allows transmission special characters allows error detection. Clock recover 8B/10B decoder performed block each eight receive channels ORT8850. This recovered data then aligned 10-bit word boundry detecting aligning commacodeword. Word alignment done either polarity this codeword. 10-bit code word passed decoder, which provides 8-bit byte data COMMADET signal multi-channel alignment block. 8B/10B mode, receiver handle bytes skew between channels which would timing skews between cards along backplane trace other transmission medium. order this multi-channel alignment capability operate properly, should noted that while skew between channels very large, they must operate exact same frequency frequency deviation), thus requiring their transmitters driven same clock source. This alignment FIFO bypassed. COMMADET signal also provided FPGA logic channel signal doutxy_fp, where designates either four-channel macro while designates channel each macro. Lattice Semiconductor
ORCA ORT8850 FPSC Eight-Channel Mbits/s Backplane Transceiver
Backplane Transceiver Core Detailed Description (continued)
8B/10B Link Alignment Setup order align receive channels 8B/10B mode, following procedure should followed: Enable 8B/10B mode eight channels setting EN10BIT found control register address 0xe0 (bit Enable ENCOMMA bits used channels control register address 0x300e3 (one channel). streams aligned, including disabled streams, into their required alignment mode. Transmit least packets across each link aligned. Write 0x01 FIFO alignment resync register bits required control register 0x30017 0x30018.
Pointer Mover Block (Backplane FPGA)
pointer mover maps incoming frames line framing that supplied FPGA logic. There separate pointer mover Smacro slices, each which handles STS-48 (four channels), there only line frame pulse imput (line_fp) shared both pointer mover blocks. K1/K2 bytes H1-SS bits also passed through pointer generator that FPGA receive them. pointer mover handles both concatenations inside STS-12, other STS-12s inside core. pointer mover block correctly process length concatenation frames (multiple three) long begins STS-3 boundary (i.e., STS-1 number one, four, seven, ten, etc.) contained within smaller STS-3, details Table Table Valid Starting Positions STS-Mc STS-1 Number STS-3cSPE STS-6cSPE STS-9cSPE STS-12cSPE STS-15cSPE STS-18c STS-48c SPEs
Note: STS-Mc start that STS-1. STS-Mc cannot start that STS-1. depending particular value
Lattice Semiconductor
ORCA ORT8850 FPSC Eight-Channel Mbits/s Backplane Transceiver
Backplane Transceiver Core Detailed Description (continued)
NORM
Pointer Interpreter State Machine. pointer interpreter's highest priority maintain accurate data flow (i.e., valid only) into elastic store. This will ensure that errors pointer value will corrected standard, fully SONET compliant, pointer interpreter without data hits. This means that error checking increment, decrement, data flag (NDF) (i.e., maintained order ensure accurate data flow. single valid pointer (i.e., 0-782) that differs from current pointer will ignored. consecutive incoming valid pointers that differ from current pointer will cause reset location latest pointer value (the generator will then produce NDF). This block designed handle single errors without affecting data flow changing state. pointer interpreter only three states (NORM, AIS, CONC). NORM state will begin whenever consecutive NORM pointers received. consecutive NORM pointers that both differ from current offset received, then current offset will reset last received NORM pointer. When pointer interpreter changes offset, causes pointer generator receive value position. When pointer generator gets unexpected resets offset value location declares NDF. interpreter only looking consecutive pointers that different from current value. These consecutive NORM pointers have have same value. example, current pointer NORM pointer with offset second NORM pointer with offset received, then interpreter will change current pointer receipt consecutive CONC pointers causes CONC state entered. Once this state, offset values from head concatenation chain used determine location each chain. consecutive pointers cause state occur. consecutive normal concatenation pointers will this state. This state will cause data leaving pointer generator overwritten with 0xFF.
CONC CONC
5-8589
Figure Pointer Mover State Machine Pointer Generator. pointer generator maps corresponding bytes into their appropriate location outgoing byte stream. generator also creates offset pointers based location byte indicated pointer interpreter. generator will signal NDFs when interpreter signals that coming state. pointer generator resets pointer value generates every time byte marked read from elastic store that doesn't match previous offset. Increment decrement signals from pointer interpreter latched once frame either byte times (depending collisions); this ensures constant values during through times. choice which byte time latching made once when relative frame phases (i.e., received system) determined. This latch point then stable unless relative framing changes received byte times collide with system times, which case latch point would switched collision-free byte time. There restriction many often increments decrements processed. received increment decrement immediately passed generator implementation regardless when last pointer adjustment made. responsibility meeting SONET criteria maximum frequency pointer adjustments left upstream pointer processor. When interpreter signals state, generator will immediately begin sending 0xFF place data This will continue until interpreter returns NORM CONC (pointer mover state machine) states byte received.
Lattice Semiconductor
ORCA ORT8850 FPSC Eight-Channel Mbits/s Backplane Transceiver
SRedundancy Protection Switching
ORT8850 supports STS-12/STS-48 redundancy either software hardware control protection switching applications. transmitter mode, additional functionality required redundant operation. receiving data, STS-12 STS-48 data redundancy implemented within same device, while STS-192 above data stream requires multiple ORT8850 devices support redundancy. STS-12 mode, channel receive data port used both channel channel Similarly, channel receive data port used both channel channel Channel channel become redundant channels. channel channel receive data ports unused. Soft registers provide independent control protection switching MUXes both parallel data ports serial data ports. When direct hardware control protection switching needed, external protection switch pins available channels also channels external protection switch pins only support parallel SPE/TOH data protection switching, serial data. these protection switching pins listed Table prot_switch_xx. STS-48 redundancy, 4-channel macro blocks both used: four channels work four channels protect. switching between work protect extended either between four-channel macros between channels within both macros. STS-192 mode, multiple independent devices required work protect redundancy. Parallel serial port output pins FPGA side should 3-stated basis supporting redundancy. existing local enable signals used 3-state controls FPGA data needed, which easily accessed software control. Users also create their protection switch 3-state enable signals either FPGA logic external device, depending specific application. Sprotection switch circuitry available 8B/10B mode Spointer mover alignment FIFO bypass mode. available when only pointer mover bypassed.
Backplane Transceiver Core Detailed Description (continued)
Receive Bypass Options FPGA Interface
blocks receive direction required used. following bypass options valid receive (backplane FPGA) direction:
SPointer Mover bypass: this mode, data from alignment FIFOs transferred FPGA logic. channels synchronous fpga_sysclk signals driven FPGA logic, also case when pointer mover bypassed. During bypass SPE, C1J1, data parity signals valid. When pointer mover bypassed, frame pulse from aligned channels (doutxy_fp) provided embedded core. When pointer mover used, FPGA logic provides frame pulse line_fp signal. SPointer Mover Alignment FIFO bypass: this mode, data from framer block transferred FPGA logic. channels supply data frame pulses synchronous with their individual recovered clock (cdr_clk_xy) channel. During bypass, SPE, C1J1, data parity signals valid. 8B/10B Alignment FIFO bypass: When 8B/10B mode, data from 8B/10B decoder passed FPGA logic alignment FIFO bypassed. channels suppply data COMMADET signals synchronous with their individual recovered clock (cdr_clk_xy) channel. When bypassed, 8B/10B alignment clock provides channels COMMADET signal synchronous fpga_sysclk signal FPGA logic.
Powerdown Mode
Powerdown mode will entered when corresponding channel disabled. Channels independently enabled disabled under software control. Parallel data output enable serial data output enable signals made available FPGA logic. macrocell's corresponding channel also powered down. device will power with eight channels powerdown mode.
Lattice Semiconductor
ORCA ORT8850 FPSC Eight-Channel Mbits/s Backplane Transceiver
Backplane Transceiver Core Detailed Description (continued)
LVDS Protection Switching
Each SERDES link sends receives data LVDS buffers. example, data transmitted through SERDES tx_b[0] work link tx_c[0] protect link. Data received through LVDS buffers switch provided select between work protect buffer. signal lvds_prot_aa provided FPGA logic selects between work link buffer (rx_b[0]) protect link buffer (rx_c[0]). These signals select protect link when high work link when low. LVDS protection switching used either mode when using STM. Sredundancy protection switching discussed previous section only used with STM. LVDS protection switching also switched using software control. Consult memory Table more information.
FPGA logic array. example, byte-wide data converted 32-bit wide data FPGA interface. primary task RapidIO process bytes data known octets transmitted group known cell. octet described bits found within cell. Once first octet cell received, subsequent octets part uninterrupted data stream until entire cell been received. beginning next cell will determine boundary previous cell. beginning cell indicated pulse start-of-cell, signal. signal always accompanies cell data. boundary, cell data present 8-bit data with first octet aligned with rising edge clock. FPGA end, cell data present 32-bit data bus. Thus, RapidIO used translate between 32bit data 8-bit data while monitoring integrity cells being processed.
Receive Cell Interface
receive interface performs demultiplexing from four sequential octets eight pairs LVDS pins using both edges high-speed clock onto internal 32-bit buses low-speed clock. interface includes following signals (see Figure 14):
RapidIO Interface Pi-Sched
Overview
ORT8850 includes three byte-wide, full-duplex RapidIO interfaces running (622 Mbits/s) line total Gbits/s each interface. Each input output interface includes byte-wide data, control signal (such start-ofcell), clock signal. three RapidIO interfaces always available. other RapidIO interface available only eight channels being used. function ORT8850 interface with protocol independent scheduler (Pi-Sched) device port card. Pi-Sched part high-speed switching (HSSW) family devices. offers highly integrated, innovative, complete VLSI solution implementing scheduling buffer management functionality cell (e.g., ATM) packet (e.g., switching system port OC-48c. RapidIO ORT8850 will support dedicated receive transmit interfaces off-chip communication. Both interfaces drive receive off-chip through LVDS pads. LVDS I/Os fully terminated on-chip allow driving high-speed parallel backplanes speeds MHz. Internally, each 8-bit RapidIO interface connected 32-bit interface which single-edge clocked connected
LVDS clock pair running MHz-311 MHz. relationship intended receive cell data. LVDS start-of-cell pair, which indicates that word data cell receive data port. Eight LVDS data pairs, double-edge clocked LVDS clock.
eight LVDS data pairs double-edge clocked LVDS receive clock (RXCLK). RXCLK aligned center received data start-of-cell (RXD RXSOC). achieve optimal timing margin, receiver required maintain this alignment. RapidIO interface requires that spacing integer multiple clock cycles proper operation that SOCs occur only rising edge receive clock (RXCLK).
Lattice Semiconductor
ORCA ORT8850 FPSC Eight-Channel Mbits/s Backplane Transceiver
RapidIO Interface Pi-Sched (continued)
REPEATED TIMES (ONE EACH RXD[1:7]) CLOCK DOMAIN CLOCK DOMAIN INPUT DATA CAPTURE SHIFT REGISTERS ZRXD_23 FPGA ZRXD_15 ZRXD_31 ZRXD_7
RXD[0]
RXD[7]
RXSOC
WRXCLK (133 MHz)
RXCLK
ZRXSOC
0676
Figure RapidIO Receive Cell Interface Octets Start Cell Cells will transmitted high-speed LVDS inputs octets. first octet (consisting d0_0, d1_0 d7_0) will present bits 31:24 low-speed 32-bit FPGA bus. Similarly, octet (consisting d0_1, d7_1) will present bits 23:16 32-bit bus. Thus, octets will always transmitted from first octet last. minimum number octets present high-speed ports should always divisible evenly representing relationship with 32-bit core ASIC interface. start-of-cell signal always aligned with first octet each cell. Once first octet cell received, subsequent octets part uninterrupted data stream until entire cell been received. number octets cell determined register bits OCELLSIZE. RapidIO support varying minimum cell sizes from four octets increments RapidIO programmed with cell size writing OCELLSIZE register microprocessor interface. transmitted cell size less than programmed cell size, violation occurs IRXSOCVIOL flag active. This flag ignored given minimum cell size needed.
Lattice Semiconductor
ORCA ORT8850 FPSC Eight-Channel Mbits/s Backplane Transceiver
RapidIO Interface Pi-Sched (continued)
EVEN BYTE POSITIVEEDGE FLOPS UTXD [31:0] UTXSOC WUTXCLK MHz-146 MHz) COMMON TRANSMIT FIFO BYTE NEGATIVEEDGE FLOPS
EVEN BYTE OUTPUT PORT DATA ALIGNMENT MUXes TXD[7:0] BYTE OUTPUT PORT DATA ALIGNMENT MUXes INTERFACE
0677
CONTROLLER
OUTPUT PORT CLOCK ALIGNMENT TXCLK
INPUT REGISTER
OUTPUT PORT ALIGNMENT TXSOC
PFCLK OUTPUT CLOCK FROM PLL) (240 MHz-584 MHz)
Figure RapidIO Transmit Cell Interface
Transmit Cell Interface
transmit interface performs multiplexing bits low-speed data onto four sequential octets eight pairs LVDS signal pins using both edges high-speed clock. transmitter module consists following LVDS signal pairs (see Figure 15):
Eight LVDS data pairs (TXD), double-edge clocked LVDS clock TXCLK. data pairs carry biphase data MHz-311 MHz. start-of-cell LVDS pair that indicates that octet data cell TXD. transitions this signal degrees also with crossing points LVDS clock (TXCLK). LVDS clock pair output TXCLK operating MHz-311 MHz. relationship intended exactly degree phase with transitions data TXSOC.
high-speed data outputs (TXD[0:7]) well start-of-cell signal TXSOC generated result positive edge PFCLK. This accomplished multiplexing between even bytes data PFCLK rate. PFCLK derived from internal operates base frequency between MHz. PFCLK expected have duty cycle with more than ±150 jitter. duty cycle PFCLK will directly affect accuracy high-speed clock ability maintain data. degree phase shift output clock puts TXCLK data. Lattice Semiconductor
OFF-CHIP
FPGA
ORCA ORT8850 FPSC Eight-Channel Mbits/s Backplane Transceiver
RapidIO Interface Pi-Sched (continued)
Table RapidIO Signals to/from FPGA Interface Name (All with Depending Channel) Receive Cell Interface ZRXD<31:0> From FPGA
FPGA
Description
ZRXSOC ZRXSOCVIOL
ZRXALNVIOL
ZCLKSTAT
CSYSENB
RSTN_RX WRXCLK_[chan]_FPGA Transmit Cell Interface UTXD[31:0]
32-bit data from receive module. contains four octets reflects data received high-speed data bus. Indicates presence first octet cell within first 32-bit data word positions [31:24]. Indicates minimum cell violation within receive module. This signal will transition active-high coincident with RXSOC. active state signals cell overran previous cell, previous cell violation minimum cell size. Signals alignment error. active state signals RXSOC captured negative RXCLK edge. violation condition this signal will stay high single WRXCLK_[chan]_FPGA cycle coincident with RXSOC. Indicates loss absence clock LVDS clock (RXCLK). This signal will present duration absence clock, following period validate absence. System cell processing enable. After reset released, drive this signal high when RapidIO ready transmit cells. This signal should active after control signals into RapidIO stable. Synchronous reset memory elements clocked WRXCLK_[chan]_FPGA (derived from PLL). Derived from high-speed LVDS clock RXCLK (RXCLK/2).
Transmit data containing four octets synchronized with rising edge MHz-146 WUTXCLK_FPGA (derived from PLL) clocked into transmit FIFO within RapidIO. UTXSOC Start cell, originating within core, synchronized with rising edge WUTXCLK_FPGA into transmit FIFO. Indicates first data word includes first octet cell positions [31:24]. RSTN_UTX Synchronous reset memory elements WUTXCLK domain. UTXTRISTN Output 3-state enable (active-low). When active, TXD, TXSOC, TXCLK LVDS drivers 3-stated. 3-state TXD, TXSOC TXCLK drivers. Normal operation. FPGA Interface Clocks (Common Channels) WUTXCLK_FPGA core clock generated from internal circuit. Synchronous UTXD UTXSOC data inputs. HALFCLK_FPGA main output clock. Phase-aligned with PFCLK. Nominal frequency MHz. Duty cycle spec 47%/ 53%.
Lattice Semiconductor
ORCA ORT8850 FPSC Eight-Channel Mbits/s Backplane Transceiver
RapidIO Interface Pi-Sched (continued)
Table Signals Used Register Bits Register Bit(s) OSHLBENB Description
Used during internal built-in self-test mode. Indicates that single-ended versions transmit module outputs should looped back into single-ended inputs receive module. OSHLENB loopback. OSHLENB Loopback. OCELLSIZE[4:0] This value indicates minimum cell size will used detect cell underrun errors. This value should stable prior initialization operation stable thereafter. OTESTENB Enables internal self-test RapidIO block. loopback paths exist during test, internal external. During both tests, data passed through modules verified. ITESTDONE Indicates completion internal test. Only valid during test when OTESTENB high. ITESTDONE Test running. ITESTDONE Test complete. ITESTPASS Indicates success internal test. This signal valid only when ITESTDONE high. ITESTPASS Test failed. ITESTPASS Test passed. TRISTN Active-low. 3-state override transmit outputs. This signal ignored during reset, takes priority over 3-state control signals when active.
Memory
Definition Register Types
There structural register elements: sreg, creg, preg, iareg, isreg, iereg. There mixed registers chip. This means that bits particular register (particular address) structurally same. these registers accessed FPGA system which, turn, accessed block through FPGA logic.
Lattice Semiconductor
ORCA ORT8850 FPSC Eight-Channel Mbits/s Backplane Transceiver
Memory (continued)
Table Structural Register Elements
Element sreg Register Status Register Description
creg
preg
iareg
isreg
ereg
status register read only, and, name implies, used convey status information particular element function ORT8850 core. reset value sreg really reset value particular element function that being read. some cases, sreg really fixed value; example which fixed revision registers. Control control register read writable memory element inside core control. value Register creg will always value written Events inside ORT8850 core cannot affect creg value. only exception soft reset, which case creg will return default value. Pulse Each element, bit, pulse register control event signal that asserted Register then deasserted when value written This means that each always value until written upon which pulsed value then returned value pulse register will always have read value Interrupt Alarm Each interrupt alarm register event latch. When particular event proRegister duced ORT8850 core, occurrence latched associated iareg bit. clear particular iareg bit, value must written ORT8850 core, isreg reset values Interrupt Status Each interrupt status register physically logical-OR function. conRegister solidation lower-level interrupt alarms and/or isreg bits from other registers. direct result fact that each isreg logical-OR function means that will have read value consolidation signals value one, will value only consolidation signals value ORT8850 core, isreg default values Interrupt Enable Each status register alarm register associated enable bit. this Register value one, then event allowed propagate next higher level consolidation. this zero, then associated iareg isreg still asserted alarm will propagate next higher level. interrupt enable interrupt mask when value
Registers Access General Description memory comprises three address blocks:
Generic register block: revision, scratch pad, lock, FIFO alignment, reset registers. Device register block: control status bits, common four channels each quad interfaces. Channel register blocks: each four channels both quads have address block. four address blocks both quads have same structure, with constant address offset between channel register blocks.
registers write-protected lock register, except scratch register. lock register 16-bit read/write register. Write access given registers only when value 0x0580 present lock register. error flag will upon detecting write access when write permission denied. default value 0x0000. After powerup reset soft reset, unused register bits will read zeros. Unused address locations also read zeros. Write-only register bits will read zeros. detailed information register access function described tables, memory map, memory description. memory included Table followed detailed descriptions Table These tables list only memory core registers ORT8850 device. remaining FPGA registers found Series data sheet. Lattice Semiconductor
ORCA ORT8850 FPSC Eight-Channel Mbits/s Backplane Transceiver
Memory (continued)
This table constructed show correct values when read written system interface. When using this table while interfacing with system user logic master interface, data values will need byte flipped. This opposite orientation master interface ordering. More information this found MPI/System Application Note (AP01-032NCIP). Table Memory (This table resides memory offset 0X30000 ORT8850.)
ADDR [7:0] Register Type sreg sreg sreg creg creg creg preg Reset Value [7:0] global reset comman lvds lpbk control (CDR only) device reg. generic register block Comment
fixed [0:7] fixed [0:7] fixed [0:7] scratch [0:7] lockreg [0:7] lockreg [0:7]
Device Register Block creg frame" enable" control prot
creg
creg creg creg
parallel parallel serial serial port parallel parallel serial serial port port port output port port port port output output output output output output output select select select select ch#5 select select select select ch#7 ch#5 ch#7 ch#3 ch#1 ch#3 ch#1 FIFO aligner threshold value (min) [0:4] FIFO aligner threshold value (max) [0:4] scraminput/ line lpbk number consecutive errors bler/ descrambler control output parallel parity control control generate [0:3]
device
creg creg creg
error insert value [0:7] error insert value [0:7] transmitter error insert mask [0:7]
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ORCA ORT8850 FPSC Eight-Channel Mbits/s Backplane Transceiver
Memory (continued)
Table Memory (continued)
ADDR [7:0] Register Type isreg Reset Value [7:0] Comment
device
iereg iareg
top-level interrupts
enable/mask register [0:4] write locked register error flag
frame offset error flag
iereg isreg iereg creg
STM-A mode control
STM-A mode control
enable/mask register [6:7] STM-B mode control STM-B mode control
0x00
enable/mask register [0:3]
creg
creg
Stream resync.
Stream Stream Stream Stream Stream Stream Stream resync resync resync resync resync resync resync Resync resync (all (all streams streams hi-z control parallel output channel enable/ disable control Resync (all streams parallel output parity source select source select Twins Twins Twins Twins resync Resync resync (streams resync (streams (streams (streams
Channel Register Block creg hi-z control data output k1/k2 source select serial output port source select source select disable insert force ais-l control behavior control signals
creg
mode source source operatio select select source select source select source select
source select source select disable A1/A2 insert
source select source select error insert comman
source select source select error comman
control signals
creg
creg
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ORCA ORT8850 FPSC Eight-Channel Mbits/s Backplane Transceiver
Memory (continued)
Table Memory (continued)
ADDR [7:0] Register Type sreg Concat indication Concat indication sts-12 alarm flag Reset Value [7:0] sts#1 flag Comment
Concat indication Concat indication
Concat indication Concat indication elastic store overflow flag
Concat indication Concat indication ais-p flag
sreg
Concat indication
Concat indication
Concat indication
Concat indication
isreg
channel interrupt consolidation
iereg
enable/mask register [0:3]
iareg
FIFO (Out Sync) error flag
serial input port parity error flag
input parallel parity error flag
LVDS link parity error flag
flag
Receiver internal path parity error flag
FIFO* aligner threshold error flag
sts-12 interrupt flags
iereg
enable/mask register [0:5]
FIFO aligner threshold error flag only valid FIFO sync error flag also present.
Lattice Semiconductor
ORCA ORT8850 FPSC Eight-Channel Mbits/s Backplane Transceiver
Memory (continued)
Table Memory (continued)
ADDR [7:0] iereg iareg interrupt flag interrupt flag interrupt flag interrupt flag Register Type iareg interrupt flags interrupt flag enable/ mask interrupt flags enable/ mask interrupt flag overflow flags overflow flag sts-1 interrupt flags Reset Value [7:0] Comments
interrupt flags interrupt flag enable/ mask interrupt flags enable/ mask interrupt flag overflow flags
interrupt flag interrupt flag enable/ mask interrupt flag enable/ mask interrupt flag overflow flag overflow flag
interrupt flags interrupt flag enable/ mask interrupt flags enable/ mask interrupt flag overflow flags overflow flag
iereg
enable/ mask interrupt flag
enable/ mask interrupt flag
enable/ mask interrupt flag
enable/ mask interrupt flag
iareg
iareg
overflow flag
overflow flag
overflow flag
overflow flag
overflow flag
iereg
enable/ enable/ enable/ enable/ mask mask mask mask overflow overflow overflow overflow flags flag flags flags
iereg
enable/ enable/ enable/ enable/ enable/ enable/ enable/ enable/ mask mask mask mask mask mask mask mask overflow overflow overflow overflow overflow overflow overflow overflow flag flag flag flag flag flag flag flag
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ORCA ORT8850 FPSC Eight-Channel Mbits/s Backplane Transceiver
Memory (continued)
Table Memory (continued)
ADDR [7:0]
counter Sampler phase error count
Register Type counter
Reset Value [7:0]
Comments
overflow
LVDS link BIP-8 parity error counter
counter
overflow
counter
binning
counter
overflow
frame error counter
creg
Reserved
FIFO depth register
0x0c
creg
Framer Disable
Sync control
LVDS redundant select
Bypass Alignment FIFO Pointer Mover EN10BIT
Bypass Pointer Mover
Specific Registers creg creg creg RapidIO OPIMODE (shim) (Reserved) Loopback enable MODE BYPASS LOOP BKEN PHASE Shim Mode
ENCOMMA[0:7] OCELLSIZE[3:7]
Pi-Sched Registers
sreg creg
ITESTDO IBYPASS
ITEST PASS OTEST
Lattice Semiconductor
ORCA ORT8850 FPSC Eight-Channel Mbits/s Backplane Transceiver
Memory (continued)
Table Memory Descriptions Bit/Register Name(S)
fixed [0:7] fixed [0:7] fixed [7:0] scratch [0:7] lockreg [0:7] lockreg [0:7]
Bit/ Reset Register Register Value Location Type (Hex) (Hex)
[0:7] [0:7] [0:7] [0:7] [0:7] [0:7] sreg
Description
creg creg
global reset command
preg
scratch function used anywhere core. However, this register written read from. order write registers memory locations 06~7F, lockreg lockreg must respectively values lockreg values {05, 80}, then values written registers memory locations 06~7F will ignored. After reset (both hard soft), core write locked mode. core needs unlocked before written Also note that scratch register (03) always written unaffected write lock mode. global reset command accessed pulse register memory address global reset command soft (software initiated) reset. Nevertheless, global reset command will have exact reset effect hard (RST_N pin) reset.
Device Register Blocks lvds lpbk control
creg
loopback. LVDS loopback, transmit receive Serieal data looped back serial input.
prot
creg
port LVDS Protection Switching controlled software control MUX) Output buffers' enables controlled software control channel) controlled hardware pins.
frame" enable" control
creg
TOH_CK_FP_EN used 3-state RX_TOH_CK_EN RX_TOH_FP signals. Function mode.
Lattice Semiconductor
ORCA ORT8850 FPSC Eight-Channel Mbits/s Backplane Transceiver
Memory (continued)
Table Memory Descriptions (continued) Bit/Register Name(S) Bit/ Register Register Reset Location Type Value (Hex) (Hex) creg [0:4] [0:4] creg These minimum maximum thresholds values channel receive direction alignment FIFOs. when minimum maximum threshold value violated particular channel, then interrupt event "FIFO aligner threshold error" will gener
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