SKEW, 1-TO-15, LVCMOS CLOCK GENERATOR Fully integrated single end

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SKEW, 1-TO-15, LVCMOS CLOCK GENERATOR Fully integrated single end

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ICS87974I
SKEW, 1-TO-15, LVCMOS CLOCK GENERATOR
Fully integrated single ended 3.3V LVCMOS outputs Selectable CLK0 CLK1 inputs redundant clock applications Maximum output frequency: 125MHz range: 200MHz 500MHz External feedback "zero delay" clock regeneration Cycle-to-cycle jitter: ±100ps (typical) Output skew: 350ps (maximum) 3.3V operating supply compatible with MPC974 -40°C 85°C ambient operating temperature
GENERAL DESCRIPTION
ICS87974I skew, jitter 1-to-15 LVCMOS clock generator/zero delay buffer HiPerClockSa member HiPerClockS family high performance clock solutions from ICS. device fully integrated three banks whose divider ratios independently controlled, providing output frequency relationships 1:1, 2:1, 3:1, 3:2, 3:2:1. addition, external feedback connection provides wide selection output-to-input frequency ratios. CLK0 CLK1 pins allow redundant clocking input dynamically switching between clock sources. ICS87974I compatible with MPC974.
Guaranteed jitter output skew characteristics make ICS87974I ideal those applications demanding well defined performance repeatability.
ASSIGNMENT
VCO_SEL VDDOC VDDOC VDDOB
CLK_EN SELB SELC PLL_SEL SELA CLK_SEL CLK0 CLK1 VDDA
VDDOB VDDOB FB_IN VDDOFB
ICS87974I
FB_SEL0 VDDOA FB_SEL1 VDDOA VDDOA
52-Lead LQFP 10mm 10mm 1.4mm package body package View
87974AYI
MARCH 2002
ICS87974I
SKEW, 1-TO-15, LVCMOS CLOCK GENERATOR
BLOCK DIAGRAM
SELA CLK_SEL
(Internal Pulldown) (Internal Pulldown)
CLK0 (Internal Pulldown) CLK1 (Internal Pullup) FB_IN (Internal Pullup) PLL_SEL (Internal Pullup) VCO_SEL (Internal Pulldown) SELB (Internal Pulldown)
QA0:QA4
QB0:QB4
QC0:QC3
SELC (Internal Pulldown)
(Internal Pullup) FB_SEL0 FB_SEL1
(Internal Pulldown)
(Internal Pulldown)
CLK_EN (Internal Pullup)
87974AYI
REV. MARCH 2002
ICS87974I
SKEW, 1-TO-15, LVCMOS CLOCK GENERATOR
Type Power Description Power supply ground. Master reset. When HIGH, outputs enabled. When LOW, outputs disabled dividers reset. LVCMOS LVTTL interface levels. Clock enable. When LOW, outputs except low. Selects divide value Bank output described Table LVCMOS LVTTL interface levels. Selects divide value Bank output described Table LVCMOS LVTTL interface levels. Selects between reference clock input dividers. When HIGH, selects PLL. When LOW, selects reference clock. LVCMOS LVTTL interface levels. Selects divide value Bank output described Table LVCMOS LVTTL interface levels. Clock select input. LVCMOS LVTTL interface levels. Reference clock input. LVCMOS LVTTL interface levels. connect. Positive supply pin. Connect 3.3V. Analog supply pin. Connect 3.3V. Selects divide value Bank feedback output described Pulldown Table LVCMOS LVTTL interface levels. Bank clock outputs. typical output impedance. LVCMOS LVTTL interface levels. Output supply pins. Connect 3.3V. Output supply pin. Connect 3.3V. Clock output. LVCMOS LVTTL interface levels. Feedback input phase detector generating clocks with Pullup "zero delay". Connect LVCMOS LVTTL interface levels. Bank clock outputs. typical output impedance. LVCMOS interface levels. Output supply pins. Connect 3.3V. Bank clock outputs. typical output impedance. LVCMOS interface levels. Output supply pins. Connect 3.3V. Selects when HIGH. Selects when LOW. Pulldown LVCMOS LVTTL interface levels.
TABLE DESCRIPTIONS
Number Name
CLK_EN SELB SELC PLL_SEL SELA CLK_SEL CLK0 CLK1 VDDA FB_SEL0, FB_SEL1 QA4, QA3, QA2, QA1, VDDOA VDDOFB FB_IN
Input Input Input Input Input Input Input Input Input Unused Power Power Input Output Power Power Output Input Output Power Output Power Input
Pullup Pullup Pulldown Pulldown Pullup Pulldown Pulldown Pullup
Pulldown Reference clock input. LVCMOS LVTTL interface levels.
QB4, QB3, QB2, QB1, VDDOB QC3, QC2, QC1, VDDOC VCO_SEL
NOTE: Pullup Pulldown refer internal input resistors. Table Characteristics, typical values.
87974AYI
MARCH 2002
ICS87974I
SKEW, 1-TO-15, LVCMOS CLOCK GENERATOR
Test Conditions Minimum Typical VDD, VDDA, VDDOx 3.465V Maximum Units
TABLE CHARACTERISTICS
Symbol RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor
Input Pulldown Resistor Power Dissipation Capacitance (per output); Note NOTE VDDOx denotes VDDOA, VDDOB, VDDOC, VDDOFB.
TABLE OUTPUT CONTROL FUNCTION TABLE
Inputs CLK_EN QA0:QA4 Enable QB0:QB4 Enable Outputs QC0:QC3 Enable Enable Enable
TABLE OPERATING MODE FUNCTION TABLE
Inputs PLL_SEL Operating Mode Bypass
TABLE INPUT FUNCTION TABLE
Inputs CLK_SEL Input CLK0 CLK1
TABLE SELECT FUNCTION TABLE
SELA SELB SELC
TABLE SELECT FUNCTION TABLE
Inputs FB_SEL0 FB_SEL1 Outputs
TABLE SELECT FUNCTION TABLE
Inputs VCO_SEL fVCO VCO/2 VCO/4
87974AYI
REV. MARCH 2002
ICS87974I
SKEW, 1-TO-15, LVCMOS CLOCK GENERATOR
4.6V -0.5V 0.5V -0.5V VDDO 0.5V 73.2°C/W lfpm) -65°C 150°C
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDDx Inputs, Outputs, Package Thermal Impedance, Storage Temperature, TSTG
Stresses beyond those listed under Absolute Maximum Ratings cause permanent damage device. These ratings stress specifications only. Functional operation product these conditions conditions beyond those listed Characteristics Characteristics implied. Exposure absolute maximum rating conditions extended periods affect product reliability.
TABLE POWER SUPPLY CHARACTERISTICS, VDDA VDDO 3.3V±5%, -40°C 85°C
Symbol VDDA VDDOx IDDA
Parameter Positive Supply Voltage Analog Supply Voltage Output Supply Voltage; NOTE Power Supply Current Analog Supply Current
Test Conditions
Minimum 3.135 3.135 3.135
Typical
Maximum 3.465 3.465 3.465
Units
Output Supply Current; NOTE IDDOx NOTE VDDOx denotes VDDOA, VDDOB, VDDOC, VDDOFB. NOTE IDDOx denotes IDDOA, IDDOB, IDDOC, IDDOFB
TABLE LVCMOS/LVTTL CHARACTERISTICS, VDDA VDDO 3.3V±5%, -40°C 85°C
Symbol
Parameter SELA:SELC, FB_IN, VCO_SEL, PLL_SEL, Input CLK_SEL, CLK_EN, High Voltage FB_SEL0, FB_SEL1, CLK0, CLK1 SELA:SELC, FB_IN, VCO_SEL, PLL_SEL, Input CLK_SEL, CLK_EN, Voltage FB_SEL0, FB_SEL1, CLK0, CLK1 FB_SEL0, FB_SEL1, SELA:SELC, CLK0, Input VCO_SEL, CLK_SEL High Current CLK1, FB_IN, nMR, PLL_SEL, CLK_EN FB_SEL0, FB_SEL1, SELA:SELC, CLK0, Input VCO_SEL, CLK_SEL Current CLK1, FB_IN, nMR, PLL_SEL, CLK_EN Output High Voltage; NOTE Output Voltage; NOTE
Test Conditions
Minimum
Typical
Maximum
Units
3.465V 3.465V 3.465V 3.465V -100
NOTE Outputs terminated with VDDOx/2.
87974AYI
MARCH 2002
ICS87974I
SKEW, 1-TO-15, LVCMOS CLOCK GENERATOR
TABLE CHARACTERISTICS, VDDA VDDO 3.3V±5%, -40°C 85°C
Symbol fMAX fVCO Parameter Output Frequency Lock Range; NOTE SYNC Feedback Propagation Delay; NOTE Output Skew; NOTE Cycle-to-Cycle Jitter NOTE Lock Time Output Rise Time Output Fall Time Output Pulse Width Output Enable Time 0.8V 2.0V 0.8V 2.0V 0.15 0.15 tCycle/2 tCycle/2 Test Conditions PLL_SEL 3.3V, fREF 50MHz Measured rising edge VDDO/2 -250 Minimum Typical Maximum ±100 tCycle/2 Units
tsk(o) tjit(cc)
Output Disable Time tDIS parameters measured fMAX unless noted otherwise. NOTE Measured from VDD/2 point input theVDDOx/2 output. NOTE Defined time difference between input reference clock averaged feedback input signal when locked input reference frequency stable. NOTE Defined skew within bank with equal load conditions. NOTE Defined skew between outputs same supply voltage with equal load conditions. Measured VDDOx/2. NOTE This parameter defined accordance with JEDEC Standard NOTE Measured peak-to-peak.
87974AYI
REV. MARCH 2002
ICS87974I
SKEW, 1-TO-15, LVCMOS CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
1.65V±5%
VDD, VDDA, VDDOx
SCOPE
LVCMOS
-1.65V±5%
3.3V OUTPUT LOAD TEST CIRCUIT
DDOx
DDOx
tsk(o)
OUTPUT SKEW
DDOx
DDOx
DDOx
QAx, QBx, QCx,
tcycle
jit(cc) tcycle -tcycle
Cycle-to-Cycle Jitter
87974AYI
tcycle
MARCH 2002
ICS87974I
SKEW, 1-TO-15, LVCMOS CLOCK GENERATOR
0.8V Clock Inputs Outputs
0.8V
INPUT
OUTPUT RISE
FALL TIME
CLK0, CLK1
DDOx
SYNC
FEEDBACK PROPAGATION DELAY
QAx, QBx, QCx,
DDOx
DDOx
PERIOD
PERIOD
tPERIOD
87974AYI
REV. MARCH 2002
ICS87974I
SKEW, 1-TO-15, LVCMOS CLOCK GENERATOR
POWER SUPPLY FILTERING TECHNIQUES
high speed analog circuitry, power supply pins vulnerable random noise. ICS87974I provides separate power supplies isolate high switching noise from outputs internal PLL. VDD, VDDA, VDDOx should individually connected power supply plane through vias, bypass capacitors should used each pin. achieve optimum jitter performance, power supply isolation required. Figure illustrates resistor along with 10µF .01µF bypass capacitor should connected each VDDA pin.
3.3V .01µF .01µF
FIGURE POWER SUPPLY FILTERING
87974AYI
MARCH 2002
ICS87974I
SKEW, 1-TO-15, LVCMOS CLOCK GENERATOR RELIABILITY INFORMATION
TABLE JAVS. FLOW TABLE
Velocity (Linear Feet Minute)
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 58.0°C/W 42.3°C/W
47.1°C/W 36.4°C/W
42.0°C/W 34.0°C/W
NOTE: Most modern designs multi-layered boards. data second pertains most designs.
TRANSISTOR COUNT
transistor count ICS87974I 4225
87974AYI
REV. MARCH 2002
ICS87974I
SKEW, 1-TO-15, LVCMOS CLOCK GENERATOR
PACKAGE OUTLINE SUFFIX
TABLE PACKAGE DIMENSIONS
JEDEC VARIATION DIMENSIONS MILLIMETERS SYMBOL 0.45 -0.05 1.35 0.22 0.22 MINIMUM NOMINAL -1.40 0.32 0.30 12.00 BASIC 10.00 BASIC 12.00 BASIC 10.00 BASIC 0.65 BASIC -0.10 0.13 1.60 0.15 1.45 0.38 0.33 MAXIMUM
Reference Document: JEDEC Publication MS-026
87974AYI
MARCH 2002
ICS87974I
SKEW, 1-TO-15, LVCMOS CLOCK GENERATOR
Marking ICS87974AYI ICS87974AYI Package Lead LQFP Lead LQFP Tape Reel Count tray Temperature -40°C 85°C -40°C 85°C
TABLE ORDERING INFORMATION
Part/Order Number ICS87974AYI ICS87974AYIT
While information presented herein been checked both accuracy reliability, Integrated Circuit Systems, Incorporated (ICS) assumes responsibility either infringement patents other rights third parties, which would result from use. other circuits, patents, licenses implied. This product intended normal commercial industrial applications. other applications such those requiring high reliability, other extraordinary environmental requirements recommended without additional processing ICS. reserves right change circuitry specifications without notice. does authorize warrant product life support devices critical medical instruments. 87974AYI
REV. MARCH 2002

SKEW, 1-TO-15, LVCMOS CLOCK GENERATOR Fully integrated single end

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