SKEW, CLOCK GENERATOR ICS87949I-147 skew, Clock Generator member
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ICS87949I-147
SKEW, CLOCK GENERATOR
ICS87949I-147 skew, Clock Generator member HiPerClockSHiPerClockSfamily High Performance Clock Solutions from ICS. ICS87949I-147 selectable single ended clock LVPECL clock inputs. single ended clock input accepts LVCMOS LVTTL input levels. PCLK, nPCLK pair accept LVPECL, CML, SSTL input levels. impedance LVCMOS outputs designed drive series parallel terminated transmission lines. effective fanout increased from utilizing ability outputs drive series terminated lines.
FEATURES
single ended LVCMOS outputs, typical output impedance Selectable LVCMOS LVPECL clock inputs CLK0 CLK1 accept following input levels: LVCMOS LVTTL PCLK, nPCLK supports following input types: LVPECL, CML, SSTL Maximum input frequency: 250MHz Output skew: 250ps (maximum) Part-to-part skew: 1.0ns (maximum) 3.3V 2.5V supply voltage -40°C 85°C ambient operating temperature compatible MPC949
divide select inputs, DIV_SELx, control output frequency each bank. outputs utilized combination modes. master reset input, MR/nOE, resets internal frequency dividers also controls active high impedance states outputs. ICS87949I-147 characterized 3.3V 2.5V. Guaranteed output part-to-part skew characteristics make ICS87949I-147 ideal those clock distribution applications demanding well defined performance repeatability.
BLOCK DIAGRAM
CLK_SEL CLK0 CLK1 PCLK nPCLK PCLK_SEL DIV_SELA QB0:QB2 DIV_SELB QC0:QC3 DIV_SELC QD0:QD5 DIV_SELD MR/nOE QA0:QA1
ASSIGNMENT
VDDB VDDA VDDB
MR/nOE CLK_SEL CLK0 CLK1 PCLK nPCLK PCLK_SEL DIV_SELA DIV_SELB DIV_SELC DIV_SELD
VDDC VDDC
ICS87949I-147
VDDD VDDD VDDD
52-Lead LQFP 10mm 10mm 1.4mm package body Package View
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TABLE DESCRIPTIONS
Number Name MR/nOE CLK_SEL CLK0, CLK1 PCLK nPCLK PCLK_SEL DIV_SELA DIV_SELB DIV_SELC DIV_SELD QD0, QD1, QD2, QD3, QD4, VDDD QC3, QC2, QC1, VDDC VDDB QB2, QB1, QA1, VDDA Input Input Power Input Input Input Input Input Input Input Input Power Unused Output Power Output Power Power Output Output Power Type Description Master reset output enable. When HIGH, resets outputs Pulldown tristate. When LOW, enables outputs. LVCMOS LVTTL interface levels. Clock select input. When HIGH, selects CLK1. When LOW, Pulldown selects CLK0. LVCMOS LVTTL interface levels. Positive supply pin. Pullup Pullup Pulldown Pulldown Pulldown Pulldown Pulldown LVCMOS LVTTL clock inputs. Inver ting differential LVPECL clock input. PCLK select input. When HIGH, selects LVPECL clock input. When LOW, selects single ended clock input. LVCMOS LVTTL interface levels. Controls frequency division Bank outputs. LVCMOS LVTTL interface levels. Controls frequency division Bank outputs. LVCMOS LVTTL interface levels. Controls frequency division Bank outputs. LVCMOS LVTTL interface levels. Controls frequency division Bank outputs. LVCMOS LVTTL interface levels. Power supply ground. connect. Bank outputs. LVCMOS LVTTL interface levels. typical output impedance. Positive supply pins Bank outputs. Bank outputs. LVCMOS LVTTL interface levels. typical output impedance. Positive supply pins Bank outputs. Positive supply pins Bank outputs. Bank outputs. LVCMOS LVTTL interface levels. typical output impedance. Bank outputs. LVCMOS LVTTL interface levels. typical output impedance. Positive supply Bank outputs.
Pulldown Non-inver ting differential LVPECL clock input.
NOTE: Pullup Pulldown refer internal input resistors. Table Characteristics, typical values.
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Maximum Units
TABLE CHARACTERISTICS
Symbol RPULLUP RPULLDOWN ROUT Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Power Dissipation Capacitance (per output) Output Impedance 3.47V 2.625V Test Conditions Minimum Typical
TABLE FUNCTION TABLE
MR/nOE DIV_SELA Inputs DIV_SELB DIV_SELC DIV_SELD QA0, fIN/1 fIN/2 Active Active Active Active Active Active Outputs QB0:QB2 QC0:QC3 Active Active Active Active fIN/1 Active fIN/2 Active Active fIN/1 Active fIN/2 Active Active Active Active QD0:QD5 Active Active Active Active Active Active fIN/1 fIN/2
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ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDDx Inputs, Outputs, Package Thermal Impedance, Storage Temperature, TSTG 4.6V -0.5V 0.5V -0.5V 0.5V 42.3°C/W lfpm) -65°C 150°C
Stresses beyond those listed under Absolute Maximum Ratings cause permanent damage device. These ratings stress specifications only. Functional operation product these conditions conditions beyond those listed Characteristics Characteristics implied. Exposure absolute maximum rating conditions extended periods affect product reliability.
TABLE POWER SUPPLY CHARACTERISTICS, 3.3V±5%, -40°C 85°C
Symbol VDDx
Parameter Positive Supply Voltage Output Supply Voltage; NOTE Core Power Supply Current
Test Conditions
Minimum 3.135 3.135
Typical
Maximum 3.465 3.465
Units
Output Power Supply Current; NOTE IDDx NOTE VDDx denotes VDDA, VDDB, VDDC, VDDD. NOTE IDDx denotes IDDA, IDDB, IDDC, IDDD.
TABLE CHARACTERISTICS, 3.3V±5%, -40°C 85°C
Symbol VCMR
Parameter Input High Voltage Input Voltage Peak-to-Peak Input Voltage Common Mode Input Voltage; NOTE DIV_SELA:DIV_SELD, CLK_SEL, PCLK_SEL, Input High MR/nOE Current CLK0, CLK1 DIV_SELA:DIV_SELD, CLK_SEL, PCLK_SEL, Input MR/nOE Current CLK0, CLK1 Output High Voltage
Test Conditions
Minimum -0.3
Typical
Maximum
Units
3.465V 3.465V 3.465V, 3.465V, -20mA -150
Output Voltage 20mA NOTE Common mode voltage defined VIH. NOTE single ended applications, maximum input voltage PCLK nPCLK 0.3V.
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TABLE CHARACTERISTICS, 3.3V±5%, -40°C 85°C
Symbol fMAX
Parameter Input Frequency Propagation Delay; NOTE PCLK, nPCLK CLK0, CLK1
Test Conditions
Minimum
Typical
tsk(o) tsk(pp)
tPZL, tPZH
Output Skew; NOTE t-to-Par Skew; NOTE Output Rise Time Output Fall Time Output Duty Cycle Output Enable Time; NOTE
Measured rising edge VDDx/2 Measured rising edge VDDx/2
tPLZ, tPHZ Output Disable Time; NOTE NOTE Measured from VDD/2 crosspoint input VDDx/2 output. NOTE Defined skew across banks outputs same supply voltages with equal load conditions. Measured VDDx/2. NOTE Defined skew between outputs different devices operating same supply voltages, same temperature, with equal load conditions. Using same type inputs each device, outputs measured VDDx/2. NOTE These parameters guaranteed characterization. tested production. NOTE This parameter defined accordance with JEDEC Standard
TABLE POWER SUPPLY CHARACTERISTICS, 2.5V±5%, -40°C 85°C
Symbol VDDx
Parameter Positive Supply Voltage Output Supply Voltage; NOTE Core Power Supply Current
Test Conditions
Minimum 2.375 2.375
Typical
Maximum 2.625 2.625
Units
Output Power Supply Current; NOTE IDDx NOTE VDDx denotes VDDA, VDDB, VDDC, VDDD. NOTE IDDx denotes IDDA, IDDB, IDDC, IDDD.
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Maximum Units
TABLE CHARACTERISTICS, 2.5V±5%, -40°C 85°C
Symbol VCMR
Parameter Input High Voltage Input Voltage Peak-to-Peak Input Voltage Common Mode Input Voltage; NOTE DIV_SELA:DIV_SELD, CLK_SEL, PCLK_SEL, Input High MR/nOE Current CLK0, CLK1 DIV_SELA:DIV_SELD, CLK_SEL, PCLK_SEL, Input MR/nOE Current CLK0, CLK1 Output High Voltage
Test Conditions
Minimum -0.3
Typical
3.465V 3.465V 3.465V, 3.465V, -20mA -150
Output Voltage 20mA NOTE Common mode voltage defined VIH. NOTE single ended applications, maximum input voltage PCLK nPCLK 0.3V.
TABLE CHARACTERISTICS, 2.5V±5%, -40°C 85°C
Symbol fMAX
Parameter Input Frequency Propagation Delay; NOTE Output Skew; NOTE t-to-Par Skew; NOTE Output Rise Time Output Fall Time Output Duty Cycle Output Enable Time; NOTE
Test Conditions
Minimum
Typical
Maximum
Units
tsk(o) tsk(pp)
tPZL, tPZH
Measured rising edge VDDx/2 Measured rising edge VDDx/2
tPLZ, tPHZ Output Disable Time; NOTE NOTE Measured from VDD/2 crosspoint input VDDx/2 output. NOTE Defined skew across banks outputs same supply voltages with equal load conditions. Measured VDDx/2. NOTE Defined skew between outputs different devices operating same supply voltages, same temperature, with equal load conditions. Using same type inputs each device, outputs measured VDDx/2. NOTE These parameters guaranteed characterization. tested production. NOTE This parameter defined accordance with JEDEC Standard
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PARAMETER MEASUREMENT INFORMATION
1.65V±5%
VDDx
SCOPE
LVCMOS
-1.65V±5%
3.3V OUTPUT LOAD TEST CIRCUIT
1.25V±5%
VDDx
SCOPE
LVCMOS
-1.25V±5%
2.5V OUTPUT LOAD TEST CIRCUIT
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nPCLK PCLK
Cross Points
DIFFERENTIAL INPUT LEVEL
tsk(o)
OUTPUT SKEW
PART
PART
tsk(pp)
PART-TO-PART SKEW
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Clock Inputs Outputs
INPUT
OUTPUT RISE
FALL TIME
CLK0, CLK1
nPCLK PCLK
QAx, QBx, QCx,
QAx, QBx, QCx,
87949AYI-147
PROPAGATION DELAY
Pulse Width
PERIOD
PERIOD
tPERIOD
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RELIABILITY INFORMATION
TABLE JAVS. FLOW TABLE
Velocity (Linear Feet Minute)
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 58.0°C/W 42.3°C/W
47.1°C/W 36.4°C/W
42.0°C/W 34.0°C/W
NOTE: Most modern designs multi-layered boards. data second pertains most designs.
TRANSISTOR COUNT
transistor count ICS87949I-147 1545
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PACKAGE OUTLINE SUFFIX
TABLE PACKAGE DIMENSIONS
JEDEC VARIATION DIMENSIONS MILLIMETERS SYMBOL 0.45 -0.05 1.35 0.22 0.22 MINIMUM NOMINAL -1.40 0.32 0.30 12.00 BASIC 10.00 BASIC 12.00 BASIC 10.00 BASIC 0.65 BASIC -0.10 0.13 1.60 0.15 1.45 0.38 0.33 MAXIMUM
Reference Document: JEDEC Publication MS-026
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Temperature -40°C 85°C -40°C 85°C
TABLE ORDERING INFORMATION
Part/Order Number ICS87949AYI-147 ICS87949AYI-147T Marking 7949AI147 7949AI147 Package Lead LQFP Lead LQFP Tape Reel Count tray
While information presented herein been checked both accuracy reliability, Integrated Circuit Systems, Incorporated (ICS) assumes responsibility either infringement patents other rights third parties, which would result from use. other circuits, patents, licenses implied. This product intended normal commercial industrial applications. other applications such those requiring high reliability, other extraordinary environmental requirements recommended without additional processing ICS. reserves right change circuitry specifications without notice. does authorize warrant product life support devices critical medical instruments. 87949AYI-147
REV. 2002
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