VREF VREF LC2MOS High Speed 8-Channel 8-Bit ADCs AD7824/AD7828

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VREF VREF LC2MOS High Speed 8-Channel 8-Bit ADCs AD7824/AD7828

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FEATURES 8-Analog Input Channels Built-In Track/Hold Function Signal Handling Each Channel Fast Microprocessor Interface Single Supply Power: Fast Conversion Rate, s/Channel Tight Error Specification:
VREF VREF
LC2MOS High Speed 8-Channel 8-Bit ADCs AD7824/AD7828
FUNCTIONAL BLOCK DIAGRAM
4-BIT FLASH (4MSB) 4-BIT VREF 4-BIT FLASH (4LSB) TIMING CONTROL CIRCUITRY THREE STATE DRIVERS
MUX*
ADDRESS LATCH DECODE A2** *AD7824 4-CHANNEL **AD7828 8-CHANNEL AD7828 ONLY
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
AD7824 AD7828 high-speed, multichannel, 8-bit ADCs with choice (AD7824) (AD7828) multiplexed analog inputs. half-flash conversion technique gives fast conversion rate channel parts have builtin track/hold function capable digitizing full-scale signals (157 mV/µs slew rate) channels. AD7824 AD7828 operate from single supply have analog input range using external reference. Microprocessor interfacing parts simple, using standard Chip Select (CS) Read (RD) signals initiate conversion read data from three-state data outputs. half-flash conversion technique means that there need generate clock signal ADC. AD7824 AD7828 interfaced easily most popular microprocessors. AD7824 AD7828 fabricated advanced, ion-implanted, linear-compatible CMOS process (LC2MOS) have power dissipation (typ). AD7824 available 0.3" wide, 24-lead "skinny" DIP, while AD7828 available 0.6" wide, 28-lead 28terminal surface mount packages.
8-channel input multiplexer gives cost-effective spacesaving multichannel system. Fast conversion rate µs/channel features channel sampling frequency AD7824 AD7828. Built-in track-hold function allows handling 8channels bandwidth (157 mV/µs slew rate). Tight total unadjusted error spec channel-to-channel matching eliminate need user trims. Single supply simplifies system power requirements. Fast, easy-to-use digital interface allows connection most popular microprocessors with minimal external components. clock signal required ADC.
REV.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices. Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Site: http://www.analog.com Fax: 781/326-8703 Analog Devices, Inc., 2000
AD7824/AD7828-SPECIFICATIONS (Vapply 5forV,Mode(+) noted. specifications unless otherwise noted. Specifications
REF(-)
unless otherwise
Parameter ACCURACY Resolution Total Unadjusted Error2 Minimum Resolution which Missing Codes Guaranteed Channel-to-Channel Mismatch REFERENCE INPUT Input Resistance VREF(+) Input Voltage Range VREF(-) Input Voltage Range ANALOG INPUT Input Voltage Range Input Leakage Current Input Capacitance3 LOGIC INPUTS VINH VINL IINH IINL Input Capacitance3 LOGIC OUTPUTS DB0-DB7 IOUT (DB0-DB7) Output Capacitance3 VOL4 IOUT Output Capacitance SLEW RATE, TRACKING3 POWER SUPPLY IDD5 Power Dissipation Power Supply Sensitivity
NOTES Temperature ranges follows:
Version1 Version Versions 1.0/4.0 VREF(-)/ GND/ VREF(+) VREF(-)/ VREF(+) 1.0/4.0 VREF(-)/ GND/ VREF(+) VREF(-)/ VREF(+) 1.0/4.0 VREF(-)/ GND/ VREF(+) VREF(-)/ VREF(+)
Versions Unit 1.0/4.0 VREF(-)/ GND/ VREF(+) VREF(- VREF(+) Bits Bits min/k min/V min/V
Conditions/Comments
min/V Analog Input Channel
Typically
0.157
0.157
0.157
0.157
V/µs V/µs Volts
ISOURCE ISINK Floating State Leakage Typically ISINK Floating State Leakage Typically
Specified Performance 1/16
Versions; 70°C Versions; -40°C +85°C Versions; -55°C +125°C Total Unadjusted Error includes offset, full-scale linearity errors. Sample tested 25°C Product Assurance ensure compliance. open drain output. Typical Performance Characteristics. Specifications subject change without notice.
REV.
AD7824/AD7828 TIMING CHARACTERISTICS1
Parameter tCSS tCSH tRDY2 tCRD tACC13 tACC23 tlNTH2 tDH4 Limit (All Grades)
VREF(+) VREF(-) unless otherwise noted)
Limit TMIN, TMAX Grades)
Limit TMIN, TMAX Grades)
Unit
Conditions/Comments Setup Time Hold Time Multiplexer Address Setup Time Multiplexer Address Hold Time Delay. Pull-Up Resistor Conversion Time, Mode Data Access Time after Data Access Time after INT, Mode Delay Data Hold Time Delay Time between Conversions Read Pulsewidth, Mode
NOTES Sample tested 25°C ensure compliance. input control signals specified with timed from voltage level Measured with load circuits Figure defined time required output cross Defined time required data lines change when loaded with circuits Figure Specifications subject change without notice.
Test Circuits
Figure Load Circuits Data Access Time Test
Figure Load Circuits Data Hold Time Test
REV.
AD7824/AD7828
ABSOLUTE MAXIMUM RATINGS*
25°C unless otherwise noted)
Digital Input Voltage (RD, -0.3 Digital Output Voltage (DB0, DB7, INT) -0.3 VREF VREF (-), VREF VREF Analog Input (Any Channel) -0.3
Operating Temperature Range Commercial Versions) 70°C Industrial Versions) -25°C +85°C Extended Versions) -55°C +125°C Storage Temperature Range -65°C +150°C Lead Temperature (Soldering, secs) 300°C Power Dissipation (Any Package) 75°C Derates above 75°C mW/°C
*Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only; functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
CAUTION (electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although these devices feature proprietary protection circuitry, permanent damage occur devices subjected high-energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality. CONFIGURATIONS DIP/SOIC/SSOP
WARNING!
SENSITIVE DEVICE
LCCC
ORDERING GUIDE
Model AD7824KN AD7824LN AD7824KR AD7824BQ AD7824CQ AD7824TQ* AD7824UQ* AD7828KN AD7828LN AD7828KP AD7828LP AD7828BQ AD7828CQ AD7828BR AD7828BRS AD7828TQ* AD7828UQ* AD7828TE* AD7828UE*
Temperature Range 70°C 70°C 70°C -40°C +85°C -40°C +85°C -55°C +125°C -55°C +125°C 70°C 70°C 70°C 70°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -55°C +125°C -55°C +125°C -55°C +125°C -55°C +125°C
Total Unadjusted Package Error (LSBs) Option N-24 N-24 R-24 Q-24 Q-24 Q-24 Q-24 N-28 N-28 P-28A P-28A Q-28 Q-28 R-28 RS-28 Q-28 Q-28 E-28A E-28A
PLCC
*Available /883B processing only. Contact local sales office military data sheet. U.S. Standard Military Drawing (SMD) DESC Drawing #5692-88764.
REV.
Typical Performance Characteristics-AD7824/AD7828
Conversion Time Temperature
Power Supply Current Temperature (Not Including Reference Ladder)
Accuracy VREF [VREF VREF(+) VREF(-)]
Accuracy
Signal-Noise Ratio Input Frequency
Output Current Temperature
REV.
AD7824/AD7828
OPERATIONAL DIAGRAM
APPLYING AD7824/AD7828
REFERENCE INPUT
AD7824 4-channel 8-bit converter AD7828 8-channel 8-bit converter. Operational diagrams both these devices shown Figures addition just reference allows devices perform analog-to-digital function.
reference inputs AD7824/AD7828 fully differential define zero full-scale input range converter. result, span analog input voltage channels easily varied. reducing reference span, VREF VREF (-), less than sensitivity converter increased (e.g., VREF then mV). input/reference arrangement also facilitates ratiometric operation. This reference flexibility also allows input channel voltage span offset from zero. voltage VREF sets input level channels which produces digital output zeroes. Therefore, although analog inputs themselves differential, they have nearly differential-input capability most measurement applications because reference design. Figures show some configurations that possible.
Figure AD7824 Operational Diagram
Figure Power Supply Reference
Figure AD7828 Operational Diagram
Figure External Reference Using AD580, Full-Scale Input
CIRCUIT INFORMATION
BASIC DESCRIPTION
AD7824/AD7828 uses half-flash conversion technique whereby 4-bit flash converters used achieve 8-bit result. Each 4-bit flash contains comparators which compare unknown input reference ladder 4-bit result. full 8-bit reading realized, upper 4-bit flash, most significant (MS) flash, performs conversion provide most significant data bits. internal DAC, driven MSBs, then recreates analog approximation input voltage. This analog result subtracted from input, difference converted lower flash ADC, least significant (LS) flash, provide least significant bits output data.
Figure Input Referenced
REV.
AD7824/AD7828
INPUT CURRENT INHERENT SAMPLE-HOLD
novel conversion techniques employed AD7824/ AD7828, analog input behaves somewhat differently than conventional devices. ADC's sampled-data comparators take varying amounts input current depending which cycle conversion equivalent input circuit AD7824/AD7828 shown Figure When conversion starts going low), input switches close, selected input channel connected most significant least significant comparators. Therefore, analog input connected thirty-one input capacitors same time.
major benefit AD7824's AD7828's analog input structure ability measure variety high-speed signals without help external sample-and-hold. conventional type converter, regardless speed, input must remain stable least throughout conversion process rated accuracy maintained. Consequently, many high-speed signals, this signal must externally sampled held stationary during conversion. AD7824/AD7828 input comparators, nature their input switching inherently accomplish this sample-and-hold function. Although conversion time AD7824/AD7828 time which selected analog input must stable much smaller. AD7824/AD7828 tracks selected input channel approximately after conversion start. value analog input that instant from conversion start) measured value. This value then used least significant flash generate lower 4-bits data.
SINUSOIDAL INPUTS
Figure AD7824/AD7828 Equivalent Input Circuit
AD7824/AD7828 measure input signals with slew rates high mV/µs rated specifications. This means that analog input frequency without external sample hold. Furthermore, AD7828 measure eight signals without sample hold. Nyquist criterion requires that sampling rate twice input frequency (i.e., kHz). This requires ideal antialiasing filter with infinite roll-off. ease problem antialiasing filter design, sampling rate usually much greater than Nyquist criterion. maximum sampling rate (FMAX) AD7824/AD7828 calculated follows: FMAX FMAX 0.5E
input capacitors must charge input voltage through resistance analog switches (about addition, about input stray capacitance must charged. analog input channel modelled network shown Figure increases, takes longer input capacitance charge.
tCRD AD7824/AD7828 Conversion Time Minimum Delay Between Conversion This permits maximum sampling rate each channels when using AD7828 each channels when using AD7824.
Figure Network Model
time which input comparators track analog input approximately start conversion. Because input transients analog inputs, recommended that source impedance greater than ohms connected analog inputs. output impedance equal open loop output impedance divided loop gain frequency interest. important that amplifier driving AD7824/AD7828 analog inputs have sufficient loop gain input signal frequency make output impedance low. Suitable amps driving AD7824/AD7828 AD544 AD644.
REV.
AD7824/AD7828
UNIPOLAR OPERATION
analog input range channel AD7824/ AD7828 shown unipolar operational diagram Figure Figure shows designed code transitions which occur midway between successive integer values (i.e., LSB, LSB, LSB, LSBs). output code Natural Binary with FS/256 (5/256) 19.5
Figure AD7824/AD7828 Bipolar Operation
Figure AD7824/AD7828 Unipolar Operation
Figure Ideal Input/Output Transfer Characteristic Operation
TIMING CONTROL
Figure Ideal Input/Output Transfer Characteristic Unipolar Operation
BIPOLAR OPERATION
circuit Figure designed bipolar operation. AD544 op-amp conditions signal input (VIN) that only positive voltages appear closed loop transfer function resistor values shown given below: (2.5 0.625 VIN) Volts analog input range size 31.25 output code complementary offset binary. ideal input/output characteristic shown Figure
AD7824/AD7828 digital inputs timing control. These Chip Select (CS) Read (RD). READ operation brings which starts conversion channel selected multiplexer address inputs (see Table There modes operation outlined timing diagrams Figures Mode designed microprocessors which driven into WAIT state. READ operation (i.e., taken low) starts conversion data read when conversion complete. Mode does require microprocessor WAIT states. READ operation initiates conversion reads previous conversion results.
Table Truth Table Input Channel Selection
AD7824
AD7828
Channel
REV.
AD7824/AD7828
MODE MODE
Figure shows timing diagram Mode operation. This mode only used microprocessors which have WAIT state facility, whereby READ instruction cycle extended accommodate slow memory devices. READ operation brings which starts conversion. analog multiplexer address inputs must remain valid while low. data (DB7-DB0) remains three-state condition until conversion complete. There converter status outputs AD7824/AD7828, interrupt (INT) ready (RDY) which used drive microprocessor READY/ WAIT input. open drain output internal pull-up device) which goes falling edge goes high impedance conversion, when 8-bit conversion result appears data outputs. status required, then external pull-up resistor omitted output tied GND. goes when conversion complete returns high rising edge
Mode operation designed applications where microprocessor forced into WAIT state. READ operation takes which triggers conversion (see Figure 15). multiplexer address inputs latched rising edge Data from previous conversion read from three-state data outputs (DB7-DB0). This data disregarded required. Note, output (open drain output) does provide status information this mode must connected GND. conversion goes low. second READ operation required access conversion result. This READ operation latches address into multiplexer inputs starts another conversion. returns high second READ operation, when returns high. delay must allowed between READ operations.
Figure Mode Timing Diagram
Figure Mode Timing Diagram
REV.
AD7824/AD7828
MICROPROCESSOR INTERFACING MC68000 MICROPROCESSOR
AD7824/AD7828 designed interface microprocessors Read Only Memory (ROM). Analog channel selection, conversion start data read operations controlled channel address inputs. These signals common memory peripheral devices.
MICROPROCESSOR
Figure shows MC68000 interface. AD7824/AD7828 operating Mode Assume again assigned memory block starting address C000. MOVE instruction addresses Table starts conversion reads conversion result. $C000,D0 Once conversion begun, MC68000 inserts WAIT states, until goes asserting DTACK conversion. microprocessor then places conversion results register.
Figure shows typical AD7824/AD7828-Z80 interface. AD7824/AD7828 operating Mode Assume assigned memory block starting address C000. following LOAD instruction addresses listed Table will start conversion selected channel read conversion result. (C000) beginning instruction cycle when address selected, asserts WAIT input, that forced into WAIT state. conversion returns high conversion result placed register microprocessor.
Figure AD7824/AD7828-MC68000 Interface
TMS32010 MICROCOMPUTER
TMS32010 interface shown Figure AD7824/ AD7828 operating Mode (i.e., WAIT states). mapped port address. following instruction starts conversion reads previous conversion result into accumulator.
Figure AD7824/AD7828-Z80 lnterface
Table Address Channel Selection
PORT ADDRESS) port address (000 111) selects analog channel converted. When conversion complete second instruction (IN, reads up-to-date data into accumulator starts another conversion. delay must allowed between conversions.
Address C000 C001 C002 C003 C004 C005 C006 C007
AD7824 Channel
AD7828 Channel
Figure AD7824/AD7828-TMS32010 Interface
-10-
REV.
AD7824/AD7828
BANDPASS FILTER BANDPASS FILTER SPEECH INPUT BANDPASS FILTER BANDPASS FILTER VREF VREF
VREF VOUT VOUT VOUT VOUT DGND AGND SAMPLE PULSE +15V +10V
AD7828
DATA
AD7226
AD7824
VREF VREF
Figure Speech Analysis Using Real-Time Filtering
Figure 4-Channel Fast Infinite Sample-and-Hold
OUTLINE DIMENSIONS
Dimensions shown inches (mm).
24-Lead Plastic (N-24)
1.228 (31.19) 1.226 (31.14)
24-Lead Small Outline Package (R-24)
0.6141 (15.60) 0.5985 (15.20)
0.260 (6.61
0.001 0.03)
0.32 (8.128) 0.30 (7.62)
0.130 (3.30) 0.128 (3.25)
0.2992 (7.60) 0.2914 (7.40) 0.4193 (10.65) 0.3937 (10.00)
0.011 (0.28) 0.02 (0.5) 0.11 (2.79) 0.07 (1.78) 0.009 (0.23) 0.05 (1.27) 0.016 (0.41) 0.09 (2.28) LEAD IDENTIFIED NOTCH PLASTIC LEADS WILL EITHER SOLDER DIPPED TIN/LEAD PLATED ACCORDANCE WITH MIL-M-38510 REQUIREMENTS
SEATING PLANE
0.1043 (2.65) 0.0926 (2.35)
0.0291 (0.74) 0.0098 (0.25)
0.0118 (0.30) 0.0500 0.0040 (0.10) (1.27)
0.0192 (0.49) SEATING 0.0125 (0.32) PLANE 0.0138 (0.35) 0.0091 (0.23)
0.0500 (1.27) 0.0157 (0.40)
24-Lead Cerdip (Q-24)1
1.290 (32.77)
28-Lead Plastic (N-28)
1.45 (36.83) 1.44 (36.58)
0.295 (7.493)
0.320 (8.128) 0.290 (7.366)
0.070 (1.778) 0.180 0.225 0.020 (0.508) (4.572) (5.715) 0.125 (3.175) SEATING PLANE 0.012 (0.305) 0.021 (0.533) 0.110 (2.794) 0.065 (1.651) 0.008 (0.203) 0.015 (0.381) 0.090 (2.286) 0.055 (1.397) LEAD IDENTIFIED NOTCH CERDIP LEADS WILL EITHER TIN/LEAD PLATED SOLDER DIPPED ACCORDANCE WITH MIL-M-38510 REQUIREMENTS
0.55 (13.97) 0.53 (13.47)
(5.08) 0.175 (4.45) 0.12 (3.05)
0.16 (4.07) 0.15 (3.56)
0.606 (15.4) 0.594 (15.09)
0.065 (1.66) 0.02 (0.508) 0.105 (2.67) 0.045 (1.15) 0.015 (0.381) 0.095 (2.42)
SEATING PLANE
0.012 (0.305) 0.008 (0.203)
LEAD IDENTIFIED NOTCH PLASTIC LEADS WILL EITHER SOLDER DIPPED TIN/LEAD PLATED ACCORDANCE WITH MIL-M-38510 REQUIREMENTS
NOTE Analog Devices reserves right ship either cerdip (Q-24, Q-28) ceramic (D-24A, D-28) hermetic packages.
REV.
-11-
AD7824/AD7828
OUTLINE DIMENSIONS
Dimensions shown inches (mm).
28-Lead Cerdip (Q-28)1
1.490 (37.84)
28-Lead Shrink Small Outline Package (RS-28)
0.407 (10.34) 0.397 (10.08)
0.525 (13.33) 0.515 (13.08)
GLASS SEALANT 0.22 (5.59) 0.125 (3.175) 0.02 (0.5) 0.06 (1.52) SEATING 0.016 (0.406) 0.05 (1.27) PLANE
0.18 (4.57)
0.311 (7.9) 0.301 (7.64)
0.11 (2.79) 0.099 (2.28)
0.012 (0.305) 0.008 (0.203)
LEAD IDENTIFIED NOTCH CERDIP LEADS WILL EITHER PLATED SOLDER DIPPED ACCORDANCE WITH MIL-M-38510 REQUIREMENTS
0.078 (1.98) 0.068 (1.73)
0.07 (1.79) 0.066 (1.67)
0.212 (5.38) 0.205 (5.21)
0.62 (15.74) 0.59 (14.93)
0.008 (0.203) 0.0256 (0.65) 0.002 (0.050)
0.015 (0.38) SEATING 0.009 (0.229) 0.010 (0.25) PLANE 0.005 (0.127)
0.03 (0.762) 0.022 (0.558)
28-Lead Small Outline Package (R-28)
0.7125 (18.10) 0.6969 (17.70)
28-Terminal LCCC (E-28A)
0.100 (2.54)1 0.064 (1.63) 0.055 (1.40) 0.045 (1.14)
0.075 (1.91)
0.2992 (7.60) 0.2914 (7.40)
0.4193 (10.65) 0.3937 (10.00)
0.458 (11.63)2 0.442 (11.23)
0.050 (1.27
0.005 0.13)
BOTTOM VIEW
0.028 (0.71) 0.022 (0.56) INDEX
0.1043 (2.65) 0.0926 (2.35)
0.0291 (0.74) 0.0098 (0.25)
0.020 (0.51 THIS DIMENSION CONTROLS OVERALL PACKAGE THICKNESS APPLIES FOUR SIDES TERMINALS GOLD PLATED
0.040 (1.02 PLCS
0.0118 (0.30) 0.0040 (0.10)
0.0500 (1.27)
0.0192 (0.49) SEATING 0.0125 (0.32) 0.0138 (0.35) PLANE 0.0091 (0.23)
0.0500 (1.27) 0.0157 (0.40)
28-Leaded PLCC (P-28A)
0.495 (12.57) 0.485 (12.32)
IDENTIFIER
0.180 (4.51) 0.165 (4.20)
0.021 (0.533) 0.013 (0.331) 0.032 (0.812) 0.026 (0.661)
VIEW
(PINS DOWN)
0.456 (11.582) 0.450 (11.430)
0.120 (3.04) 0.090 (2.29)
NOTE Analog Devices reserves right ship either cerdip (Q-24, Q-28) ceramic D-24A, D-28) hermetic packages.
-12-
REV.
PRINTED U.S.A.
0.050 (1.27
0.005) 0.13)
0.430 (10.5) 0.390 (9.9)
C01323c-0-8/00 (rev.

VREF VREF LC2MOS High Speed 8-Channel 8-Bit ADCs AD7824/AD7828

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