Megabit (131,072 8-Bit) CMOS Volt-only, Sector Erase Flash Memory

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Megabit (131,072 8-Bit) CMOS Volt-only, Sector Erase Flash Memory

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Am29F010
Megabit (131,072 8-Bit) CMOS Volt-only, Sector Erase Flash Memory
DISTINCTIVE CHARACTERISTICS
read write operations Minimizes system level power requirements Compatible with JEDEC-standards Pinout software compatible with single-power-supply Flash Superior inadvertent write protection 32-pin PLCC 32-pin TSOP 32-pin PDIP Minimum 100,000 write/erase cycles guaranteed High performance maximum access time Sector erase architecture Uniform sectors Kbytes each combination sectors erased. Also supports full chip erase Sector protection Hardware method that disables combination sector(s) from write erase operations Embedded EraseAlgorithms Automatically preprograms erases chip sector Embedded ProgramAlgorithms Automatically programs verifies data specified address Data Polling Toggle feature detection program erase cycle completion power consumption maximum active read current maximum program/erase current Enhanced power management standby mode typical standby current
V-only Flash
GENERAL DESCRIPTION
Am29F010 Mbit, Volt-only Flash memory organized Kbytes bits each. Mbit data divided into sectors Kbytes flexible erase capability. bits data will appear DQ0- DQ7. Am29F010 offered 32-pin packages which allows upgrades Mbit densities same out. This device designed programmed in-system with standard system Volt supply. 12.0 Volt required program erase operations. device also reprogrammed standard EPROM programmers. standard Am29F010 offers access times between allowing operation high-speed microprocessors without wait states. eliminate contention device separate chip enable (CE), write enable (WE), output enable (OE) controls. Am29F010 entirely command compatible with JEDEC single-power-supply Flash standard. Commands written command register using standard microprocessor write timings. Register contents serve input internal state-machine which controls erase programming circuitry. Write cycles also internally latch addresses data needed programming erase operations. Reading data device similar reading from 12.0 Volt Flash EPROM devices. Am29F010 programmed executing program command sequence. This will invoke Embedded Program Algorithm which internal algorithm that automatically times program pulse widths verifies proper cell margin. Erase accomplished executing erase command sequence. This will invoke Embedded Erase Algorithm which internal algorithm that automatically preprograms array already programmed before executing erase operation. During erase, device automatically times erase pulse widths verifies proper cell margin. This device also features sector erase architecture. This allows sectors memory erased reprogrammed without affecting data contents
Publication# 16736 Rev: Amendment/+1 Issue Date: April 1997
other sectors. sector typically erased verified within second. Am29F010 erased when shipped from factory. Am29F010 device also features hardware sector protection. This feature will disable both program erase operations combination eight sectors memory. device features single Volt power supply operation both read write functions. Internally generated regulated voltages provided program erase operations. detector automatically inhibits write operations during power transitions. program erase detected Data Polling Toggle (DQ6). Once program erase cycle been completed, device automatically resets read mode. Flash memory manufacturing experience produce highest levels quality, reliability cost effectiveness. Am29F010 memory electrically erases bits within sector simultaneously Fowler-Nordheim tunneling. bytes programmed byte time
using EPROM programming mechanism electron injection.
Flexible Sector-Erase Architecture
Eight Kbyte sectors Individual-sector multiple-sector erase capability Sector protection user definable
Kbyte Kbyte Kbyte Kbyte Kbyte Kbyte Kbyte Kbyte
1FFFFh 1BFFFh 17FFFh 13FFFh 0FFFFh 0BFFFh 07FFFh 03FFFh 00000h
16736F-1
Am29F010
PRODUCT SELECTOR GUIDE
Family Part Ordering Part Access Time (ns) Access (ns) Access (ns) (J,E,F) -120 Am29F010
BLOCK DIAGRAM
V-only Flash
DQ0-DQ7
Erase Voltage Switch
Input/Output Buffers
State Control Command Register Voltage Switch Chip Enable Output Enable Logic Data Latch
Embedded Algorithms Detector Timer Address Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
A0-A16
16736F-2
Am29F010
CONNECTION DIAGRAMS PDIP
PLCC
16736F-3
16736F-4
TSOP
16736F-5
29F010 Standard Pinout
29F010 Reverse Pinout
16736F-6
Am29F010
CONFIGURATION
A0-A16 DQ0-DQ7 Addresses Chip Enable Data Inputs/Outputs Connected Internally Output Enable +5.0 Volt Single-Power Supply (±10% -55, -70, -90, -120) (±5% -45) Device Ground
LOGIC SYMBOL
A0-A16 DQ0-DQ7
V-only Flash
Write Enable
16736F-7
Am29F010
ORDERING INFORMATION Standard Products
standard products available several packages operating ranges. order number (Valid Combination) formed combination
AM29F010
OPTIONAL PROCESSING Blank Standard Processing Burn-In VOLTAGE TOLERANCE TEMPERATURE RANGE Commercial (0°C +70°C) Industrial (-40°C +85°C) Extended (-55°C +125°C) PACKAGE TYPE 32-Pin Plastic 032) 32-Pin Rectangular Plastic Leaded Chip Carrier 032) 32-Pin Thin Small Outline Package (TSOP) Standard Pinout 032) 32-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR032) SPEED OPTION Product Selector Guide Valid Combinations
DEVICE NUMBER/DESCRIPTION Am29F010 Megabit (128K 8-Bit) CMOS Flash Memory Volt-only Program Erase
Valid Combinations AM29F010-45 AM29F010-55 AM29F010-55 ±10% AM29F010-70 AM29F010-90 AM29F010-120 PC5, PC5B, PI5, PI5B JCB, JIB, ECB, EIB, FCB, PCB, PIB, PEB, JCB, JIB, JEB, ECB, EIB, EEB, FCB, FIB,
Valid Combinations Valid Combinations list configurations planned supported volume this device. Consult local sales office confirm availability specific valid combinations check newly released combinations.
Am29F010
Am29F010 User Operations
Operation Autoselect, Manuf. Code Autoselect Device Code Read Standby Output Disable Write Verify Sector Protect DQ0-DQ7 Code Code DOUT HIGH HIGH Code
V-only Flash
Legend: logic logic Don't Care. Characteristics voltage levels. Notes: Manufacturer device codes also accessed command register write sequence. Refer Table Refer section Sector Protection.
Read Mode
Am29F010 control functions which must satisfied order obtain data outputs. power control should used device selection. output control should used gate data output pins device selected. Address access time (tACC) equal delay from stable addresses valid output data. chip enable access time (tCE) delay from stable addresses stable valid data output pins. output enable access time delay from falling edge valid data output pins (assuming addresses have been stable least tACC-tOE time).
type. This mode intended programming equipment purpose automatically matching device programmed with corresponding programming algorithm. This mode functional over entire temperature range device. activate this mode, programming equipment must force (11.5 12.5 address A9.Two identifier bytes then sequenced from device outputs toggling address from VIH. addresses don't cares except (see Table manufacturer device codes also read command register, instances when Am29F010 erased programmed system without access high voltage pin. command sequence illustrated Table (see Autoselect Command Sequence). Byte VIL) represents manufacturer's code (AMD 01H) byte VIH) device identifier code Am29F010 20H. These bytes given table below. identifiers manufacturer device will exhibit parity with defined parity bit. order read proper device codes when executing Autoselect, must (see Table autoselect mode also facilitates determination sector protection system. performing read operation address location XX02H with higher order address bits A14, A15, desired sector address, device will return protected sector non-protected sector.
Standby Mode
There ways implement standby mode Am29F010 device, both using pin. CMOS standby mode achieved with held Under this condition current typically reduced less than standby mode achieved with held VIH. Under this condition current typically reduced standby mode outputs high impedance state, independent input.
Output Disable
With input logic high level (VIH), output from device disabled. This will cause output pins high impedance state.
Autoselect
autoselect mode allows reading binary code from device will identify manufacturer
Am29F010
Table
Type Manufacturer Code Am29F010 Device Sector Protection
Am29F010 Sector Protection Verify Autoselect Codes
Code (HEX) 01H*
Sector Address
*Outputs protected sector addresses
Write
Device erasure programming accomplished command register. contents register serve inputs internal state machine. state machine outputs dictate function device. command register itself does occupy addressable memory location. register latch used store commands, along with address data information needed execute command. command register written bringing VIL, while VIH. Addresses latched falling edge whichever happens later; while data latched rising edge Standard microprocessor write timings used. Refer Write Characteristics Erase/ Programming Waveforms specific timing parameters.
Table
Sector Address Table
Address Range 00000h-03FFFh 04000h-07FFFh 08000h-0BFFFh 0C000h-0FFFFh 10000h-13FFFh 14000h-17FFFh 18000h-1BFFFh 1C000h-1FFFFh
Sector Protection
Am29F010 features hardware sector protection. erase operations combination eight sectors memory. sector protect feature enabled using programming equipment user's site. device shipped with sectors unprotected. Alternatively, program protect sectors factory prior shipping device (AMD's ExpressFlashService).
possible determine sector protected system writing Autoselect command. Performing read operation address location XX02H, where higher order address bits A14, A15, desired sector address, will produce logical protected sector. Table Autoselect codes.
Command Definitions
Device operations selected writing specific address data sequences into command register. Writing incorrect address data values writing them improper sequence will reset device read mode. Table defines valid register command sequences.
Am29F010
Table
Write Cycles Req'd First Write Cycle Addr Data
Am29F010 Command Definitions
Third Write Cycle Addr 5555H 5555H Data Fourth Read/Write Cycle Addr XX00H/ XX01H 5555H 5555H Data 01H/20H 2AAAH 2AAAH 5555H Fifth Write Cycle Addr Data Sixth Write Cycle Addr Data
Second Write Cycle Addr Data
Command Sequence Reset/Read Autoselect Byte Program Chip Erase Sector Erase
5555H 2AAAH 5555H 2AAAH 5555H 2AAAH 5555H 2AAAH 5555H 2AAAH
5555H 5555H 5555H
V-only Flash
Notes: operations defined Table Address memory location read. Address memory location programmed. Addresses latched falling edge pulse. Address sector erased. combination A16, A15, will uniquely select sector. Data read from location during read operation. Data programmed location Data latched rising edge Address Don't Care. Address Don't Care address commands except Program Address (PA) Sector Address (SA).
Read/Reset Command
read reset operation initiated writing read/reset command sequence into command register. Microprocessor read cycles retrieve array data from memory. device remains enabled reads until command register contents altered. device will automatically power-up read/ reset state. this case, command sequence required read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that spurious alteration memory content occurs during power transition. Refer Read Characteristics Waveforms specific timing parameters.
read cycle from address XX01H returns device code (see Table manufacturer device codes will exhibit parity with defined parity bit. Furthermore, write protect status sectors read this mode. Scanning sector addresses (A14, A15, A16) while (A1, will produce logical device output protected sector. terminate operation, necessary write read/reset command sequence into register.
Byte Programming
device programmed byte-by-byte basis. Programming four cycle operation. There "unlock" write cycles. These followed program set-up command data write cycles. Addresses latched falling edge whichever happens later data latched rising edge whichever happens first. rising edge (whichever happens first) begins programming using Embedded Program Algorithm. Upon executing algorithm, system required provide further controls timings. device will automatically provide adequate internally generated program pulses verify programmed cell margin. automatic programming operation completed when data (also used Data Polling) equivalent data written this which time device returns read mode addresses longer latched (See Table Write Operation Status).
Autoselect Command
Flash memories intended applications where local alter memory contents. such, manufacture device codes must accessible while device resides target system. PROM programmers typically access signature codes raising high voltage. However, multiplexing high voltage onto address lines generally desirable system design practice. device contains autoselect command operation supplement traditional PROM programming methodology. operation initiated writing autoselect command sequence into command register. Following command write, read cycle from address XX00H retrieves manufacturer code 01H.
Am29F010
Therefore, device requires that valid address device supplied system this particular instance time Data Polling operations. Data Polling must performed memory location which being programmed. commands written chip during Embedded Program Algorithm will ignored. Programming allowed sequence across sector boundaries. Beware that data cannot programmed back "1". Attempting cause device exceed programming time limits (DQ5 result apparent success, according data polling algorithm, read from reset/read mode will show that data still "0". Only erase operations convert "0"s "1"s. Figure illustrates Embedded Programming Algorithm using typical command strings operations.
(30H) latched rising edge After timeout from rising edge last sector erase command, sector erase operation will begin. Multiple sectors erased concurrently writing cycle operations described above. This sequence followed with writes Sector Erase command addresses other sectors desired concurrently erased. time between writes must less than otherwise that command will accepted erasure will start. recommended that processor interrupts disabled during this time guarantee this condition. interrupts re-enabled after last Sector Erase command written. time-out from rising edge last will initiate execution Sector Erase command(s). another falling edge occurs within time-out window timer reset. (Monitor determine sector erase timer window still open, section DQ3, Sector Erase Timer.) command other than Sector Erase during this period will reset device read mode, ignoring previous command string. that case, restart erase those sectors allow them complete. (Refer Write Operation Status Section DQ3, Sector Erase Timer operation). Loading sector erase buffer done sequence with number sectors used, multiple sectors should erased groups ensure that group sectors exposed same number program/erase cycles. addition, chip erase command should used device that uses sector erase multiple sector erase commands. Sector erase does require user program device prior erase. device automatically programs memory locations sector(s) erased prior electrical erase. When erasing sector sectors remaining unselected sectors affected. system required provide controls timings during these operations. automatic sector erase begins after time from rising edge pulse last sector erase command pulse terminates when data DQ7, Data Polling, (see Write Operation Status section) which time device returns read mode. Data Polling must performed address within sectors being erased. Figure illustrates Embedded Erase Algorithm using typical command strings operations.
Chip Erase
Chip erase cycle operation. There "unlock" write cycles. These followed writing "set-up" command. more "unlock" write cycles then followed chip erase command. chip erase command should used devices that sector erase commands. Likewise, sector erase commands should used devices that chip erase command. Chip erase does require user program device prior erase. Upon executing Embedded Erase Algorithm command sequence device will automatically program verify entire memory zero data pattern prior electrical erase. erase performed concurrently sectors same time (see Table "Erase Programming Performance" erase times). system required provide controls timings during these operations. automatic erase begins rising edge last pulse command sequence terminates when data (see Write Operation Status section) which time device returns read mode. Figure illustrates Embedded Erase Algorithm using typical command strings operations.
Sector Erase
Sector erase cycle operation. There "unlock" write cycles. These followed writing "set-up" command. more "unlock" write cycles then followed sector erase command. sector address (any address location within desired sector) latched falling edge while command
Am29F010
WRITE OPERATION STATUS
Table
Status Byte Program Embedded Program Algorithm Progress Embedded Erase Algorithm Exceeded Time Limits Byte Program Embedded Program Algorithm Program/Erase Embedded Erase Algorithm Toggle Toggle Toggle
Write Operation Status
Toggle DQ2-DQ0 Reserved future Reserved future
Notes: Performing successive read operations from address will cause toggle.
Data Polling Am29F010 device features Data Polling method indicate host that embedded algorithms progress completed. During Embedded Program Algorithm, attempt read device will produce complement data last written DQ7. Upon completion Embedded Program Algorithm, attempt read device will produce true data last written DQ7. During Embedded Erase Algorithm, attempt read device will produce output. Upon completion Embedded Erase Algorithm attempt read device will produce output. flowchart Data Polling (DQ7) shown Figure chip erase, Data Polling valid after rising edge sixth pulse write pulse sequence. sector erase, Data Polling valid after last rising edge sector erase pulse. Data Polling must performed sector addresses within sectors being erased sector that protected. Otherwise, status valid. Just prior completion Embedded Algorithm operations change asynchronously while output enable (OE) asserted low. This means that device driving status infor mation instant time then that byte's valid data next instant time. Depending when system samples output, read status valid data. Even device completed Embedded Algorithm operations valid data, data outputs DQ0-DQ6 still invalid. valid data DQ0-DQ7 read successive read attempts. Data Polling feature only active during Embedded Programming Algorithm, Embedded Erase Algorithm sector erase time-out (see Table Figure Data Polling timing specifications diagrams.
Toggle Am29F010 also features "Toggle Bit" method indicate host system that embedded algorithms progress completed. During Embedded Program Erase Algorithm cycle, successive attempts read toggling) data from device address will result toggling between zero. Once Embedded Program Erase Algorithm cycle completed, will stop toggling valid data will read next successive attempt. During programming, Toggle valid after rising edge fourth pulse four write pulse sequence. chip erase, Toggle valid after rising edge sixth pulse write pulse sequence. Sector erase, Toggle valid after last rising edge sector erase pulse. Toggle active during sector erase time-out. Either toggling will cause toggle. Figure Toggle timing specifications diagrams.
V-only Flash
Exceeded Timing Limits will indicate program erase time exceeded specified limits (internal pulse count). Under these conditions will produce "1". This failure condition which indicates that program erase cycle successfully completed. Data Polling only operating function device under this condition. circuit will partially power down device under these conditions approximately mA). pins will control output disable functions described Table failure condition will also appear user tries program location that previously programmed this case device locks never completes Embedded Program Algorithm. Hence, system never reads valid data never stops toggling. Once device exceeded timing limits, will indicate
Am29F010
"1." Please note that this device failure condition since device incorrectly used. this occurs, reset device.
control register architecture, alteration memory contents only occurs after successful completion specific multi-bus cycle command sequences. device also incorporates several features prevent inadvertent write cycles resulting from power-up power-down transitions system noise.
Sector Erase Timer After completion initial sector erase command sequence sector erase time-out will begin. will remain until time-out complete. Data Polling Toggle valid after initial sector erase command sequence. Data Polling Toggle indicates device been written with valid erase command, used determine sector erase timer window still open. high ("1") internally controlled erase cycle begun; attempts write subsequent commands device will ignored until erase operation completed indicated Data Polling Toggle Bit. ("0"), device will accept additional sector erase commands. insure command been accepted, system software should check status prior following each subsequent sector erase command. were high second status check, command have been accepted. Refer Table Write Operation Status.
Write Inhibit
avoid initiation write cycle during power-up power-down, Am29F010 locks write cycles VLKO (see Characteristics section voltages). When VLKO, command register disabled, internal program/erase circuits disabled, device resets read mode. Am29F010 ignores writes until VLKO. user must ensure that control pins correct logic state when VLKO prevent unintentional writes.
Write Pulse "Glitch" Protection
Noise pulses less than (typical) will initiate write cycle.
Logical Inhibit
Writing inhibited holding VIL,CE VIH, VIH. initiate write cycle must logical zero while logical one.
Data Protection
Am29F010 designed offer protection against accidental erasure programming caused spurious system level signals that exist during power transitions. During power device automatically resets internal state machine Read mode. Also, with
Power-Up Write Inhibit
Power-up device with will accept commands rising edge internal state machine automatically reset read mode power-up.
Am29F010
EMBEDDED ALGORITHMS
Start
Write Program Command Sequence (see below)
Data Poll Device
Increment Address
V-only Flash
Last Address
Programming Completed Program Command Sequence (Address/Command):
5555H/AAH
2AAAH/55H
5555H/A0H
Program Address/Program Data
16736F-8
Figure
Embedded Programming Algorithm
Am29F010
EMBEDDED ALGORITHMS
Start Write Erase Command Sequence (see below) Data Polling Toggle Successfully Completed
Erasure Completed
Chip Erase Command Sequence (Address/Command):
Individual Sector/Multiple Sector Erase Command Sequence (Address/Command): 5555H/AAH
5555H/AAH
2AAAH/55H
2AAAH/55H
5555H/80H
5555H/80H
5555H/AAH
5555H/AAH
2AAAH/55H
2AAAH/55H
5555H/10H
Sector Address/30H
Sector Address/30H Additional sector erase commands optional Sector Address/30H
16736F-9
Note: ensure command been accepted, system software should check status prior following each subsequent sector erase command. were high second status check, command have been accepted.
Figure
Embedded Erase Algorithm
Am29F010
Start
Read Byte (DQ0-DQ7) Addr
Byte address programming sector addresses within sector being erased during sector erase operation XXXXH during chip erase
Data
V-only Flash
Read Byte (DQ0-DQ7) Addr
Data Fail
Pass
16736F-10
Note: rechecked even because change simultaneously with DQ5.
Figure
Data Polling Algorithm
Am29F010
Start
Read Byte (DQ0-DQ7) Addr Don't Care
Toggle Read Byte (DQ0-DQ7) Addr Don't Care
Toggle Fail
Pass
16736F-11
Note: rechecked even because stop toggling same time changing "1".
Figure
Toggle Algorithm
+0.8 -0.5 -2.0
16736F-12
Figure
Maximum Negative Overshoot Waveform
16736F-13
Figure
Maximum Positive Overshoot Waveform
Am29F010
ABSOLUTE MAXIMUM RATINGS
Storage Temperature Plastic Packages -65°C +125°C Ambient Temperature with Power Applied. .-55°C 125°C Voltage with Respect Ground pins except (Note -2.0 +7.0 (Note -2.0 +7.0 (Note -2.0 +14.0 Output Short Circuit Current (Note
Notes: Minimum voltage input pins -0.5 During voltage transitions, inputs overshoot -2.0 periods Maximum voltage input pins During voltage transitions, input pins overshoot periods 20ns. Minimum input voltage -0.5 During voltage transitions, overshoot -2.0 periods Maximum input voltage +12.5 which overshoot 14.0 periods more than output shorted ground time. Duration short circuit should greater than second. Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only; functional operation device these other conditions above those indicated operational sections this specification implied. Exposure device absolute maximum rating conditions extended periods affect device reliability.
OPERATING RANGES
Commercial Devices Ambient Temperature (TA). .0°C +70°C Industrial Devices Ambient Temperature (TA). .-40°C +85°C Extended Devices Ambient Temperature (TA). .-55°C +125°C Supply Voltages Am29F010-45, +4.75 +5.25 Am29F010-55 -4.50 +5.50
Operating ranges define those limits between which functionality device guaranteed.
V-only Flash
Am29F010
CHARACTERISTICS TTL/NMOS Compatible
Parameter Symbol ILIT ICC1 ICC2 ICC3 VLKO Parameter Description Input Load Current Input Load Current Output Leakage Current Active Current (Note Active Current (Notes Standby Current Input Voltage Input High Voltage Voltage Autoselect Sector Unprotect Output Voltage Output High Voltage Lock-Out Voltage -2.5 Test Conditions VCC, Max, 12.5 VOUT VCC, VIL, VIL, Max, -0.5 11.5 ±1.0 ±1.0 12.5 0.45 Unit
Notes: current listed includes both operating current frequency dependent component MHz). frequency component typically less than mA/MHz, with VIH. active while Embedded Program Erase Algorithm progress. 100% tested.
Am29F010
CHARACTERISTICS (continued) CMOS Compatible
Parameter Symbol ILIT ICC1 ICC2 ICC3 VOH1 VOH2 VLKO Lock-Out Voltage Parameter Description Input Load Current Input Load Current Output Leakage Current Active Current (Note Active Current (Notes Standby Current Input Voltage Input High Voltage Voltage Autoselect Temporary Sector Unprotect Output Voltage Output Voltage -2.5 -100 0.85 Test Conditions VCC, Max, 12.5 VOUT VCC, VIL, VIL, Max, -0.5 11.5 ±1.0 ±1.0 12.5 0.45 Unit
V-only Flash
Notes: current listed includes both operating current frequency dependent component MHz). frequency component typically less than mA/MHz, with VIH. active while Embedded Program Erase Algorithm progress. 100% tested.
Am29F010
CHARACTERISTICS Read Only Operations Characteristics
Parameter Symbols JEDEC Standard tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tACC Description Read Cycle Time (Note Address Output Delay Chip Enable Output Delay Output Enable Output Delay Chip Enable Output High (Notes Output Enable Output High (Notes Output Hold Time From Addresses, Whichever Occurs First Test Setup -120 (Note (Note (Note (Note (Note
Unit
tAXQX
Notes: Test Conditions: Output Load: gate Input rise fall times: Input pulse levels: Timing measurement reference level Input: Output:
Test Conditions: Output Load: gate Input rise fall times: Input pulse levels: 0.45 Timing measurement reference level Input: Output:
Output driver disable time. 100% tested.
IN3064 Equivalent
Device Under Test
Diodes IN3064 Equivalent
Notes: -45: including capacitance others: including capacitance
16736F-14
Figure
Test Conditions
Am29F010
CHARACTERISTICS Write/Erase/Program Operations
Parameter Symbols JEDEC Standard Description tAVAV tAVWL tWLAX tDVWH tWHDX tOEH Write Cycle Time (Note Address Setup Time Address Hold Time Data Setup Time Data Hold Time Read (Note Output Enable Toggle Data Polling Hold Time (Note Read Recover Time Before Write High Low) Setup Time Hold Time Write Pulse Width Write Pulse Width High Byte Programming Operation Sector Erase Operation (Note Setup Time (Note Voltage Transition Time (Note Setup Time Active (Note -120 Unit
V-only Flash
tGHWL tELWL tWHEH tWLWH tWHWL tWHWH1 tWHWH2
tGHWL tWPH tWHWH1 tWHWH2 tVCS tVLHT tOESP
Notes: This does include preprogramming time. 100% tested.
Am29F010
SWITCHING WAVEFORMS
WAVEFORM INPUTS Must Steady Change from Change from Don't Care, Change Permitted Does Apply OUTPUTS Will Steady Will Changing from Will Changing from Changing, State Unknown Center Line HighImpedance "Off" State KS000010
SWITCHING WAVEFORMS
Addresses tACC Addresses Stable
tOEH (tDF)
(tCE) (tOH) High High
Outputs
Output Valid
16736F-15
Figure
Waveforms Read Operations
Am29F010
SWITCHING WAVEFORMS
Cycle Addresses 5555H tGHWL tWPH Data
16736F-16
Data Polling
tWHWH1
V-only Flash
DOUT
Notes: address memory location programmed. data programmed byte address. output complement data written device. DOUT output data written device. Figure indicates last cycles four cycle sequence.
Figure
Addresses 5555H
Program Operation Timings
2AAAH
5555H
5555H
2AAAH
tGHWL tWPH Data tVCS 10H/30H
16736F-17
Note: sector address Sector Erase. Addresses don't care Chip Erase.
Figure
Waveforms Chip/Sector Erase Operations
Am29F010
SWITCHING WAVEFORMS
tOEH
Valid Data High
tWHWH DQ0-DQ6 DQ0-DQ6 Invalid DQ0-DQ6 Valid Data
16736F-18
*DQ7=Valid Data (The device completed Embedded operation).
Figure
Waveforms Data Polling During Embedded Algorithm Operations
tOEH
Data (DQ0-DQ7) Toggle oggle
16736F-19
Stop Toggling
DQ0-DQ7 Valid
*DQ6 stops toggling (The device completed Embedded operation).
Figure
Waveforms Toggle During Embedded Algorithm Operations
Am29F010
CHARACTERISTICS Write/Erase/Program Operations
Alternate Controlled Writes
Parameter Symbols JEDEC Standard Description tAVAV tAVEL tELAX tDVEH tEHDX tOES tOEH tGHEL tWLEL tEHWH tELEH tEHEL tWHWH1 tWHWH2 tGHEL tCPH tWHWH1 tWHWH2 Write Cycle Time (Note Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time (Note -120 Unit
V-only Flash
Output Enable Read (Note Hold Time Toggle Data Polling (Note Read Recover Time Before Write Setup Time Hold Time Write Pulse Width Write Pulse Width High Byte Programming Operation Sector Erase Operation (Note
Notes: This does include preprogramming time. 100% tested.
Am29F010
Data Polling Addresses 5555H tGHEL Data
16736F-20
tWHWH1
tCPH DOUT
address memory location programmed. data programmed byte address. output complement data written device. DOUT output data written device. Figure indicates last cycles four cycle sequence.
Figure
Alternate Controlled Program Operation Timings
Am29F010
ERASE PROGRAMMING PERFORMANCE
Limits Parameter Chip/Sector Erase Time Byte Programming Time Chip Programming Time (Note (Note 1000 (Note 12.5 (Notes Unit Comments Excludes programming prior erasure Excludes system-level overhead (Note Excludes system-level overhead (Note
Notes: 25°C, VCC, 100,000 cycles. Although Embedded Algorithms allow longer chip program erase time, actual time will considerably less since bytes program erase significantly faster than worst case byte. Under worst case condition 90°C, VCC, 100,000 cycles. System-level overhead defined time required execute four cycle command necessary program each byte. preprogramming step Embedded Erase algorithm, bytes programmed before erasure. Embedded Algorithms allow byte program time. only after byte takes theoretical maximum time program. minimal number bytes require significantly more programming pulses than typical byte. majority bytes will program within pulses. This demonstrated Typical Maximum Programming Times listed above. 100,000 program/erase cycles guaranteed; 1,000,000 program/erase cycles typical.
V-only Flash
LATCHUP CHARACTERISTICS
Input Voltage with respect pins except pins (Including Input Voltage with respect pins Current Includes pins except VCC. Test conditions: time. -1.0 -1.0 -100 13.5 +100
TSOP CAPACITANCE
Parameter Symbol COUT CIN2 Parameter Description Input Capacitance Output Capacitance Control Capacitance Test Setup VOUT Unit
Notes: Sampled, 100% tested. Test conditions 25°C, MHz.
Am29F010
PLCC CAPACITANCE
Parameter Symbol COUT CIN2 Parameter Description Input Capacitance Output Capacitance Control Capacitance Test Setup VOUT Unit
Notes: Sampled, 100% tested. Test conditions 25°C, MHz.
PDIP CAPACITANCE
Parameter Symbol COUT CIN2 Parameter Description Input Capacitance Output Capacitance Control Capacitance Test Setup VOUT Unit
Notes: Sampled, 100% tested. Test conditions 25°C, MHz.
DATA RETENTION
Parameter Minimum Pattern Data Retention Time 125°C Years Test Conditions 150°C Unit Years
Am29F010
REVISION SUMMARY
Product Selector Guide: There supply operating ranges available speed option. PDIP package only available operating range. other packages available ±10% operating range. Ordering Information: speed grade also available configuration (PDIP package, commercial temperature.) Operating Ranges:
Characteristics:
Write/Erase/Program Operations: Corrected indicate tVLHT, tOESP, tWHWH1, tWHWH2 typical values, minimum values. Changed value tWHWH2.
Characteristics:
Write/Erase/Program Operations, Alternate Controlled Writes: Corrected indicate WHWH1 tWHWH2 typical values, minimum values. Changed value tWHWH2.
Erase Programming Performance: Combined chip sector erase specifications; changed typical maximum values. Added Note
Supply Voltages: Changed reflect available speed options.
V-only Flash
Am29F010

Megabit (131,072 8-Bit) CMOS Volt-only, Sector Erase Flash Memory

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