October 1987 Revised March 2002 CD4001BC/CD4011BC Quad 2-Input Bu

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

October 1987 Revised March 2002 CD4001BC/CD4011BC Quad 2-Input Bu

Datasheet Thumbnail

Top Searches for this datasheet

CD4001BC/CD4011BC Quad 2-Input Buffered Series Gate Quad 2-Input NAND Buffered Series Gate
October 1987 Revised March 2002
CD4001BC/CD4011BC Quad 2-Input Buffered Series Gate Quad 2-Input NAND Buffered Series Gate
CD4001BC CD4011BC quad gates monolithic complementary (CMOS) integrated circuits constructed with P-channel enhancement mode transistors. They have equal source sink current capabilities conform standard series output drive. devices also have buffered outputs which improve transfer characteristics providing very high gain. inputs protected against static discharge with diodes VSS.
Features
power TTL: driving compatibility: 5V-10V-15V parametric ratings Symmetrical output characteristics Maximum input leakage over full temperature range driving 74LS
Ordering Code:
Order Number CD4001BCM CD4001BCSJ CD4001BCN CD4011BCM CD4011BCN Package Number M14A M14D N14A M14A N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 14-Lead Small Outline Package (SOP), EIAJ TYPE 5.3mm Wide 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available Tape Reel. Specify appending suffix letter ordering code.
Connection Diagrams
Assignments DIP, SOIC CD4001BC Assignments SOIC CD4011BC
View
View
2002 Fairchild Semiconductor Corporation
DS005939
www.fairchildsemi.com
CD4001BC/CD4011BC
Schematic Diagrams
CD4001BC
device shown
J=A+B Logical HIGH Logical inputs protected standard CMOS protection circuit.
CD4011BC
device shown
Logical HIGH Logical inputs protected standard CMOS protection circuit.
www.fairchildsemi.com
CD4001BC/CD4011BC
Absolute Maximum Ratings(Note
(Note Voltage Power Dissipation (PD) Dual-In-Line Small Outline Range Storage Temperature (TS) Lead Temperature (TL) (Soldering, seconds) 260°C (Note
Recommended Operating Conditions
Operating Range (VDD) Operating Temperature Range CD4001BC, CD4011BC
-0.5V +0.5V
-55°C +125°C
-0.5 -65°C +150°C
Note "Absolute Maximum Ratings" those values beyond which safety device cannot guaranteed. Except "Operating Temperature Range" they meant imply that devices should operated these limits. Electrical Characteristics tables provide conditions actual device operation. Note voltages measured with respect unless otherwise specified.
Electrical Characteristics
Symbol Parameter Quiescent Device Current Level Output Voltage HIGH Level Output Voltage Level Input Voltage HIGH Level Input Voltage Level Output Current (Note HIGH Level Output Current (Note Input Current Conditions
-55°C 0.25 0.05 0.05 0.05 4.95 4.95 9.95 14.95 11.0 0.64 -0.64 -1.6 -4.2 -0.10 11.0 0.51 -0.51 -1.3 -3.4
+25°C 0.004 0.005 0.006 0.88 2.25 -0.88 -2.25 -8.8 -10-5 10-5 -0.10 0.10 0.25 0.50 0.05 0.05 0.05
+125°C 0.05 0.05 0.05 4.95 9.95 14.95 11.0 0.36 -0.36 -0.9 -2.4 -1.0
Units
10V, 15V, 4.5V 10V, 9.0V 15V, 13.5V 0.5V 10V, 1.0V 15V, 1.5V 0.4V 10V, 0.5V 15V, 1.5V 4.6V 10V, 9.5V 15V, 13.5V 15V, 15V, |IO| 9.95 14.95 |IO|
Note tested output time.
Electrical Characteristics
Symbol tPHL Parameter Propagation Delay Time, HIGH-to-LOW Level tPLH Propagation Delay Time, LOW-to-HIGH Level tTHL, tTLH Transition Time
(Note
Conditions Units
CD4001BC: 25°C, Input 200k. Typical temperature coefficient 0.3%/°C.
Average Input Capacitance Power Dissipation Capacity
Input Gate
Note Parameters guaranteed correlated testing.
www.fairchildsemi.com
CD4001BC/CD4011BC
Electrical Characteristics
Symbol tPHL Parameter Propagation Delay, HIGH-to-LOW Level tPLH Propagation Delay, LOW-to-HIGH Level tTHL, tTLH Transition Time
(Note
Conditions Units
CD4011BC: 25°C, Input 200k. Typical Temperature Coefficient 0.3%/°C. Average Input Capacitance Power Dissipation Capacity Input Gate
Note Parameters guaranteed correlated testing.
Typical Performance Characteristics
Typical Transfer Characteristics Typical Transfer Characteristics
Typical Transfer Characteristics
www.fairchildsemi.com
CD4001BC/CD4011BC
Typical Performance Characteristics Typical Transfer Characteristics
(Continued)
www.fairchildsemi.com
CD4001BC/CD4011BC
Typical Performance Characteristics
(Continued)
www.fairchildsemi.com
CD4001BC/CD4011BC
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M14A
www.fairchildsemi.com
CD4001BC/CD4011BC
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Small Outline Package (SOP), EIAJ TYPE 5.3mm Wide Package Number M14D
www.fairchildsemi.com
CD4001BC/CD4011BC Quad 2-Input Buffered Series Gate Quad 2-Input NAND Buffered Series Gate
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N14A
Fairchild does assume responsibility circuitry described, circuit patent licenses implied Fairchild reserves right time without notice change said circuitry specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS AUTHORIZED CRITICAL COMPONENTS LIFE SUPPORT DEVICES SYSTEMS WITHOUT EXPRESS WRITTEN APPROVAL PRESIDENT FAIRCHILD SEMICONDUCTOR CORPORATION. used herein: Life support devices systems devices systems which, intended surgical implant into body, support sustain life, whose failure perform when properly used accordance with instructions provided labeling, reasonably expected result significant injury user. critical component component life support device system whose failure perform reasonably expected cause failure life support device system, affect safety effectiveness. www.fairchildsemi.com
www.fairchildsemi.com

October 1987 Revised March 2002 CD4001BC/CD4011BC Quad 2-Input Bu

Top Searches for this datasheet

Other recent searches