RadHard Schmitt CMOS 16-bit Bidirectional MultiPurpose Voltage Transce

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RadHard Schmitt CMOS 16-bit Bidirectional MultiPurpose Voltage Transce

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UT54ACS162245S
RadHard Schmitt CMOS 16-bit Bidirectional MultiPurpose Voltage Transceiver Advanced Datasheet
April 2002
FEATURES Voltage translation 3.3V 2.5V 2.5V 3.3V Cold sparing pins 0.25µ Commercial RadHard CMOS Total dose: 300Krad(Si) 1Mrad(Si) Single Event Latchup immune High speed, power consumption Schmitt trigger inputs filter noisy signals Cold Warm Spare outputs Available processes Standard Microcircuit Drawing Package: 48-lead flatpack, pitch (.390 .640) DESCRIPTION 16-bit wide UT54ACS162245S MultiPurpose voltage transceiver built using Aeroflex UTMC's Commercial RadHard LOGIC SYMBOL
(48) (25) DIR1 2EN1 (BA) 2EN2 (AB) 1EN1 (BA) 1EN2 (AB) (24) DIR2
Direction Control Inputs
(47) (46) (44)
(43) (41) (40) (38) (37) (36) (35) (33) (32) (30) (29) (27) (26)
(11) (12) (13) (14) (16) (17) (19) (20)
epitaxial CMOS technology ideal space applications. This high speed, power UT54ACS162245S voltage transceiver designed perform multiple functions including: asynchronous two-way communication, Schmitt input buffering, voltage translation, warm cold sparing. With equal zero volts, UT54ACS162245S outputs inputs present minimum impedance making ideal "cold spare" applications. Balanced outputs "on" output impedance make UT54ACS162245S well suited driving high capacitance loads impedance backplanes. UT54ACS162245S enables system designers interface volt CMOS compatible components with volt CMOS components. voltage translation, port interfaces with volt bus; port interfaces with volt bus. direction control (DIRx) controls direction data flow. output enable (OEx) overrides direction control disables both ports. These signals driven from either port direction output enable controls operate these devices either independent 8-bit transceivers 16-bit transceiver.
(22) (23)
DESCRIPTION
Names DIRx Description Output Enable Input (Active Low)
Side Inputs 3-State Outputs (2.5V Port) Side Inputs 3-State Outputs (3.3V Port)
PINOUTS
POWER TABLE
Port Volts Volts Port Volts Volts Volts OPERATION Voltage Translator Translating Translating
48-Lead Flatpack View
DIR1 VDD1 VDD1 DIR2 VDD2 VDD2
Volts
When volts, either volts CMOS logic levels applied control inputs. proper operation connect power ground pins (i.e., floating input pins). unused inputs Always insure during operation part. FUNCTION TABLE
ENABLE DIRECTION DIRx OPERATION Data Data Isolation
COLD/WARM SPARE FUNCTION
device will place outputs into high-impedance state either supply taken zero volts warm spare), both supplies zero volts cold spare). DEVICE POWER FUNCTION device will place outputs into high-impedance during power-up. high impedance state maintained time period approximately equal rise time
LOGIC DIAGRAM
DIR1
(48)
DIR2
(24) (25)
(47)
(36) (13)
(46)
(35) (14)
(44)
(33) (16)
PORT
2.5V PORT
2.5V PORT
(41) (40) (38) (11) (37) (12)
(17) (30)
(29) (27) (26)
(19)
(20)
(22)
(23)
PORT
(43)
(32)
RADIATION HARDNESS SPECIFICATIONS PARAMETER Total Dose Latchup Neutron Fluence (Note
LIMIT 1.0E5 >120 1.0E14
UNITS rad(Si) MeV-cm2 n/cm
Notes: Logic will latchup during radiation exposure within limits defined table. tested, inherent CMOS technology.
ABSOLUTE MAXIMUM RATINGS SYMBOL (Note TSTG (Note PARAMETER Voltage Supply voltage Supply voltage Storage Temperature range Maximum junction temperature LIMIT (Mil only) -0.3 -0.3 UNITS °C/W
Thermal resistance junction case input current
Maximum power dissipation
Maximum junction temperature increased +175 during burn-in life test.
DUAL SUPPLY OPERATING CONDITIONS SYMBOL
PARAMETER Supply voltage Supply voltage
Note: Stresses outside listed absolute maximum ratings cause permanent damage device. This stress rating only, functional operation device these other conditions beyond limits indicated operational sections recommended. Exposure absolute maxim rating conditions extended periods affect device reliability performance Cold Spare mode =VSS, 2=VSS), -0.3V maximum recomended operating level VDD1 +0.3V.
+150 LIMIT
+150
UNITS
VDD1
Input voltage Temperature range
ELECTRICAL CHARACTERISTICS -55°C +125°C) SYMBOL PARAMETER
CONDITION from from from from from
.7VDD
UNIT
Schmitt Trigger, positive going threshold2 Schmitt Trigger, negative going threshold2 Schmitt Trigger range hysteresis9 Schmitt Trigger range hysteresis9 Input leakage current
Three-state output leakage current9
from
Cold sparing input leakage current 3,11
VDD2 VDD2 Short-circuit output current
Warm sparing input leakage current11
VDD,
-200
from Short-circuit output current
-100
IOL=
from
Low-level output voltage9
IOL= 100µA IOL= IOL= 100µA -8mA
Low-level output voltage9
VOH1
High-level output voltage9
VOH2
-100µA -8mA -100µA
High-level output voltage9
total1
Power dissipation
50pF from
total2
Power dissipation
50pF from
Standby Supply Current 25oC
Pre-Rad
OE=V OE=V OE=V 1MHz from
Pre-Rad +125 Post-Rad 25oC Input capacitance
COUT
Output capacitance8
1MHz
Notes: specifications valid radiation dose rad(Si) MIL-STD-883, Method 1019. Functional tests conducted accordance with MIL-STD-883 with following input test conditions: (min) 20%, (max) 50%, specified herein, TTL, CMOS, Schmitt compatible inputs. Devices tested using input voltage within above specified range, guaranteed VIH(min) VIL(max). combinations DIRx Guaranteed characterization. more than output shorted time maximum duration second. Power does include power contribution CMOS output sink current. Power dissipation specified switching output. 8.Capacitance measured initial qualification when design changes affect value. Capacitance measured between designated terminal frequency 1MHz signal amplitude 50mV maximum. 9.Guaranteed; tested sample pins device. Supplied design limit, guaranteed tested. Volts defined Volts 0.4Volts.
from
ELECTRICAL CHARACTERISTICS1 (Port Volt, Port Volt) 3.0V 3.6V; 2.3V 2.7V, -55°C +125°C) SYMBOL tPLH tPHL tPZL tPZH tPLZ tPHZ tPZL2 tPZH tPLZ2 tPHZ tSLH tSHL PARAMETER Propagation delay Data Propagation delay Data Output enable time Output enable time Output disable time high impedance Output disable time high impedance Output enable time DIRx Output enable time DIRx Output disable time DIRx high impedance Output disable time DIRx high impedance Skew between outputs (50pF each output) Skew between outputs (50pF each output) MINIMUM MAXIMUM UNIT
tPHL tPLZ .2VDD tPHZ .8VDD tPLZ .2VDD tPHZ
Propagation Delay Input Output
Notes: specifications valid radiation dose (Si) MIL-STD-883, Method 1019. DIRx times guaranteed design, tested. times tested
tPLH
Enable Disable Times Control Input 3.3V Output Normally 3.3V Output Normally High 2.5V Output Normally 2.5V Output Normally High
tPZL /2-0.2
DD/2 DD/2
tPZH /2+0.2 tPZL DD/2-0.2 tPZH /2+0.2
ELECTRICAL CHARACTERISTICS (Port Port Volt Operation) 3.6V; 3.0V 3.6V, -55°C +125°C) SYMBOL tPLH tPHL tPZL tPZH tPLZ tPHZ tPZL tPZH tPLZ tPHZ tSLH PARAMETER Propagation delay Data Propagation delay Data Output enable time Output enable time Output disable time high impedance Output disable time high impedance Output enable time DIRx Output enable time DIRx Output disable time DIRx high impedance Output disable time DIRx high impedance Skew between outputs (50pF each output) MINIMUM MAXIMUM UNIT
tPLZ tPHZ
tSHL
Skew between outputs (50pF each output)
tPLH tPHL DD/2-0.2 DD/2+0.2
Notes: specifications valid radiation dose rad(Si) MIL-STD-883, Method 1019. DIRx times guaranteed design, tested. times tested
Propagation Delay Input Output
DD/2 DD/2
Enable Disable Times
Control Input
tPZL
3.3V Output Normally 3.3V Output Normally High
.2VDD
DD/2 DD/2 DD/2
tPZH
.8VDD
ELECTRICAL CHARACTERISTICS1 (Port Port Volt Operation) 2.3V 2.7V; VDD2 2.3V 2.7V, -55°C +125°C) SYMBOL tPLH tPHL tPZL tPZH tPLZ tPHZ tPZL2 tPZH tPLZ2 tPHZ tSLH PARAMETER Propagation delay Data Propagation delay Data Output enable time Output enable time Output disable time high impedance Output disable time high impedance Output enable time DIRx Output enable time DIRx Output disable time DIRx high impedance Output disable time DIRx high impedance Skew between outputs (50pF each output) MINIMUM MAXIMUM UNIT
tPHL tPLZ DD/2-0.2 tPHZ
tSHL
Skew between outputs (50pF each output)
Notes:
Propagation Delay Input Output
specifications valid radiation dose rad(Si) MIL-STD-883, Method 1019. DIRx times guaranteed design, tested. times tested.
tPLH
DD/2 DD/2
Enable Disable Times Control Input
tPZL DD/2 DD/2 .7VDD DD/2
2.5V Output Normally 2.5V Output Normally High
tPZH DD/2+0.2
.7VDD
PACKAGE
mark symbol vendor option.
With solder, increase maximum 0.003.
exposed metalized areas gold plated over electroplated nickel MIL-PRF-38535. electrically connected VSS. Lead finishes accordance with MIL-PRF-38535. Lead position colanarity measured.
Figure 48-Lead Flatpack
ORDERING INFORMATION
UT54ACS162245S:
5962
98580
Lead Finish: Gold
Case Outline: lead (Gold only)
Class Designator: Class Class Device Type (01) 16-bit MultiPurpose Voltage ransceiver
Notes: Total dose radiation must specified when ordering. available without radiation hardening.
Total Dose: rad(Si) rad(Si) rad(Si) rad(Si)
Drawing Number: 98580
UT54ACS162245S
UT54 ******
Lead Finish: Gold
Screening: Temp Prototype
Package Type: 48-lead (Gold only)
Part Number: (16245SLV 16-bit MultiPurpose Voltage Transceiver
Type: (ACS)=
CMOS compatible Level
UTMC Core Part Number
Notes: Military Temperature Range flow UTMC Manufacturing Flows Document. Devices tested -55C, room temp, 125C. Radiation either tested guaranteed. Prototype flow UTMC Manufacturing Flows Document Tested only. Lead finish gold only.

RadHard Schmitt CMOS 16-bit Bidirectional MultiPurpose Voltage Transce

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