REFOUT LC2MOS 12-Bit Serial DACPORT AD7243 FUNCTIONAL BLOCK

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REFOUT LC2MOS 12-Bit Serial DACPORT AD7243 FUNCTIONAL BLOCK

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FEATURES 12-Bit CMOS with On-Chip Voltage Reference Output Amplifier Three Selectable Output Ranges Serial Interface Update Rate Small Size: 16-Lead SOIC Nonlinearity: Power Dissipation: Typical APPLICATIONS Process Control Industrial Automation Digital Signal Processing Systems Input/Output Ports
REFOUT
LC2MOS 12-Bit Serial DACPORT AD7243
FUNCTIONAL BLOCK DIAGRAM
VOUT REFIN AGND
AD7243
LATCH DGND
INPUT SHIFT REGISTER
SDIN BIN/ SCLK SYNC LDAC DCEN COMP
GENERAL DESCRIPTION
AD7243 complete 12-bit, voltage output, digital-toanalog converter with output amplifier Zener voltage reference monolithic CMOS chip. external trims required achieve full specified performance. output amplifier capable developing across load. output voltage ranges with single supply operation while additional bipolar output range available with dual supplies. ranges selected using internal gain resistor. data format natural binary both unipolar ranges, while either offset binary two's complement format selected bipolar range. function provided which sets output both unipolar ranges two's complement bipolar range, while with offset binary data format, output -REFIN. This function useful power-on reset allows output known voltage level. AD7243 features fast versatile serial interface which allows easy connection both microcomputers 16-bit digital signal processors with serial ports. serial data applied rates allowing update rate kHz. serial data output capability also provided which allows daisy chaining multi-DAC systems. This feature allows number DACs used system with simple 4-wire interface. DACs updated simultaneously using LDAC.
AD7243 fabricated Linear Compatible CMOS (LC2MOS), advanced, mixed technology process. packaged 16-lead 16-lead SOIC packages.
PRODUCT HIGHLIGHTS
Complete 12-Bit DACPORT® AD7243 complete, voltage output, 12-bit single chip. single chip design inherently more reliable than multichip designs. Single Dual Supply Operation. Minimum 3-wire interface most processors. Update Rate-300 kHz. Serial Data Output allows easy daisy-chaining multiple systems.
DACPORT registered trademark Analog Devices, Inc.
REV.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices. Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Site: http://www.analog.com Fax: 781/326-8703 Analog Devices, Inc., 2000
AD7243-SPECIFICATIONS
Parameter STATIC PERFORMANCE Resolution Relative Accuracy Differential Nonlinearity3 Unipolar Offset Error Bipolar Zero Error3 Full-Scale Error3, Full-Scale Temperature Coefficient REFERENCE OUTPUT Reference Output Range, REFOUT Reference Temperature Coefficient5 Reference Load Change (REFOUT REFERENCE INPUT Reference Input Range, REFIN Input Current DIGITAL INPUTS Input High Voltage, VINH Input Voltage, Input Current, Input Capacitance5 DIGITAL OUTPUT Serial Data (SDO) Output Voltage, Output High Voltage, ANALOG OUTPUT Output Range Resistor, Output Voltage Ranges Output Voltage Ranges Output Impedance CHARACTERISTICS Voltage Output Settling-Time Positive Full-Scale Change Negative Full-Scale Change Digital-to-Analog Glitch Impulse Digital Feedthrough3 POWER REQUIREMENTS Range Range (Dual Supplies) (Dual Supplies)
(VDD AGND DGND REFIN AGND. Specifications TMIN TMAX unless otherwise noted.)
Unit Bits FSR/ min/V ppm/°C min/V Test Conditions/Comments
Guaranteed Monotonic Latch Contents Latch Contents Guaranteed Process
4.95/5.05 4.95/5.05
4.95/5.05 4.95/5.05
4.95/5.05 4.95/5.05
Guaranteed Process Reference Load Current Change (0-100 Specified Performance
15/30 +10,
15/30 +10,
15/30 +10,
min/max
ISINK ISOURCE Typically Guaranteed Process Single Supply; Dual Supply;
+10.8/+16.5 -10.8/-16.5
+10.8/+16.5 -10.8/-16.5
+11.4/+15.75 -11.4/-15.75
secs secs min/V min/V
Settling Time Within Final Value Typically Typically Latch Contents Toggled Between LDAC High Specified Performance Unless Otherwise Stated Specified Performance Unless Otherwise Stated Output Unloaded; Typically Output Unloaded; Typically
NOTES Power Supply Tolerance Versions: 10%; Version: Temperature ranges follows: Versions: -40°C +85°C; Version: -55°C +125°C. terminology. Measured with respect REFIN includes unipolar/bipolar offset error. Guaranteed design characterization, production tested. output range available only with +14.25 Specifications subject change without notice.
REV.
AD7243 TIMING CHARACTERISTICS
Parameter t104, t114,
(VDD +10.8 +16.5 -10.8 -16.5 AGND DGND
Specifications TMIN TMAX unless otherwise noted.)
Units Conditions/Comments SCLK Cycle Time SYNC SCLK Falling Edge Setup Time SYNC SCLK Hold Time Data Setup Time Data Hold Time SYNC High LDAC LDAC Pulsewidth LDAC High SYNC Pulsewidth SCLK Falling Edge Valid SCLK Falling Edge Invalid
Limit TMIN, TMAX (All Versions)
NOTES Sample tested +25°C ensure compliance. input signals specified with (10% timed from voltage level Figures SCLK mark/space ratio range 40/60 60/40. load capacitance greater than 25°C max. Guaranteed design.
ABSOLUTE MAXIMUM RATINGS
+25°C unless otherwise noted)
AGND, DGND -0.3 AGND, DGND +0.3 AGND DGND -0.3 VOUT2 AGND REFOUT AGND REFIN AGND -0.3 Digital Inputs DGND -0.3 DGND -0.3 Operating Temperature Range Industrial Versions) -40°C +85°C Extended Version) -55°C +125°C
Storage Temperature Range -65°C +150°C Lead Temperature (Soldering, secs) +300°C Power Dissipation (Any Package) +75°C Derates above +75°C mW/°C
NOTES Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only; functional operation device these other conditions above those listed operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability. Only Absolute Maximum Rating applied time. outputs shorted voltages this range provided power dissipation package exceeded. Short circuit current typically
ORDERING GUIDE
Model AD7243AN AD7243BN AD7243AR AD7243BR AD7243AQ AD7243BQ AD7243SQ2
Temperature Range -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -55°C +125°C
Relative Accuracy
Package Option1 N-16 N-16 R-16 R-16 Q-16 Q-16 Q-16
NOTES Plastic DIP; SOIC; Cerdip. Available /883B processing only. Contact your local sales office military data sheet.
CAUTION (electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although AD7243 features proprietary protection circuitry, permanent damage occur devices subjected high-energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
WARNING!
SENSITIVE DEVICE
REV.
AD7243
TERMINOLOGY Bipolar Zero Error Relative Accuracy (Linearity)
Bipolar Zero Error voltage measured VOUT when configured bipolar output loaded with (Two's Complement Coding) with 1000 0000 0000 (Offset Binary Coding). combination offset errors DAC, amplifier mismatch between internal gain resistors around amplifier.
Full-Scale Error
Relative Accuracy, endpoint linearity, measure maximum deviation transfer function from straight line passing through endpoints transfer function. measured after allowing zero full-scale errors expressed LSBs percentage full-scale reading.
Single Supply Linearity Gain Error
Full-Scale Error measure output error when amplifier output full scale (for bipolar output range full scale either positive negative full scale). measured with respect reference input voltage includes offset errors.
Digital-to-Analog Glitch Impulse
output amplifier AD7243 have true negative offsets even when part operated from single supply. However, because negative supply rail (VSS) output cannot actually negative. Instead, when output offset voltage negative, output voltage sits resulting transfer function shown Figure
This voltage spike that appears VOUT when digital code latch changes, before output settles final value. energy glitch specified secs, measured codes change from 0000 0000 0000 1111 1111 1111 vice versa.
Digital Feedthrough
OUTPUT VOLTAGE
NEGATIVE OFFSET
This measure voltage spike that appears VOUT result feedthrough from digital inputs AD7243. measured with LDAC held high.
CODE
Figure Effect Negative Offset (Single Supply)
AD7243 FUNCTION DESCRIPTIONS (DIP SOIC NUMBERS) Mnemonic REFIN REFOUT BIN/COMP Description Voltage Reference Input. internally buffered before being applied DAC. nominal reference voltage specified operation AD7243 Voltage Reference Output. internal analog reference provided this pin. operate part using internal reference, REFOUT should connected REFIN. Clear, Logic Input. Taking this input sets VOUT both unipolar ranges two's complement bipolar range -REFIN offset binary bipolar range. Logic Input. This input selects data format either binary two's complement. both unipolar ranges, natural binary format selected connecting this input Logic "0." bipolar configuration, offset binary format selected with Logic while Logic selects two's complement format. Serial Clock, Logic Input. Data clocked into input register each falling SCLK edge. Serial Data Logic Input. 16-bit serial data word applied this input. Data Synchronization Pulse, Logic Input. Taking this input initializes internal logic readiness data word. Digital Ground. Ground reference digital circuitry. Load DAC, Logic Input. Updates output. output updated falling edge this signal alternatively this line permanently low, automatic update mode selected whereby updated 16th falling SCLK pulse. Daisy-Chain Enable, Logic Input. Connect this high daisy-chain interface being used, otherwise this must connected low. Serial Data Out, Logic Output. With DCEN Logic this output enabled, serial data input shift register clocked each falling SCLK edge. Analog Ground. Ground reference analog circuitry. Output Offset Resistor amplifier. connected VOUT range, AGND range REFIN range. Analog Output Voltage. This buffer amplifier output voltage. Three different output voltage ranges chosen: Negative Power Supply (used output amplifier only, connected single supply operation dual supplies). Positive Power Supply (+12 REV.
SCLK SDIN SYNC DGND LDAC
DCEN AGND ROFS VOUT
AD7243
TERMINOLOGY (Continued) Internal Reference
This "knee" offset effect, linearity error, transfer function would have followed dotted line output voltage could have gone negative. Normally, linearity measured between zero (all input code) full scale (all input code) after offset full scale have been adjusted allowed for, this possible single supply operation offset negative, knee transfer function. Instead, linearity AD7243 unipolar mode measured between full scale lowest code which guaranteed produce positive output voltage. This code calculated from maximum specification negative offset. versions linearity measured between Codes 4095. grade, linearity measured between Code Code 4095.
Differential Nonlinearity
AD7243 on-chip temperature compensated buried Zener reference which factory trimmed reference voltage provided REFOUT pin. This reference used provide reference voltage converter connecting REFOUT REFIN pin.) reference voltage also used reference other components capable providing external load. maximum recommended capacitance REFOUT normal operation reference required external with capacitive loads greater than then should decoupled AGND with resistor series with parallel combination tantalum capacitor ceramic capacitor.
Differential Nonlinearity difference between measured change ideal change between adjacent codes. specified differential nonlinearity less over operating temperature range ensures monotonicity.
Unipolar Offset Error
REFOUT
LOAD
Figure Reference Decoupling Scheme
External Reference
Unipolar Offset Error measured output voltage from VOUT with zeros loaded into latch when configured unipolar output. combination offset errors output amplifier.
CONFIGURATION SOIC
REFIN REFOUT
some applications, user require system reference some other external reference drive AD7243. References such AD586 provide ideal external reference source (see Figure 10). REFIN voltage internally buffered unity gain amplifier before being applied converter. converter scaled reference device tested with applied REFIN. Other reference voltages used with degraded performance. Figure shows typical degradation linearity REFIN.
+15V -15V
BIN/COMP
AD7243
VIEW (Not Scale)
VOUT ROFS AGND
SCLK SDIN SYNC DGND
DCEN LDAC
LINEARITY ERROR LSBs
REFIN Volts
CIRCUIT INFORMATION
Section AD7243 contains 12-bit voltage mode converter consisting highly stable thin film resistors high speed NMOS single-pole, double-throw switches. output voltage from converter same polarity reference voltage, REFIN, allowing single supply operation.
DB10 VOUT DB11
Figure Typical Linearity REFIN Voltage
Section
output voltage mode converter buffered noninverting CMOS amplifier. ROFS input allows three output voltage ranges selected. buffer amplifier capable developing across load AGND. output amplifier operated from single supply tying amplifier also operated from dual supplies allow additional bipolar output range Dual supplies necessary bipolar output range also used unipolar ranges give faster settling time voltages near
REFIN* AGND *BUFFERED REFIN VOLTAGE
SHOWN
Figure Simplified Circuit Diagram
REV.
AD7243
allow full sink capability over entire output range eliminate effects negative offsets transfer characteristic (outlined previously). plot output sink capability amplifier shown Figure
circuitry shown Figure Serial data SDIN input loaded input register under control DCEN, SYNC SCLK. When complete word held shift register, then loaded into latch under control LDAC. Only data latch determines analog output AD7243. DCEN (daisy-chain enable) input used select either standalone mode daisy-chain mode. loading format slightly different depending which mode selected.
-15V
SINK
Serial Data Loading Format (Standalone Mode)
OUTPUT VOLTAGE Volts
Figure Amplifier Sink Current
DIGITAL INTERFACE
With DCEN Logic standalone mode selected. this mode SYNC input provides frame synchronization signal which tells AD7243 that valid serial data SDIN input will available next falling edges SCLK. internal counter/decoder circuit provides gating signal that only data bits clocked into input shift register. After SCLK pulses internal gating signal goes inactive (high) thus locking further clock pulses. Therefore, either continuous clock burst clock source used clock data. SYNC input should taken high after complete 16-bit word loaded
AD7243 contains input serial parallel shift register latch. simplified diagram input loading
DCEN SYNC RESET
GATING SIGNAL GATED SCLK INPUT SHIFT REGISTER BITS)
COUNTER/ DECODER SCLK SDIN AUTO UPDATE CIRCUITRY LDAC
LATCH BITS)
Figure Simplified Loading Structure
SCLK
SYNC
SDIN DB15* DB14* DB13* DB12*
DB11
LDAC
DON'T CARE
Figure Timing Diagram (Standalone Mode)
REV.
AD7243
Although bits data clocked into input register, only latter bits transferred into latch. first bits stream don't cares since their value does affect latch data. Therefore, data format don't cares followed 12-bit data word with last serial stream. There ways which latch hence analog output updated. status LDAC input examined after SYNC taken low. Depending status, update modes selected. LDAC then automatic update mode selected. this mode latch analog output updated automatically when last serial data stream clocked update thus takes place sixteenth falling SCLK edge. LDAC then automatic update disabled latch updated taking LDAC time after 16-bit data transfer complete. update occurs falling edge LDAC. Note that LDAC input must taken back high again before next data transfer initiated.
Serial Data Loading Format (Daisy-Chain Mode)
SYNC low. data clocked into register each falling SCLK edge after SYNC going low. more than clock pulses applied, data ripples shift register appears line. connecting this line SDIN input next AD7243 chain, multi-DAC interface constructed. Sixteen SCLK pulses required each system. Therefore, total number clock cycles must equal where total number devices chain. When serial transfer devices complete, SYNC should taken high. This prevents further data being clocked into input register. continuous SCLK source used arranged that SYNC held correct number clock cycles. Alternatively, burst clock containing exact number clock cycles used SYNC taken high some time later. When transfer input registers complete, common LDAC signal updates latches with lower bits data each input register. analog outputs therefore updated simultaneously falling edge LDAC. Clear Function (CLR) clear function bypasses input shift register loads Latch with activated taking low. ranges except Offset Binary bipolar range output voltage reset offset binary bipolar range output -REFIN. clear function especially useful power-up enables output reset known state.
connecting DCEN high daisy-chain mode enabled. This mode operation designed multi-DAC systems where several AD7243s connected cascade (see Figure 16). this mode internal gating circuitry SCLK disabled, serial data output facility enabled. internal gating signal permanently active (low) that SCLK signal continuously applied input shift register when
SCLK
SYNC
SDIN
DB15 (N)*
DB15* DB11
DB11
UNDEFINED LDAC
DB15 (N)* DB11
DON'T CARE
Figure Timing Diagram (Daisy-Chain Mode)
REV.
AD7243
APPLYING AD7243 Unipolar Configuration
Power Supply Decoupling achieve optimum performance when using AD7243, lines should each decoupled DGND using capacitors. noisy environments recommended that capacitors connected parallel with capacitors. internal scaling resistors provided AD7243 allow several output voltage ranges. part produce unipolar output ranges bipolar output range Connections various ranges outlined below.
Unipolar Configuration
output voltage range achieved connecting ROFS VOUT. Once again, AD7243 operated using either single dual supplies. table output voltage digital code Table with 2REFIN replaced REFIN. Note, this range, REFIN (2-12 (REFIN/4096).
Bipolar Configuration
first configurations provides output voltage range This achieved connecting output offset resistor ROFS (Pin AGND. Natural Binary data format selected connecting BIN/COMP (Pin DGND. this configuration, AD7243 operated using either single dual supplies. Note that supply must +14.25 this range order maintain sufficient amplifier headroom. Dual supplies used improve settling time give increased current sink capability amplifier. Figure shows connection diagram unipolar operation AD7243. Table shows digital code analog output this configuration.
bipolar configuration AD7243, which gives output range achieved connecting ROFS REFIN. AD7243 must operated from dual supplies achieve this output voltage range. Either offset binary two's complement data format selected. Figure shows connection diagram bipolar operation. AD586 provides reference voltage this could provided on-chip reference connecting REFOUT REFIN.
ROFS +VIN
VOUT AD586 VOUT REFIN BIN/ COMP DGND AGND *ADDITIONAL PINS OMITTED CLARITY
AD7243*
REFOUT
AD7243*
ROFS
Figure Bipolar Configuration with External Reference
VOUT
REFIN BIN/ COMP
Bipolar Operation (Two's Complement Data Format) AD7243 configured two's complement data format connecting BIN/COMP (Pin high. analog output digital code shown Table
Table Two's Complement Bipolar Code Table
DGND
AGND
*ADDITIONAL PINS OMITTED CLARITY
Input Data Word XXXX XXXX XXXX XXXX XXXX XXXX 0111 0000 0000 1111 1000 1000 1111 0000 0000 1111 0000 0000 1111 0001 0000 1111 0001 0000
Analog Output, VOUT +REFIN (2047/2048) +REFIN (1/2048) -REFIN (1/2048) -REFIN (2047/2048) -REFIN (2048/2048) -REFIN
Figure Unipolar Configuration
Table Unipolar Code Table Range)
Input Data Word XXXX XXXX XXXX XXXX XXXX XXXX 1111 1000 1000 0111 0000 0000 1111 0000 0000 1111 0000 0000 1111 0001 0000 1111 0001 0000
Analog Output, VOUT REFIN (4095/4096) REFIN (2049/4096) REFIN (2048/4096) +REFIN REFIN (2047/4096) REFIN (1/4096)
Don't Care. Note: REFIN/2048.
Bipolar Operation (Offset Binary Data Format) AD7243 configured Offset Binary data format connecting BIN/COMP (Pin low. analog output digital code obtained inverting Table
Don't Care. Note: REFIN/4096.
REV.
AD7243
MICROPROCESSOR INTERFACING AD7243-DSP56000 Interface
Microprocessor interfacing AD7243 serial which uses standard protocol compatible with processors microcontrollers. communications channel requires three-wire interface consisting clock signal, data signal synchronization signal. AD7243 requires 16-bit data word with data valid falling edge SCLK. interfaces, update done automatically when data clocked done under control LDAC. Figures show AD7243 configured interfacing number popular processors microcontrollers.
AD7243-ADSP-2101/ADSP-2102 Interface
serial interface between AD7243 DSP56000 shown Figure DSP56000 configured Normal Mode Asynchronous operation with Gated Clock. also 16-bit word with outputs control "0." internally generated DSP56000 applied AD7243 SCLK input. Data from DSP56000 valid falling edge SCK. output provides framing pulse valid data. This line must inverted before being applied SYNC input AD7243. LDAC input AD7243 connected DGND update latch takes place automatically sixteenth falling edge SCLK. external timer could also used previous interface external update required.
LDAC
Figure shows serial interface between AD7243 ADSP-2101/ADSP-2102 processor. ADSP-2101/ ADSP-2102 contains serial ports, either port used interface. data transfer initiated going low. Data from ADSP-2101/ADSP-2102 clocked into AD7243 falling edge SCLK. When data transfer complete, taken high. interface shown updated using external timer which generates LDAC pulse. This could also done using control decoded address line from processor. Alternatively, LDAC input could hard wired this case update takes place automatically sixteenth falling edge SCLK.
TIMER
DSP56000
AD7243*
SCLK SDIN SYNC
*ADDITIONAL PINS OMITTED CLARITY
Figure AD7243-DSP56000 Interface
AD7243-TMS32020 Interface
LDAC
ADSP 2101/ ADSP 2102*
AD7243*
SCLK SYNC SCLK SDIN
Figure shows serial interface between AD7243 TMS32020 processor. this interface, CLKX signals TMS32020 should generated using external clock/timer circuitry. TMS32020 must configured input. Data from TMS32020 valid falling edge CLKX. clock/timer circuitry generates LDAC signal AD7243 synchronize update output with serial transmission. Alternatively, automatic update mode selected connecting LDAC DGND.
CLOCK/ TIMER
*ADDITIONAL PINS OMITTED CLARITY
Figure AD7243-ADSP-2101/ADSP-2102 Interface
TMS32020
CLKX LDAC
AD7243*
SYNC SCLK SDIN
*ADDITIONAL PINS OMITTED CLARITY
Figure AD7243-TMS32020 Interface
REV.
AD7243
AD7243-87C51 Interface
serial interface between AD7243 87C51 microcontroller shown Figure 87C51 drives SCLK AD7243, while drives serial data line part. SYNC signal derived from port line P3.3. 87C51 provides SBUF register first serial data stream. Therefore, user will have ensure that data SBUF register arranged correctly that don't care bits first transmitted AD7243 last sent word loaded AD7243. When data transmitted part, P3.3 taken low. Data valid falling edge TXD. 87C51 transmits serial data 8-bit bytes with only eight falling clock edges occurring transmit cycle. load data AD7243, P3.3 left after first eight bits transferred second byte data then transferred serially AD7243. When second serial transfer complete, P3.3 line taken high. Figure shows LDAC input AD7243 hard wired low. result, latch analog output will updated sixteenth falling edge after SYNC signal gone low. Alternatively, scheme used previous interfaces, whereby LDAC input driven from timer, used.
Figure shows LDAC input AD7243 hardwired low. result, latch analog output will updated sixteenth falling edge after respective SYNC signal gone low. Alternatively, scheme used previous interfaces, whereby LDAC input driven from timer, used.
LDAC
68HC11*
AD7243*
SYNC SCLK SDIN
MOSI
*ADDITIONAL PINS OMITTED CLARITY
Figure AD7243-68HC11 Interface
Multiple Daisy-Chain Interface
multi-DAC serial interface shown Figure This scheme used with interfaces previously discussed more than required system. enable facility DCEN must connected high devices, including last device chain.
LDAC
MICROCONTROLLER
SDIN
87C51*
AD7243*
SYNC SCLK SDIN
AD7243*
SCLK SYNC LDAC DCEN SDIN
P3.3
*ADDITIONAL PINS OMITTED CLARITY
Figure AD7243-87C51 Interface
AD7243-68HC11 Interface
AD7243*
SCLK SYNC LDAC DCEN
Figure shows serial interface between AD7243 68HC11 microcontroller. 68HC11 drives SCLK AD7243 while MOSI output drives serial data line AD7243. SYNC signal derived from port line (PC7 shown). correct operation this interface, 68HC11 should configured such that CPOL CPHA When data transmitted part, taken low. When 68HC11 configured like this, data MOSI valid falling edge SCK. 68HC11 transmits serial data 8-bit bytes with only eight falling clock edges occurring transmit cycle. load data AD7243, left after first eight bits transferred second byte data then transferred serially AD7243. When second serial transfer complete, line taken high.
SDIN
AD7243*
SCLK SYNC LDAC *ADDITIONAL PINS OMITTED CLARITY DCEN
Figure AD7243 Daisy-Chain Configuration
-10-
REV.
AD7243
Common clock, data, synchronization signals applied DACs chain. loading sequence starts taking SYNC low. data then clocked into input registers falling edge SCLK. Sixteen clock pulses required each chain. data ripples through input registers with first 16-bit word filling last register chain after clock pulses where total number DACs chain. When valid data been loaded into registers, SYNC input should taken high common LDAC pulse used update DACs simultaneously. Figure shows 4-channel isolated interface using AD7243. DCEN must connected high enable daisy-chain facility. Four channels with 12-bit resolution provided circuit shown, this expanded accommodate number channels without extra isolation circuitry. sequence events program output channels follows: Take SYNC line low. Transmit data four 16-bit words. total clock pulses required clock data through chain. Take SYNC line high. Pulse LDAC line low. This updates output channels simultaneously falling edge LDAC. reduce number opto-couplers, LDAC line could driven from shot which triggered rising edge SYNC line. level pulse duration greater that required update outputs.
APPLICATIONS
OPTO-ISOLATED INTERFACE many process control type applications necessary provide isolation barrier between controller unit being controlled. Opto-isolators provide voltage isolation excess serial loading structure AD7243 makes ideal opto-isolated interfaces number interface lines kept minimum.
DATA
CONTROLLER
CLOCK
SDIN
AD7243*
SCLK SYNC LDAC DCEN SDIN VOUT VOUT(A)
SYNC
CONTROL
AD7243*
SCLK SYNC QUAD OPTO-COUPLER LDAC DCEN SDIN VOUT VOUT(B)
AD7243*
SCLK SYNC DCEN LDAC VOUT VOUT(C)
SDIN
AD7243*
SCLK SYNC LDAC *ADDITIONAL PINS OMITTED CLARITY DCEN VOUT VOUT(D)
Figure Four-Channel Opto-lsolated Interface
REV.
-11-
AD7243
OUTLINE DIMENSIONS
Dimensions shown inches (mm).
Plastic (N-16)
0.87 (22.1) 0.035 (0.89) 0.18 (4.57) 0.125 (3.18) 0.033 (0.84) (2.54) 0.011 (0.28) (7.62) 0.018 (0.46) 0.18 (4.57)
Cerdip (Q-16)
VIEW
(Not Scale)
0.310 (7.87) 0.220 (5.59)
0.840 (21.34) 0.200 (5.08)
0.060 (1.52) 0.015 (0.38)
0.320 (8.13) 0.290 (7.37)
0.150 (3.81)
0.015 (0.381) 0.008 (0.204)
0.022 (0.558) 0.014 (0.356)
0.100 (2.54 BSC)
0.070 (1.78) 0.30 (0.76)
SOIC (R-16)
0.413 (10.49) 0.398 (10.11)
0.300 (7.62) 0.292 (7.42)
0.419 (10.64) 0.394 (10.01)
0.02 (0.508) CHAMP
0.350 (8.89) 0.011 (0.279) 0.004 (0.102) STANDOFF 0.104 (2.64) 0.093 (2.36)
0.050 (1.27)
0.019 (0.483) 0.014 (0.356)
0.01 (0.254)
0.050 (1.27)
-12-
REV.
PRINTED U.S.A.
C1498a-1-6/00 (rev. 00993
0.25 0.31 (6.35) (7.87)

REFOUT LC2MOS 12-Bit Serial DACPORT AD7243 FUNCTIONAL BLOCK

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