Matrix Driver APR. 2002 Version SUNPLUS TECHNOLOGY infringem

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SPLC501C
Matrix Driver
APR. 2002 Version
SUNPLUS TECHNOLOGY infringement patent other rights third parties which result from use. addition, SUNPLUS products authorized critical components life support devices/ systems aviation devices/systems, where malfunction failure product reasonably expected result significant injury user, without express written approval Sunplus.
SPLC501C
Table Contents
PAGE
GENERAL DESCRIPTION. FEATURES. BLOCK DIAGRAM SIGNAL DESCRIPTIONS 4.1. 4.2. 4.3. 4.4. 4.5. POWER SUPPLY PINS POWER SUPPLY CIRCUIT TERMINALS SYSTEM CONNECTION TERMINALS. LIQUID CRYSTAL DRIVE TERMINALS TEST TERMINALS
FUNCTIONAL DESCRIPTIONS. 5.1. 5.2. 5.3. 5.4. 5.5. 5.6. 5.7. 5.8. 5.9. INTERFACE CHIP SELECT ACCESSING DISPLAY DATA INTERNAL REGISTERS BUSY FLAG DISPLAY DATA DISPLAY DATA LATCH CIRCUIT OSCILLATOR CIRCUIT COMMON OUTPUT STATUS SELECT. DISPLAY TIMING GENERATOR CIRCUIT
5.10. LIQUID CRYSTAL DRIVER CIRCUITS 5.11. POWER SUPPLY CIRCUITS 5.12. HIGH POWER MODE 5.13. INTERNAL POWER SUPPLY SHUTDOWN COMMAND SEQUENCE 5.14. REFERENCE CIRCUIT EXAMPLES 5.15. RESET CIRCUIT COMMANDS 6.1. 6.2. 6.3. 6.4. 6.5. 6.6. 6.7. 6.8. 6.9. DISPLAY ON/OFF DISPLAY START LINE PAGE ADDRESS COLUMN ADDRESS STATUS READ DISPLAY DATA WRITE DISPLAY DATA READ SELECT (SEGMENT DRIVER DIRECTION SELECT) DISPLAY NORMAL/REVERSE
6.10. DISPLAY POINTS ON/OFF. 6.11. BIAS 6.12. READ/MODIFY/WRITE. 6.13. END. 6.14. RESET 6.15. COMMON OUTPUT MODE SELECT 6.16. POWER CONTROLLER Sunplus Technology Co., Ltd. Proprietary Confidential APR. 2002 Version:
SPLC501C
6.17. VOLTAGE REGULATOR INTERNAL RESISTOR RATIO 6.18. ELECTRONIC VOLUME (DOUBLE BYTE COMMAND). 6.19. STATIC INDICATOR (DOUBLE BYTE COMMAND). 6.20. PAGE BLINKING (DOUBLE BYTE COMMAND). 6.21. DRIVING MODE (DOUBLE BYTE COMMAND) 6.22. POWER SAVE (COMPOUND COMMAND) 6.23. 6.24. TEST 6.25. TABLE TABLE SPLC501C COMMANDS COMMAND DESCRIPTION 7.1. 7.2. INSTRUCTION SETUP: REFERENCE (REFERENCE). PRECAUTIONS TURNING POWER
ELECTRICAL SPECIFICATIONS 8.1. 8.2. 8.3. 8.4. 8.5. 8.6. 8.7. 8.8. 8.9. ABSOLUTE MAXIMUM RATINGS CHARACTERISTICS DISPLAY PATTERN DISPLAY PATTERN CHECKER. DISPLAY PATTERN CHECKER. TIMING CHARACTERISTICS. INTERFACE (REFERENCE EXAMPLES). CONNECTIONS BETWEEN DRIVERS (REFERENCE EXAMPLE) CONNECTIONS BETWEEN DRIVERS (REFERENCE EXAMPLES)
8.10. VLCD VOLTAGE (VOLTAGE BETWEEN RELATIONSHIP VOLTAGE REGULATOR INTERNAL RESISTOR RATIO REGISTER
ELECTRONIC VOLUME CONTROL REGISTER
PACKAGE/PAD LOCATIONS 9.1. 9.2. 9.3. ASSIGNMENT ORDERING INFORMATION LOCATIONS
DISCLAIMER. REVISION HISTORY
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SPLC501C
MATRIX DRIVER
GENERAL DESCRIPTION
SPLC501C, single-chip matrix liquid crystal display drivers, specially designed connect directly with microprocessor bus. 8-bit parallel serial display data sent from microprocessor stored internal display data RAM. generates liquid crystal drive signal independent microprocessor. Since SPLC501C contains bits display data RAM, 1-to-1 correspondence between liquid crystal panel pixels internal bits, able enable displays with high degree flexibility. SPLC501C contains common output circuits, segment output circuits therefore, single chip drive display (capable displaying columns rows kanji font). addition, capacity display also extended through master/slave structures between chips. chips save great amount power because external operating clock required display data read write operations. Since each chip equipped internally with low-power liquid crystal driver power supply, resistors liquid crystal driver power voltage adjustment display clock oscillator circuit, SPLC501C used creating lowest power display system with fewest components high performance portable devices. These chips designed resistance light Resistance radiation. High-speed 8-bit interface (capability connected directly both series MPUs 68000 series MPUs)/Serial interface supported. Wide range operating temperatures. CMOS process oscillator circuit equipped internally (External clock also input). Abundant command functions Display data Read/Write, display ON/OFF, Normal/Reverse display mode, page address set, display start line set, column address set, status read, display points ON/OFF, bias set, electronic volume, read/modify/write, segment driver direction select, power saver, static indicator, common output status select, voltage regulation internal resistor ratio set. Low-power liquid crystal display power supply circuit equipped internally. Booster circuit (with Boost ratios Double/Triple/Quad, where step-up voltage reference power supply input externally). High-accuracy voltage adjustment circuit (Thermal gradient -0.05%/ external input). voltage regulator resistors equipped internally, voltage divider resistors equipped internally, electronic volume function equipped internally, voltage follower. Driving Mode register provided different size panel loading. Extremely power consumption. operating power when built-in power supply used Power supply Operable voltage Logic power supply 2.4V 5.5V Boost reference voltage: VSS2 2.4V 6.0V Liquid crystal drive power supply: 4.5V
FEATURES
Direct display data through display data RAM. `1': Non-illuminated. `0': Illuminated. capacity. 8580 bits. Display driver circuits. SPLC501C: common outputs segment outputs. Static drive circuit equipped internally indicators. system, with variable flashing speed.)
Product Name SPLC501C
Duty 1/65
Bias 1/9,
VREG Temperature Gradient -0.05%/
Shipping Forms Bare Chip with Gold Bump
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SPLC501C
BLOCK DIAGRAM
SEG131
COM63
Drivers
Drivers
output status select circuit CAP1P CAP1N CAP2P CAP2N CAP3N VOUT VSS2 Display data latch circuit Display timing generation circuit
COMS
COMS
COM0
SEG0
Page address circuit
Power supply circuit
buffer
Display data
Line address circuit
Column address circuit Oscillator circuit
holder
Command decoder interface
Status
(RWP)
(EP)
D6(SCL)
RESET
D7(SI)
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SIGNAL DESCRIPTIONS
4.1. Power Supply Pins
Mnemonic VSS2 Type Description Shared with power supply terminal terminal connected system GND. reference power supply step-up voltage circuit liquid crystal drive external-input VREG power supply power supply voltage regulator. only enabled models with VREG external input option. multi-level power supply liquid crystal drive. changing impedance using amp. V1V2V3V4V5 Master operation: When power supply turns internal power supply circuits generate voltages shown below. voltage settings selected bias command. voltage applied determined liquid crystal cell, changed through resistive voltage divided through Voltage levels determined based VDD, must maintain relative magnitudes shown below. These
SPLC501C
Power Supply
1/9V5 1/7V5 2/9V5 2/7V5 7/9V5 5/7V5 8/9V5 6/7V5
4.2. Power Supply Circuit Terminals
Mnemonic CAP1P CAP1N CAP2P CAP2N CAP3N VOUT Type Description DC/DC voltage converter. capacitor connected between this terminal CAP1N terminal. DC/DC voltage converter. capacitor connected between this terminal CAP1P terminal. DC/DC voltage converter. capacitor connected between this terminal CAP2N terminal. DC/DC voltage converter. capacitor connected between this terminal CAP2P terminal. DC/DC voltage converter. capacitor connected between this terminal CAP1P terminal. DC/DC voltage converter. capacitor connected between this terminal VSS. Output voltage regulator terminal. Provides voltage between through resistive voltage divider. used (IRS `L'). used (IRS `H'). These only enabled when voltage regulator internal resistors These cannot used when voltage regulator internal resistors
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4.3. System Connection Terminals
Mnemonic (SI) (SCL) Type Description This 8-bit bi-directional data that connects 8-bit 16-bit standard data bus. When serial interface selected `L'), serves serial data input terminal (SI) serves serial clock input terminal (SCL). high impedance. same time, When chip select inactive, high impedance.
This connected least significant normal address bus, determines whether data bits data command. `H': Indicates display data. `L': Indicates control data.
RESET
When RESET `L', settings initialized. RESET signal level performs reset operation.
(EP)
This chip select signal.
When `H', chip select becomes active,
data/command enabled.
When connected 8080 MPU, this active. This connected signal This 68000 Series 8080 MPU, SPLC501C data output status when this signal `L'. When connected 6800 Series MPU, this HIGH active. enable clock input terminal. When connected 8080 MPU, this active.
(RWP)
This terminal connects 8080
signal. signals data latched rising edge signal. When connected 6800 Series MPU: This read/write control signal input terminal. When `H': Read. When `L': Write. This interface switch terminal. `H': 6800 Series interface. `L': 8080 interface. This parallel data input/serial data input switch terminal. `H': Parallel data input. `L': Serial data input. following applies depending status:
Data/Command Data SI(DB7) Read/Write Write only Serial Clock
(DB6)
When `L', high impedance. (EP) (RWP) fixed either `L'. reading supported.
`H', Open.
With serial data input, display data
Terminal select whether enable disable display clock internal oscillator circuit. `H': Internal oscillator circuit enabled. `L': Internal oscillator circuit disabled (requires external input). When `L', input display clock through terminal.
This liquid crystal alternating current signal terminal. `H': Output `L': Input When SPLC501C chip used master/slave mode, various terminals must connected.
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Mnemonic Type Description
This terminal selects master/slave operation SPLC501C chips. Master operation outputs timing signals that required display, while slave operation inputs timing signals required liquid crystal display, synchronizing liquid crystal display system. `H': Master operation `L': Slave operation following true depending status:
Oscillator Circuit Enabled Disabled Disabled Disabled Power Supply Circuit Enabled Enabled Disabled Disabled Output Input Input Input Output Output Input Input Output Output Output Output Output Output Input Input
This display clock input terminal following true depending status.
Output Input Input Input
When SPLC501C chips used master/slave mode, various terminals must connected. This liquid crystal display blanking control terminal. `H': Output `L': Input When SPLC501C chip used master/slave mode, various terminals must connected. This output terminal static drive. This terminal only enabled when static indicator display when master operation mode, used conjunction with terminal. This terminal selects resistors voltage level adjustment. `H': internal resistors. `L': internal resistors. voltage level regulated external resistive voltage divider attached terminal. This enabled only when master operation mode selected. fixed either when slave operation mode selected. This power control terminal power supply circuit liquid crystal drive. `H': Normal mode. `L': High power mode. This enabled only when master operation mode selected. when slave operation mode selected. This reference source select terminal power supply circuit liquid crystal drive. "H"; external reference source from terminal. "L"; internal reference source from SPLC501C terminal. This enable only when master operation mode selected. when slave operation mode selected. Sunplus Technology Co., Ltd. Proprietary Confidential APR. 2002 Version: fixed either fixed either
SPLC501C
4.4. Liquid Crystal Drive terminals
Mnemonic Type Description
SEG131
These liquid crystal segment drive outputs. Through combination contents display with signal, single level selected from VDD,
DATA Power save COM63
Output Voltage Normal Display Reverse Display
These liquid crystal common drive outputs.
Part SPLC501C COM63
Through combination contents scan data with signal, single level selected from VDD,
Scan Data
Power Save
Output Voltage
COMS
These output terminals indicator. Leave these pins open they used. output both master slave.
Both terminals output same signal.
When master/slave mode, same signal
4.5. Test Terminals
Mnemonic Type Description
TEST TEST3, TEST4 TEST5, TEST6
This terminal chip testing only. These terminals chip testing only. These terminals chip testing only.
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FUNCTIONAL DESCRIPTIONS
5.1. Interface 5.1.1. Selecting interface type
SPLC501C, data transfers accomplished through 8-bit bi-directional data (DB7 through serial data input (SI). selecting terminal polarity `L', possible
Table
select either parallel data input serial data input shown Table
Parallel Input Serial Input
(HiZ)
indicates fixed either
5.1.2. parallel interface
When parallel interface selected `H'), possible connect directly either 8080-system 6800 Series
Table
shown Table selecting terminal either `L'.
6800 Series 8080
Data signals recognized combination A0P, (EP), (RWP) signals, shown Table
Table Shared 6800 Series 8080 Series Function
Read display data Write display data Read Status Write control data (command)
5.1.3. serial interface
When serial interface selected `L') when chip active state CS1= `H'), serial data input (SI) serial clock input (SCL) received. clocks DB7, through order. serial data input determines whether serial data input display data command data; when `H', data display data, when `L', data command data. clock after chip active. input read used detecting every rising edge serial
read from serial data input rising edge serial data converted 8-bit parallel data rising edge eighth serial clock.
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Figure serial interface signal chart. Note1: When chip active, shift registers counter reset their initial states. Note2: Reading acceptable serial interface mode. Note3: Caution required signal when comes line-end reflections external noise. SUNPLUS recommends that operation should rechecked actual equipment.
5.2. Chip Select
Writing
SPLC501C have chip-select-terminals: CS2. interface serial interface enabled only when `H'. When chip select inactive, enter into high impedance state, A0P, inputs inactive. When serial interface selected, shift register counter reset.
DATA Internal Timing
Latch
Holder Write Signal
Reading
DATA
INternal Timing
5.3. Accessing Display Data Internal Registers
Data transferring high speed ensured since required satisfy cycle time (tCYC) requirement alone accessing SPLC501C. Wait time considered. Also, SPLC501C chips, each time data sent from MPU. holder attached internal data bus.
Address Preset
Read Signal Column Address Preset Increment
Holder
Address
Dummy Read
Data Read
Data Read #n+1
Figure2
type pipeline process between LSIs performed through example, when writes data display data RAM, once data stored holder, written display data before next data write cycle. Moreover, when reads display data RAM, first data read cycle (dummy) stores read data holder, then data read from holder system next data read cycle. There certain restriction read sequence display data RAM. Note that data specified address generated read instruction issued immediately after address setup. This data generated data read second time. cycle operation conducted. Figure Sunplus Technology Co., Ltd. Proprietary Confidential Thus, dummy read required whenever addresses setup write This relationship shown
5.4. Busy Flag
When busy flag `1', indicates that SPLC501C running internal processes. this moment, command aside busy flag outputted cycle time (tCYC) from status read will received. with read instruction. command.
remained, necessary check this flag before each This makes vast improvements processing capabilities possible.
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SPLC501C
5.5. Display Data 5.5.1. Display data
display data that stores data display. page 132-bit structure. possible access desired specifying page address column address. Because, shown Figure
Table Output SEG0 SEG131
relationship between display data column address segment output. Because this, constraints layout when module assembled minimized.
display data from corresponds liquid crystal display common direction, there constraints time display data transfer when multiple SPLC501C chips used. Therefore, display structures created easily with high degree freedom.
(DB0)
83(H)
Column Address "83(H) Column Address 0(H)
5.5.4.
COM0 COM1 COM2 COM3 COM4
line address circuit
line address circuit, shown Figure specifies line address relating output when contents display data displayed. specified. Using display start line address command, which normally line display This COM0 output when common display area output mode normal COM63 output SPLC501C when common output mode reversed. address. 65-line area SPLC501C from display start line line addresses changed dynamically using display start line address command, screen scrolling, page swapping, .etc. performed.
Page Address Data Line Address When common output mode normal Output COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 COM51 COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63 CMOS
Regardless display start line address, SPLC501A access 65th line
Display data
Liquid crystal display
Figure
Moreover, reading from writing display side performed through buffer, which independent operation from signal reading liquid crystal driver. Consequently, even display data accessed asynchronously during liquid crystal display, will cause adverse effects display (such flickering).
Page
5.5.2. page address circuit
Page
shown Figure page address display data specified through Page Address Command. page
address must specified again when changing pages perform access. Page address (DB3, DB2, DB1, page region used only indicators, only display data used.
Page
Page
Page
5.5.3. column addresses
shown Figure display data column address
Page
specified Column Address command. read/write command.
specified
column address incremented (+1) with each display data This allows display data Moreover, increment column Because column address
Page
accessed continuously. depends
addresses stops with 83H.
Page
page address, necessary re-specify both
Page
SEG124 SEG125 SEG126 SEG127 SEG128 SEG129 SEG130 SEG131
SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7
Furthermore, shown Table command (segment driver direction select command) used reverse Sunplus Technology Co., Ltd. Proprietary Confidential
Figure
example, from page column page column 00H.
Column Address
page address column address when moving,
APR. 2002 Version:
SPLC501C
5.6. Display Data Latch Circuit
display data latch circuit temporarily stores display data that output liquid crystal driver circuit from display data RAM. Because display normal/reverse status, display ON/OFF status, display points ON/OFF commands control only data within latch, they change data within display data itself.
Table Status Scan Direction SPLC501C
Normal Reverse
COM0"COM63 COM63"COM0
5.7. Oscillator Circuit
This CR-type oscillator that produces display clock. oscillator circuit only enabled when `H'. When `L', oscillation stops, display clock input through terminal.
5.9. Display Timing Generator Circuit
display timing generator circuit generates timing signal line address circuit display data latch circuit using display clock. display data latched into display data latch circuit synchronized with display clock, output data driver output terminal. display data MPU. Reading display data liquid Consequently, even display crystal driver circuits completely independent accesses data accessed asynchronously during liquid crystal display, there absolutely adverse effect (such flickering) display. Moreover, display timing generator circuit generates common timing liquid crystal alternating current signal (FR) from display clock. generates drive-wave form using 2-frame alternating current drive method, shown Figure liquid crystal drive circuit.
5.8. Common Output Status Select
SPLC501C chips, output scan direction selected common output status select command (See Table 5.). Consequently, constraints layout time module assembly minimized.
Two-frame alternating current drive-wave form (SPLC501C)
COM0 COM1 DATA SEGn
Figure
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When multiple SPLC501C chips used, slave chips must supplied display timing signals (FR, from master chip(s). signals. Table shows status
Operating Mode Slave `L'):
internal oscillator circuit enabled (CLS `H') internal oscillator circuit
Input Input
Input Input
Input Input
Table Operating Mode Master `H'):
disabled (CLS `L')
5.10. Liquid Crystal Driver Circuits
Output Output Output Input Output Output These 197-channel (SPLC501C) that generates four voltage levels driving liquid crystal. combination display data, scan signals, signal produces liquid crystal drive voltage output. Figure shows examples output waveform.
internal oscillator circuit enabled (CLS `H') internal oscillator circuit disabled (CLS `L')
COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15
COM0
COM1
COM2
SEG0
SEG1
SEG2
COM0-SEG0
COM0-SEG1
Figure
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5.11. Power Supply Circuits
power supply circuits low-power consumption power supply circuits that generate voltage levels liquid crystal drivers. They comprise Booster circuits, voltage regulator circuits, They only enabled master Booster circuit control Voltage regulator circuit regulator circuit) control Voltage follower circuit (V/F circuit) control power supply circuits turn Booster circuits, voltage follower circuits. operation.
Table Control Details Each Power Control Command Item Status
voltage regulator circuits, voltage follower circuits independently through Power Control command. Consequently, possible make external power supply internal power supply function parallel. Table shows Power Control Command 3-bit data control functions, Table shows reference combinations.
Table Reference Combinations Settings Step-up circuit
regulator circuit
circuit
External voltage input
Step-up Voltage SystemTerminal
Only internal power supply used Only regulator circuit circuit used Only circuit used Only external power supply used
VSS2 VOUT, VSS2 VSS2
Used Open Open Open
Note1: `step-up system terminals' refer CAP1P, CAP1N, CAP2P, CAP2N, CAP3N. Note2: While other combinations, shown above, also possible, these combinations recommended because they have practical use.
5.11.1. step-up voltage circuits
Using step-up voltage circuits equipped within SPLC501C chips, possible product Quad step-up, Triple step-up, Double step-up VSS2 voltage levels. Quad step-up: Connect capacitor between CAP1P CAP1N, between CAP2P CAP2N, between CAP1P CAP3N, between VSS2 VOUT, produce voltage level negative direction VOUT terminal that times voltage level between VSS2. Triple step-up: Connect capacitor between CAP1P CAP1N, between CAP2P CAP2N between VSS2 VOUT, short between CAP3N VOUT produce voltage level negative direction VOUT terminal that times voltage difference between VSS2. Double step-up: Connect capacitor between CAP1P CAP1N, between VSS2 VOUT, leave CAP2P open, short between CAP2N, CAP3N VOUT produce voltage negative direction VOUT terminal that twice voltage between VSS2.
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step-up voltage relationships shown Figure
VSS2 VOUT CAP3N CAP1P CAP1N CAP2N CAP2P step-up voltage circuit VSS2 VOUT VSS2 -12V step-up voltage relationships step-up voltage relationships step-up voltage relationships SPLC501C VSS2 VOUT CAP3N CAP1P CAP1N CAP2N CAP2P step-up voltage circuit SPLC501C VSS2 VOUT CAP3N CAP1P CAP1N CAP2N OPEN CAP2P step-up voltage circuit SPLC501C
VSS2 VOUT VSS2
VSS2 VOUT=2 VSS2 -10V
Figure Note: VSS2 voltage range must that VOUT terminal voltage does exceed absolute maximum rate.
5.11.2. voltage regulator circuit
step-up voltage generated VOUT outputs liquid crystal driver voltage through voltage regulator circuit. Because SPLC501C chips have internal high-accuracy fixed voltage power supply with 64-level electronic volume function internal resistors voltage regulator, systems constructed without having include high-accuracy voltage regulator circuit components. Moreover, SPLC501C,
Internal VREG
162) VREG]
Equation
(constant voltage supply electronic volume)
types thermal gradients have been prepared VREG options: approximately -0.05%/ external input (supplied terminal).
Internal
5.11.2.1. When voltage regulator internal resistors used
Through voltage regulator internal resistors electronic volume function, liquid crystal power supply voltage, controlled commands alone (without adding external resistors), making possible adjust liquid crystal display brightness. voltage calculated using equation over range where VOUT VREG IC-internal fixed voltage supply, voltage shown Table
Figure
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Table Equipment Type Thermal Gradient Units VREG Units
5.11.2.2. When external resistance used (i.e., Voltage Regulator Internal Resistors used)
liquid crystal power supply voltage also without using voltage regulator internal resistors (IRS terminal `L') adding resistors between between respectively. When this done,
Internal Power Supply External Input
-0.05
[%/]
-2.1
level possible levels electronic volume
function depending data 6-bit electronic volume register. Table shows value depending electronic volume register settings.
Table
electronic volume function makes possible adjust brightness liquid crystal display controlling liquid crystal power supply voltage through commands. range where VOUT voltage calculated using equation based external resistance, Rb'.
VREG
162) VREG]
Equation (fixed voltage power supply electronic volume)
External resistor
Rb/Ra voltage regulator internal resistor ratio, different levels through voltage regulator internal resistor ratio command. Rb/Ra) ratio assumes values shown Table depending 3-bit data settings voltage regulator internal resistor ratio register. voltage regulator internal resistance ratio register value Rb/Ra) ratio (Reference value)
Table SPLC501C Register Equipment Type Thermal Gradient [Units:
Figure
External resistor
Setup example: When selecting -7.0V SPLC501C model where temperature gradient -0.05%/. When central value electron volume register (DB5, DB4, DB3, DB2, DB1, DB0) then VREG -2.1V. According equation B-1:
-0.05
VREG External Input
7.0V -2.1)
Equation
Moreover, when value current running through 5µA,
1.4M
Equation
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Consequently, equations B-3,
5.11.2.3. When external resistors used (i.e. Voltage Regulator Internal Resistors Used).
When external resistor described above used, adding variable resistor makes possible perform fine adjustments Rb', liquid crystal drive voltage this case, electronic volume function makes possible control liquid crystal power supply voltage commands adjust liquid crystal display brightness. range where VOUT voltage calculated equation
3.12
340k 1060k
this time, voltage variable range notch width, based electron volume function, given Table
Table Min. Typ. Max. Units
below based (variable resistor) settings, where subjected fine adjustments (R2). -8.6 levels) -7.0 -5.3
Variable Range Notch width
(central value) level)
[mV]
(VREG)
162) VREG]
Equation (fixed voltage power supply electronic volume)
External resistor
External resistor
External resistor
Figure
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Setup example: When selecting -5.0V -9.0V (using SPLC501C model where temperature gradient -0.05%/.
5.11.3. liquid crystal voltage generator circuit
voltage produced resistive voltage divider within produced voltage levels required liquid crystal driving. Moreover, when voltage follower changes impedance, provides liquid crystal drive circuit. bias bias SPLC501C selected.
When central value electronic volume register (DB5, DB4, DB3, DB2, DB1, DB0)
-2.1V
according equation C-1, when order make -9.0V,
5.12. High Power Mode
power supply circuit equipped SPLC501C chips very power consumption (normal mode: `H'). However, LCDs panels with large loads, this low-power power supply cause display quality degrade. When this occurs, setting
Equation
9.0V (-2.1)
When order make -5.0V,
terminal (high power mode) improve quality display. recommend that display checked actual equipment determine whether this mode. Moreover, improvement display inadequate even after high power mode been set, necessary liquid crystal drive power supply externally.
5.0V (-2.1)
Equation
Moreover, when current flowing 5µA, 1.4M Equation
5.13. Internal Power Supply Shutdown Command Sequence
sequence shown Figure recommended shutting down internal power supply. First place power supply
With this, according equation C-2, C-4, 264k 211k 925k this time, voltage variable range notch width based electron volume function shown Table
Table Min. Typ. Max. Units
power saver mode then turn power supply OFF.
Sequence Step1
Details (Command, status) Display
Command address Power saver commands (compound)
Step2
Display points
Internal power supply
Figure
Variable Range Notch width
-8.6 levels)
-7.0 (central value)
-5.3 level)
[mV]
Note1: When voltage regulator internal resistors electronic volume function used, necessary least voltage regulator circuit voltage follower circuit operating mode using power control commands. Moreover, necessary provide voltage from VOUT when Booster circuit OFF. Note2: terminal enabled only when voltage regulator internal resistors used (i.e. terminal `L'). When voltage regulator internal resistors used (i.e. when terminal `H'), terminal left open. Note3: Because input impedance terminal high, necessary take into consideration short leads, shield cables, etc. handle noise.
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5.14. Reference Circuit Examples
Figure shows reference circuit examples.
5.14.1.1. When using step-up circuit, voltage regulating circuit circuit
When voltage regulator internal resistor used. Example where VSS2 VSS, with step-up When voltage regulator internal resistor used. Example where VSS2 VSS, with step-up
VSS2 VOUT CAP3CAP1+
VSS2 VOUT CAP3CAP1+ CAP1CAP2+ CAP2V5
CAP1CAP2+ CAP2V5
SPLC501C
Figure
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5.14.1.2. When voltage regulator circuit circuit alone used
When voltage regulator internal resistor used. When voltage regulator internal resistor used.
VSS2 VOUT CAP3N External power supply CAP1P CAP1N CAP2P CAP2N
VSS2 VOUT External power supply CAP3N CAP1P CAP1N CAP2P CAP2N
SPLC501C
Figure
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When circuit alone used. When built-in power used.
VSS2 VOUT CAP3N External power supply CAP1P CAP1N CAP2P
VSS2 VOUT CAP3N CAP1P CAP1N CAP2P
SPLC501C
CAP2N
CAP2N External power supply
Figure
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SPLC501C
5.15. Reset Circuit
When RESET input comes level, these LSIs return default state. Display Normal display select: Normal (ADC command `L') Power control register: (DB2, DB1, DB0) Serial interface internal register data clear power supply bias rate: SPLC501C.1/9 bias All-indicator lamps-on (All-indicator lamps ON/OFF command `L') Power saving clear voltage regulator internal resistors, connected. 10). Output conditions terminals SEG: VDD, COM: 11). Read modify write 12). Static indicator Static indicator register: (DB1, DB2) 13). Display start line first line 14). Column address Address 15). Page address Page 16). Common output status normal 17). voltage regulator internal resistor ratio mode clear 18). Electronic volume register mode clear Electronic volume register: (DB5, DB4, DB3, DB2, DB1, DB0) 19). Test mode clear 20). Driving mode register: (DB7, DB6)=(0, other hand, when reset command used, only above default settings from executed. When power After turned internal state becomes unstable, necessary initialize using RESET terminal. 8080 interface, commands launched inputting pulse terminal reading, inputting pulse terminal writing. input terminal. 6800 Series Their default states follows: supply short-circuits when RESET `L.'. While RESET `L,' oscillator display timing generator stop, terminals fixed `H'. terminals affected.
level output means that When
from output terminals.
internal resistor connected between
internal liquid crystal power supply circuit used other models SPLC501C, necessary that RESET when external liquid crystal power supply turned While RESET
`L,' oscillator works, display timing generator stops, terminals fixed `H'. terminals affected.
COMMANDS
SPLC501C chips identify data signals combination A0P, (EP), (RWP) signals. Command
interpretation execution depend external clock, rather performed through internal timing only, thus processing fast enough that normally busy check required.
interface, interface placed read mode when signal placed write mode when Then, command Consequently, signal input terminal.
launched inputting high pulse terminal (See `10. Timing Characteristics' regarding timing). 6800 Series interface different from 80x86 Series interface that explanation commands display commands status read display data read (EP) becomes `1(H)'. explanations below, commands explained using 8080 Series interface example. When serial interface selected, data inputted sequence starting from DB7.
initialization, each input terminal should controlled normally. Moreover, when control signal from high impedance, over-current flow After applying current, necessary take proper measures prevent input terminal from getting into high impedance state. internal liquid crystal power supply circuit used SPLC501C, necessary that RESET when external liquid crystal power supply turned This function
discharge when RESET `L,' external power
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<Explanation Commands>
6.1. Display ON/OFF
This command turns display OFF.
Setting
Display Display
When display command executed when display points mode, power saver mode entered. power saver details.
section
6.2. Display Start Line
This command used specify display start line address display data shown Figure explanation this function `The Line Address Circuit'.
Line Address
further details,
6.3. Page Address
This command specifies page address corresponding address when accesses display data (see Figure Specifying page address column address enables access desired display data RAM.
Page Address
Changing page address does accompany change status display. page address circuit Function Description (page detail.
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6.4. Column Address
This command specifies column address display data shown Figure column address split into sections (the higher bits lower bits) when (fundamentally, continuously). Each time display data accessed, column address automatically incremented (+1),
making possible continuously read from/write display data. 83H. details.
Column Address
column address increment topped
This does change page address continuously.
function explanation `The Column Address Circuit'
High bits bits
6.5. Status Read
BUSY
ON/OFF
RESET
BUSY
When BUSY `1', indicates that either processing occurring internally reset condition process. condition.
While
chip does accept commands until BUSY `0', cycle time satisfied, there need check BUSY This shows relationship between column address segment driver. Reverse (column address 131-n$SEG Normal (column address n$SEG (The command switches polarity.) ON/OFF ON/OFF: indicates display ON/OFF state. Display Display (This display ON/OFF command switches polarity.) RESET This indicates that chip process initialization either because RESET signal because reset command. Operating state Reset progress
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6.6. Display Data Write
This command writes 8-bit data specified display data address. Since column address automatically incremented
after write, write display data.
Write data
6.7. Display Data Read
This command reads 8-bit data from specified display data address. Since column address automatically dummy read required immediately
after column address being set. registers.
function explanation
"Display Data RAM" explanation accessing internal When serial interface used, reading display data becomes unavailable.
incremented after read, continuously read multiple-word data.
Read Data
6.8. Select (Segment Driver Direction Select)
This command reverse correspondence between display data column address segment driver output. Thus, sequence segment driver output pins reversed command.
detail.
Increment column address `1')
accompanying reading writing display data done according column address indicated Figure
column address circuit (page
Setting
Normal Reverse
6.9. Display Normal/Reverse
This command reverse unlit display without overwriting contents display data RAM. When this
Setting
done, display data contents maintained.
Data voltage (normal Data voltage (reverse)
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6.10. Display Points ON/OFF
This command makes possible force display points regardless content display data RAM. contents display data maintained when this done.
Setting
command command.
takes
priority
over
display
normal/reverse
This
Normal display mode Display points
When display mode, executing display points command will place display power save mode.
more details, Power Save Section.
6.11. Bias
This command selects voltage bias ratio liquid crystal display.
Select Status SPLC501C
bias bias
6.12. Read/Modify/Write
This command used paired with `END' command. Once command inputted, column address returns address when read/modify/write command entered. This function makes possible reduce load when there repeating data changes specified display region, such when there blanking cursor. this command been inputted, display data read command does change column address, only display data write command increment (+1) column address. remains until command inputted.
This mode
When
Note: Even read/modify/write mode, other commands aside from display data read/write commands also used. command cannot used.
However, column address
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6.12.1. sequence cursor display
Page address
Column address
Read/modify/write
Dummy read Data read Data process Data write
Change complete?
Figure
6.13.
This command releases read modify write mode, returns column address address when mode entered.
Return Column address
Read/modify/write mode
Figure
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6.14. RESET
This command initializes display start line, column address, page address, common output mode, voltage regulator internal resistor ratio, electronic volume, static indicator reset, read/modify/write mode test
mode released.
There impact display data RAM. reset
function explanation "Reset" details.
operation performed after reset command entered.
initialization must done through applying reset signal RESET terminal when power supply applied.
6.15. Common Output Mode Select
This command select scan direction output terminal. details, function explanation "Common
Select Status SPLC501C
Output Mode Select Circuit".
Normal Reverse
COM0 COM63
COM63 COM0
Note: *Disabled
6.16. Power Controller
This command sets power supply circuit functions.
Selected Mode
function explanation "The Power Supply Circuit" more details.
Booster circuit: Booster circuit: Voltage regulator circuit :OFF Voltage regulator circuit: Voltage follower circuit: Voltage follower circuit:
Note: Display command masks power control circuits
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6.17. Voltage Regulator Internal Resistor Ratio
This command sets voltage regulator internal resistor ratio. Circuits".
Setting
details, function explanation "The Power Supply
Small
Large
6.18. Electronic Volume (Double Byte Command)
This command makes possible adjust brightness liquid crystal display controlling liquid crystal drive voltage through output from voltage regulator circuits internal liquid crystal power supply. This command bytes command used pair with electronic volume mode command electronic volume register command, both commands must issued after other.
6.18.1. electronic volume mode
When this command input, electronic volume register command becomes enabled. Once electronic volume mode Once electronic volume been set, other command except electronic volume register command used. register command been used data into register, electronic volume mode released.
6.18.2. Electronic volume register
using this command bits data electronic volume register, liquid crystal driving voltage, assumes voltage levels.
electronic volume mode released after electronic volume register been set.
When this command input,
Note: *Inactive
Small
Large
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6.18.3. electronic volume register sequence
electrodes connected terminal, other connected terminal.
Electronic volume mode
different pattern
recommended static indicator electrodes than dynamic drive electrodes. pattern close, result deterioration liquid crystal electrodes.
Electronic volume register Electronic volume mode clear Changes complete?
Figure
static indicator command double byte command paired with static indicator register command, thus must execute after other. single byte command. static indicator command
6.19.1. Static indicator ON/OFF
When static indicator command entered, static indicator register command enabled. Once static This
6.19. Static Indicator (Double Byte Command)
This command controls static drive system indicator display. static indicator display controlled this command only, independent from other display control commands. used when static indicator liquid crystal drive
indicator command entered, other command aside from static indicator register command used. indicator register command. mode cleared when data register static
This
Static Indicator
6.19.2. Static indicator register
This command sets bits data into static indicator register, used static indicator into blinking mode.
Static Indicator
(blinking approximately second intervals) (blinking approximately second intervals) (constantly
Note: *Disabled
6.20. Page Blinking (Double Byte Command) 6.20.1. page blinking mode
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6.20.2. Page blinking register
either will corresponding PAGE0 PAGE7 blink.
Blinking Page
PAGE blink PAGE blink PAGE blink PAGE blink
6.20.3. Page blinking indicator register sequence
6.21. Driving Mode (Double Byte Command)
This command makes possible reduce power consumption instruction command using different liquid crystal panel. User select appropriate mode their liquid crystal panel display pattern. driving capability sequence Mode1>Mode2>Mode3>Mode4, current
Page Blinking mode
Blinking Page (Page Blinking mode clear) Changes complete?
Figure
consumption.
6.21.1. driving mode
6.21.2. Mode selection register
Driving Duty Selection
Mode Mode Mode Mode
Note1: bits must fill Note2: Mode2 (DB7, DB6)=(0,0) default. Note3: Driving capability Mode1>Mode2>Mode3>Mode4.
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6.22. Power Save (Compound Command)
When display points performed while display mode, power saver mode entered therefore, reduces great amount power. power saver mode different modes: sleep mode standby mode. When static indicator OFF, sleep mode entered. When static indicator standby mode entered. sleep mode standby mode, display data saved operating mode that effect before power saver mode initiated, still able access display data RAM. Refer figure power save sequence.
Static indicator
Static indicator
Power saver (compound command) Sleep mode Power save (compound command) Display points command Static indicator bytes command) Sleep mode cancel
Figure
Standby mode
Power save (Display points command)
Standby mode cancel
6.22.1. Sleep mode
This stops operations display system, long there accesses from MPU, consumption current reduced value close static current. modes during sleep mode follows: oscillator circuit power supply circuit halted. liquid crystal drive circuits halted, segment common drive outputs output level. internal
Note1: When external power supply used, recommended that functions external power supply circuit should stopped when power saver mode started. example, when various levels liquid crystal drive voltage provided external resistive voltage dividers, recommended that circuit added order electrical current flowing through resistive voltage divider circuit when power saver mode effect. SPLC501C chips have liquid crystal display blanking control
When reset command performed while standby mode, system enters sleep mode.
6.22.2. Standby mode
duty display system operations halted only static drive system indicator continues operate, providing minimum required consumption current static drive. internal modes following states during standby mode. power supply circuits halted. circuit continues operate. duty drive system liquid crystal drive circuits halted segment common driver outputs level. static drive system does operate. oscillator
terminal
This terminal enters state when power Using output possible
saver mode launched.
stop function external power supply circuit. Note2: When master turned oscillator circuit operable immediately after power
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6.23.
Non-Operation Command
6.24. TEST
This command chip testing. Please applying signal RESET input reset command using NOP. test command used accident, cleared
Note: SPLC501C chips maintain their operating modes until some conditions occurred change them. measurement prevent noise from influencing chip. prevent effects.
Consequently, excessive external noise, etc.,
change internal modes SPLC501C chip. Thus, packaging system design, necessary suppress noise take Moreover, recommended that operating modes refreshed periodically
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6.25. Table Table SPLC501C Commands
Command Command Code Function
Display ON/OFF
display ON/OFF OFF, Sets display display start line address Sets display page address Sets most significant bits display column address. least significant bits display column address.
Display start line Page address Column address upper Column address lower Status read Display data write Display data read select
Display start address Page address Most significant column address
Least significant column address
Status
Reads status data Writes display Reads from display
Write data Read data
Sets display address output correspondence normal, 1:reverse Sets display normal/ reverse normal, 1:reverse Display points normal display points Sets driver voltage bias ratio SPLC501C.0:1/9, 1:1/7 Column address increment write: read:
Display normal/reverse 10). Display ON/OFF 11). bias 12). Read/modify/write points
13). 14). Reset 15). Common output mode select 16). Power control 17). voltage regulator internal resistor ratio 18). Electronic volume mode Electronic volume register
Clear read/modify/write Internal reset Select output scan direction normal direction, reverse direction
Operating mode Resistor ratio
Select internal power supply operating mode Select internal resistor ratio (Rb/Ra) mode
output voltage electronic volume register
Electronic volume value
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Command
Command Code
Function
19). Static indicator ON/OFF Static indicator Register 20). Page Blink Page selection 21). Driving Mode Mode selection 22). Power saver 23). 24). Test
OFF, flashing mode
Mode
blinking page blinking, normal display driving mode register Driving capability (D1, D0): (1,1)>(0,0)>(0,1)>(1,0) Display display points compound command
Command non-operation Command test. this command
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COMMAND DESCRIPTION
7.1. Instruction Setup: Reference (Reference) 7.1.1. Initialization
Note: When power applied, driving non-selective potentials (SEG pin) (COM pin) output through driving output pins COM. When electric charge remaining smoothing capacitor connecting between driving voltage output pins pin, picture display become totally dark instantaneously when power turned avoid occurrence such failure, recommend
When power stabilized Arrange start power saver within after releasing reset state. Execute procedures from turning power setting power control 5ms. Turn VDD-VSS power keeping RESET "L".
When built-in power being used immediately after turning power:
following flow when turning power.
Release reset state. (RESET "H")
When built-in power being used immediately after turning power:
Turn VDD-VSS power keeping RESET "L".
Function setup command input(User setup) (11) bias setting selection (15) Common output state selection Initialized state (Default)
Power saver START (multiple commands)
When power stabilized
Release reset state. (RESET "H")
Function setup command input(User setup) (17) Setting built-in resistance radio regulation voltage (18) Electronic volume control
Initialized state (Default) Arrange execute procedures from releasing reset state through setting power control within 5ms. Execute procedures from turning power setting power control 5ms.
Function setup command input(User setup) (11) bias setting selection (15) Common output state selection
Power saver Arrange start power control setting within after turning power saver.
Function setup command input(User setup) (16) Power control setting
Function setup command input(User setup) (17) Setting built-in resistance radio regulation voltage (18) Electronic volume control
This concludes initialization
Function setup command input(User setup) (16) Power control setting
Figure Note1: target time varied depending panel characteristics
This concludes initialization
capacitance smoothing capacitor. equipment.
Therefore,
Figure Note1: target time varied depending panel characteristics capacitance smoothing apacitor. equipment. Note2: Refer respective sections paragraphs listed below. *1:Description functions; Reset circuit *2:Command description; bias setting *3:Command description; selection *4:Command description; Common output state selection *5:Description functions; Power circuit Command description; Setting built-in resistance radio regulation voltage *6:Description functions; Power circuit Command description; Electronic volume control *7:Description functions; Power circuit Command description; Power control setting. Therefore,
suggest users conduct operation check using actual
Note2: Refer respective sections paragraphs listed below. *1:Description functions; Resetting circuit *2:Command description; bias setting *3:Command description; selection *4:Command description; Common output state selection *5:Description functions; Power circuit Command description; Setting built-in resistance radio regulation voltage *6:Description functions; Power circuit Command description; Electronic volume control *7:Description functions; Power circuit Command description; Power control setting *8:The power saver state either sleep state stand-by state. Command description; Power saver START (multiple commands)
suggest users conduct operation check using actual
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7.1.2. Data display
initialization
Function setup command input (User setup) Display start line Page address Column address Function setup command input (User setup) Display data write Function setup command input (User setup) Display ON/OFF data display
Figure
Notes: Reference items Command Description; Display start line *10: Command Description; Page address *11:Command Description; Column address *12: Command Description; Display data write *13: Command Description; Display ON/OFF Avoid displaying data data display start(when display white.
7.1.3. Power
Optional status Function setup command input (User setup) (20) Power save Reset active( RESET "L") time (tL) from reset active turning Power longer than time (tH) when potential becomes below threshold voltage (approximately panel. refer <Reference Data> this event. When long, insert resistor between reduct
power
Figure Note: Reference items *14:The logic circuit this IC's power supply controls driver power supply Therefore, power supply when power supply still residual voltage, driver (COM. SEG) output uncontrolled voltage. When turning power, observe following basic procedures: After turning internal power supply, make sure that potential become below threshold voltage panel, then turn this IC's power supply (VDD VSS). Refer Description Function, Power Circuit" more information. *15: After inputting power save command, sure reset function using RESET terminal until power supply turned off. Refer Command Description, (20) Power Save" more information.
7.2. Precautions Turning Power 7.2.1. Power save (the powers (VDD off.) Reset input Power (VDD VSS)
Observe When irregular display occur. according software. driver's discharging capacity. determined according external capacity (smoothing capacity
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Power save Reset Power RESET
Since power (VDD-VSS) off, output comes fixed.
About Below Panel
Figure
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ELECTRICAL SPECIFICATIONS
8.1. Absolute Maximum Ratings
(Unless otherwise noted,
Parameter Symbol Conditions Unit
Power Supply Voltage Power supply voltage (VDD standard) With Triple step-up With Quad step-up Power supply voltage (VDD standard) Power supply voltage (VDD standard) Input voltage Output voltage Operating temperature Storage temperature Bare chip
VSS2 VOUT TOPR TSTR
-0.3 -7.0 +0.3 -4.0 +0.3 -3.0 +0.3 -12.0 +0.3 +0.3 -0.3 +0.3 -0.3 +0.3 +125
VSS2,V1
VOUT
System (MPU) side
SPLC501C chip side
Figure Notes Cautions: VSS2, VOUT relative reference. Insure that voltage levels always such that VDDV1V2V3V4V5. Permanent damage result used outside absolute maximum ratings. have negative impact reliability well. Moreover, recommended that normal operation chip used electrical characteristic conditions, outside these conditions only result malfunctions LSI,
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8.2. Characteristics
(Unless otherwise specified, 3.0V±10%,
Item Symbol Condition Rating Min. Typ. Max. Units Applicable
Operating Voltage
Recommended Voltage Possible Operating Voltage
(Relative VDD) (Relative VDD) (Relative VDD) (Relative VDD) (Relative VDD) -3.3 -6.0 -12.0 -0.5mA 0.5mA (Relative VDD) -12V -8.0V -1.0 -3.0 -12V (Relative VDD) 1.0MHz SPLC501C
0.01 0.01
-2.7 -1.8 -4.5
VDD*1 VDD*1 VSS2 VSS2 V5*2 SEGn COMn*7 VSS, VSS2
Operating Voltage
Recommended Voltage Possible Operating Voltage
VSS2 VSS2 VIHC VILC VOHC VOLC ISSQ fOSC
Operating Voltage
Possible Operating Voltage Possible Operating Voltage Possible Operating Voltage
High-level Input Voltage Low-level Input Voltage High-level Input Voltage Low-level Input Voltage Input leakage current Output leakage current Liquid Crystal Driver Resistance Static Consumption Current Output Leakage Current Input Terminal Capacitance Oscillator Frequency Internal Oscillator External Input
Item
Symbol
Condition
Rating Min. Typ. Max.
Units
Application
Input Voltage
VSS2 VSS2 VOUT VOUT VREG0
With Triple (Relative VDD) With Quad (Relative VDD) (Relative VDD) (Relative VDD) (Relative VDD) (Relative VDD) -0.05%/
-4.0 -3.0 -2.28
-2.22
-2.4 -2.4 -6.0 -4.5 -2.16
VSS2 VSS2 VOUT VOUT
Internal Power
Supply Setup-up output voltage Circuit Voltage regulator Circuit Operating Voltage Voltage Follower Circuit Operating Voltage Base Voltage
Note: Dynamic Consumption Current (1), During Display, with Internal Power Supply OFF. Current consumed total when external power supply used.
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8.3. Display Pattern
Item Symbol Condition Rating Min. Typ. Max. Units Notes
SPLC501C
IDD(1)
5.0V, -11V 3.0V, -11V
12.6
8.4. Display Pattern Checker
Item Symbol Condition Rating Min. Typ. Max. Units Notes
SPLC501C
IDD(1)
5.0V, -11V 3.0V, -11V
Note: Dynamic Consumption Current (2), During Display, with Internal Power Supply
8.5. Display Pattern Checker
Item Symbol Condition Rating Min. Typ. Max. Units Notes
5.0V, Double step-up Normal Mode SPLC501C IDD(2) voltage. -9.0V 3.0V, Quad High-Power Mode
step-up Normal Mode High-Power Mode
voltage.
Note: Duty Selection register
-9.0V
Item
Symbol
Condition
Rating Min. Typ. Max.
Units
Notes
Sleep Mode SPLC501C Standby Mode SPLC501C
IDDS1 IDDS2
0.01
Item
fOSC
fOSC 4x65
When internal oscillator circuit used
SPLC501C When internal oscillator circuit used
External input (fCL)
References items market with While broad range operating voltages guaranteed, performance cannot guaranteed there sudden fluctuations voltage while being accessed. operating voltage range system system applied when external power supply being used. A0P, DB5, (SCL), (SI), (EP), (RWP), CS2, CLS, C86, IRS, terminals. DB7, FRS, terminals. A0P, (EP), (RWP), CS2, CLS, C86, IRS, terminals. Applies when DB5, (SCL), (SI), terminals high impedance state.
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These resistance values when 0.1V voltage applied between output terminal SEGn COMn various power supply terminals (V1, V4). These specified operating voltage range. 0.1V/ (Where current that flows when 0.1V applied while power supply ON.) relationship between oscillator frequency frame rate frequency. voltage regulator circuit regulates within operating voltage range voltage follower. This internal voltage reference supply voltage regulator circuit. VREG options: approximately -0.05%/C, external input. *11, indicates current consumed alone when internal oscillator circuit display turned SPLC501C biased. access from MPU. value model having VREG option temperature gradient -0.05%/C when voltage regulator internal resistor used. Does include current panel capacity wiring capacity. Applicable only when there SPLC501C, temperature range come three types
8.6. Timing Characteristics 8.6.1. System read/write characteristics (For 8080 Series MPU)
tAW8 (CS2="1") tCYC8 tCCLR, tCCLW tCCHR tCCHW tDS8 (Write) tACC8 (Read) tOH8 tDS8 tAH8
(VDD 4.5V 5.5V,
Item Signal Symbol Condition Rating Min. Max. Units
Address hold time Address setup time System cycle time Control pulse width Control pulse width Control pulse width Control pulse width Data setup time Address hold time access time Output disable time
tAH8 tAW8 tCYC8 tCCLW tCCLR tCCHW tCCHR tDS8
100pF
tDH8 tACC8 tOH8
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(VDD 2.7V 4.5V,
Item Signal Symbol Condition Rating Min. Max. Units
Address hold time Address setup time System cycle time Control pulse width Control pulse width Control pulse width Control pulse width Data setup time Address hold time access time Output disable time
tAH8 tAW8 tCYC8 tCCLW tCCLR tCCHW tCCHR tDS8
100pF
tDH8 tACC8 tOH8
(VDD 2.4V 2.7V,
Item Signal Symbol Condition Rating Min. Max. Units
Address hold time Address setup time System cycle time Control pulse width Control pulse width Control pulse width Control pulse width Data setup time Address hold time access time Output disable time
tf)(tCYC8 tCCLR tCCHR) specified.
tAH8 tAW8 tCYC8 tCCLW tCCLR tCCHW tCCHR tDS8
1000 100pF
tDH8 tACC8 tOH8
Note1: input signal rise time fall time (tr, specified less. When system cycle time extremely fast, tf)(tCYC8 tCCLW tCCHW) Note2: timing specified using reference. Note3: tCCLW tCCLR specified overlap between being 'H') being level.
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8.6.2. System read/write characteristics (6800 series MPU)
tAW6 (CS2="1") tCYC6 tEWHR, tEWHW tEWLR tEWLW tDS6 (Write) tACC6 (Read) tOH6 tDH6 tAH6
(VDD 4.5V 5.5V,
Item Signal Symbol Condition Rating Min. Max. Units
Address hold time Address setup time System cycle time Data setup time Data hold time Access time Output disable time Enable pulse time Enable pulse time Read Write Read Write
tAH6 tAW6 tCYC6 tDS6 tDH6 tACC6 tOH6 tEWHR tEWHW tEWLR tEWLW 100pF
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(VDD 2.7V 4.5V,
Item Signal Symbol Condition Rating Min. Max. Units
Address hold time Address setup time System cycle time Data setup time Data hold time Access time Output disable time Enable pulse time Enable pulse time Read Write Read Write
tAH6 tAW6 tCYC6 tDS6 tDH6 tACC6 tOH6 tEWHR tEWHW tEWLR tEWLW 100pF
(VDD 2.4V 2.7V,
Item Signal Symbol Condition Rating Min. Max. Units
Address hold time Address setup time System cycle time Data setup time Data hold time Access time Output disable time Enable pulse time Enable pulse time Read Write Read Write
tAH6 tAW6 tCYC6 tDS6 tDH6 tACC6 tOH6 tEWHR tEWHW tEWLR tEWLW 100pF
1000
Note1: input signal rise time fall time (tr, specified less. When system cycle time extremely fast, tf)(tCYC6 tEWLW tEWHW) tf)(tCYC6 tEWLR tEWHR) specified. Note2: timing specified using reference. Note3: tEWLW tEWLR specified overlap between being (CS2 'H')
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8.6.3. serial interface
tCSS (CS2="1")
tCSH
tSAS
tSAH
tSCYC tSLW tSHW tSDS tSDH
(VDD 4.5V 5.5V,
Item Signal Symbol Condition Rating Min. Max. Units
Serial Clock Period pulse width pulse width Address setup time Address hold time Data setup time Data hold time CS-SCL time
tSCYC tSHW tSLW tSAS tSAH tSDS tSDH tCSS tCSH
(VDD 2.7V 4.5V,
Item Signal Symbol Condition Rating Min. Max. Units
Serial Clock Period pulse width pulse width Address setup time Address hold time Data setup time Data hold time CS-SCL time
tSCYC tSHW tSLW tSAS tSAH tSDS tSDH tCSS tCSH
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(VDD 2.4V 2.7V,
Item Signal Symbol Condition Rating Min. Max. Units
Serial Clock Period pulse width pulse width Address setup time Address hold time Data setup time Data hold time CS-SCL time
tSCYC tSHW tSLW tSAS tSAH tSDS tSDH tCSS tCSH
Note1: input signal rise fall time (tr, specified less. Note2: timing specified using standard.
8.6.4. Display control output timing
(OUT) tDFR
(VDD 4.5V 5.5V,
Item Signal Symbol Condition Rating Min. Typ. Max. Units
delay time
tDFR
50pF
(VDD 2.7V 4.5V,
Item Signal Symbol Condition Rating Min. Typ. Max. Units
delay time
tDFR
50pF
(VDD 2.4V 2.7V,
Item Signal Symbol Condition Rating Min. Typ. Max. Units
delay time
tDFR
50pF
Note1: Valid only when master mode selected. Note2: timing based VDD.
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8.6.5. Reset timing
RESET
Internal status During reset Reset complete
(VDD 4.5V 5.5V,
Item Signal Symbol Condition Rating Min. Typ. Max. Units
Reset time Reset pulse width
(VDD 2.7V 4.5V,
Item Signal Symbol Condition Rating Min. Typ. Max. Units
Reset time Reset pulse width
(VDD 2.4V 2.7V,
Item Signal Symbol Condition Rating Min. Typ. Max. Units
Reset time Reset pulse width
Note: timing specified with standard.
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8.7. Interface (Reference Examples)
SPLC501C connected either Series MPUs 68000 Series MPUs. Moreover, serial interface possible operate SPLC501C chips with fewer signal lines. display area enlarged using multiple SPLC501C chips. When this done, chip select signal used select individual access.
8.7.1. 8080 series MPUs
IORQ RESET RESET Decoder
RESET
SPLC501C
Figure
8.7.2. 6800 series MPUs
RESET RESET Decoder
RESET
SPLC501C
Figure
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8.7.3. Using serial interface
Decoder
Port Port RESET RESET
RESET
SPLC501C
Figure
8.8. Connections Between Drivers (Reference Example)
liquid crystal display area enlarged with ease through multiple SPLC501C chips. same equipment type.
8.8.1. SPLC501C (Master)<->SPLC501C (Slave)
SPLC501C Master Output Input
SPLC501C Slave
Figure
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8.9. Connections Between Drivers (Reference Examples)
liquid crystal display area enlarged with ease through multiple SPLC501C chips. same equipment type, composition these chips.
8.9.1. Single-chip structure
Dots
SPLC501C Master
Figure
8.10. VLCD Voltage (Voltage between relationship Voltage Regulator Internal Resistor Ratio Register Electronic Volume Control Register
14.000 12.000 10.000 8.000 6.000
voltage
4.000 2.000 0.000
regulator internal resistance ratio registers (D2,
Note: External VOUT Power Supply.
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PACKAGE/PAD LOCATIONS
9.1. Assignment
SEG131 SEG130 SEG129 SEG2 SEG1 SEG0
COM55 COM56 COM57
COM32 COM33 COM34
COMS1 COM0 COM1
COM22 COM23 COM24
COM58 COM59 COM60 COM61 COM62 COM63 COMS2 TEST RESET
Bump Pitch
Bump Size
Note1: Chip size included scribe line. Note2: ensure that functions properly, please bond VDD, VSS, AVDD AVSS pins. Note3: 0.1µF capacitor between should placed close possible. Note4: Gold Bump Height 17µm.
9.2. Ordering Information
Product Number Package Type
SPLC501C-nnnnV-C
Note1: Code number (nnnnV) assigned customer. Note2: Code number (nnnn 0000 9999); version
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VSS2 VSS2 VSS2 VSS2 VOUT VOUT VOUT CAP3N CAP3N CAP1P CAP1P CAP1N CAP1N CAP2N CAP2N CAP2P CAP2P TEST4 TEST3 TEST5 TEST6 COM31 COM30 COM29 COM28 COM27 COM26 COM25
Chip Size: 8290µm 1720µm This substrate should connected
60µm(Min.)
Chip form with Gold Bump
NOV. 2001 Version:
SPLC501C
9.3. Locations
Name Name
COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 COM51 COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63 COMS2 TEST CS1N RESET
-4020 -4020 -4020 -4020 -4020 -4020 -4020 -4020 -4020 -4020 -4020 -4020 -4020 -4020 -4020 -4020 -4020 -4020 -4020 -4020 -4020 -4020 -4020 -4020 -4020 -4020 -3932 -3872 -3812 -3752 -3692 -3632 -3572 -3484 -3377 -3271 -3163 -3057 -2969 -2836 -2729 -2596 -2508 -2401
-139 -199 -259 -319 -379 -439 -499 -559 -619 -679 -739 -724 -724 -724 -724 -724 -724 -724 -724 -724 -724 -724 -724 -724 -724 -724 -724 -724 -724
VSS2 VSS2 VSS2 VSS2 VOUT VOUT VOUT CAP3N CAP3N CAP1P CAP1P CAP1N CAP1N CAP2N CAP2N CAP2P CAP2P
-2268 -2181 -2073 -1941 -1853 -1746 -1639 -1532 -1426 -1318 -1212 -1105 -972 -884 -796 -736 -629 -569 -509 -402 -342 -282 -222 -162 -102 1038
-724 -724 -724 -724 -724 -724 -724 -724 -724 -724 -724 -724 -724 -724 -724 -724 -724 -724 -724 -724 -686 -686 -686 -686 -686 -686 -686 -686 -686 -686 -686 -686 -686 -686 -686 -686 -686 -686 -686 -686 -686 -686 -686 -686 NOV. 2001 Version:
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SPLC501C
Name Name
TEST4 TEST3
TEST5 TEST6 COM31 COM30 COM29 COM28 COM27 COM26 COM25 COM24 COM23 COM22 COM21 COM20 COM19 COM18 COM17 COM16 COM15
1098 1158 1218 1278 1338 1398 1458 1518 1578 1638 1698 1758 1852 1946 2006 2139 2246 2353 2436 2574 2681 2814
2901 2989 3122 3210 3343 3450 3568 3628 3688 3748 3808 3868 3928 4016 4016 4016 4016 4016 4016 4016 4016 4016 4016
-686 -686 -686 -686 -686 -686 -686 -686 -686 -686 -686 -686 -686 -686 -724 -724 -724 -724 -724 -724 -724 -724
-724 -724 -724 -724 -724 -724 -724 -724 -724 -724 -724 -724 -724 -739 -679 -619 -559 -499 -439 -379 -319 -259 -199
COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 COMS1 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5
SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28
4016 4016 4016 4016 4016 4016 4016 4016 4016 4016 4016 4016 4016 4016 4016 4016 3928 3868 3808 3748 3688 3628
3568 3508 3448 3388 3328 3268 3208 3148 3088 3028 2968 2908 2848 2788 2728 2668 2608 2548 2488 2428 2368 2308 2248
-139
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Name Name
SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73
2188 2128 2068 2008 1948 1888 1828 1768 1708 1648 1588 1528 1468 1408 1348 1288 1228 1168 1108 1048 -152 -212 -272 -332 -392 -452
SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 SEG81 SEG82 SEG83 SEG84 SEG85 SEG86 SEG87 SEG88 SEG89 SEG90 SEG91 SEG92 SEG93 SEG94 SEG95 SEG96 SEG97 SEG98 SEG99 SEG100 SEG101 SEG102 SEG103 SEG104 SEG105 SEG106 SEG107 SEG108 SEG109 SEG110 SEG111 SEG112 SEG113 SEG114 SEG115 SEG116 SEG117 SEG118
-512 -572 -632 -692 -752 -812 -872 -932 -992 -1052 -1112 -1172 -1232 -1292 -1352 -1412 -1472 -1532 -1592 -1652 -1712 -1772 -1832 -1892 -1952 -2012 -2072 -2132 -2192 -2252 -2312 -2372 -2432 -2492 -2552 -2612 -2672 -2732 -2792 -2852 -2912 -2972 -3032 -3092 -3152
NOV. 2001 Version:
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Name Name
SEG119 SEG120 SEG121 SEG122 SEG123 SEG124 SEG125
-3212 -3272 -3332 -3392 -3452 -3512 -3572
SEG126 SEG127 SEG128 SEG129 SEG130 SEG131
-3632 -3692 -3752 -3812 -3872 -3932
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DISCLAIMER
information appearing this publication believed accurate. Integrated circuits sold Sunplus Technology covered warranty patent indemnification provisions stipulated terms sale only. SUNPLUS makes warranty, express, statutory implied description regarding information this publication FURTHERMORE, SUNPLUS MAKES WARRANTY SUNPLUS reserves right halt production alter specifications regarding freedom described chip(s) from patent infringement. MERCHANTABILITY FITNESS PURPOSE. prices time without notice. publication current before placing orders.
Accordingly, reader cautioned verify that data sheets other information this Products described herein intended normal commercial applications.
Applications involving unusual environmental reliability requirements, e.g. military equipment medical life support equipment, specifically recommended without additional processing SUNPLUS such applications. Please note that application circuits illustrated this document reference purposes only.
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REVISION HISTORY
Date Revision Description Page
JUN. 2001 JUL, 2001
Original Delete "PRELIMINARY" Change title description "4.3.System Connection Terminals" Modify base voltage
NOV. 2001
Modify Boost reference voltage: VSS2 2.4V -6.0V 2.4V 6.0V Modify Liquid crystal drive power supply: -4.5V -12V 4.5V "Driving Mode register provided different size panel loading" FEATURES" Modify Mnemonic:COM64 COM63 No.: "20.) Driving mode register: (DB7, DB6)=(0, "5.15 Reset Circuit" Note1 Note2 "6.21.2 Mode selection register set" "Driving capability (D1, D0): (1,1)>(0,0)>(0,1)>(1,0)" "6.25 Table Table
SPLC501C Commands"
"8.10 VLCD Voltage (Voltage between relationship Voltage
Regulator Internal Resistor Ratio Register Electronic Volume Control Register"
Modify "75µm(Min.)" "60µm(Min.)" "9.1 Assignment" Note4 "9.1 Assignment" APR. 2002 BLOCK DIAGRAM" description "4.3 System Connection Terminal" connection 5.14.1.1 5.14.1.2
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Matrix Driver APR. 2002 Version SUNPLUS TECHNOLOGY infringem

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