Supports eight 10/100 Mbit/s Ethernet ports, each using SMII interface

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Supports eight 10/100 Mbit/s Ethernet ports, each using SMII interface

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EtherMapTM-3 Device Ethernet into STS-3/STM-1 SONET/SDH Mapper TXC-04226 TECHNICAL OVERVIEW PRODUCT PREVIEW FEATURES
Supports eight 10/100 Mbit/s Ethernet ports, each using SMII interface Supports single 1000 Mbit/s Ethernet port, using parallel GMII interface (lead shared with SMII interfaces) Supports Ethernet Management interface control configuration externally connected PHYs. Supports IEEE 802.3 flow control management statistics (RMON) 10/100/1000 Mbit/s Ethernet ports Supports Ethernet frame encapsulation/decapsulation protocols: ITU-T G.7041, Generic Framing Procedure (GFP) ITU-T X.86/X.85, Link Access Procedure (LAPS) ITU-T Q.922, Link Access Procedure Frame Mode (LAPF) Performs mapping/demapping encapsulated Ethernet frames into/from order (VT1.5 SPE/VC-12) high order (STS-1 SPE/VC-3) virtual concatenated payloads Performs mapping/demapping encapsulated Ethernet frames into/from single contiguous concatenated (STS-3c-SPE/VC-4) payload Supports optional LCAS processing (per ITU-T G.7042) high order virtual concatenated payloads Glueless memory interface external 64/128Mb SDRAMs Supports 84/63 VT/TU Order Pointer processing Supports High Order processing STS-1/VC-3/STS-3c/VC-4 Byte-wide parallel Drop Telecom interfaces Supports per-port Ethernet side SONET/SDH system side loopback system level diagnostics 16-bit wide microprocessor interface, selectable between Motorola Intel Boundary scan (IEEE 1149.1 standard) 3.3V +1.8V power supplies, tolerant leads 324-lead plastic ball grid array package
EtherMapTM-3 highly integrated device that provides mapping 10/100/1000 Mbit/s Ethernet into SONET/SDH STS-3/STM-1 Transport payloads. device supports connection eight 10/100 Mbit/s Ethernet ports, using SMII interfaces, single 1000 Mbit/s Ethernet port, using GMII interface. transmit direction, each port, received Ethernet frames encapsulated using either LAPS LAPF protocol. encapsulated Ethernet frames then mapped into configurable number virtual concatenated high order payloads, such VT1.5 SPE/VC-12/STS-1 SPE/VC-3, contiguous concatenated payload such STS-3c SPE/VC-4. both high order payloads, required SONET/SDH bytes encapsulated Ethernet payload generated output using byte-wide parallel interface TranSwitch Telecom format. EtherMap-3 supports Drop timing modes. receive direction, each Ethernet port, configurable number high order payloads terminated, with complete byte processing virtual contiguous concatenated payloads. Using external SDRAM, alignment differential delay compensation received high order virtual concatenated payloads performed. Ethernet frames then decapsulated using LAPS LAPF protocol forwarded each Ethernet port. both high order virtual concatenated payloads, optional standards based LCAS processing provided allow hitless dynamic bandwidth adjustments. addition support full-rate Ethernet transfer, over-subscribed Ethernet transfers also supported using back pressure mechanisms order prevents frame loss.
APPLICATIONS
SONET/SDH add/drop terminal multiplexers Multi-service access platforms Next generation Ethernet switches DSLAMS Integrated access devices
TELECOM SIDE
+1.8V +3.3V
HO/LO RING Ports
HO/LO Ports
Controls
CLOCKS (SONET/SDH Ref, System, Sec.)
ETHERNET LINE SIDE
DROP
EtherMap-3
Ethernet into STS-3/STM-1 SONET/SDH Mapper
10/100 Mbit/s SMII (Port 1000 Mbit/s GMII
TXC-04226
10/100 Mbit/s SMII (Port
Microprocessor SDRAM Interface Interface
Boundary Scan
Ethernet Management Interface
U.S. and/or foreign patents issued pending Copyright 2002 TranSwitch Corporation EtherMap trademark TranSwitch Corporation TranSwitch registered trademarks TranSwitch Corporation
Document Number: PRODUCT PREVIEW TXC-04226-MA March 2002
TranSwitch Corporation Enterprise Drive Shelton, Connecticut 06484 Tel: 203-929-8810 Fax: 203-926-9453 www.transwitch.com
PRODUCT PREVIEW information documents contain information products their formative design phase development. Features, characteristic data other specifications subject change. Contact TranSwitch Applications Engineering current information this product.
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TABLE CONTENTS
Section Page
List Figures Features. Mappings Encapsulation Protocols: Ethernet Ports. 10/100/1000 Mbit/s Ethernet Media Access Controller (MAC) Block SDRAM Interface. Telecom Timing. Ring Port Interface. Port Interface Microprocessor Interface JTAG Interface Special Features. Block Diagram Data Processing/Flow. Ethernet Ports. 10/100/1000 Mbit/s Ethernet Media Access Controller (MAC) Block Mapper Block. Demapper Block Microprocessor Interface SDRAM Memory Interface. Parallel Telecom Interface. High Order (Path Overhead Byte) Port Interface. High Order Ring Port Interface Alarms Performance Monitoring Block. JTAG Interface Application Example Selected Parameter Values Absolute Maximum Ratings Environmental Limitations (Referenced VSS) Thermal Characteristics. Power Requirements Package Information. Ordering Information. Related Products Documentation Update Registration Form*
Please note that TranSwitch provides documentation products. Current editions many documents available from Products page TranSwitch site www.transwitch.com. Customers using TranSwitch Product, planning should register with TranSwitch Marketing Department receive relevant updated supplemental documentation issued. They should also contact Applications Engineering Department ensure that they provided with latest available information about product, especially before undertaking development designs incorporating product.
LIST FIGURES
Figure
Page
Functional Block Diagram EtherMap-3. Order Virtual Concatenation Structure SONET High Order Virtual Concatenation Structure SONET Typical Application using EtherMap-3 PHAST-3N Devices. EtherMap-3 TXC-04226 Package Diagram
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FEATURES
EtherMap-3 supports following features. Please note that convention used here transmit add) direction from Ethernet line signal (SMII/GMII) SDH/SONET format (Telecom Bus), while receive drop) direction from SDH/SONET format Ethernet line. MAPPINGS EtherMap-3 provides following mapping features: 10/100/1000 Mbit/s Ethernet Traffic mapped into SONET/SDH High Order Order Virtual Concatenation Supported STM-1/AU-4/VC-4/C-4 STS-3/STS-1-SPE/VT-1.5 STS-3/STS-1-SPE STS-3c/STS-3c-SPE VC-12s virtually concatenated Mbit/s traffic ports). VT1.5-SPEs virtually concatenated Mbit/s traffic ports). VC-12s VC-3s virtually concatenated single VC-4 used Mbit/s traffic. VT1.5-SPEs STS-1-SPEs virtually concatenated single STS-3c-SPE used Mbit/s traffic. VC-3s virtually concatenated single VC-4 used 1000 Mbit/s traffic (only port supported). STS-1-SPEs virtually concatenated single STS-3c-SPE used 1000 Mbit/s traffic (only port supported). Mbit/s Mbit/s traffic supported ports). ENCAPSULATION PROTOCOLS: selection three encapsulation protocols supported: LAPS (Link Access Procedure SDH) LAPF (Link Access Procedure Framed Mode service) (Generic Framing Procedure) ETHERNET PORTS EtherMap-3 provides following Ethernet Port features: Eight independent SMII (Serial Medial Independent Interfaces) 10/100 Mbit/s Ethernet Global reference clock Global Synchronization signal Lead selects Switch connection external client Single GMII (Gigabit MII) 1000 Mbit/s Ethernet Lead shared with SMII ports Selection GMII SMII selected through lead Ethernet Management Interface
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10/100/1000 MBIT/S ETHERNET MEDIA ACCESS CONTROLLER (MAC) BLOCK Compliant IEEE 802.3, 802.3u, 802.3x, 802.3z, 802.3ac Full Duplex Operation control layer provides support control frames including PAUSE frames Provides support statistics gathering based RMON Group RMON Group RMON Group RMON Group RMON Ethernet MIB.
SDRAM INTERFACE Glueless interface external Mbits Mbits SDRAM devices Data, Address, Chip Select, Clock, Clock Enable, Address Strobe, Column Address Strobe, Write Enable Strobe, Data Mask, Bank Address leads Buffers TX/RX data transfers Clock frequency Programmable Refresh Period Standard SDRAM commands supported: Single/Burst Mode Read Write Operation Active Precharge Auto-Refresh Load Mode Register Programmable Burst Lengths: latency supported Refresh operation transparent user
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TELECOM TIMING Telecom interface provided interfacing SONET/SDH line through TranSwitch's TOH/POH Terminator devices such PHAST-3N PHAST12E/POP-12 chip set. EtherMap-3 provides following timing modes Telecom modes operation: Drop timing timing derived from Drop timing input signals Drop bus: C1J1, SPE, Optional Data, Clock Parity signal leads inputs bus: C1J1, SPE, Optional Data, Clock, Parity Indication signal leads outputs timing (two modes) timing supplied independent Drop timing Drop bus: C1J1, SPE, Optional Data, Clock, Parity signal leads inputs bus: C1J1, Clock, Optional signal leads inputs; Data, Parity Indication signal leads outputs timing sourced Drop bus: C1J1, SPE, Optional Data, Clock Parity signal leads inputs bus: C1J1, SPE, Optional Data, Clock, Parity Indication signal leads outputs RING PORT INTERFACE High Order Ring Port support ring applications Order Ring Port support ring applications PORT INTERFACE High Order Port access bytes Order Port access bytes MICROPROCESSOR INTERFACE 16-bit Address Data Motorola Intel style split supported Interrupt request lead Interrupt mask bits controlling generation hardware interrupt requests
JTAG INTERFACE IEEE 1149.1 compliant provided board level testing. SPECIAL FEATURES LCAS support
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BLOCK DIAGRAM
SONET/SDH SIDE
Telecom DROP Telecom High order port order port High order Ring port order Ring port
High order port order port High order Ring port order Ring port
Mapper Block SONET/SDH (VT1.5/VC-12/VC3/VC-4)
Demapper Block SONET/SDH (VT1.5/VC-12/VC-3 /VC-4)
Virtual Concatenation LCAS Block
Virtual Concatenation LCAS Block
Encapsulation Block FIFO
SDRAM Controller Block
SDRAM Interface Block
Ethernet FIFO
Ethernet Deinterleave Logic Block MicroProcessor Interface Data
Decapsulation Block Ethernet Logic Block Alarms Performance Monitoring Block
Clock Generator Block
10/100/1000 Mbit/s Ethernet Media Access Controllers (MACs); RMON statistics counters; Ethernet loopbacks 10/100 Mbit/s Ethernet SMII i/fs; 1000 Mbit/s Ethernet GMII (lead shared)
Operation Control, JTAG Block
ETHERNET LINE SIDE
Figure Functional Block Diagram EtherMap-3
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Clocks
Address
external SDRAM memory
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DATA PROCESSING/FLOW general, EtherMap-3 provides functionality mapping demapping ethernet frames from SONET/SDH virtual concatenated tributary structures both LCAS/non-LCAS mode. figures below represent virtual tributary structures that supported EtherMap-3 device. figure below shows VT1.5-Xv structure. VT1.5-Xv provides payload area VT1.5 payload capacity shown. Ethernet payload mapped into individual VT1.5 SPEs which form VT1.5-Xv SPE. Each VT1.5 sent throughout SONET network individually then reassembled destination.
VT1.5-Xv payload capacity 500µs VT1.5 500µs VT1.5 VT1.5-Xv 500µs
Figure Order Virtual Concatenation Structure SONET
figure below shows STS-1-Xv structure. This structure provides contiguous payload area STS-1 with payload capacity X*48384 kbit/s shown. payload capacity (i.e., encapsulated Ethernet frames) mapped into individual STS-1 SPEs which form STS-1-Xv SPE. Each STS-1 POH. Just like VT1.5-SPE case above, STS-1-SPEs travel through SONET network independently reassembled their destination recover Ethernet data. While these cases only show SONET examples, same principle applies payloads concatenating VC-3s VC-12s.
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Xx84
STS-1-Xv payload capacity
STS-1-Xv fixed stuff 125µs
125µs STS-1 125µs STS-1
Figure High Order Virtual Concatenation Structure SONET
SONET/SDH side, EtherMap-3 supports STM-1/STS-3/STS-3c like structure using single TranSwitch defined Telecom operating 19.44 MHz. Ethernet Line side, EtherMap-3 supports EIGHT 10/100 Mbit/s ethernet ports 1000 Mbit/s (Gigabit) ethernet port. eight 10/100 Mbit/s ethernet ports each support industry standard SMII interface. single Gigabit ethernet port supports industry standard GMII interface lead shared with SMII interfaces. transmit direction (Ethernet-to-SONET/SDH), EtherMap-3 terminates 10/100/1000 Mbit/s ethernet traffic. ethernet frames from configured port(s) extracted buffered external SDRAM memory. external SDRAM primarily used implementing flow control when ethernet line side bandwidth greater than allocated bandwidth SONET/SDH side (i.e., over-subscription situation). Based system configuration, ethernet frames from each ethernet ports encapsulated using supported link layer protocols: LAPS, LAPF independently. encapsulated ethernet
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receive direction (SONET/SDH-to-Ethernet), EtherMap-3 terminates parallel telecom with SONET/SDH containers carrying encapsulated (LAPS, LAPF, GFP) ethernet frames. EtherMap-3 provides complete High order path overhead processing SONET/SDH tributaries. SONET/SDH containers then extracted buffered using external SDRAM memory. This memory primarily used providing alignment differential delay compensation select SONET/SDH containers which form part virtual concatenation group. Once alignment delay compensation been achieved, ethernet frames byte de-interleaved from SONET/SDH containers form their original frame structure port basis. ethernet frames then extracted from encapsulations (LAPS, LAPF) used transmit side passed onto ethernet port transmission external client(s). ETHERNET PORTS EtherMap-3 provides eight independent full-duplex Serial Media Independent Interfaces (SMII) support 10/100 Mbit/s Ethernet traffic single GMII port support 1000 Mbit/s Ethernet traffic. Please note, SMII interfaces lead-shared with GMII interface they cannot used together. power-up, package signal lead used allow selection between SMII GMII interfaces. SMII ports allow EtherMap-3 connected external 10/100 Mbit/s Ethernet client (PHY/Switch). configuration choice (PHY/Switch) made power-up/initialization through package signal lead. SMII interface comprised signals port Data Data), global synchronization signal global reference clock. eight Mbit/s Ethernet signals, Mbit/s Ethernet signals, combination both interfaced with these port. Gigabit Media Independent Interface (GMII) used allow mapper connect external 1000 Mbit/s ethernet client (PHY/Switch). EtherMap-3 device supports SINGLE GMII interface. Please note, GMII interface lead-shared with SMII interfaces configuration choice made powerup/initialization. GMII interface comprised independent 8-bit data paths, transmit enable signal, receive data valid signal. Status outputs report when coding violations detected. Network status inputs provided reporting errored frames frame received error. signals synchronous clock. single Ethernet Management interface provided EtherMap-3 connect external ethernet order configure control operation. This interface used both eight 10/100 Mbit/s ports single 1000 Mbit/s port. comprised output Management Data clock signal bidirectional Management Data signal that allows serial data clocked external device. data transfers synchronous clock signal provides support PHYs.
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frames then byte interleaved over preselected SONET/SDH containers transported using virtual concatenation. EtherMap-3 provides complete High order path overhead generation SONET/SDH containers. bandwidth SONET/SDH containers using virtual concatenation, allowed increase decrease hitless fashion through integrated link capacity adjustment scheme (LCAS). SONET/SDH containers carrying ethernet frames then transmitted upstream SONET/SDH Overhead Terminator device such TranSwitch's PHAST-3N, using parallel telecom bus.
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10/100/1000 MBIT/S ETHERNET MEDIA ACCESS CONTROLLER (MAC) BLOCK interface 10/100 Mbit/s ethernet ports 1000 Mbit/s ethernet port supported integrated Ethernet block. This block supports eight 10/100 Mbit/s ports single 1000 Mbit/s port. 10/100/1000 Mbit/s Ethernet block IEEE 802.3, 802.3x, 802.3z 802.3ac compliant supports Full-Duplex (MAC implements IEEE 802.3 Control layer PAUSE operation flow control) mode operation. main features which supported this block follows: Connection external 10/100/1000 Mbit/s Ethernet PHYs 10/100/1000 Mbit/s Ethernet Switch devices either SMII interfaces single GMII interface Line side loopbacks diagnostic capability Verify frame integrity (FCS Length checks) Errored frames configured passed discarded Egress Ethernet frame encapsulation, such padding achieve minimum length generation Programmable Minimum frame size bytes, maximum frame size: 9.6k bytes Transparent IEEE 802.3-1998 VLAN (Virtual LAN) byte Supports IEEE 802.3 mandatory Control Management Registers Over Subscription support Device Configuration Flow Control Option support IEEE 802.3-1998 Flow Control each ethernet port Programmable watermarks FIFO full conditions Automatic generation Pause frames based FIFO fill levels Upper layer device flow control Ethernet ports using side band host signaling cause generation PAUSE frame Provides port side-band PAUSE state indication upstream devices Control disable acting received PAUSE frames, that enables transparent transmission Ethernet PAUSE frame Control Statistics IEEE 802.3z-1998) that includes among others: Detection device, initialization, Device Standard Control Status Registers grouped function: Receive Transmit Control Registers, Receive Transmit Status Registers, RMON registers (for Network Management), Flow Control Registers, Management Registers, Ethernet Interface Control Status Registers Performance counters ensure roll-over compliance with standards Provides statistic counters support RMON implementations (minimum support Ethernet Statistics Group, Ethernet History Group, Alarm Group, Event Group). Auto Negotiation: provides Auto Detect adjusts 10/100 Mbit/s Ethernet interface. MAPPER BLOCK This block provides mapping multiplexing order High order tributaries (carrying Ethernet framed data) into STS-3/STS-3c/STM-1 structures transmitted side telecom bus. vast assemblage SONET/SDH rates format mappings supported indicated below: STS-3 STS-1 SPEs (19.44 Mbit/s) STS-3 STS-1s VT1.5s (19.44 Mbit/s) STS-3c (19.44 Mbit/s) STM-1 AU-4 VC-4 TUG-3s TU-3s VC-3s (19.44 Mbit/s) PRODUCT PREVIEW TXC-04226-MA March 2002
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STM-1 AU-4 VC-4 TUG-3s TUG-2s TU-12s VC-12s (19.44 Mbit/s) STM-1 AU-3s VC-3 TUG-2s TU-12s VC-12s (19.44 Mbit/s) STM-1 AU-4 VC-4 (19.44 Mbit/s) SONET Order: supports VT1.5s SONET High Order: supports STS-1 SPEs Order: supports VC-12s High Order: supports VC-3s order VC/VT tributaries formatted into STS-3 STM-1 structure. pointer value carried bytes transmitted with fixed value VT1.5 TU-12. microprocessor writes signal label, value message 16-byte message. device provides either single-bit extended using bytes. Local alarms, microprocessor, generate remote payload, server, connectivity defect indications. Remote Error Indication (REI) inserted from BIP-2 errors detected receive side, BIP-2 parity generated byte. Control bits provided generating unequipped status, generating TU/VT AIS, inserting BIP-2 errors byte. Control bits also provided that enable microprocessor insert overhead byte test values, including byte. list VT/TU Overhead byte generation functions listed below: Byte Byte Microprocessor written message Forced ZERO option (Z7) Byte Signal label insertion Insertion (from receive side) Insertion Host Processor control BIP-2 calculation Insertion Insertion (from receive side) Enable bits alarms Host Processor control Single extended (bit byte bits byte) Generate least superframes Mask Alarm Bits from sending Microprocessor control Control spare bits byte bits single Bits through (Z7) byte (Z6) Byte: Tandem connection support Unequipped Channel Generation Supervisory Equipped Generation TU/VT Generation order VT/TU Pointer generation Fixed TU-12 Asynchronous Format Fixed VT1.5 Asynchronous Format High order VC-3/STS-1 Overhead byte generation Insertion bytes into STS-1s VC-3s that being mapped with asynchronous line signals byte 16-byte message insertion ETSI Applications
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64-byte message insertion ANSI Applications byte ability generate sequence lower order tributaries should provided when higher order virtual concatenation mode byte Signal Label Insertion byte BIP-8 Calculation Insertion Mask byte Single-bit (ETSI) extended generation (ANSI) (path FEBE) insertion insertion byte: tandem connection support Transmit Path Generation STS-1/AU-3/TUG-3 Overrides Unequipped generation Transmit Unequipped Generation STS-1/AU-3/TUG-3 Supervisory Unequipped generation option High order TU-3 (VC-3)/STS-1 Pointer generation: Drop timing mode pointer bytes follow drop C1J1 pulses Timing Mode pointer bytes follow C1J1 pulses Timing Mode pointer bytes fixed High order VC-4/STS-3c Overhead byte generation generated PHAST-3N EtherMap-3 High order VC-4/STS-3 Pointer generation pointer generation handled external Overhead Terminator device such PHAST-3N POP-12
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DEMAPPER BLOCK Demapper Block provides demapping de-multiplexing order High order tributaries from STS-3/STS-3c/STM-1 structures received Drop side telecom bus. same vast assemblage formats that supported Mapper Block also supported Demapper Block shown below: STS-3 STS-1 SPEs (19.44 Mbit/s) STS-3 STS-1s VT1.5s (19.44 Mbit/s) STS-3c (19.44 Mbit/s) STM-1 AU-4 VC-4 TUG-3s TU-3s VC-3s (19.44 Mbit/s) STM-1 AU-4 VC-4 TUG-3s TUG-2s TU-12s VC-12s (19.44 Mbit/s) STM-1 AU-3s VC-3 TUG-2s TU-12s VC-12s (19.44 Mbit/s) STM-1 AU-4 VC-4 (19.44 Mbit/s) SONET Order: supports VT1.5s SONET High Order: supports STS-1 SPEs Order: supports VC-12s High Order: supports VC-3s
EtherMap-3 device provides processing SONET/SDH overhead bytes follows: Microprocessor Access VT/TU overhead bytes, V1/V2 pointer bytes, byte each channel available microprocessor read cycle, well V5/K4 Bytes. Byte Multiframe Detectors pulse (C1J1V1) reference input Determines Location V1/V2 Pointer Bytes Pointer Tracking V1/V2 Pointer Bytes ETSI/ITU/ANSI State Machine Wrong Size Bits Detection Positive/Negative Justification 8-bit Counters order tributaries, this Demapper block performs pointer processing based location bytes. pointer bytes monitored loss pointer Alarm Indication Signal (AIS). pointer tracking process based ETSI/ITU-T standards, which also meets ANSI requirements. Pointer increments decrements also counted, size bits monitored correct value. This block also processes monitors various alarms found four overhead bytes. These operations including signal label mismatch detection, unequipped status detection, BIP-2 parity error detection bit/block error counter, error counting, detector, single-bit extended Remote Defect Indications (RDI). DeMapper performs 16-byte trail trace comparison channels selected. byte processing supported. Below bullet list High order VC-3/STS-1 Overhead byte processing that performed DeMapper block: received bytes applicable alarm indications made accessible micro-processor. byte trace mismatch detection 16-byte trail trace alignment (MFAS pattern) comparison ETSI Applications 64-byte message alignment (Multiframe Alignment MFAS pattern CR/LF alignment) byte ability detect generate pulse from byte sequence lower order tributaries supported.
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Demapper provides complete TU-3 pointer tracking state machines including applicable alarm indications. Other higher order processing done external device such PHAST-3N POP-12 device; high order pointer processing must done external device such PHAST-3N POP-12. MICROPROCESSOR INTERFACE EtherMap-3's microprocessor interface provides support either standard Motorola, Intel split address/data interface which allows access EtherMap-3's memory register locations through 16-bit data bus. mode operation configurable external package signal leads. interrupt request lead provided allow maskable interrupt bits generate interrupts external microprocessor, thus reducing required bandwidth. SDRAM MEMORY INTERFACE This interface used allow mapper connect external SDRAM memory device. external SDRAM memory device used buffering ethernet traffic both directions provides "glueless" interface Mbits Mbits external SDRAM memory devices. Virtually concatenated realigned differential delay accommodated SDRAM during reconstruction process received frame. PARALLEL TELECOM INTERFACE Telecom interface enables EtherMap-3 connect upstream SONET/SDH Line Overhead Terminator such TranSwitch's PHAST-3N OC-3/STM-1 applications. OC-12/STM-4 applications, EtherMap-3 would connect TranSwitch's POP-12/PHAST-12E chip set. Telecom interface collectively comprised single Drop (RX) single (TX) bus. EtherMap-3 supports single telecom architecture which consists single Drop single bus. This same architecture supported other TranSwitch Mappers (e.g. TL3M) SONET/SDH Overhead Terminators (e.g. PHAST-3N, PHAST-12E, POP-12) products. Telecom operates 19.44 rate. telecom interface consists byte wide data, 19.44 (STM-1/STS-3) clock, indication, C1J1(V1) pulses, even parity indication, active indicator. EtherMap-3 supports either Drop timing modes. package lead used provide this selection. This approach prevents contention upon power device reset. Drop timing mode: this mode, timing derived from Drop timing input signals. When Drop timing mode selected, interface output leads byte-wide data, parity indicator, add-to-bus indicator. clock, C1J1V1 signals, which derived from Drop bus, output disabled. selection performed package lead.
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byte Signal label mismatch Unequipped detection generation detection byte Single-bit (ETSI) extended detection (ANSI) (path FEBE) calculation with 16-bit Block error count access host processor access byte: supported
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Note following restrictions apply when using Drop timing mode: SONET (STS-3 STS-1-SPEs) mode, high order virtual concatenation supported. SONET (STS-3 STS-1 SPEs VT1.5s) mode, selection order tributaries (VT1.5s) order virtual concatenation need restricted remain within same STS-1 (i.e., only allow VT1.5s). (STM-1 AU-3 VC-3 TUG-2s TU-12s VC-12s) mode, selection order tributaries (VC-12s) order virtual concatenation restricted remain within same VC-3 (i.e., only allow VC-12s).
timing mode(s): these modes, interface timing independent Drop interface timing above restrictions apply. Using control bit, interface timing signals configured follows: timing mode Byte Clock, 19.44 (input); indicator (input); C1J1V1 indicator (input); Byte-wide Data (output); Parity indicator (output); Add-to-bus indicator (output);
Note: this timing mode, when operating STS-3/AU-3 mode, external timing source must ensure three pointers pulses) synchronized fixed relative each other (i.e., there must pointer movements relative each other.)
timing mode interface signals follows: Byte Clock, 19.44 (output), derived from input clock lead; indicator (output); C1J1V1 indicator (output); Byte-wide Data (output); Parity indicator (output); Add-to-bus indicator (output);
Note: this timing mode, when operating STS-3/AU-3 mode, EtherMap-3 will source timing signals.
Drop parity configured checked over data only over signals, check even parity. Drop clock monitored stuck high stuck conditions. parity generated even generated over data only over signals. indicator goes active indicate when VT/TU/VC/SPE data being added Telecom Bus. When data being added telecom bus, data parity tri-stated. HIGH ORDER (PATH OVERHEAD BYTE) PORT INTERFACE byte interface provides alternative access SONET/SDH Order High Order tributary bytes external processing. There interfaces. interface VT1.5/VC-12 second interface STS-1/VC-3 STS-3c/VC-4 POH. Individual byes except J1/J2, C2/V5/K4 Signal label BIP-2/BIP-8 fields inserted into from transmit byte interface. bytes provided their respective receive byte interface external processing.
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HIGH ORDER RING PORT INTERFACE Ring port provided transport remote information signal from mate monitor generator. remote information includes REI, various extended indications. There separate Ring ports; VT1.5/VC-12 STS-1/VC-3 STS-3c/VC-4 ALARMS PERFORMANCE MONITORING BLOCK This block maintains updates statistics/performance counters LAPS, LAPF, (for ethernet ports) accessible host. following types statistics/performance counters provided this block: Flag error counters Payload size violation counters error counters Control Field mismatch counters Total payload frames/octets transmitted counters Total payload frames/octets received counters
Mapper/Demapper statistics/performance counters (for tributaries) grouped within part Mapper/Demapper block. JTAG INTERFACE This interface provides five signal Boundary Scan capability that conforms IEEE 1149.1 standard. This standard provides external boundary scan functions read write external Input/Output leads from board component test. addition lead provided place output buffers high impedance state systems that support IEEE 1149.1 standard.
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APPLICATION EXAMPLE
EtherMap-3 used broad array telecommunications applications, such SONET/SDH add/drop terminal multiplexers Multi-service access platforms Next generation Ethernet switches DSLAMS Integrated access devices
Multi-service Ethernet Aggregation with OC-3/STM-1 Uplink
SDRAM Drop
10/100 Mbit/s SMII interfaces 10/100 Mbit/s SMII interfaces
OC-3/STM-1
PHAST-3N
EtherMap-3 TXC-04226
Ethernet Switch Ports)
TEMx28
28xDS1 21xE1
EtherMap-3 TXC-04226
1000 Mbit/s GMII interface
Gigabit Ethernet
1000 Mbit/s Line
SDRAM
Figure Typical Application using EtherMap-3 PHAST-3N Devices
Figure shows Multiservice STM-1/STS-3 application using EtherMap-3. TEMx28 device provides access 28xDS1 channels STS-3/STM-1 signal. EtherMap-3 devices used Gigabit Ethernet into STS-1-SPE/VC-3 container 10/100 Mbit/s Ethernet Traffic into VT1.5-SPE/VC-12. demonstrated this application, very small number TranSwitch components enables board developed which used simultaneously support mixture 10/100/1000 Mbit/s Ethernet Traffic T1/E1 Traffic. adding TranSwitch's TL3M device Telecom Bus, also supported.
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SELECTED PARAMETER VALUES
ABSOLUTE MAXIMUM RATINGS ENVIRONMENTAL LIMITATIONS (REFERENCED VSS) Parameter Supply voltage (3.3V) Core Supply voltage (1.8V) input voltage LVTTL input voltage LVTTL-5 input voltage Storage temperature range Ambient Operating Temperature Moisture Exposure Level Relative Humidity, during assembly Relative Humidity, in-circuit Classification Symbol -0.5 +150
-0.3 -0.3
Unit
Conditions Note Note Note
Note ft/min linear airflow EIA/JEDEC JESD22-A112-A Note non-condensing Note
Level
Notes: Conditions exceeding values cause permanent failure. Exposure conditions near values extended periods impair device reliability. Pre-assembly storage non-drypack conditions recommended. Please refer instructions "CAUTION" label drypack which devices supplied. Test method MIL-STD-883D, Method 3015.7. Notice Spec 2001V latch Over/undershoot:+/150mA, 125°C Device core only. input signals leads accept signals except SMII/GMII SDRAM memory interface signals which accept only 3.3V signals.
THERMAL CHARACTERISTICS Parameter Thermal resistance: junction ambient Unit
Test Conditions ft/min linear airflow
POWER REQUIREMENTS Parameter VDD(3.3V) IDD(3.3V) VDD(1.8V) IDD(1.8V) Power Dissipation, 1.62 1.80 3.15 3.30 3.45 1.89 Unit Test Conditions
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PACKAGE INFORMATION
EtherMap-3 device packaged 324-lead plastic ball grid array package suitable surface mounting, illustrated Figure
Bottom View -E1-
TRANSWITCH
TXC-04226AIOG
E1/4 Note
-D1-
D1/4
(A3)
Dimension (Note Notes: dimensions millimeters. Values shown reference only. Identification solder ball corner contained within this shaded zone. This package corner angle, chamfered identification. Size array: JEDEC code MO-151-AAJ-1. (Ref.) (Ref.) (BSC) (BSC) (BSC)
2.02 0.40 1.12 0.50 0.63 23.00 21.00 19.45 23.00 21.00 19.45 1.00
2.44 0.60 1.22 0.62
20.20
20.20
Figure EtherMap-3 TXC-04226 Package Diagram
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ORDERING INFORMATION
Part Number:TXC-04226AIOG 324-lead plastic ball grid array package
RELATED PRODUCTS
TXC-02030, DART VLSI Device (Advanced E3/DS3 Receiver/Transmitter). DART performs transmit receive line interface functions required transmission (34.368 Mbit/s) (44.736 Mbit/s) signals across coaxial interface. TXC-02302B, SYN155C VLSI Device (155-Mbit/s Synchronizer, Clock Data Output). Transmits receives STS-3/STM-1 rates. Provides complete STS-3/STM-1 frame synchronization function. Connects directly optical fiber interface components. TXC-03001B, SOT-1 VLSI Device (SONET STS-1 Overhead Terminator). This device performs section, line path overhead processing STS-1 SONET signals. programmable STS-1 STS-N modes. TXC-03003B, SOT-3 VLSI Device (STM-1/STS-3/STS-3c Overhead Terminator). This device performs section, line path overhead processing STM-1/STS-3/STS-3c signals. Compliant with ANSI ITU-TSS standards. TXC-03303, M13E VLSI Device. Single-chip with extended features multiplex/demultiplex device provides complete interfacing function between single signal independent signals. TXC-03305, M13X VLSI Device (DS3/DS1 Mux/Demux). This single-chip device provides functions needed multiplex demultiplex independent signals from signal with either C-bit frame format. includes some enhanced features relative M13E device. TXC-03452B, VLSI Device (Level Mapper). Maps 44.736 Mbit/s 34.368 Mbit/s asynchronous line signal into STM-1/STS-3/STS-1 formatted synchronous signal. Separate add/drop timing available loop multiplexers. provides overhead processing mapped signal. TXC-06103, PHAST-3N VLSI Device (SDH/SONET STM-1, STS-3 STS-3c Overhead Terminator) This PHAST-3N VLSI device provides Telecom interface downstream devices operates from power supply volts. TXC-06125, XBERT VLSI Device (Bit Error Rate Generator Receiver). Programmable multi-rate test pattern generator receiver single chip with serial, nibble, byte interface capability. TXC-06212, PHAST-12E VLSI Device (Programmable, High-Performance ATM/Packet/Transmission SONET/SDH Terminator Level 12). highly integrated SONET/SDH terminator device designed Acell, frame, higher-order multiplexing, transmission applications. This PHAST-12 VLSI device provides Telecom interface downstream devices operates from power supply volts. TXC-06603, POP-12 Device (OC-12 SONET/SDH Path OVerhead Processor, Retimer, Cross Connect). POP-12 integrates VC-3/VC-4 processing, AU-3/AU-4 pointer processing retiming, VC-3/VC-4 cross connect four Telecom interfaces into package. provides interface high density mapper applications when used with TranSwitch PHAST-12E (TXC-06212), mapper framer devices. POP-12 device designed provide seamless interface PHAST-12E device. PRODUCT PREVIEW TXC-04226-MA March 2002
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NOTES
TranSwitch reserves right make changes product(s) circuit(s) described herein without notice. liability assumed result their application. TranSwitch assumes liability TranSwitch applications assistance, customer product design, software performance, infringement patents services described herein. does TranSwitch warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right TranSwitch covering relating combination, machine, process which such semiconductor products services might used.
PRODUCT PREVIEW information documents contain information products their formative design phase development. Features, characteristic data other specifications subject change. Contact TranSwitch Applications Engineering current information this product.
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Supports eight 10/100 Mbit/s Ethernet ports, each using SMII interface

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