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H8S/2677 HD64F2677, HD6432677 H8S/2676 HD64F2676, HD6432676 H8S/2675 H


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H8S/2678 Series
H8S/2677 HD64F2677, HD6432677 H8S/2676 HD64F2676, HD6432676 H8S/2675 HD6432675 H8S/2673 HD6432673 H8S/2670 HD6412670
ADE-602-192 Rev. 3/15/00 Hitachi, Ltd.
Cautions
Hitachi neither warrants grants licenses rights Hitachi's third party's patent, copyright, trademark, other intellectual property rights information contained this document. Hitachi bears responsibility problems that arise with third party's rights, including intellectual property rights, connection with information contained this document. Products product specifications subject change without notice. Confirm that have received latest product standards specifications before final design, purchase use. Hitachi makes every attempt ensure that products high quality reliability. However, contact Hitachi's sales office before using product application that demands especially high quality reliability where failure malfunction directly threaten human life cause risk bodily injury, such aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment medical equipment life support. Design your application that product used within ranges guaranteed Hitachi particularly maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions other characteristics. Hitachi bears responsibility failure damage when used beyond guaranteed ranges. Even within guaranteed ranges, consider normally foreseeable failure rates failure modes semiconductor devices employ systemic measures such fail-safes, that equipment incorporating Hitachi product does cause bodily injury, fire other consequential damage operation Hitachi product. This product designed radiation resistant. permitted reproduce duplicate, form, whole part this document without written approval from Hitachi. Contact Hitachi's sales office questions regarding this document Hitachi semiconductor products.
Organization H8S/2678 Series following manuals available H8S/2678 Series products. Table
Title H8S/2600 Series, H8S/2000 Series Programming Manual H8S/2678 Series Hardware Manual H8S/2678 Series
H8S/2678 Series Manuals
Document Code ADE-602-083A ADE-602-193 ADE-602-192
H8S/2600 Series, H8S/2000 Series Programming Manual gives detailed description architecture instruction H8S/2600 incorporated into H8S/2678 Series products. H8S/2678 Series Hardware Manual describes operation on-chip functions common H8S/2678 Series products, gives detailed description related registers. H8S/2678 Series Reference Manual mainly covers information specific H8S/2678 Series products, including arrangement, ports, operating modes (memory maps), interrupt vectors, control, electrical characteristics, also includes brief description registers convenience user.
contents H8S/2678 Series Hardware Manual H8S/2678 Series Reference Manual summarized table Table
Item Overview (Including arrangement) operating modes (including memory maps) Exception handling Interrupt controller controller controller (DMAC) Data transfer controller (DTC) 16-bit timer unit (TPU) Programmable pulse generator (PPG) 8-bit timers Watchdog timer Serial communication interface (SCI) Smart card interface converter converter (flash memory) Clock pulse generator Power-down modes ports (including port block diagrams) Electrical characteristics Register reference chart address order, with function summary) Instruction Package dimension diagrams
Contents Hardware Manual Hardware Manual
Included Included (with detailed register descriptions) included
following chart shows where find various kinds information different purposes.
product evaluation information, comparative specification information current users Hitachi products H8S/2678 Series specifications Overview arrangement diagram Block diagrams function modules functions Electrical characteristics Overview Arrangement Section Peripheral Block Diagrams Functions Section Electrical Characteristics
detailed information functions
details operation H8S/2678 Series modules port information Interrupts exception handling Information other modules functions Section Ports Section Exception Handling Interrupt Controller H8S/2678 Series Hardware Manual Functions
information H8S/2678 Series operating modes List Detailed descriptions Functions Each Operating Mode Section Operating Modes
design material
information H8S/2678 Series registers List find register from address find register information function Setting procedure notes Section Registers List Registers (Address Order) List Registers Module) H8S/2678 Series Hardware Manual
information H8S/2678 Series instructions List Operation description notes Program examples H8S/2600 Series, H8S/2000 Series Programming Manual
Contents
Section
Overview Overview Block Diagram Arrangement Functions Each Operating Mode Functions. Product Lineup Package Dimensions Operating Modes Overview 2.1.1 Operating Mode Selection (F-ZTAT Version) 2.1.2 Operating Mode Selection (ROMless Mask Versions). 2.1.3 Register Configuration Register Descriptions 2.2.1 Mode Control Register (MDCR) 2.2.2 System Control Register (SYSCR). Operating Mode Descriptions 2.3.1 Mode (Expanded Mode with On-Chip Disabled) 2.3.2 Mode (Expanded Mode with On-Chip Disabled) 2.3.3 Mode 2.3.4 Mode (Expanded Mode with On-Chip Enabled). 2.3.5 Mode (External Activation Expanded Mode with On-Chip Enabled) 2.3.6 Mode (External Activation Expanded Mode with On-Chip Enabled) 2.3.7 Mode (Single-Chip Activation Mode with On-Chip Enabled). 2.3.8 Modes [F-ZTAT Version Only]. 2.3.9 Mode [F-ZTAT Version Only] 2.3.10 Mode 2.3.11 Mode 2.3.12 Modes [F-ZTAT Version Only]. 2.3.13 Mode [F-ZTAT Version Only] Functions Each Operating Mode Memory Each Operating Mode
Section
Section
Exception Handling Interrupt Controller Overview 3.1.1 Exception Handling Types Priority.
Interrupt Controller 3.2.1 Interrupt Controller Features. 3.2.2 Block Diagram 3.2.3 Configuration 3.2.4 Register Configuration. Register Descriptions 3.3.1 Interrupt Control Register (INTCR) 3.3.2 Interrupt Priority Registers (IPRA IPRK). 3.3.3 Enable Register (IER) 3.3.4 Sense Control Registers (ISCRH, ISCRL) 3.3.5 Status Register (ISR). 3.3.6 Select Register (ITSR) 3.3.7 Software Standby Release Enable Register (SSIER). Interrupt Sources 3.4.1 External Interrupts. 3.4.2 Internal Interrupts. 3.4.3 Interrupt Vector Table. Interrupt Operation. 3.5.1 Interrupt Control Modes Interrupt Operation. 3.5.2 Interrupt Control Mode 3.5.3 Interrupt Control Mode 3.5.4 Interrupt Exception Handling Sequence 3.5.5 Interrupt Response Times Usage Notes 3.6.1 Contention between Interrupt Generation Disabling 3.6.2 Instructions that Disable Interrupts. 3.6.3 Periods when Interrupts Disabled 3.6.4 Interrupts during Execution EEPMOV Instruction DMAC Activation Interrupt 3.7.1 Overview. 3.7.2 Block Diagram 3.7.3 Operation.
Section
Controller Overview 4.1.1 Features 4.1.2 Block Diagram 4.1.3 Configuration 4.1.4 Register Configuration Register Descriptions 4.2.1 Width Control Register (ABWCR) 4.2.2 Access State Control Register (ASTCR) 4.2.3 Wait Control Registers (WTCRA, WTCRB)
Read Strobe Timing Control Register (RDNCR) Assertion Period Control Registers (CSACRH, CSACRL). Area Burst Control Register (BROMCRH) Area Burst Control Register (BROMCRL) 4.2.7 Control Register (BCR) 4.2.8 DRAM Control Register (DRAMCR) 4.2.9 DRAM Access Control Register (DRACCR). 4.2.10 Refresh Control Register (REFCR) 4.2.11 Refresh Timer Counter (RTCNT). 4.2.12 Refresh Time Control Register (RTCOR) Overview Control 4.3.1 Area Division 4.3.2 Specifications. 4.3.3 Memory Interfaces 4.3.4 Chip Select Signals Basic Interface. 4.4.1 Overview. 4.4.2 Data Size Data Alignment. 4.4.3 Valid Strobes. 4.4.4 Basic Timing. 4.4.5 Wait Control. 4.4.6 Read Strobe (RD) Timing. 4.4.7 Extension Chip Select (CS) Assertion Period DRAM Interface. 4.5.1 Overview. 4.5.2 Setting DRAM Space. 4.5.3 Address Multiplexing. 4.5.4 Data 4.5.5 Pins Used DRAM Interface. 4.5.6 Basic Timing. 4.5.7 Column Address Output Cycle Control 4.5.8 Address Output Cycle Control 4.5.9 Precharge State Control 4.5.10 Wait Control. 4.5.11 Byte Access Control 4.5.12 Burst Operation. 4.5.13 Refresh Control. 4.5.14 DMAC EXDMAC Single Address Transfer Mode DRAM Interface Burst Interface 4.6.1 Overview. 4.6.2 Basic Timing. 4.6.3 Wait Control. 4.6.4 Write Access
4.2.4 4.2.5 4.2.6
Idle Cycle 4.7.1 Operation. 4.7.2 States Idle Cycle Write Data Buffer Function Release 4.9.1 Overview. 4.9.2 Operation. 4.9.3 States External Released State 4.9.4 Transition Timing 4.9.5 Usage Notes 4.10 Arbitration. 4.10.1 Overview. 4.10.2 Operation. 4.10.3 Transfer Timing 4.11 Controller Operation Reset
Section
Ports Overview Port 5.2.1 Overview. 5.2.2 Register Configuration 5.2.3 Functions. Port 5.3.1 Overview. 5.3.2 Register Configuration 5.3.3 Functions. Port 5.4.1 Overview. 5.4.2 Register Configuration 5.4.3 Functions. Port 5.5.1 Overview. 5.5.2 Register Configuration 5.5.3 Functions. Port 5.6.1 Overview. 5.6.2 Register Configuration 5.6.3 Functions. Port 5.7.1 Overview. 5.7.2 Register Configuration 5.7.3 Functions. Port
5.10
5.11
5.12
5.13
5.14
5.15
5.16
5.17
5.8.1 Overview. 5.8.2 Register Configuration 5.8.3 Functions. Port 5.9.1 Overview. 5.9.2 Register Configuration 5.9.3 Functions. Port 5.10.1 Overview. 5.10.2 Register Configuration 5.10.3 Functions. 5.10.4 Input Pull-Up Function. Port 5.11.1 Overview. 5.11.2 Register Configuration 5.11.3 Functions. 5.11.4 Input Pull-Up Function. Port 5.12.1 Overview. 5.12.2 Register Configuration 5.12.3 Functions. 5.12.4 Input Pull-Up Function. Port 5.13.1 Overview. 5.13.2 Register Configuration 5.13.3 Functions. 5.13.4 Input Pull-Up Function. Port 5.14.1 Overview. 5.14.2 Register Configuration 5.14.3 Functions. 5.14.4 Input Pull-Up Function. Port 5.15.1 Overview. 5.15.2 Register Configuration 5.15.3 Functions. Port 5.16.1 Overview. 5.16.2 Register Configuration 5.16.3 Functions. Port 5.17.1 Overview. 5.17.2 Register Configuration
5.17.3 Functions. 5.18 Functions. 5.18.1 Port States Each Processing State. 5.19 Port Block Diagrams. 5.19.1 Port 5.19.2 Port 5.19.3 Port 5.19.4 Port 5.19.5 Port 5.19.6 Port 5.19.7 Port 5.19.8 Port 5.19.9 Port 5.19.10 Port 5.19.11 Port 5.19.12 Port 5.19.13 Port 5.19.14 Port 5.19.15 Port 5.19.16 Port
Section
Supporting Module Block Diagrams. Interrupt Controller 6.1.1 Features 6.1.2 Block Diagram 6.1.3 Pins. Controller 6.2.1 Features 6.2.2 Block Diagram 6.2.3 Pins. Data Transfer Controller 6.3.1 Features 6.3.2 Block Diagram EXDMA Controller (EXDMAC). 6.4.1 Features 6.4.2 Block Diagram 6.4.3 Pins. 16-bit Timer Pulse Unit. 6.5.1 Features 6.5.2 Block Diagram 6.5.3 Pins. Programmable Pulse Generator. 6.6.1 Features
6.10
6.11
6.12
6.13
6.14
6.15
6.16
6.6.2 Block Diagram 6.6.3 Pins. 8-Bit Timer. 6.7.1 Features 6.7.2 Block Diagram 6.7.3 Pins. Watchdog Timer. 6.8.1 Features 6.8.2 Block Diagram 6.8.3 Pins. Serial Communication Interface. 6.9.1 Features 6.9.2 Block Diagram 6.9.3 Pins. Smart Card Interface 6.10.1 Features 6.10.2 Block Diagram 6.10.3 Pins. IrDA 6.11.1 Features 6.11.2 Block Diagram 6.11.3 Pins. Converter 6.12.1 Features 6.12.2 Block Diagram 6.12.3 Pins. Converter 6.13.1 Features 6.13.2 Block Diagram 6.13.3 Pins. RAM. 6.14.1 Features 6.14.2 Block Diagram ROM. 6.15.1 Features 6.15.2 Block Diagrams. Clock Pulse Generator. 6.16.1 Features 6.16.2 Block Diagram
Section
Electrical Characteristics. Electrical Characteristics Mask Version (H8S/2677, H8S/2676, H8S/2675, H8S/2673) ROMless Version (H8S/2670)
7.1.1 Absolute Maximum Ratings 7.1.2 Characteristics 7.1.3 Characteristics 7.1.4 Conversion Characteristics 7.1.5 Conversion Characteristics Electrical Characteristics F-ZTAT Version (H8S/2677, H8S/2676). 7.2.1 Absolute Maximum Ratings 7.2.2 Characteristics 7.2.3 Characteristics 7.2.4 Conversion Characteristics 7.2.5 Conversion Characteristics 7.2.6 Flash Memory Characteristics Usage Note
Section
Registers.
List Registers (Address Order) List Registers Module) Register Descriptions
viii
Section Overview
Overview
H8S/2678 Series comprises microcomputers (MCUs), built around H8S/2600 CPU, employing Hitachi's original architecture, equipped with on-chip supporting functions necessary system configuration. H8S/2600 internal 32-bit architecture, provided with sixteen 16-bit general registers concise, optimized instruction designed high-speed operation, address 16-Mbyte linear address space. instruction upward-compatible with H8/300 H8/300H instructions object-code level, facilitating migration from H8/300, H8/300L, H8/300H Series. On-chip supporting functions required system configuration include direct memory access controller (DMAC), EXDMA controller (EXDMAC), data transfer controller (DTC) masters, memory, a16-bit timer pulse unit (TPU), programmable pulse generator (PPG), 8-bit timer module (TMR), watchdog timer module (WDT), serial communication interfaces (SCI, IrDA), converter, converter, ports. high-functionality controller also provided, enabling fast easy connection DRAM other kinds memory. on-chip either single-power-supply flash memory (F-ZTATTM*) mask ROM, enabling users respond quickly flexibly changing application specifications, growing production volumes, other conditions. connected 16-bit data bus, enabling both byte word data accessed state. Instruction fetching thus speeded processing speed increased. features H8S/2678 Series shown table 1.1. Note: F-ZTAT trademark Hitachi, Ltd.
Table
Item
Overview
Specifications General-register architecture Sixteen 16-bit general registers (also usable sixteen 8-bit registers eight 32-bit registers) High-speed operation suitable realtime control Maximum operating frequency: High-speed arithmetic operations 8/16/32-bit register-register add/subtract: operation) 16-bit register-register multiply: operation) 16-bit register-register divide: operation) Instruction suitable high-speed operation Sixty-five basic instructions 8/16/32-bit transfer/arithmetic logic instructions Unsigned/signed multiply divide instructions Powerful bit-manipulation instructions operating mode Advanced mode: 16-Mbyte address space
controller
Address space divided into areas, with specifications settable independently each area Chip select output possible each area Selection 8-bit 16-bit access space each area 2-state 3-state access space designated each area Number program wait states each area Maximum 8-Mbyte DRAM directly connectable interval timer possible) External release function Selection short address mode full address mode Four channels short address mode, channels full address mode Transfer possible repeat mode, block transfer mode, etc. Single address mode transfer possible activated internal interrupt
controller (DMAC)
Item EXDMA controller (EXDMAC)
Specifications Four channels exclusively external Selection dual address mode single address mode Transfer possible burst transfer mode, block transfer mode, etc. Repeat area setting function operate parallel with internal operations internal master Activated internal interrupt software Multiple transfers multiple types transfer possible activation source Transfer possible repeat mode, block transfer mode, etc. Request sent interrupt that activated Six-channel 16-bit timer on-chip Pulse processing capability pins Automatic 2-phase encoder count capability Maximum 16-bit pulse output possible with time base Output trigger selectable 4-bit groups Non-overlap margin Direct output inverse output setting possible 8-bit up-counter (external event count capability) time constant registers Two-channel connection possible Watchdog timer interval timer selectable Asynchronous mode synchronous mode selectable Multiprocessor communication function Smart card interface function channel (SCI0) functions with IrDA Conforms IrDA specification ver. IrDA format encoding/decoding
Data transfer controller (DTC)
16-bit timer-pulse unit (TPU)
Programmable pulse generator (PPG)
8-bit timer, channels
Watchdog timer Serial communication interface (SCI), channels
Item converter
Specifications Resolution: bits Input: channels minimum conversion time operation) Single scan mode selectable Sample-and-hold function conversion activated external trigger timer trigger Resolution: bits Output: channels input/output pins, input pins Flash memory, mask High-speed static Product Name H8S/2677 H8S/2676 H8S/2675 H8S/2673 H8S/2670 ROM/RAM (Bytes) F-ZTAT Version planning stage HD64F2676 Mask Version planning stage HD6432676 planning stage HD6432673 ROMless Version HD6412670
converter
ports Memory
Interrupt controller
external interrupt pins (NMI, IRQ0 IRQ15) internal interrupt sources Eight interrupt priority levels settable Clock division mode Sleep mode Module stop mode Software standby mode Hardware standby mode
Power-down state
Item Operating modes
Specifications Selection twelve operating modes (F-ZTATversion)
Operating Mode Advanced User program mode Enabled Advanced User program mode Enabled Advanced Boot mode Enabled bits bits bits bits bits bits bits bits bits Operating Mode External Data Description On-Chip Disabled Initial Value bits bits Enabled Enabled bits bits bits Enabled Maximum Value bits bits bits bits bits bits
Advanced Expanded mode with on-chip disabled Expanded mode with on-chip enabled External activation expanded mode with on-chip enabled Single-chip activation mode with on-chip enabled
Selection operating modes (mask version, ROMless version)
Operating Mode Operating Mode External Data Description On-Chip Disabled Initial Value bits bits Enabled Enabled bits bits bits Enabled Maximum Value bits bits bits bits bits bits
Advanced Expanded mode with on-chip disabled
Advanced Expanded mode with on-chip enabled External activation expanded mode with on-chip enabled Single-chip activation mode with on-chip enabled
Note: Only modes available ROMless version.
Clock pulse generator Packages
Built-in circuits Input clock frequency MHz) 144-pin plastic (FP-144)
Block Diagram
PD7/D15 PD6/D14 PD5/D13 PD4/D12 PD3/D11 PD2/D10 PD1/D9 PD0/D8 PE7/D7 PE6/D6 PE5/D5 PE4/D4 PE3/D3 PE2/D2 PE1/D1 PE0/D0
Port
Port
H8S/2600
Internal data
Internal address
controller
EXTAL XTAL STBY WDTOVF FWE*2 PF6/AS PF5/RD PF4/HWR PF3/LWR PF2/LCAS/IRQ15 PF1/UCAS/IRQ14 PF0/WAIT PG6/BREQ PG5/BACK PG4/BREQO PG3/CS3 PG2/CS2 PG1/CS1 PG0/CS0 P65/TMO1/DACK1/IRQ13 P64/TMO0/DACK0/IRQ12 P63/TMCI1/TEND1/IRQ11 P62/TMCI0/TEND0/IRQ10 P61/TMRI1/DREQ1/IRQ9 P60/TMRI0/DREQ0/IRQ8 P85/EDACK3/(IRQ5) P84/EDACK2/(IRQ4) P83/ETEND3/(IRQ3) P82/ETEND2/(IRQ2) P81/EDREQ3/(IRQ1) P80/EDREQ2/(IRQ0)
Clock pulse generator
PA7/A23 PA6/A22 PA5/A21 PA4/A20 PA3/A19 PA2/A18 PA1/A17 PA0/A16 PB7/A15 PB6/A14 PB5/A13 PB4/A12 PB2/A10 PB1/A9 PB0/A8 PC7/A7 PC6/A6 PC5/A5 PC4/A4 PC3/A3 PC2/A2 PC1/A1 PC0/A0 P35/SCK1/(OE) P34/SCK0 P33/RxD1 P32/RxD0/IrRxD P31/TxD1 P30/TxD0/IrTxD
DMAC ROM*1 EXDMAC
Peripheral address
Interrupt controller
Port
Port
Port
8-bit timer
Port
Port
Port
Port
Port
converter
Port
Port
Vref AVCC AVSS
Port
Port
converter
P57/AN15/DA3/IRQ7 P56/AN14/DA2/IRQ6 P55/AN13/IRQ5 P54/AN12/IRQ4 P53/ADTRG//IRQ3 P52/SCK2/IRQ2 P51/RxD2/IRQ1 P50/TxD2/IRQ0
Port
Port
P10/ TIOCA0 TIOCB0 PO10 TIOCC0 TCLKA PO11 TIOCD0 TCLKB PO12 TIOCA1 PO13 TIOCB1 TCLKC PO14 TIOCA2/EDRAK2 PO15 TIOCB2 TCLKD/EDRAK3
Notes:
supported ROMless version. used only F-ZTAT version. other versions, this pin.
Figure Internal Block Diagram
/PO0 TIOCA3/(IRQ8) /PO1 TIOCB3/(IRQ9) /PO2 TIOCC3 (IRQ10) /PO3 TIOCD3 (IRQ11) /PO4 TIOCA4 (IRQ12) /PO5 TIOCB4 (IRQ13) /PO6 TIOCA5 /EDRAK0/(IRQ14) /PO7 TIOCB5 /EDRAK1/(IRQ15)
/EDACK1/(DACK1) /EDACK0/(DACK0) /ETEND1/(TEND1) /ETEND0/(TEND0) /EDREQ1/(DREQ1) /EDREQ0/(DREQ0)
PH3/CS7/OE/(IRQ7) PH2/CS6/(IRQ6) PH1/CS5 PH0/CS4
Arrangement
P51/RxD2/IRQ1 P50/TxD2/IRQ0 PH1/CS5 PH0/CS4 PG3/CS3 PG2/CS2 PG1/CS1 PG0/CS0 STBY XTAL EXTAL PLLVCC PLLVSS PF6/AS PF5/RD PF4/HWR PF3/LWR PF2/LCAS/IRQ15 PF1/UCAS/IRQ14 PF0/WAIT P65/TMO1/DACK1/IRQ13 P64/TMO0/DACK0/IRQ12 P63/TMCI1/TEND1/IRQ11 P62/TMCI0/TEND0/IRQ10 /D10 /D11 /D12 /D13 /D14
Note:
used only F-ZTAT version. other versions, this pin.
/ETEND3/(IRQ3) /EDACK2/(IRQ4) /EDACK3/(IRQ5) PC0/A0 PC1/A1 PC2/A2 PC3/A3 PC4/A4 PC5/A5 PC6/A6 PC7/A7 PB0/A8 PB1/A9 PB2/A10 PB3/A11 PB4/A12 PB5/A13 PB6/A14 PB7/A15 PA0/A16 PA1/A17 PA2/A18 PA3/A19 PA4/A20 PA5/A21 PA6/A22 PA7/A23 /EDREQ0/(DREQ0) /EDREQ1/(DREQ1) /ETEND0/(TEND0)
P52/SCK2/IRQ2 P53/ADTRG/IRQ3 PH2/CS6/(IRQ6) PH3/CS7/OE/(IRQ7) PG4/ BREQO PG5/BACK PG6/BREQ P40/ P41/ P42/ P43/ Vref AVCC P44/ P45/ AN6/ AN7/ /AN12/IRQ4 /AN13/IRQ5 AN14/DA2/IRQ6 AN15/DA3/IRQ7 AVSS SCK1/(OE) P34/ SCK0 P33/ RxD1 RxD0/IrRxD P31/ TxD1 /TxD0/IrTxD /EDREQ2/ (IRQ0) /EDREQ3/ (IRQ1) P82/ETEND2/(IRQ2)
Arrangement (FP-144)
PE0/D0 PE1/D1 PE2/D2 PE3/D3 PE4/D4 PE5/D5 PE6/D6 PE7/D7 FWE* P61/TMRI1/DREQ1/IRQ9 P60/TMRI0/DREQ0/ IRQ8 P27/ TIOCB5 /EDRAK1/(IRQ15) P26/ TIOCA5 /EDRAK0/(IRQ14) P25/ /TIOCB4 /(IRQ13) P24/ /TIOCA4 /(IRQ12) P23/ /TIOCD3 /(IRQ11) P22/ /TIOCC3 /(IRQ10) P21/PO1 /TIOCB3/(IRQ9) P20/PO0 /TIOCA3/(IRQ8) P17/ PO15 /TIOCB2 /TCLKD/EDRAK3 P16/PO14 /TIOCA2/EDRAK2 P15/ PO13 /TIOCB1 /TCLKC P14/PO12 /TIOCA1 P13/ PO11 /TIOCD0 /TCLKB P12/ PO10 /TIOCC0 /TCLKA P11/ /TIOCB0 P10/ /TIOCA0 P75/EDACK1/(DACK1) P74/EDACK0/(DACK0) P73/ETEND1/(TEND1) WDTOVF
Figure Arrangement (FP-144: View)
Table
Functions Each Operating Mode
Functions Each Operating Mode
Name Flash Memory Programmer Mode
Mode P83/ ETEND3/ (IRQ3)
Mode P83/ ETEND3/ (IRQ3)
Mode P83/ ETEND3/ (IRQ3)
Mode P83/ ETEND3/ (IRQ3)
Mode P83/ ETEND3/ (IRQ3)
Mode When EXPE P83/ETEND3/ (IRQ3) When EXPE P83/(IRQ3)
P84/ EDACK2/ (IRQ4)
P84/ EDACK2/ (IRQ4)
P84/ EDACK2/ (IRQ4)
P84/ EDACK2/ (IRQ4)
P84/ EDACK2/ (IRQ4)
When EXPE P84/EDACK2/ (IRQ4) When EXPE P84/(IRQ4)
P85/ EDACK3/ (IRQ5)
P85/ EDACK3/ (IRQ5)
P85/ EDACK3/ (IRQ5)
P85/ EDACK3/ (IRQ5)
P85/ EDACK3/ (IRQ5)
When EXPE P85/EDACK3/ (IRQ5) When EXPE P85/(IRQ5)
PC0/A0
When EXPE PC0/A0 When EXPE
PC1/A1
When EXPE PC1/A1 When EXPE
PC2/A2
When EXPE PC2/A2 When EXPE
PC3/A3
When EXPE PC3/A3 When EXPE
PC4/A4
When EXPE PC4/A4 When EXPE
Name Mode Mode Mode PC5/A5 Mode Mode Mode When EXPE PC5/A5 When EXPE PC6/A6 When EXPE PC6/A6 When EXPE PC7/A7 When EXPE PC7/A7 When EXPE PB0/A8 When EXPE PB0/A8 When EXPE PB1/A9 When EXPE PB1/A9 When EXPE PB2/A10 When EXPE PB2/A10 When EXPE PB3/A11 When EXPE PB3/A11 When EXPE PB4/A12 When EXPE PB4/A12 When EXPE PB5/A13 When EXPE PB5/A13 When EXPE
Flash Memory Programmer Mode
Name Mode Mode Mode PB6/A14 Mode Mode Mode When EXPE PB6/A14 When EXPE PB7/A15 When EXPE PB7/A15 When EXPE PA0/A16 When EXPE PA0/A16 When EXPE PA1/A17 When EXPE PA1/A17 When EXPE PA2/A18 When EXPE PA2/A18 When EXPE PA3/A19 When EXPE PA3/A19 When EXPE PA4/A20 When EXPE PA4/A20 When EXPE PA5/A21 PA5/A21 PA5/A21 PA5/A21 PA5/A21 When EXPE PA5/A21 When EXPE PA6/A22 PA6/A22 PA6/A22 PA6/A22 PA6/A22 When EXPE PA6/A22 When EXPE
Flash Memory Programmer Mode
Name Mode PA7/A23 Mode PA7/A23 Mode PA7/A23 Mode PA7/A23 Mode PA7/A23 Mode When EXPE PA7/A23 When EXPE P70/ EDREQ0/ (DREQ0) P70/ EDREQ0/ (DREQ0) P70/ EDREQ0/ (DREQ0) P70/ EDREQ0/ (DREQ0) P70/ EDREQ0/ (DREQ0) When EXPE P70/EDREQ0/ (DREQ0) When EXPE P70/(DREQ0) P71/ EDREQ1/ (DREQ1) P71/ EDREQ1/ (DREQ1) P71/ EDREQ1/ (DREQ1) P71/ EDREQ1/ (DREQ1) P71/ EDREQ1/ (DREQ1) When EXPE P71/EDREQ1/ (DREQ1) When EXPE P71/(DREQ1) P72/ ETEND0/ (TEND0) P72/ ETEND0/ (TEND0) P72/ ETEND0/ (TEND0) P72/ ETEND0/ (TEND0) P72/ ETEND0/ (TEND0) When EXPE P72/ETEND0/ (TEND0) When EXPE P72/(TEND0) WDTOVF P73/ ETEND1/ (TEND1) WDTOVF P73/ ETEND1/ (TEND1) WDTOVF P73/ ETEND1/ (TEND1) WDTOVF P73/ ETEND1/ (TEND1) WDTOVF P73/ ETEND1/ (TEND1) WDTOVF When EXPE P73/ETEND1/ (TEND1) When EXPE P73/(TEND1) P74/ EDACK0/ (DACK0) P74/ EDACK0/ (DACK0) P74/ EDACK0/ (DACK0) P74/ EDACK0/ (DACK0) P74/ EDACK0/ (DACK0) When EXPE P74/EDACK0/ (DACK0) When EXPE P74/(DACK0) P75/ EDACK1/ (DACK1) P75/ EDACK1/ (DACK1) P75/ EDACK1/ (DACK1) P75/ EDACK1/ (DACK1) P75/ EDACK1/ (DACK1) When EXPE P75/EDACK1/ (DACK1) When EXPE P75/(DACK1) P10/PO8/ TIOCA0 P10/PO8/ TIOCA0 P10/PO8/ TIOCA0 P10/PO8/ TIOCA0 P10/PO8/ TIOCA0 P10/PO8/ TIOCA0
Flash Memory Programmer Mode
Name Mode P11/PO9/ TIOCB0 P12/PO10/ TIOCC0/ TCLKA P13/PO11/ TIOCD0/ TCLKB P14/PO12/ TIOCA1 P15/PO13/ TIOCB1/ TCLKC P16/PO14/ TIOCA2/ EDRAK2 Mode P11/PO9/ TIOCB0 P12/PO10/ TIOCC0/ TCLKA P13/PO11/ TIOCD0/ TCLKB P14/PO12/ TIOCA1 P15/PO13/ TIOCB1/ TCLKC P16/PO14/ TIOCA2/ EDRAK2 Mode P11/PO9/ TIOCB0 P12/PO10/ TIOCC0/ TCLKA P13/PO11/ TIOCD0/ TCLKB P14/PO12/ TIOCA1 P15/PO13/ TIOCB1/ TCLKC P16/PO14/ TIOCA2/ EDRAK2 Mode P11/PO9/ TIOCB0 P12/PO10/ TIOCC0/ TCLKA P13/PO11/ TIOCD0/ TCLKB P14/PO12/ TIOCA1 P15/PO13/ TIOCB1/ TCLKC P16/PO14/ TIOCA2/ EDRAK2 Mode P11/PO9/ TIOCB0 P12/PO10/ TIOCC0/ TCLKA P13/PO11/ TIOCD0/ TCLKB P14/PO12/ TIOCA1 P15/PO13/ TIOCB1/ TCLKC P16/PO14/ TIOCA2/ EDRAK2 Mode P11/PO9/ TIOCB0 P12/PO10/ TIOCC0/ TCLKA P13/PO11/ TIOCD0/ TCLKB P14/PO12/ TIOCA1 P15/PO13/ TIOCB1/ TCLKC When EXPE P16/PO14/ TIOCA2/ EDRAK2 When EXPE P16/PO14/ TIOCA2 P17/PO15/ TIOCB2/ TCLKD/ EDRAK3 P17/PO15/ TIOCB2/ TCLKD/ EDRAK3 P17/PO15/ TIOCB2/ TCLKD/ EDRAK3 P17/PO15/ TIOCB2/ TCLKD/ EDRAK3 P17/PO15/ TIOCB2/ TCLKD/ EDRAK3
Flash Memory Programmer Mode
When EXPE P17/PO15/ TIOCB2/TCLKD/E DRAK3 When EXPE P17/PO15/ TIOCB2/TCLKD
P20/PO0/ TIOCA3/ (IRQ8) P21/PO1/ TIOCB3/ (IRQ9) P22/PO2/ TIOCC3/ (IRQ10) P23/PO3/ TIOCD3/ (IRQ11)
P20/PO0/ TIOCA3/ (IRQ8) P21/PO1/ TIOCB3/ (IRQ9) P22/PO2/ TIOCC3/ (IRQ10) P23/PO3/ TIOCD3/ (IRQ11)
P20/PO0/ TIOCA3/ (IRQ8) P21/PO1/ TIOCB3/ (IRQ9) P22/PO2/ TIOCC3/ (IRQ10) P23/PO3/ TIOCD3/ (IRQ11)
P20/PO0/ TIOCA3/ (IRQ8) P21/PO1/ TIOCB3/ (IRQ9) P22/PO2/ TIOCC3/ (IRQ10) P23/PO3/ TIOCD3/ (IRQ11)
P20/PO0/ TIOCA3/ (IRQ8) P21/PO1/ TIOCB3/ (IRQ9) P22/PO2/ TIOCC3/ (IRQ10) P23/PO3/ TIOCD3/ (IRQ11)
P20/PO0/ TIOCA3/ (IRQ8) P21/PO1/ TIOCB3/ (IRQ9) P22/PO2/ TIOCC3/ (IRQ10) P23/PO3/ TIOCD3/ (IRQ11)
Name Mode P24/PO4/ TIOCA4/ (IRQ12) P25/PO5/ TIOCB4/ (IRQ13) P26/PO6/ TIOCA5/ EDRAK0/ (IRQ14) Mode P24/PO4/ TIOCA4/ (IRQ12) P25/PO5/ TIOCB4/ (IRQ13) P26/PO6/ TIOCA5/ EDRAK0/ (IRQ14) Mode P24/PO4/ TIOCA4/ (IRQ12) P25/PO5/ TIOCB4/ (IRQ13) P26/PO6/ TIOCA5/ EDRAK0/ (IRQ14) Mode P24/PO4/ TIOCA4/ (IRQ12) P25/PO5/ TIOCB4/ (IRQ13) P26/PO6/ TIOCA5/ EDRAK0/ (IRQ14) Mode P24/PO4/ TIOCA4/ (IRQ12) P25/PO5/ TIOCB4/ (IRQ13) P26/PO6/ TIOCA5/ EDRAK0/ (IRQ14) Mode P24/PO4/ TIOCA4/ (IRQ12) P25/PO5/ TIOCB4/ (IRQ13) When EXPE P26/PO6/ TIOCA5/ EDRAK0/ (IRQ14) When EXPE P26/PO6/ TIOCA5/(IRQ14) P27/PO7/ TIOCB5/ EDRAK1/ (IRQ15) P27/PO7/ TIOCB5/ EDRAK1/ (IRQ15) P27/PO7/ TIOCB5/ EDRAK1/ (IRQ15) P27/PO7/ TIOCB5/ EDRAK1/ (IRQ15) P27/PO7/ TIOCB5/ EDRAK1/ (IRQ15) When EXPE P27/PO7/ TIOCB5/ EDRAK1/ (IRQ15) When EXPE P27/PO7/ TIOCB5/(IRQ15) P60/TMRI0/ P60/TMRI0/ P60/TMRI0/ P60/TMRI0/ P60/TMRI0/ DREQ0/ DREQ0/ DREQ0/ DREQ0/ DREQ0/ IRQ8 IRQ8 IRQ8 IRQ8 IRQ8 P61/TMRI1/ P61/TMRI1/ P61/TMRI1/ P61/TMRI1/ P61/TMRI1/ DREQ1/ DREQ1/ DREQ1/ DREQ1/ DREQ1/ IRQ9 IRQ9 IRQ9 IRQ9 IRQ9 FWE* FWE* PE7/D7 FWE* PE7/D7 FWE* FWE* PE7/D7 P60/TMRI0/ DREQ0/ IRQ8 P61/TMRI1/ DREQ1/ IRQ9 FWE* When EXPE PE7/D7 When EXPE PE6/D6 PE6/D6 PE6/D6 When EXPE PE6/D6 When EXPE PE5/D5 PE5/D5 PE5/D5 When EXPE PE5/D5 When EXPE
Flash Memory Programmer Mode
FWE*
Name Mode Mode PE4/D4 Mode PE4/D4 Mode Mode PE4/D4 Mode When EXPE PE4/D4 When EXPE PE3/D3 PE3/D3 PE3/D3 When EXPE PE3/D3 When EXPE PE2/D2 PE2/D2 PE2/D2 When EXPE PE2/D2 When EXPE PE1/D1 PE1/D1 PE1/D1 When EXPE PE1/D1 When EXPE PE0/D0 PE0/D0 PE0/D0 When EXPE PE0/D0 When EXPE When EXPE When EXPE When EXPE When EXPE When EXPE When EXPE When EXPE When EXPE
Flash Memory Programmer Mode
I/O7
I/O6
I/O5
I/O4
Name Mode Mode Mode Mode Mode Mode When EXPE When EXPE When EXPE When EXPE
Flash Memory Programmer Mode I/O3
I/O2
When EXPE I/O1 When EXPE
When EXPE I/O0 When EXPE
P62/TMCI0/ P62/TMCI0/ P62/TMCI0/ P62/TMCI0/ P62/TMCI0/ TEND0/ TEND0/ TEND0/ TEND0/ TEND0/ IRQ10 IRQ10 IRQ10 IRQ10 IRQ10 P63/TMCI1/ P63/TMCI1/ P63/TMCI1/ P63/TMCI1/ P63/TMCI1/ TEND1/ TEND1/ TEND1/ TEND1/ TEND1/ IRQ11 IRQ11 IRQ11 IRQ11 IRQ11 P64/TMO0/ P64/TMO0/ DACK0/ DACK0/ IRQ12 IRQ12 P65/TMO1/ P65/TMO1/ DACK1/ DACK1/ IRQ13 IRQ13 PF0/WAIT PF0/WAIT P64/TMO0/ DACK0/ IRQ12 P65/TMO1/ DACK1/ IRQ13 PF0/WAIT P64/TMO0/ DACK0/ IRQ12 P65/TMO1/ DACK1/ IRQ13 PF0/WAIT P64/TMO0/ DACK0/ IRQ12 P65/TMO1/ DACK1/ IRQ13 PF0/WAIT
P62/TMCI0/ TEND0/ IRQ10 P63/TMCI1/ TEND1/ IRQ11 P64/TMO0/ DACK0/ IRQ12 P65/TMO1/ DACK1/ IRQ13 When EXPE PF0/WAIT When EXPE
PF1/UCAS/ PF1/UCAS/ PF1/UCAS/ IRQ14 IRQ14 IRQ14
PF1/UCAS/ IRQ14
PF1/UCAS/ IRQ14
When EXPE PF1/UCAS/ IRQ14 When EXPE PF1/IRQ14
Name Mode Mode Mode PF2/LCAS/ IRQ15 Mode PF2/LCAS/ IRQ15 Mode PF2/LCAS/ IRQ15 Mode When EXPE PF2/LCAS/ IRQ15 When EXPE PF2/IRQ15 PF3/LWR PF3/LWR PF3/LWR PF3/LWR PF3/LWR When EXPE PF3/LWR When EXPE When EXPE When EXPE
Flash Memory Programmer Mode
PF2/LCAS/ PF2/LCAS/ IRQ15 IRQ15
When EXPE When EXPE
PF6/AS
PF6/AS
PF6/AS
PF6/AS
PF6/AS
When EXPE PF6/AS When EXPE
PLLVSS PLLVCC EXTAL XTAL STBY PG0/CS0
PLLVSS PLLVCC EXTAL XTAL STBY PG0/CS0
PLLVSS PLLVCC EXTAL XTAL STBY PG0/CS0
PLLVSS PLLVCC EXTAL XTAL STBY PG0/CS0
PLLVSS PLLVCC EXTAL XTAL STBY PG0/CS0
PLLVSS PLLVCC EXTAL XTAL STBY When EXPE PG0/CS0 When EXPE
EXTAL XTAL
PG1/CS1
PG1/CS1
PG1/CS1
PG1/CS1
PG1/CS1
When EXPE PG1/CS1 When EXPE
Name Mode PG2/CS2 Mode PG2/CS2 Mode PG2/CS2 Mode PG2/CS2 Mode PG2/CS2 Mode When EXPE PG2/CS2 When EXPE PG3/CS3 PG3/CS3 PG3/CS3 PG3/CS3 PG3/CS3 When EXPE PG3/CS3 When EXPE PH0/CS4 PH0/CS4 PH0/CS4 PH0/CS4 PH0/CS4 When EXPE PH0/CS4 When EXPE PH1/CS5 PH1/CS5 PH1/CS5 PH1/CS5 PH1/CS5 When EXPE PH1/CS5 When EXPE P50/TxD2/ IRQ0 P51/RxD2/ IRQ1 P52/SCK2/ IRQ2 P53/ ADTRG/ IRQ3 PH2/CS6/ (IRQ6) P50/TxD2/ IRQ0 P51/RxD2/ IRQ1 P52/SCK2/ IRQ2 P53/ ADTRG/ IRQ3 PH2/CS6/ (IRQ6) P50/TxD2/ IRQ0 P51/RxD2/ IRQ1 P52/SCK2/ IRQ2 P53/ ADTRG/ IRQ3 PH2/CS6/ (IRQ6) P50/TxD2/ IRQ0 P51/RxD2/ IRQ1 P52/SCK2/ IRQ2 P53/ ADTRG/ IRQ3 PH2/CS6/ (IRQ6) P50/TxD2/ IRQ0 P51/RxD2/ IRQ1 P52/SCK2/ IRQ2 P53/ADTRG/ IRQ3 PH2/CS6/ (IRQ6) P50/TxD2/ IRQ0 P51/RxD2/ IRQ1 P52/SCK2/ IRQ2 P53/ADTRG/ IRQ3 When EXPE PH2/CS6/(IRQ6) When EXPE PH2/(IRQ6) PH3/CS7/ OE/(IRQ7) PH3/CS7/ OE/(IRQ7) PH3/CS7/ OE/(IRQ7) PH3/CS7/ OE/(IRQ7) PH3/CS7/ OE/(IRQ7) When EXPE PH3/CS7/OE/ (IRQ7) When EXPE PH3/(IRQ7) PG4/ BREQO PG4/ BREQO PG4/ BREQO PG4/ BREQO PG4/BREQO When EXPE PG4/BREQO When EXPE
Flash Memory Programmer Mode
Name Mode PG5/BACK Mode PG5/BACK Mode PG5/BACK Mode PG5/BACK Mode PG5/BACK Mode When EXPE PG5/BACK When EXPE PG6/BREQ PG6/BREQ PG6/BREQ PG6/BREQ PG6/BREQ When EXPE PG6/BREQ When EXPE P40/AN0 P41/AN1 P42/AN2 P43/AN3 Vref AVCC P44/AN4 P45/AN5 P46/ AN6/DA0 P47/AN7/ P54/AN12/ IRQ4 P55/AN13/ IRQ5 P56/AN14/ DA2/IRQ6 P57/AN15/ DA3/IRQ7 AVSS P35/SCK1/ (OE) P40/AN0 P41/AN1 P42/AN2 P43/AN3 Vref AVCC P44/AN4 P45/AN5 P46/ AN6/DA0 P47/AN7/ P54/AN12/ IRQ4 P55/AN13/ IRQ5 P56/AN14/ DA2/IRQ6 P57/AN15/ DA3/IRQ7 AVSS P35/SCK1/ (OE) P40/AN0 P41/AN1 P42/AN2 P43/AN3 Vref AVCC P44/AN4 P45/AN5 P46/ AN6/DA0 P47/AN7/ P54/AN12/ IRQ4 P55/AN13/ IRQ5 P56/AN14/ DA2/IRQ6 P57/AN15/ DA3/IRQ7 AVSS P35/SCK1/ (OE) P40/AN0 P41/AN1 P42/AN2 P43/AN3 Vref AVCC P44/AN4 P45/AN5 P46/ AN6/DA0 P47/AN7/ P54/AN12/ IRQ4 P55/AN13/ IRQ5 P56/AN14/ DA2/IRQ6 P57/AN15/ DA3/IRQ7 AVSS P35/SCK1/ (OE) P40/AN0 P41/AN1 P42/AN2 P43/AN3 Vref AVCC P44/AN4 P45/AN5 P40/AN0 P41/AN1 P42/AN2 P43/AN3 Vref AVCC P44/AN4 P45/AN5
Flash Memory Programmer Mode
P46/AN6/DA0 P46/AN6/DA0 P47/AN7/DA1 P47/AN7/DA1 P54/AN12/ IRQ4 P55/AN13/ IRQ5 P56/AN14/ DA2/IRQ6 P57/AN15/ DA3/IRQ7 AVSS P35/SCK1/ (OE) P54/AN12/ IRQ4 P55/AN13/ IRQ5 P56/AN14/ DA2/IRQ6 P57/AN15/ DA3/IRQ7 AVSS When EXPE P35/SCK1/(OE) When EXPE P35/SCK1
P34/SCK0 P33/RxD1
P34/SCK0 P33/RxD1
P34/SCK0 P33/RxD1
P34/SCK0 P33/RxD1
P34/SCK0 P33/RxD1
P34/SCK0 P33/RxD1
Name Mode P32/RxD0/ IrRxD P31/TxD1 P30/TxD0/ IrTxD P80/ EDREQ2/ (IRQ0) Mode P32/RxD0/ IrRxD P31/TxD1 P30/TxD0/ IrTxD P80/ EDREQ2/ (IRQ0) Mode P32/RxD0/ IrRxD P31/TxD1 P30/TxD0/ IrTxD P80/ EDREQ2/ (IRQ0) Mode P32/RxD0/ IrRxD P31/TxD1 P30/TxD0/ IrTxD P80/ EDREQ2/ (IRQ0) Mode P32/RxD0/ IrRxD P31/TxD1 P30/TxD0/ IrTxD P80/ EDREQ2/ (IRQ0) Mode P32/RxD0/ IrRxD P31/TxD1 P30/TxD0/ IrTxD When EXPE P80/EDREQ2/ (IRQ0) When EXPE P80/(IRQ0) P81/ EDREQ3/ (IRQ1) P81/ EDREQ3/ (IRQ1) P81/ EDREQ3/ (IRQ1) P81/ EDREQ3/ (IRQ1) P81/ EDREQ3/ (IRQ1) When EXPE P81/EDREQ3/ (IRQ1) When EXPE P81/(IRQ1) P82/ ETEND2/ (IRQ2) P82/ ETEND2/ (IRQ2) P82/ ETEND2/ (IRQ2) P82/ ETEND2/ (IRQ2) P82/ ETEND2/ (IRQ2) When EXPE P82/ETEND2/ (IRQ2) When EXPE P82/(IRQ2)
Flash Memory Programmer Mode
Note: F-ZTAT version only. other versions, this pin.
Table
Functions
Functions
Type Power
Symbol
FP-144
Input
Name Function Power: connection power supply. pins should connected system power supply. Ground: connection power supply. pins should connected system power supply power: on-chip oscillator power supply. ground: on-chip oscillator ground. connection crystal oscillator. section Clock Pulse Generator, H8S/2678 Series Hardware Manual typical connection diagrams crystal oscillator external clock input. connection crystal oscillator. EXTAL also input external clock. section Clock Pulse Generator, H8S/2678 Series Hardware Manual typical connection diagrams crystal oscillator external clock input. System clock: Supplies system clock external devices.
Input
PLLVCC PLLVSS Clock XTAL
Input Input Input
EXTAL
Input
Output
Type Operating mode control Symbol FP-144 144, Input Name Function Mode pins: These pins operating mode. relation between settings pins operating mode shown below. These pins should changed while operating.
Operating Mode Mode Mode Mode Mode Mode Mode
System control
STBY
Input Input
Reset input: When this driven low, chip reset. Standby: When this driven low, transition made hardware standby mode. request: Requests chip release external master. request output: External request signal used when internal master accesses external space when external released. request acknowledge: Indicates that been released external master. Flash write enable: Enables/disables flash memory.
BREQ BREQO
Input Output
BACK
Output
FWE*
Input
Type Interrupt signals Symbol FP-144 Input Name Function Nonmaskable interrupt: Requests nonmaskable interrupt. high when used. Interrupt request These pins request maskable interrupt.
IRQ15 IRQ0
(IRQ15) (IRQ0)
127, 107, 112, 111, 112, 111,
Input
Address
Output
Address bus: These pins output address.
Data
Input/ output
Data bus: These pins constitute bidirectional data bus.
control
Output Output
Chip select: Signals that select areas Address strobe: When this low, indicates that address output address valid. Read: When this low, indicates that external address space being read. High write/write enable: Strobe signal indicating that external space written, upper half (D15 data enabled. Write enable signal DRAM interface space.
Output
Output
Output
write: Strobe signal indicating that external space written, lower half data enabled.
Type control Symbol UCAS FP-144 Output Name Function Upper column address strobe: Upper column address strobe signal 16-bit DRAM interface space. Column address strobe signal 8-bit DRAM interface space. LCAS Output Lower column address strobe: Lower column address strobe signal 16-bit DRAM interface space. Wait: Requests insertion wait state cycle when accessing external 3-state address space. Output enable: Output enable signal DRAM interface space. transfer request These signals request DMAC activation.
WAIT
Input
(OE) controller (DMAC) DREQ1, DREQ0, (DREQ1), (DREQ0) TEND1, TEND0, (TEND1), (TEND0) DACK1, DACK0, (DACK1), (DACK0), EXDMA controller EDREQ3 (EXDMAC) EDREQ0 ETEND3 ETEND0 EDACK3 EDACK0 EDRAK3 EDRAK0
141, 140, 142,
Output Input
Output
transfer These signals indicate DMAC data transfer.
Output
transfer acknowledge DMAC single address transfer acknowledge signals. EXDMA transfer request These signals request EXDMAC activation. EXDMA transfer These signals indicate EXDMAC data transfer. EXDMA transfer acknowledge EXDMAC single address transfer acknowledge signals. EDREQ acknowledge These signals notify external device acceptance start execution external request.
Input Output
Output
Output
Type 16-bit timer pulse unit (TPU) Symbol TCLKD TCLKA TIOCA0, TIOCB0, TIOCC0, TIOCD0 TIOCA1, TIOCB1 FP-144 Input Input/ output Name Function Clock input External clock input pins. Input capture/output compare match TGR0A TGR0D input capture input/output compare output/PWM output pins. Input capture/output compare match TGR1A TGR1B input capture input/output compare output/PWM output pins. Input capture/output compare match TGR2A TGR2B input capture input/output compare output/PWM output pins. Input capture/output compare match TGR3A TGR3D input capture input/output compare output/PWM output pins. Input capture/output compare match TGR4A TGR4B input capture input/output compare output/PWM output pins. Input capture/output compare match TGR5A TGR5B input capture input/output compare output/PWM output pins. Pulse output Pulse output pins. Compare match output: Compare match output pins. Counter external clock input: Input pins external clock input counter. Counter external reset input: Counter reset input pins.
Input/ output
TIOCA2, TIOCB2
Input/ output
TIOCA3, TIOCB3, TIOCC3, TIOCD3 TIOCA4, TIOCB4
Input/ output
Input/ output
TIOCA5, TIOCB5
Input/ output
Programmable pulse generator (PPG) 8-bit timer
PO15 TMO0, TMO1 TMCI0, TMCI1 TMRI0, TMRI1
Output
Output Input
Input
Type Watchdog timer (WDT) Serial communication interface (SCI)/smart card interface (SCI0 with IrDA function) Symbol WDTOVF FP-144 Output Name Function Watchdog timer overflow: Counter overflow signal output watchdog timer mode. Transmit data (channels Data output pins. Receive data (channels Data input pins. Serial clock (channels Clock input/output pins. Analog Analog input pins. conversion external trigger input: input external trigger start conversion. Analog output: converter analog output pins. power supply converter converter. When converter converter used, this should connected system power supply AVSS Input ground converter converter. This should connected system power supply Vref Input reference voltage input converter converter. When converter converter used, this should connected system power supply
TxD2, TxD1, TxD0/IrTxD
107, 138,
Output
RxD2, RxD1, 108, 135, RxD0/IrRxD SCK2, SCK1, 109, 133, SCK0
Input Input/ output Input
converter
AN15 AN12, ADTRG
127, 123,
Input
converter
DA3, DA2, DA1,
130, 129, 126,
Output
converter, converter
AVCC
Input
Type ports Symbol FP-144 Input/ output Name Function Port Eight input/output pins. direction each selected port data direction register (P1DDR). Port Eight input/output pins. direction each selected port data direction register (P2DDR). Port input/output pins. direction each selected port data direction register (P3DDR). Port Eight input pins. Port Four input pins four input/output pins. direction each input/output selected port data direction register (P5DDR). Port input/output pins. direction each selected port data direction register (P6DDR). Port input/output pins. direction each selected port data direction register (P7DDR). Port input/output pins. direction each selected port data direction register (P8DDR). Port Eight input/output pins. direction each selected port data direction register (PADDR). Port Eight input/output pins. direction each selected port data direction register (PBDDR).
Input/ output
135,
Input/ output
123, 127,
Input Input Input/ output Input/ output
Input/ output
Input/ output
Input/ output
Input/ output
Type ports Symbol FP-144 Input/ output Name Function Port Eight input/output pins. direction each selected port data direction register (PCDDR). Port Eight input/output pins. direction each selected port data direction register (PDDDR). Port Eight input/output pins. direction each selected port data direction register (PEDDR). Port Eight input/output pins. direction each selected port data direction register (PFDDR). Port Seven input/output pins. direction each selected port data direction register (PGDDR). Port Four input/output pins. direction each selected port data direction register (PHDDR).
Input/ output
Input/ output
Input/ output
113,
Input/ output
112, 111, 106,
Input/ output
Note: F-ZTAT version only. other versions, this pin.
Table
Product Lineup
H8S/2678 Series Product Lineup
Model F-ZTATversion F-ZTATversion HD64F2677 HD64F2676 Marking HD64F2677VFC HD64F2676VFC HD6432676FC HD6432675FC HD6432673FC HD6412670VFC 144-pin plastic (FP-144) 144-pin plastic (FP-144) 144-pin plastic (FP-144) Package (Hitachi Package Code) 144-pin plastic (FP-144) 144-pin plastic (FP-144)
Product Type H8S/2677*2 H8S/2676*
Mask version HD6432676 H8S/2675* H8S/2673* H8S/2670*
Mask version HD6432675 Mask version HD6432673 ROMless version HD6412670
Notes: Under development planning stage
Package Dimensions
22.0
Unit:
22.0
*0.22 0.05 0.20 0.04
3.05
*0.17 0.05 0.15 0.04
2.70
0.10
1.25
0.10
*Dimension including plating thickness Base material dimension
0.10 +0.15 -0.10
Hitachi Code JEDEC EIAJ Weight (reference value)
FP-144G Conforms
Figure FP-144 Package Dimensions
Section Operating Modes
2.1.1
Overview
Operating Mode Selection (F-ZTAT Version)
H8S/2678 Series F-ZTAT version twelve operating modes (modes that selected flash write enable (FWE) mode pins (MD2 MD0). input these pins determines operating mode initial width, shown table 2.1. Table lists operating modes.
Table
Operating Mode Selection (F-ZTAT Version)
External Data On-Chip Initial Width Max. Width bits bits bits
Operating Operating Mode Mode Description Advanced Expanded mode with on-chip disabled Expanded mode with on-chip enabled External activation expanded mode with on-chip enabled Single-chip activation mode with on-chip enabled
Disabled bits bits Enabled bits
Enabled
bits bits
bits bits
Enabled
bits
Advanced
Boot mode
Enabled
bits
bits bits bits bits bits
Advanced
User program mode User program mode
Enabled
bits bits
Advanced
Enabled
bits
CPU's architecture allows gigabytes address space, H8S/2678 Series chip actually accesses maximum Mbytes. Modes externally expanded modes that allow access external memory peripheral devices. externally expanded modes allow switching between 8-bit 16-bit modes. After program execution starts, 8-bit 16-bit address space each area, depending controller setting. 16-bit access selected area, 16-bit mode set; 8bit access selected areas, 8-bit mode set. functions depend operating mode. Mode single-chip activation externally expanded mode that allows access external memory peripheral devices switched start program execution. single-chip activation externally expanded mode, possible switch between externally expanded mode single-chip mode means EXPE system control register (SYSCR). Immediately after reset, chip starts single-chip mode, after start program execution, possible change externally expanded mode setting EXPE accordingly. functions depend operating mode. Modes boot modes user program modes that allow programming erasing flash memory. details section ROM, H8S/2678 Series Hardware Manual. H8S/2678 Series F-ZTAT Version used only modes This means that flash write enable mode pins must select these modes. change inputs mode pins during operation. 2.1.2 Operating Mode Selection (ROMless Mask Versions)
H8S/2678 Series ROMless mask versions have operating modes* (modes that selected mode pins (MD2 MD0). input these pins determines operating mode, enabling disabling on-chip ROM, initial width, shown table 2.2. Table lists operating modes.
Table
Operating Mode Selection* (ROMless Mask Versions)
External Data Description Expanded mode with on-chip disabled Expanded mode with on-chip enabled External activation expanded mode with on-chip enabled Single-chip activation mode with on-chip enabled On-Chip Initial Width Max. Width bits bits bits
Operating Mode
Operating Mode Advanced
Disabled bits bits Enabled bits
Advanced
bits
bits
bits
bits bits
Note: Only modes available ROMless version.
CPU's architecture allows gigabytes address space, H8S/2678 Series chip actually accesses maximum Mbytes. Modes externally expanded modes that allow access external memory peripheral devices. externally expanded modes allow switching between 8-bit 16-bit modes. After program execution starts, 8-bit 16-bit address space each area, depending controller setting. 16-bit access selected area, 16-bit mode set; 8bit access selected areas, 8-bit mode set. functions depend operating mode. single-chip activation externally expanded mode, possible switch between externally expanded mode single-chip mode. Immediately after reset, chip starts single-chip mode, after start program execution, possible change externally expanded mode setting EXPE system control register (SYSCR) accordingly. functions depend operating mode.
H8S/2678 Series mask version used only modes ROMless version only modes This means that mode pins must select these modes. change inputs mode pins during operation. 2.1.3 Register Configuration
H8S/2678 Series mode control register (MDCR) that indicates inputs mode pins (MD2 MD0), system control register (SYSCR) that controls operation chip. Table summarizes these registers. Table
Name Mode control register System control register
Registers
Abbreviation MDCR SYSCR Initial Value Undefined H'C1/H'C3*
Address*1 H'FF3E H'FF3D
Notes: Lower bits address. Determined pins MD0.
2.2.1
Register Descriptions
Mode Control Register (MDCR)
MDS2 MDS1 MDS0
Initial value Read/Write
Note: Determined pins MD0.
MDCR 8-bit read-only register that monitors current operating mode H8S/2678 Series chip. Bits 3-Reserved: These bits always read cannot modified. write value should always Bits 0-Mode Select (MD2 MD0): These bits indicate input levels pins (the current operating mode). Bits MDS2 MDS0 correspond pins MD0. MDS2 MDS0 read-only bits-they cannot written mode (MD2 MD0) input levels latched into these bits when MDCR read. These latches canceled reset.
2.2.2
System Control Register (SYSCR)
MACS FLSHE EXPE RAME
Initial value Read/Write
Note: Determined pins MD0.
Bits 6-Reserved: These readable/writable bits, write value should always 5-MAC Saturation (MACS): Selects either saturating non-saturating calculation instruction.
MACS Description Non-saturating calculation instruction Saturating calculation instruction (Initial value)
4-Reserved: This readable/writable bit, write value should always 3-Flash Memory Control Register Enable (FLSHE): Controls access flash memory control registers (FLMCR1, FLMCR2, EBR1, EBR2). details section ROM, H8S/2678 Series Hardware Manual. mask ROMless versions, should written this bit.
FLSHE Description Flash memory control registers selected area H'FFFFC8 H'FFFFCB (Initial value) Flash memory control registers selected area H'FFFFC8 H'FFFFCB
2-Reserved: This always read cannot modified. write value should always 1-External Mode Enable (EXPE): Sets external mode. modes this fixed cannot modified. modes this initial value read written.
Writing EXPE when value should only carried when external cycle* being executed. Note: There cases where external internal cycles executed parallel write data buffer function, refresh control function, EXDMAC, bus-released state, forth.
EXPE Description External disabled External enabled
0-RAM Enable (RAME): Enables disables on-chip RAM. RAME initialized when reset state released. initialized software standby mode.
RAME Description On-chip disabled On-chip enabled (Initial value)
2.3.1
Operating Mode Descriptions
Mode (Expanded Mode with On-Chip Disabled)
access 16-Mbyte address space advanced mode. on-chip disabled. Ports function address bus, ports function data bus, parts ports carry control signals. initial mode after reset bits, with 16-bit access areas. However, 8-bit access designated areas controller, mode switches bits. 2.3.2 Mode (Expanded Mode with On-Chip Disabled)
This externally expanded mode with on-chip disabled. Operation same mode except that initial external mode after reset bits. 2.3.3 Mode
This mode supported H8S/2678 Series, must selected.
2.3.4
Mode (Expanded Mode with On-Chip Enabled)
access 16-Mbyte address space advanced mode. on-chip enabled. Ports function input ports immediately after reset, function address bus. details section Ports. Port functions data bus, parts ports carry control signals. initial mode after reset bits, with 8-bit access areas. program on-chip connected first half area executed. However, 16-bit access designated area controller, mode switches bits port functions data bus. 2.3.5 Mode (External Activation Expanded Mode with On-Chip Enabled)
access 16-Mbyte address space advanced mode. on-chip ROM*1 enabled. Ports function address bus, ports function data bus, parts ports carry control signals. initial mode after reset bits, with 16-bit access areas. program on-chip ROM*2 connected first half area executed. However, 8-bit access designated area controller, mode switches bits. Notes: H8S/2678: H'100000 H'180000; H8S/2675: H'100000 H'140000 H8S/2678, H8S/2675: H'000000 H'100000 2.3.6 Mode (External Activation Expanded Mode with On-Chip Enabled)
This external activation expanded mode with on-chip disabled. Operation same mode except that initial external mode after reset bits. 2.3.7 Mode (Single-Chip Activation Mode with On-Chip Enabled)
access 16-Mbyte address space advanced mode. on-chip enabled, chip starts single-chip mode. External addresses cannot used single-chip mode, they made accessible means setting system control register (SYSCR). When external addresses enabled, settings made designate ports address output, ports data bus. details section Ports. initial mode after reset single-chip mode, with ports available input/output ports. However, mode switched externally expanded mode means setting SYSCR. When externally expanded mode selected, areas initially designated 16-bit access space. function pins ports same externally expanded mode with on-chip enabled.
2.3.8
Modes [F-ZTAT Version Only]
Modes supported H8S/2678 Series, must selected. 2.3.9 Mode [F-ZTAT Version Only]
This flash memory boot mode. details section ROM, H8S/2678 Series Hardware Manual. Except flash memory erasing programming, operation same mode (advanced expanded mode with on-chip enabled). 2.3.10 Mode
This flash memory boot mode. details section ROM, H8S/2678 Series Hardware Manual. Except flash memory erasing programming, operation same mode (advanced single-chip activation expanded mode with on-chip enabled). 2.3.11 Mode
This flash memory user program mode. details section ROM, H8S/2678 Series Hardware Manual. Except flash memory erasing programming, operation same mode (advanced expanded mode with on-chip enabled). 2.3.12 Modes [F-ZTAT Version Only]
This flash memory user program mode. details section ROM, H8S/2678 Series Hardware Manual. Except flash memory erasing programming, operation same modes (advanced external activation expanded mode with on-chip enabled). 2.3.13 Mode [F-ZTAT Version Only]
This flash memory user program mode. details section ROM, H8S/2678 Series Hardware Manual. Except flash memory erasing programming, operation same mode (advanced single-chip activation expanded mode with on-chip enabled).
Functions Each Operating Mode
functions ports vary depending operating mode. Table shows their functions each operating mode. Table Functions Each Operating Mode
Mode Mode Mode Mode Mode Mode Mode Mode Mode Mode Mode Mode P*/A P/D* PF7, PF5, Port Port P/C* P/C* P*/C P*/C P/C* P*/C P*/A P*/D P/C* P/C* P*/C P*/C P/C* P*/C P*/A P*/A P/D* P/C* P/C* P*/C P*/C P*/C P*/C P*/A P*/A P/D* P/C* P/C* P*/C P*/C P/C* P*/C P*/A P*/D P/C* P/C* P*/C P*/C P/C* P*/C P*/C P*/C P*/A P*/A P*/D P*/D P*/C P*/A P*/A P*/D P*/C P/C* P*/C P*/C P/C* P*/C P*/C P*/C P*/A P*/A P*/D P*/D P*/C P*/A P*/A P*/A P*/A P*/A P*/A P*/D P/C* P/C* P*/C P*/C P*/C P*/C P/D* P/C* P/C* P*/C P*/C P/C* P*/C P*/A P*/A P*/D P/C* P/C* P*/C P*/C P/C* P*/C P*/C P*/C P*/A P*/A P*/D P*/D P*/C P*/A
Port Port Port Port Port Port Port
Legend: port Address output Data input/output Control signals, clock input/output Note: After reset
Memory Each Operating Mode
Figures 2.13 show memory maps each operating modes. address space Mbytes. on-chip capacity kbytes H8S/2677, kbytes H8S/2676, kbytes H8S/2675, kbytes H8S/2673; on-chip capacity kbytes. address space divided into eight areas. details section Controller. Only advanced mode supported H8S/2678 Series.
Modes (expanded modes with on-chip disabled) H'000000
Mode (expanded mode with on-chip enabled) H'000000
On-chip
External address space
H'060000
External address space
H'FFA000 On-chip RAM/external address space* H'FFC000 External address space H'FFFC00 Internal registers
H'FFA000 On-chip RAM/external address space* H'FFC000 External address space H'FFFC00 Internal registers H'FFFF00 H'FFFF20 H'FFFFFF External address space Internal registers
H'FFFF00 External address space H'FFFF20 Internal registers H'FFFFFF
Note: External addresses accessed clearing RAME SYSCR
Figure H8S/2677 Memory Each Operating Mode
Modes (external activation expanded modes with on-chip enabled) H'000000
Mode (single-chip activation expanded mode with on-chip enabled) H'000000
On-chip External address space
H'060000
H'100000
On-chip External address space/reserved area*2
H'160000 External address space
H'FFA000 On-chip RAM/external address space*1 H'FFC000 External address space H'FFFC00 Internal registers
H'FFA000 On-chip RAM/external address space*3 H'FFC000 H'FFFC00 H'FFFF00 H'FFFF20 H'FFFFFF
External address space/reserved area*2
Internal registers
External address space/reserved area*2
H'FFFF00 External address space H'FFFF20 H'FFFFFF Internal registers
Internal registers
Notes: External addresses accessed clearing RAME SYSCR When EXPE external address space; when EXPE reserved area. When EXPE external address space when RAME on-chip when RAME When EXPE on-chip area.
Figure H8S/2677 Memory Each Operating Mode
Mode Boot mode (expanded mode with on-chip enabled) H'000000
Mode Boot mode (single-chip activation expanded mode with on-chip enabled) H'000000
On-chip
On-chip
H'060000
H'060000
External address space
External address space/reserved area*1
H'FFA000 On-chip RAM*2 H'FFC000 External address space H'FFFC00 Internal registers
H'FFA000 On-chip RAM*2 H'FFC000 H'FFFC00 H'FFFF00 H'FFFF20 H'FFFFFF
External address space/reserved area*1
Internal registers
External address space/reserved area*1
H'FFFF00 External address space H'FFFF20 Internal registers H'FFFFFF
Internal registers
Notes: When EXPE external address space; when EXPE reserved area. On-chip used flash memory programming. clear RAME SYSCR
Figure H8S/2677 Memory Each Operating Mode [F-ZTATVersion Only]
Mode User program mode (expanded mode with on-chip enabled) H'000000
Modes (external activation expanded modes with on-chip enabled) H'000000
Mode User program mode (single-chip activation expanded mode with on-chip enabled) H'000000
On-chip
External address space
On-chip
H'060000 H'100000
H'060000
On-chip External address space H'160000 External address space External address space/reserved area*1
H'FFA000 On-chip RAM*2 H'FFC000 External address space H'FFFC00 Internal registers
H'FFA000 On-chip RAM*2 H'FFC000 External address space H'FFFC00 Internal registers
H'FFA000 On-chip RAM*2 H'FFC000 H'FFFC00 H'FFFF00 H'FFFF20 H'FFFFFF
External address space/reserved area*1
Internal registers
External address space/reserved area*1
H'FFFF00 External address space H'FFFF20 Internal registers H'FFFFFF
H'FFFF00 External address space H'FFFF20 H'FFFFFF Internal registers
Internal registers
Notes: When EXPE external address space; when EXPE reserved area. On-chip used flash memory programming. clear RAME SYSCR
Figure H8S/2677 Memory Each Operating Mode [F-ZTATVersion Only]
Modes (expanded modes with on-chip disabled) H'000000
Mode (expanded mode with on-chip enabled) H'000000
On-chip
H'040000
External address space
External address space
H'FFA000 On-chip RAM/external address space* H'FFC000 External address space H'FFFC00 Internal registers
H'FFA000 On-chip RAM/external address space* H'FFC000 External address space H'FFFC00 Internal registers H'FFFF00 External address space H'FFFF20 Internal registers H'FFFFFF
H'FFFF00 External address space H'FFFF20 Internal registers H'FFFFFF
Note: External addresses accessed clearing RAME SYSCR
Figure H8S/2676 Memory Each Operating Mode
Modes (external activation expanded modes with on-chip enabled) H'000000
Mode (single-chip activation expanded mode with on-chip enabled) H'000000
On-chip External address space
H'040000
H'100000 External address space/reserved area*2
On-chip
H'140000 External address space
H'FFA000 On-chip RAM/external address space*1 H'FFC000 External address space H'FFFC00 Internal registers
H'FFA000 On-chip RAM/external address space*3 H'FFC000 H'FFFC00 H'FFFF00 H'FFFF20 H'FFFFFF
External address space/reserved area*2
Internal registers
External address space/reserved area*2
H'FFFF00 External address space H'FFFF20 Internal registers H'FFFFFF
Internal registers
Notes: External addresses accessed clearing RAME SYSCR When EXPE external address space; when EXPE reserved area. When EXPE external address space when RAME on-chip when RAME When EXPE on-chip area.
Figure H8S/2676 Memory Each Operating Mode
Mode Boot mode (expanded mode with on-chip enabled)
Mode Boot mode (single-chip activation expanded mode with on-chip enabled)
H'000000
H'000000
On-chip
On-chip
H'040000
H'040000
External address space
External address space/reserved area*1
H'FFA000
H'FFA000
On-chip RAM*2
H'FFC000 External address space H'FFFC00 H'FFFF00 H'FFFF20 H'FFFFFF H'FFC000 H'FFFC00 H'FFFF00 H'FFFF20 H'FFFFFF
On-chip RAM*2
External address space/reserved area*1
Internal registers External address space Internal registers
Internal registers
External address space/reserved area*1
Internal registers
Notes: When EXPE external address space; when EXPE reserved area. On-chip used flash memory programming. clear RAME SYSCR
Figure H8S/2676 Memory Each Operating Mode [F-ZTATVersion Only]
Mode User program mode (expanded mode with on-chip enabled)
H'000000
Modes (external activation expanded modes with on-chip enabled) H'000000
Mode User program mode (single-chip activation expanded mode with on-chip enabled)
H'000000
On-chip
On-chip
H'040000
External address space
H'040000
H'100000 External address space External address space/reserved area*1
On-chip
H'140000 External address space
H'FFA000
H'FFA000 On-chip RAM*2 On-chip RAM*2
H'FFA000
On-chip RAM*2
H'FFC000 H'FFFC00 H'FFFF00 H'FFFF20 H'FFFFFF
External address space/reserved area*1
H'FFC000 External address space H'FFFC00 H'FFFF00 H'FFFF20 H'FFFFFF
H'FFC000 External address space H'FFFC00 Internal registers
Internal registers External address space Internal registers
Internal registers
External address space/reserved area*1
H'FFFF00 External address space H'FFFF20 Internal registers H'FFFFFF
Internal registers
Notes: When EXPE external address space; when EXPE reserved area. On-chip used flash memory programming. clear RAME SYSCR
Figure H8S/2676 Memory Each Operating Mode [F-ZTATVersion Only]
Modes (expanded modes with on-chip disabled) H'000000
Mode (expanded mode with on-chip enabled) H'000000 On-chip H'020000
External address space
External address space
H'FFA000 On-chip RAM/external address space* H'FFC000 External address space H'FFFC00 Internal registers
H'FFA000 On-chip RAM/external address space* H'FFC000 External address space H'FFFC00 Internal registers H'FFFF00 External address space H'FFFF20 Internal registers H'FFFFFF
H'FFFF00 External address space H'FFFF20 Internal registers H'FFFFFF
Note: External addresses accessed clearing RAME SYSCR
Figure H8S/2675 Memory Each Operating Mode
Modes (external activation expanded modes with on-chip enabled) H'000000
Mode (single-chip activation expanded mode with on-chip enabled) H'000000 On-chip H'020000
External address space
H'100000 On-chip H'120000
External address space/reserved area*2
External address space
H'FFA000 On-chip RAM/external address space*1 H'FFC000 External address space H'FFFC00 Internal registers
H'FFA000 On-chip RAM/external address space*3 H'FFC000 H'FFFC00 H'FFFF00 H'FFFF20 H'FFFFFF
External address space/reserved area*2
Internal registers
External address space/reserved area*2
H'FFFF00 External address space H'FFFF20 Internal registers H'FFFFFF
Internal registers
Notes: External addresses accessed clearing RAME SYSCR When EXPE external address space; when EXPE reserved area. When EXPE external address space when RAME on-chip when RAME When EXPE on-chip area.
Figure 2.10 H8S/2675 Memory Each Operating Mode
Modes (expanded modes with on-chip disabled) H'000000
Mode (expanded mode with on-chip enabled) H'000000 H'010000
On-chip
External address space
External address space
H'FFA000 On-chip RAM/external address space* H'FFC000 External address space H'FFFC00 Internal registers
H'FFA000 On-chip RAM/external address space* H'FFC000 External address space H'FFFC00 Internal registers H'FFFF00 External address space H'FFFF20 Internal registers H'FFFFFF
H'FFFF00 External address space H'FFFF20 Internal registers H'FFFFFF
Note: External addresses accessed clearing RAME SYSCR
Figure 2.11 H8S/2673 Memory Each Operating Mode
Modes (external activation expanded modes with on-chip enabled) H'000000
Mode (single-chip activation expanded mode with on-chip enabled) H'000000 H'010000
On-chip
External address space
H'100000 H'110000
External address space/reserved area*2 On-chip
External address space
H'FFA000 On-chip RAM/external address space*1 H'FFC000 External address space H'FFFC00 Internal registers
H'FFA000 On-chip RAM/external address space*3 H'FFC000 H'FFFC00 H'FFFF00 H'FFFF20 H'FFFFFF
External address space/reserved area*2
Internal registers
External address space/reserved area*2
H'FFFF00 External address space H'FFFF20 Internal registers H'FFFFFF
Internal registers
Notes: External addresses accessed clearing RAME SYSCR When EXPE external address space; when EXPE reserved area. When EXPE external address space when RAME on-chip when RAME When EXPE on-chip area.
Figure 2.12 H8S/2673 Memory Each Operating Mode
Modes (expanded modes with on-chip disabled) H'000000
External address space
H'FFA000 On-chip RAM/external address space* H'FFC000 External address space H'FFFC00 Internal registers
H'FFFF00 External address space H'FFFF20 Internal registers H'FFFFFF Note: External addresses accessed clearing RAME SYSCR
Figure 2.13 H8S/2670 Memory Each Operating Mode
Section Exception Handling Interrupt Controller
3.1.1
Overview
Exception Handling Types Priority
table indicates, exception handling caused reset, trap instruction, interrupt. Exception handling prioritized shown table 3.1. more exceptions occur simultaneously, they accepted processed order priority. Trap instruction exceptions accepted times program execution state. Exception handling sources, stack structure, operation vary depending interrupt control mode INTM0 INTM1 bits INTCR. details exception handling interrupt controller, section Exception Handling, section Interrupt Controller, H8S/2678 Series Hardware Manual. Table
Priority High
Exception Types Priority
Exception Type Reset Trace*1 Interrupt Start Exception Handling Starts after low-to-high transition pin, when watchdog timer overflows Starts when execution current instruction exception handling ends, trace Starts when execution current instruction exception handling ends, interrupt request been issued*2 Started execution trap instruction (TRAPA)
Trap instruction*3 (TRAPA)
Notes: Traces enabled only interrupt control mode Trace exception handling executed after execution instruction. Interrupt detection performed completion ANDC, ORC, XORC, instruction execution, completion reset exception handling. Trap instruction exception handling requests accepted times program execution state.
3.2.1
Interrupt Controller
Interrupt Controller Features
interrupt control modes Either interrupt control modes means INTM1 INTM0 bits interrupt control register (INTCR). Priorities settable with IPRs Interrupt priority registers (IPRs) provided setting interrupt priorities. Eight priority levels each module interrupts except NMI. assigned highest priority level accepted times. Independent vector addresses interrupt sources assigned independent vector addresses, making unnecessary source identified interrupt handling routine. Seventeen external interrupt pins highest-priority interrupt, accepted times. Rising edge falling edge selected NMI. Falling edge, rising edge, both edge detection, level sensing, selected independently IRQ15 IRQ0. DMAC control DMAC activation controlled means interrupts.
3.2.2
Block Diagram
Figure shows block diagram interrupt controller.
INTM1 INTM0 INTCR NMIEG input input input unit input unit ITSR Internal interrupt sources SWDTEND Interrupt controller Legend ISCR: IER: ISR: IPR: INTCR: ITSR: ISCR Priority determination Interrupt request Vector number
sense control register enable register status register Interrupt priority register Interrupt control register select register
Figure Block Diagram Interrupt Controller
3.2.3
Configuration
Table summarizes interrupt controller pins. Table
Name Nonmaskable interrupt External interrupt request
Interrupt Controller Pins
Abbreviation IRQ15 IRQ0 Input Input Function Nonmaskable external interrupt; rising falling edge selected Maskable external interrupts; rising, falling, both edges, level sensing, selected
3.2.4
Register Configuration
Table summarizes registers interrupt controller. Table
Name Interrupt control register sense control register sense control register enable register status register select register Software standby release enable register Interrupt priority register Interrupt priority register Interrupt priority register Interrupt priority register Interrupt priority register Interrupt priority register Interrupt priority register Interrupt priority register Interrupt priority register Interrupt priority register Interrupt priority register Notes: Lower bits address. Only written, clear flags.
Interrupt Controller Registers
Abbreviation INTCR ISCRH ISCRL ITSR SSIER IPRA IPRB IPRC IPRD IPRE IPRF IPRG IPRH IPRI IPRJ IPRK R/(W)*
Initial Value H'00 H'0000 H'0000 H'0000 H'0000 H'0000 H'0007 H'7777 H'7777 H'7777 H'7777 H'7777 H'7777 H'7777 H'7777 H'7777 H'7777 H'7777
Address*1 H'FF31 H'FE1A H'FE1C H'FF32 H'FF34 H'FE16 H'FE18 H'FE00 H'FE02 H'FE04 H'FE06 H'FE08 H'FE0A H'FE0C H'FE0E H'FE10 H'FE12 H'FE14
3.3.1
Register Descriptions
Interrupt Control Register (INTCR)
INTM1 INTM0 NMIEG
Initial value Read/Write
INTCR 8-bit readable/writable register that selects interrupt control mode, detected edge NMI. INTCR initialized H'00 reset hardware standby mode. initialized software standby mode. Bits 6-Reserved: These bits always read cannot modified. Bits 4-Interrupt Control Mode (INTM1, INTM0): These bits select either interrupt control modes interrupt controller.
INTM1 INTM0 Interrupt Control Mode Description Interrupts controlled Setting prohibited Interrupts controlled bits Setting prohibited (Initial value)
3-NMI Edge Select (NMIEG): Selects input edge pin.
NMIEG Description Interrupt request generated falling edge input Interrupt request generated rising edge input (Initial value)
Bits 0-Reserved: These bits always read cannot modified.
3.3.2
Interrupt Priority Registers (IPRA IPRK)
IPR14 IPR6 IPR13 IPR5 IPR12 IPR4 IPR10 IPR2 IPR9 IPR1 IPR8 IPR0
Initial value Read/Write
Initial value Read/Write
registers eleven 16-bit readable/writable registers that priorities (levels interrupts other than NMI. correspondence between interrupt sources settings shown table 3.4. registers priority (level each interrupt source other than NMI. registers initialized H'7777 reset hardware standby mode. Bits 3-Reserved: These bits always read cannot modified. Table Correspondence between Interrupt Sources Settings
Bits IRQ1 IRQ5 IRQ9 IRQ13 Interval timer converter channel Bits IRQ2 IRQ6 IRQ10 IRQ14 channel channel Bits IRQ3 IRQ7 IRQ11 IRQ15 Refresh timer channel channel EXDMAC channel
Register Bits IPRA IPRB IPRC IPRD IPRE IPRF IPRG IPRH IPRI IPRJ IPRK IRQ0 IRQ4 IRQ8 IRQ12 channel
8-bit timer channel 8-bit timer channel DMAC
EXDMAC channel EXDMAC channel EXDMAC channel channel channel channel
Note: Reserved bits. These bits read H'7, write value should H'7.
shown table 3.4, multiple interrupts assigned IPR. Setting value range from 3-bit groups bits sets priority corresponding interrupt. lowest priority level, level assigned setting H'0, highest priority level, level setting H'7. When interrupt requests generated, highest-priority interrupt according priority levels registers selected. This interrupt level then compared with interrupt mask level interrupt mask bits extend register (EXR) CPU, priority level interrupt higher than mask level, interrupt request issued CPU. 3.3.3
Enable Register (IER)
IRQ15E IRQ14E IRQ6E IRQ13E IRQ5E IRQ12E IRQ4E IRQ11E IRQ3E IRQ10E IRQ2E IRQ9E IRQ1E IRQ8E IRQ0E
Initial value Read/Write
IRQ7E
Initial value Read/Write
16-bit readable/writable register that controls enabling disabling interrupt requests IRQ15 IRQ0. initialized H'0000 reset hardware standby mode. Bits 0-IRQ15 IRQ0 Enable (IRQ15E IRQ0E): These bits select whether interrupts IRQ15 IRQ0 enabled disabled.
IRQnE Description IRQn interrupts disabled IRQn interrupts enabled (Initial value)
3.3.4 ISCRH
Sense Control Registers (ISCRH, ISCRL)
IRQ15SCB IRQ15SCA IRQ14SCB IRQ14SCA IRQ13SCB IRQ13SCA IRQ12SCB IRQ12SCA
Initial value Read/Write
IRQ11SCB IRQ11SCA IRQ10SCB IRQ10SCA IRQ9SCB IRQ9SCA IRQ8SCB IRQ8SCA
Initial value Read/Write
ISCRL
IRQ7SCB IRQ7SCA IRQ6SCB IRQ6SCA IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA
Initial value Read/Write
IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA
Initial value Read/Write
ISCR registers 16-bit readable/writable registers that select rising edge, falling edge, both edge detection, level sensing, input pins IRQ15 IRQ0. ISCR registers initialized H'0000 reset hardware standby mode.
Bits 0-IRQ15 Sense Control (IRQ15SCA, IRQ15SCB) IRQ0 Sense Control (IRQ0SCA, IRQ0SCB)
IRQnSCB IRQnSCA Description Interrupt request generated IRQn input level Interrupt request generated falling edge IRQn input Interrupt request generated rising edge IRQn input Interrupt request generated both falling rising edges IRQn input (Initial value)
3.3.5
Status Register (ISR)
IRQ15F IRQ14F R/(W)* IRQ6F R/(W)* IRQ13F R/(W)* IRQ5F R/(W)* IRQ12F R/(W)* IRQ4F R/(W)* IRQ11F R/(W)* IRQ3F R/(W)* IRQ10F R/(W)* IRQ2F R/(W)* IRQ9F R/(W)* IRQ1F R/(W)* IRQ8F R/(W)* IRQ0F R/(W)*
Initial value Read/Write
R/(W)* IRQ7F
Initial value Read/Write
R/(W)*
Note: Only written, clear flag.
16-bit readable/writable register that indicates status IRQ15 IRQ0 interrupt requests. initialized H'0000 reset hardware standby mode. IRQnF depending states after reset, necessary read ISR, then write following reset.
Bits 0-IRQ15 IRQ0 Flags (IRQ15F IRQ0F): These bits indicate status IRQ15 IRQ0 interrupt requests.
IRQnF Description [Clearing conditions] When written IRQnF after reading IRQnF When interrupt exception handling executed when low-level detection (IRQnSCB IRQnSCA IRQn input high When IRQn interrupt exception handling executed when falling, rising, bothedge detection (IRQnSCB IRQnSCA When activated IRQn interrupt DISEL When IRQn input goes when low-level detection (IRQnSCB IRQnSCA When falling edge occurs IRQn input when falling edge detection (IRQnSCB IRQnSCA When rising edge occurs IRQn input when rising edge detection (IRQnSCB IRQnSCA When falling rising edge occurs IRQn input when both-edge detection (IRQnSCB IRQnSCA (Initial value)
[Setting conditions]
3.3.6
Select Register (ITSR)
ITS15 ITS14 ITS6 ITS13 ITS5 ITS12 ITS4 ITS11 ITS3 ITS10 ITS2 ITS9 ITS1 ITS8 ITS0
Initial value Read/Write
ITS7
Initial value Read/Write
ITSR 16-bit readable/writable register that selects input pins IRQ15 IRQ0. ITSR initialized H'0000 reset hardware standby mode. Bits 0-IRQ Input Select (ITS15 ITS0): IRQn input pins used pins shown below according value ITSn.
ITS15 ITS14 ITS13 ITS12 ITS11 ITS10 ITS9 ITS8 ITS7 ITS6 ITS5 ITS4 ITS3 ITS2 ITS1 ITS0 (Initial Value)
When ITSR setting changed, selected level before change different from selected level after change, edge generated internally IRQnF unintended timing. IRQn interrupt enabled this time, associated interrupt exception handling will executed. prevent unintended interrupts, make changes ITSR settings with IRQn interrupts disabled, then clear IRQnF 15). 3.3.7
Software Standby Release Enable Register (SSIER)
SSI15 SSI14 SSI6 SSI13 SSI5 SSI12 SSI4 SSI11 SSI3 SSI10 SSI2 SSI9 SSI1 SSI8 SSI0
Initial value Read/Write
SSI7
Initial value Read/Write
SSIER 16-bit readable/writable register that selects pins used recover from software standby state. SSIER initialized H'0007 reset hardware standby mode. interrupt used recover from software standby state must activation source. Bits 0-Software Standby Release Setting (SSI15 SSI0): These bits select pins used recover from software standby state.
SSIn Description IRQn requests sampled software standby state (Initial value when When IRQn request occurs software standby state, chip recovers from software standby state after elapse oscillation settling time (Initial value when
Interrupt Sources
Interrupt sources comprise external interrupts (NMI IRQ15 IRQ0) internal interrupts sources). 3.4.1 External Interrupts
There external interrupt sources: IRQ15 IRQ0. Setting SSIER enables corresponding IRQ15-IRQ0 interrupt used software standby mode release source. Interrupt: highest-priority interrupt, always accepted regardless interrupt control mode status interrupt mask bits. NMIEG INTCR specifies whether interrupt requested rising edge falling edge pin. vector number interrupt exception handling IRQ15 IRQ0 Interrupts: Interrupts IRQ15 IRQ0 requested input signal pins IRQ15 IRQ0. Interrupts IRQ15 IRQ0 have following features: Using ISCR, possible select whether interrupt generated level, falling edge, rising edge, both edges, pins IRQ15 IRQ0. Enabling disabling interrupt requests IRQ15 IRQ0 selected with IER. interrupt priority level with IPR. status interrupt requests IRQ15 IRQ0 indicated ISR. flags cleared software. block diagram interrupts IRQ15 IRQ0 shown figure 3.2.
IRQnE
IRQnSCA, IRQnSCB IRQnF Edge/ level detection circuit Clear signal Note:
IRQn interrupt request
IRQn input
Figure Block Diagram Interrupts IRQ15 IRQ0
Figure shows timing setting IRQnF.
IRQn input
IRQnF
Figure Timing Setting IRQnF vector numbers IRQ15 IRQ0 interrupt exception handling Detection IRQ15 IRQ0 interrupts does depend whether relevant been input output. When used external interrupt input pin, clear corresponding another function. When interrupt request generation level selected IRQ15 IRQ0 interrupt means ISCR setting, when interrupt requested relevant should held until interrupt handling starts. should then returned high level, IRQnF cleared, interrupt handling routine. returned high level before interrupt handling started, associated interrupt executed. 3.4.2 Internal Interrupts
There sources internal interrupts from on-chip supporting modules. each on-chip supporting module there flags that indicate interrupt request status, enable bits that select enabling disabling these interrupts. these interrupt request issued interrupt controller. interrupt priority level means IPR. DMAC activated TPU, SCI, other interrupt request. When DMAC activated interrupt, interrupt control mode interrupt mask bits have effect.
3.4.3
Interrupt Vector Table
Table shows interrupt exception handling sources, their vector addresses, their priority order. default priority order, smaller vector numbers have higher priority. Priorities among modules means IPR. priority order when more modules same priority, priority order within module, fixed shown table 3.5.
Table
Interrupt Sources, Vector Addresses, Priority Order
Origin Interrupt Source Vector Number Vector Address* H'0000 H'0004 H'0008 H'000C H'0010 H'0014 H'0018 H'001C H'0020 H'0024 H'0028 H'002C H'0030 H'0034 H'0038 H'0040 H'0044 H'0048 H'004C H'0050 H'0054 H'0058 H'005C H'0060 H'0064 H'0068 H'006C H'0070 H'0074 H'0078 H'007C IPRA14-IPRA12 IPRA10-IPRA8 IPRA6-IPRA4 IPRA2-IPRA0 IPRB14-IPRB12 IPRB10-IPRB8 IPRB6-IPRB4 IPRB2-IPRB0 IPRC14-IPRC12 IPRC10-IPRC8 IPRC6-IPRC4 IPRC2-IPRC0 IPRD14-IPRD12 IPRD10-IPRD8 IPRD6-IPRD4 IPRD2-IPRD0 Activation DMAC Activation
Interrupt Source Power-on reset Reserved Reserved system
Priority High
Trace Reserved system Trap instruction sources) External
Reserved system
IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15
External
Interrupt Source SWDTEND (softwareactivated data transfer end) WOVI (interval timer) Reserved (compare match) Reserved
Origin Interrupt Source
Vector Number
Vector Address* H'0080
IPRE14- IPRE12 IPRE10-IPRE8 IPRE6-IPRE4 IPRE2-IPRE0 IPRF14-IPRF12
Priority High
Activation
DMAC Activation
Watchdog timer Refresh controller
H'0084 H'0088 H'008C H'0090 H'0094 H'0098 H'009C H'00A0 H'00A4 H'00A8 H'00AC H'00B0 H'00B4 H'00B8 H'00BC H'00C0 H'00C4 H'00C8 H'00CC H'00D0 H'00D4 H'00D8 H'00DC
(A/D conversion end) Reserved TGI0A (TGR0A input capture/compare match) TGI0B (TGR0B input capture/compare match) TGI0C (TGR0C input capture/compare match) TGI0D (TGR0D input capture/compare match) TCI0V (overflow Reserved
channel
IPRF10-IPRF8 IPRF6-IPRF4
TGI1A (TGR1A input capture/compare match) TGI1B (TGR1B input capture/compare match) TCI1V (overflow TCI1U (underflow TGI2A (TGR2A input capture/compare match) TGI2B (TGR2B input capture/compare match) TCI2V (overflow TCI2U (underflow
channel
IPRF2-IPRF0 IPRG14- IPRG12
channel
Interrupt Source TGI3A (TGR3A input capture/compare match) TGI3B (TGR3B input capture/compare match) TGI3C (TGR3C input capture/compare match) TGI3D (TGR3D input capture/compare match) TCI3V (overflow Reserved
Origin Interrupt Source channel
Vector Number
Vector Address* H'00E0 H'00E4 H'00E8 H'00EC H'00F0 H'00F4 H'00F8 H'00FC H'0100 H'0104 H'0108 H'010C H'0110 H'0114 H'0118 H'011C H'0120 H'0124 H'0128 H'012C H'0130 H'0134 H'0138 H'013C
IPRG10- IPRG8
Priority High
Activation
DMAC Activation
TGI4A (TGR4A input capture/compare match) TGI4B (TGR4B input capture/compare match) TCI4V (overflow TCI4U (underflow TGI5A (TGR5A input capture/compare match) TGI5B (TGR5B input capture/compare match) TCI5V (overflow TCI5U (underflow
channel
IPRG6-IPRG4 IPRG2-IPRG0 IPRH14-IPRH12 IPRH10-IPRH8
channel
CMIA0 (compare match 8-bit timer CMIB0 (compare match channel OVI0 (overflow Reserved
CMIA1 (compare match 8-bit timer CMIB1 (compare match channel OVI1 (overflow Reserved
Interrupt Source
Origin Interrupt Source
Vector Number
Vector Address* H'0140 H'0144 H'0148 H'014C H'0150 H'0154 H'0158 H'015C H'0160 H'0164 H'0168 H'016C H'0170 H'0174 H'0178 H'017C H'0180 H'0184 H'0188 H'018C
IPRH6-IPRH4
Priority High
Activation
DMAC Activation
DMTEND0A (channel DMAC 0/channel transfer end) DMTEND0B (channel transfer end) DMTEND1A (channel 1/channel transfer end) DMTEND1B (channel transfer end) EXDMTEND0 (channel transfer end) EXDMTEND1 (channel transfer end) EXDMTEND2 (channel transfer end) EXDMTEND3 (channel transfer end) RXI0 (receive completed channel TXI0 (transmit data empty TEI0 (transmit RXI1 (receive completed channel TXI1 (transmit data empty TEI1 (transmit ERI2 (receive error RXI2 (receive completed channel TXI2 (transmit data empty TEI2 (transmit ERI1 (receive error ERI0 (receive error EXDMAC
IPRH2-IPRH0 IPRI14-IPRI12 IPRI10-IPRI8 IPRI6-IPRI4 IPRI2-IPRI0
IPRJ14-IPRJ12
IPRJ10-IPRJ8
Interrupt Source Reserved
Origin Interrupt Source
Vector Number
Vector Address* H'0190 H'0194 H'0198 H'019C H'01A0 H'01A4 H'01A8 H'01AC H'01B0 H'01B4 H'01B8 H'01BC H'01C0 H'01C4 H'01C8 H'01CC H'01D0 H'01D4 H'01D8 H'01DC H'01E0 H'01E4 H'01E8 H'01EC H'01F0 H'01F4 H'01F8 H'01FC
IPRJ6-IPRJ4
Priority High
Activation
DMAC Activation
IPRJ2-IPRJ0
IPRK14-IPRK12
IPRK10-IPRK8
IPRK6-IPRK4
IPRK2-IPRK2
Notes: Interrupt sources vary depending model. reference manual relevant model details. Lower bits start address.
3.5.1
Interrupt Operation
Interrupt Control Modes Interrupt Operation
Interrupt operations H8S/2678 Series differ depending interrupt control mode. interrupts accepted times except reset state hardware standby state. case interrupts on-chip supporting module interrupts, enable provided each interrupt. Clearing enable disables corresponding interrupt request. Interrupt sources which enable bits controlled interrupt controller. Table shows interrupt control modes. interrupt controller performs interrupt control according interrupt control mode INTM1 INTM0 bits INTCR, priorities IPR, masking state indicated CPU's CCR, bits EXR. Table
Interrupt Control Mode
Interrupt Control Modes
INTCR INTM1 INTM0 Priority Setting Registers
Interrupt Mask Bits
Description Interrupt mask control performed bit. Setting prohibited 8-level interrupt mask control performed bits priority levels with IPR.
Setting prohibited
Figure shows block diagram priority decision circuit.
Interrupt control mode
Interrupt acceptance control Default priority determination
Interrupt source
Vector number
8-level mask control
Interrupt control mode
Figure Block Diagram Interrupt Control Operation Interrupt Acceptance Control: interrupt control mode interrupt acceptance control performed means CCR. Table shows interrupts that selected each interrupt control mode. Table Interrupts Selected Each Interrupt Control Mode
Interrupt Mask Interrupt Control Mode Don't care Selected Interrupts interrupts interrupt interrupts
8-Level Control: interrupt control mode 8-level mask level determination performed according interrupt priority level (IPR) interrupts selected interrupt acceptance control. interrupt source selected interrupt with highest priority level, which priority level higher than mask level. Table Interrupts Selected Each Interrupt Control Mode
Selected Interrupts interrupts Highest-priority-level (IPR) interrupt whose priority level greater than mask level (IPR
Interrupt Control Mode
Default Priority Determination: When interrupt selected 8-level control, priority determined vector number generated. same value IPR, acceptance multiple interrupts enabled, only interrupt source with highest priority according preset default priorities selected vector number generated. Interrupt sources with lower priority than accepted interrupt source held pending. Table shows operations control signal functions each interrupt control mode. Table Operations Control Signal Functions Each Interrupt Control Mode
Interrupt Acceptance Control
Setting Interrupt Control Mode INTM1 INTM0
8-Level Control I2-I0
Default Priority Determination (Trace)
Legend Interrupt operation control performed operation (all interrupts enabled) Used interrupt mask Sets priority. used. Notes: when interrupt accepted. Keep initial setting (IPR writes prohibited).
3.5.2
Interrupt Control Mode
Enabling disabling interrupts on-chip supporting module interrupts means CPU's CCR. Interrupts enabled when cleared disabled when Figure shows flowchart interrupt acceptance operation this case. interrupt source occurs when corresponding interrupt enable interrupt request sent interrupt controller. then referenced. cleared interrupt request accepted. only interrupt accepted, other interrupt requests held pending. Interrupt requests sent interrupt controller, highest-priority interrupt according priority order selected, others held pending. When interrupt request accepted, processing instruction being executed that time completed before interrupt exception handling started. saved stack area interrupt exception handling. value saved stack shows address first instruction executed after returning from interrupt service routine. Next, This masks interrupts except NMI. vector address generated accepted interrupt, execution interrupt service routine starts address indicated contents that vector address.
Program execution state
Interrupt generated? NMI?
Hold pending
IRQ0?
IRQ1?
TEI2?
Save Read vector address Branch interrupt service routine
Figure Flowchart Procedure Interrupt Acceptance Interrupt Control Mode
3.5.3
Interrupt Control Mode
Eight-level masking implemented interrupts on-chip supporting module interrupts comparing interrupt mask level bits with IPR. Figure shows flowchart interrupt acceptance operation this case. interrupt source occurs when corresponding interrupt enable interrupt request sent interrupt controller. When interrupt requests sent interrupt controller, interrupt with highest priority level according interrupt priority levels selected, lower-priority interrupt requests held pending. number interrupt requests with same priority generated same time, interrupt request with highest priority according priority system shown table selected. Next, priority selected interrupt request compared with interrupt mask level EXR. interrupt request with priority higher than mask level that time held pending, only interrupt request with priority higher than interrupt mask level accepted. When interrupt request accepted, processing instruction being executed that time completed before interrupt exception handling started. CCR, saved stack area interrupt exception handling. value saved stack shows address first instruction executed after returning from interrupt service routine. cleared result, interrupt mask level rewritten with priority level accepted interrupt. accepted interrupt NMI, interrupt mask level H'7. vector address generated accepted interrupt, execution interrupt service routine starts address indicated contents that vector address.
Program execution state
Interrupt generated? NMI? Level interrupt? Level interrupt? Mask level below?
Level interrupt? Mask level below?
Mask level
Save CCR,
Hold pending
Clear
Update mask level
Read vector address
Branch interrupt service routine
Figure Flowchart Procedure Interrupt Acceptance Interrupt Control Mode
3.5.4
Interrupt Exception Handling Sequence
Figure shows interrupt exception handling sequence. example shown case where interrupt control mode advanced mode, program area stack area on-chip memory.
Interrupt acceptance Instruction prefetch Stack Vector fetch Internal operation Internal operation Interrupt service routine instruction prefetch (11) (13) (10) (12) (14)
Interrupt level determination Wait instruction
Interrupt request signal
Internal address
Internal read signal
Internal write signal
Figure Interrupt Exception Handling
Internal data
(2), (6), (9), (11) (10), (12) (13) (14)
Instruction prefetch address (not executed; saved contents (return address)) Instruction code (not executed) Instruction prefetch address (not executed) Saved saved Vector address Interrupt service routine start address (vector address contents) Interrupt service routine start address ((13) (10), (12)) First instruction interrupt service routine
3.5.5
Interrupt Response Times
H8S/2678 Series capable fast word access on-chip memory, program area provided on-chip stack area on-chip RAM, enabling high-speed processing. Table 3.10 shows interrupt response times-the interval between generation interrupt request execution first instruction interrupt service routine. symbols used table 3.10 explained table 3.11. Table 3.10 Interrupt Response Times
Advanced Mode Item Interrupt priority determination*
INTM1
INTM1
Number wait states until executing instruction ends*2 Saving CCR, stack Vector fetch Instruction fetch*
Internal processing*
Total (using on-chip memory) Notes:
states case internal interrupt. Refers MULXS DIVXS instructions. Prefetch after interrupt acceptance interrupt service routine prefetch. Internal processing after interrupt acceptance internal processing after vector fetch.
Table 3.11 Number States Interrupt Exception Handling
Object Access External Device 8-Bit Symbol Instruction fetch Branch address read Stack manipulation Legend Number wait states external device access Internal Memory 2-State Access 3-State Access 16-Bit 2-State Access 3-State Access
3.6.1
Usage Notes
Contention between Interrupt Generation Disabling
When interrupt enable cleared disable interrupts, disabling becomes effective after execution instruction. other words, when interrupt enable cleared instruction such BCLR MOV, interrupt generated during execution instruction, interrupt concerned will still enabled completion instruction, interrupt exception handling that interrupt will executed completion instruction. However, there interrupt request higher priority than that interrupt, interrupt exception handling will executed higher-priority interrupt, lower-priority interrupt will ignored. same also applies when interrupt source flag cleared Figure shows example which TGIEA TPU's TIER0 register cleared
TIER0 write cycle TGI0A exception handling
Internal address Internal write signal
TIER0 address
TGIEA
TGFA
TGI0A interrupt signal
Figure Contention between Interrupt Generation Disabling above contention will occur enable interrupt source flag cleared while interrupt masked.
3.6.2
Instructions that Disable Interrupts
Instructions that disable interrupts LDC, ANDC, ORC, XORC. After these instructions executed, interrupts except disabled next instruction always executed. When these instructions, value valid states after instruction execution completed. 3.6.3 Periods when Interrupts Disabled
There periods during which interrupt acceptance interrupt controller disabled. interrupt controller disables interrupt acceptance 3-state period after updated mask level with LDC, ANDC, ORC, XORC instruction. 3.6.4 Interrupts during Execution EEPMOV Instruction
EEPMOV.B instruction EEPMOV.W instruction differ their reaction interrupt requests. With EEPMOV.B instruction, interrupt request (including NMI) issued during transfer accepted until transfer completed. With EEPMOV.W instruction, interrupt request issued during transfer, interrupt exception handling starts break transfer cycle. value saved stack this case address next instruction. following coding should used allow interrupts generated during execution EEPMOV.W instruction.
MOV.W EEPMOV.W R4,R4
3.7.1
DMAC Activation Interrupt
Overview
DMAC activated interrupt. this case, following options available. Some models have on-chip DMAC; reference manual relevant model details.
Interrupt request Activation request Activation request DMAC Selection number above
details interrupt requests that used activate DMAC, section Data Transfer Controller, section Controller, H8S/2678 Series Hardware Manual. 3.7.2 Block Diagram
Figure shows block diagram DTC, DMAC, interrupt controller.
DMAC
Disable signal
Clear signal
Interrupt request interrupt
Selection circuit Select signal Clear signal DTCER
activation request vector number
Control logic Clear signal
Interrupt source On-chip clear signal supporting module
DTVECR SWDTE clear signal Priority determination Interrupt controller interrupt request vector number
Figure Interrupt Control DMAC
3.7.3
Operation
interrupt controller three main functions DMAC control. Selection Interrupt Source: With DMAC, activation source input directly each channel. activation source each DMAC channel selected with bits DTF3 DTF0 DMACR. selected activation source managed DMAC selected with DMABCR. When interrupt source constituting that DMAC activation source does function activation source interrupt source. interrupt sources other than interrupts managed DMAC, possible select activation request interrupt request with DTCE DTCERA DTCERH DTC. DISEL DTC's register used specify clearing DTCE issuance interrupt request after data transfer. When performed specified number data transfers transfer counter value following data transfer DTCE cleared interrupt request sent CPU. Determination Priority: activation source selected accordance with default priority order, affected mask priority levels. Priorities shown table 3.12. With DMAC, activation source input directly each channel. Operation Order: same interrupt selected activation source interrupt source, data transfer performed first, followed interrupt exception handling. same interrupt selected DMAC activation source activation source interrupt source, operations performed them independently according their respective operating statuses mastership priorities. Table 3.13 summarizes interrupt source selection interrupt source clearance control according settings DMABCR DMAC, DTCE DTCERA DTCERH DTC, DISEL DTC.
Table 3.12 Interrupt Sources, Vector Addresses, Corresponding DTCE Bits
Origin Interrupt Source Software External Vector Number DTVECR channel channel channel Vector Address Advanced Mode H'0400+ (DTVECR[6:0]<<1) H'0420 H'0422 H'0424 H'0426 H'0428 H'042A H'042C H'042E H'0430 H'0432 H'0434 H'0436 H'0438 H'043A H'043C H'043E H'044C H'0450 H'0452 H'0454 H'0456 H'0460 H'0462 H'0468 H'046A
Interrupt Source Write DTVECR IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 (A/D conversion end) TGI0A (TGR0A compare match/input capture) TGI0B (TGR0B compare match/input capture) TGI0C (TGR0C compare match/input capture) TGI0D (TGR0D compare match/input capture) TGI1A (TGR1A compare match/input capture) TGI1B (TGR1B compare match/input capture) TGI2A (TGR2A compare match/input capture) TGI2B (TGR2B compare match/input capture)
DTCE* DTCEA7 DTCEA6 DTCEA5 DTCEA4 DTCEA3 DTCEA2 DTCEA1 DTCEA0 DTCEB7 DTCEB6 DTCEB5 DTCEB4 DTCEB3 DTCEB2 DTCEB1 DTCEB0 DTCEC6 DTCEC5 DTCEC4 DTCEC3 DTCEC2 DTCEC1 DTCEC0 DTCED7 DTCED6
Priority High
Interrupt Source TGI3A (TGR3A compare match/input capture) TGI3B (TGR3B compare match/input capture) TGI3C (TGR3C compare match/input capture) TGI3D (TGR3D compare match/input capture) TGI4A (TGR4A compare match/input capture) TGI4B (TGR4B compare match/input capture) TGI5A (TGR5A compare match/input capture) TGI5B (TGR5B compare match/input capture) CMI0A (compare match CMI0B (compare match CMI1A (compare match CMI1B (compare match DMTEND0A (channel 0/channel transfer end) DMTEND0B (channel transfer end) DMTEND1A (channel 1/channel transfer end) DMTEND1B (channel transfer end) RXI0 (receive completed TXI0 (transmit data empty RXI1 (receive completed TXI1 (transmit data empty RXI2 (receive completed TXI2 (transmit data empty
Origin Interrupt Source channel
Vector Number
Vector Address Advanced Mode H'0470 H'0472 H'0474 H'0476 H'0480 H'0482 H'0488 H'048A H'0490 H'0492 H'0498 H'049A H'04A0 H'04A2 H'04A4 H'04A6 H'04B2 H'04B4 H'04BA H'04BC H'04C2 H'04C4
DTCE* DTCED5 DTCED4 DTCED3 DTCED2 DTCED1 DTCED0 DTCEE7 DTCEE6 DTCEE3 DTCEE2 DTCEE1 DTCEE0 DTCEF7 DTCEF6 DTCEF5 DTCEF4 DTCEF3 DTCEF2 DTCEF1 DTCEF0 DTCEG7 DTCEG6
Priority High
channel
channel
8-bit timer channel
8-bit timer channel
DMAC
channel
channel
channel
Note: DTCE bits with corresponding interrupt reserved, should written with When clearing software standby state all-module-clocks-stop mode with interrupt, write corresponding DTCE bit.
Table 3.13 Interrupt Source Selection Clearing Control
Settings DMAC DTCE DISEL Interrupt Source Selection/Clearing Control DMAC
Legend relevant interrupt used. Interrupt source clearing performed. (The should clear source flag interrupt service routine.) relevant interrupt used. interrupt source cleared. relevant cannot used. Don't care
Usage Note: converter interrupt sources cleared when DMAC reads writes prescribed register, dependent DISEL bits.
Section Controller
Overview
H8S/2678 Series on-chip controller (BSC) that manages external address space divided into eight areas. specifications, such width number access states, independently each area, enabling multiple memories external devices connected easily. controller also arbitration function, controls operation internal masters-the CPU, controller (DMAC), data transfer controller (DTC), external transfer DMAC (EXDMAC). 4.1.1 Features
features controller listed below. Manages external address space area units Manages external space eight areas Mbytes specifications independently each area 8-bit access 16-bit access selected each area DRAM burst interfaces Basic interface Chip select signals (CS0 CS7) output areas 2-state access 3-state access selected each area Program wait states inserted each area assertion period extension states inserted each area DRAM interface DRAM interface areas address/column address multiplexed output (8/9/10/11 bits) 2-CAS access method byte control Burst operation using fast page mode cycle insertion secure precharging time Selection CAS-before-RAS (CBR) refreshing self-refreshing signal output Continuous DRAM space designated areas Burst interface Burst interface area area Area area burst interfaces independently
Idle cycle insertion idle cycle inserted case external read cycles different areas idle cycle inserted case external write cycle immediately after external read cycle Write buffer function External write cycle internal access executed parallel DMAC single address mode internal access executed parallel arbitration function Includes arbiter that arbitrates mastership between CPU, DMAC, DTC, EXDMAC Other features Refresh counter (refresh timer) used interval timer External release function EXDMAC external transfer internal access executed parallel
4.1.2
Block Diagram
EXDMAC address Internal address
Address selector
Area decoder
External controller
WAIT BREQ BACK BREQO
Internal master request signal EXDMAC request signal Internal master acknowledge signal EXDMAC acknowledge signal
External arbiter
External control signals
Internal control signals Internal controller request signal request signal DMAC request signal acknowledge signal acknowledge signal DMAC acknowledge signal
Internal arbiter
Control registers Internal data ABWCR ASTCR DRAMCRH DRAMCRL DRACCR REFCRH RTCNT CSACRL REFCRL RTCOR WTCRAH WTCRAL WTCRBH WTCRBL RDNCR CSACRH
BROMCRH BROMCRL BCRH BCRL
Figure Block Diagram Controller
4.1.3
Configuration
Table summarizes pins controller. Table
Name Address strobe
Controller Pins
Abbreviation Output Function Strobe signal indicating that address output address enabled during access basic interface space. Strobe signal indicating that basic interface space being read. Strobe signal indicating that basic interface space being written upper half (D15 data enabled. DRAM interface space write enable signal.
Read High write/write enable
Output Output
write
Output
Strobe signal indicating that basic interface space being written lower half data enabled. Strobe signal indicating that area selected. Strobe signal indicating that area selected. Strobe signal indicating that area selected. DRAM address strobe signal when area DRAM interface space areas continuous DRAM interface space.
Chip select Chip select Chip select 2/row address strobe
Output Output Output
Chip select 3/row address strobe
Output
Strobe signal indicating that area selected. DRAM address strobe signal when area DRAM interface space.
Chip select 4/row address strobe
Output
Strobe signal indicating that area selected. DRAM address strobe signal when area DRAM interface space.
Name Chip select 5/row address strobe
Abbreviation
Output
Function Strobe signal indicating that area selected. DRAM address strobe signal when area DRAM interface space.
Chip select Chip select Upper column address strobe
UCAS
Output Output Output
Strobe signal indicating that area selected. Strobe signal indicating that area selected. 16-bit DRAM interface space upper column address strobe signal. 8-bit DRAM interface space column address strobe signal.
Lower column strobe Output enable Wait request request acknowledge request output
LCAS WAIT BREQ BACK BREQO
Output Output Input Input Output Output
16-bit DRAM interface space lower column address strobe signal. DRAM interface space output enable signal. Wait request signal when accessing external space. Request signal release external device. Acknowledge signal indicating that been released. External request signal used when internal master accesses external space when external released. Data transfer acknowledge signal single address transfer DMAC channel Data transfer acknowledge signal single address transfer DMAC channel Data transfer acknowledge signal single address transfer EXDMAC channel Data transfer acknowledge signal single address transfer EXDMAC channel Data transfer acknowledge signal single address transfer EXDMAC channel Data transfer acknowledge signal single address transfer EXDMAC channel
Data transfer acknowledge (DMAC) Data transfer acknowledge (DMAC) Data transfer acknowledge (EXDMAC) Data transfer acknowledge (EXDMAC) Data transfer acknowledge (EXDMAC) Data transfer acknowledge (EXDMAC)
DACK1 DACK0 EDACK3 EDACK2 EDACK1 EDACK0
Output Output Output Output Output Output
4.1.4
Register Configuration
Table summarizes registers controller. Table Controller Registers
Initial Value Name width control register Access state control register Wait control register Wait control register Read strobe timing control register Chip select assertion period control registers Burst interface control registers Abbreviation ABWCR ASTCR WTCRA WTCRB RDNCR CSACRH CSACRL BROMCRH BROMCRL control register DRAM control register DRAM access control register Refresh control register Refresh timer counter Refresh time constant register DRAMCR DRACCR REFCR RTCNT RTCOR Reset Address*1 Register Size (Bits)
H'FF/H'00*2 H'FEC0 H'FF H'7777 H'7777 H'00 H'00 H'00 H'00 H'00 H'1C00 H'0000 H'00 H'0000 H'00 H'FF H'FEC1 H'FEC2 H'FEC4 H'FEC6 H'FEC8 H'FEC9 H'FECA H'FECB H'FECC H'FED0 H'FED2 H'FED4 H'FED6 H'FED7
Notes: Lower bits address. Determined operating mode.
4.2.1
Register Descriptions
Width Control Register (ABWCR)
ABW7 ABW6 ABW5 ABW4 ABW3 ABW2 ABW1 ABW0
Modes Initial value Read/Write Modes Initial value Read/Write
ABWCR 8-bit readable/writable register that designates each area either 8-bit access space 16-bit access space. ABWCR sets data width external memory space. width on-chip memory internal registers fixed regardless settings ABWCR. After reset hardware standby mode, ABWCR initialized H'FF modes H'00 modes initialized software standby mode. Bits 0-Area Width Control (ABW7 ABW0): These bits select whether corresponding area designated 8-bit access space 16-bit access space.
ABWn Description Area designated 16-bit access space Area designated 8-bit access space
4.2.2
Access State Control Register (ASTCR)
AST7 AST6 AST5 AST4 AST3 AST2 AST1 AST0
Initial value Read/Write
ASTCR 8-bit readable/writable register that designates each area either 2-state access space 3-state access space.
ASTCR sets number access states external memory space. number access states on-chip memory internal registers fixed regardless settings ASTCR. ASTCR initialized H'FF reset hardware standby mode. initialized software standby mode. Bits 0-Area Access State Control (AST7 AST0): These bits select whether corresponding area designated 2-state access space 3-state access space. Wait state insertion enabled disabled same time.
ASTn Description Area designated 2-state access space Wait state insertion area external space access disabled Area designated 3-state access space Wait state insertion area external space access enabled (Initial value)
4.2.3
Wait Control Registers (WTCRA, WTCRB)
WTCRA WTCRB 16-bit readable/writable registers that select number program wait states each area. Program waits inserted on-chip memory internal register access. WTCRA WTCRB initialized H'7777 reset hardware standby mode. They initialized software standby mode. WTCRA
Initial value Read/Write Initial value Read/Write
WTCRB
Initial value Read/Write Initial value Read/Write
Bits 3-Reserved: These bits always read cannot modified. Bits 0-Wait Control (Wn2, Wn1, Wn0): These bits select number program wait states areas designated 3-state access space ASTCR.
Description Program wait inserted area external access program wait state inserted area external access program wait states inserted area external access program wait states inserted area external access program wait states inserted area external access program wait states inserted area external access program wait states inserted area external access program wait states inserted area external access
4.2.4
Read Strobe Timing Control Register (RDNCR)
RDN7 RDN6 RDN5 RDN4 RDN3 RDN2 RDN1 RDN0
Initial value Read/Write
RDNCR 8-bit readable/writable register that selects read strobe (RD) negation timing when area designated basic interface space.
RDNCR initialized H'00 reset hardware standby mode. initialized software standby mode. Bits 0-Read Strobe Timing Control (RDNn): shown figure 4.2, read strobe area which RDNn negated half-state earlier than that area which RDNn cleared read data setup hold time specifications also half-state earlier. read strobe negated half-state earlier regardless 2-state 3-state access designation, number program waits.
Bits RDNn Description area read access, strobe negated read cycle (Initial value) area read access, strobe negated half-state

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