CDMA Transmitter Subsystem with Integrated Voltage Regulator AD6122

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CDMA Transmitter Subsystem with Integrated Voltage Regulator AD6122

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FEATURES Fully Compliant with IS98A Specifications Linear Amplifier Linear-in-dB Gain Control Temperature-Compensated Gain Control Quadrature Modulator Modulates from Integral Dropout Regulator Accepts Input from Battery Power 10.4 Midgain Sleep Mode Operation Companion Receiver Chip Available (AD6121) APPLICATIONS CDMA, W-CDMA, AMPS TACS Operation QPSK Transmitters GENERAL DESCRIPTION
CDMA Transmitter Subsystem with Integrated Voltage Regulator AD6122
range amplifiers with voltage-controlled gain powerdown control input. integral dropout regulator allows operation from battery voltages from gain control input accepts external gain control voltage input from DAC. provides gain control with nominal dB/V scale factor. Either internal external reference used gain-control scale factor. modulator accepts differential quadrature baseband inputs from CDMA baseband converter. local oscillator injected twice frequency. divide-by-two quadrature generator followed dual polyphase filters ensures quadrature accuracy. modulator provides common-mode reference output bias transmit DACs baseband converter same common-mode voltage modulator inputs, allowing coupling between thus eliminating need charge discharge coupling capacitors. This allows fastest power-up power-down times AD6122 CDMA baseband ICs. AD6122 fabricated using silicon BiCMOS process packaged 28-lead SSOP 32-leadless LPCC chip scale package mm).
AD6122 power transmitter subsystem, specifically designed CDMA applications. consists modulator, divide-by-two quadrature generator, high dynamic
FUNCTIONAL BLOCK DIAGRAM
QUADRATURE MODULATOR OUTPUT QUADRATURE MODULATOR INPUT
ATTENUATOR
AMPLIFIER INPUT
AMPLIFIERS LOCAL OSCILLATOR INPUT INPUT COMMON-MODE REFERENCE OUTPUT VPOS DROPOUT REGULATOR VREG TRANSMIT OUTPUT
AD6122
GAIN CONTROL SCALE FACTOR
TEMPERATURE COMPENSATION
POWER- POWERDOWN DOWN
1.23 GAIN CONTROL GAIN CONTROL VOLTAGE REFERENCE REFERENCE INPUT OUTPUT VOLTAGE INPUT
REV.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices.
Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Site: http://www.analog.com Fax: 781/326-8703 Analog Devices, Inc., 2000
AD6122-SPECIFICATIONS1 noted) NOTE: powers shown referred
+3.0
REFIN 1.23 Enabled, unless otherwise
Unit
Specification MODULATOR Output Level Output Third Order Harmonic Inputs Differential Input Voltage Bandwidth Resistance Quadrature Accuracy Amplitude Balance Output Referred Noise Modulator Common-Mode Reference Input Resistance Input Capacitance Carrier Leakage AMPLIFIER Noise Figure Input Compression Point Input Third-Order Intercept Gain Flatness Input Capacitance Differential Input Resistance Differential Output Resistance Differential Output Capacitance GAIN CONTROL INTERFACE Gain Scaling Gain Scaling Linearity Minimum Gain Maximum Gain Gain Control Response Time Input Resistance REFIN Input Resistance VGAIN POWER-DOWN INTERFACE Logic Threshold High Logic Threshold Input Current Logical High Turn-On Response Time Turn-Off Response Time DROPOUT REGULATOR Input Range Nominal Output Dropout Voltage Reference Output POWER SUPPLY Supply Range Bypassing Internal Supply Current Standby Current OPERATING TEMPERATURE TMIN TMAX
Specifications subject change without notice.
Conditions 260.76 IF), Differential Inputs; Output Level Referred Differential Load
-169 1.408 0.25 1.34 1.30
dBm/Hz dB/V dB/V
Differential
Offsets Differential Input 260.38 Differential Input 260.38 Bias Using MODCMREF 130.38 VGAIN Differential Load VGAIN VGAIN Shunt Equivalent Model 130.38 Shunt Equivalent Model 130.38 130.38 130.38 Using Internal Reference Typical Dynamic Range VGAIN VGAIN Gain Change, Gain Gain
Power-Up Logical High
Measure Settling from Standby Mode Supply Current External Pass Transistor, -0.4 Max, 100/300 Min/Max
2.9-4.2 2.70 1.23 2.7-5.0 10.4
VGAIN (Unity Gain)
REV.
AD6122
ABSOLUTE MAXIMUM RATINGS
Supply Voltage DVCC, IFVCC, TXVCC DGND, IFGND Internal Power Dissipation2 Operating Temperature Range -40°C +85°C Storage Temperature Range -65°C +150°C Lead Temperature Range (Soldering sec) +300°C
NOTES Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only; functional operation device these other conditions above those indicated operational section this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability. Thermal Characteristics: 28-lead SSOP Package: 115.25°C/W.
CONFIGURATIONS
SSOP Package
LPCC Package
REFOUT
VGAIN
REFIN
LDOE LDOB LDOC LDOGND DGND LOIPP LOIPN
VGAIN REFIN REFOUT IFVCC IFGND
IFVCC
LDOE
LDOB LDOC LDOGND LDOGND DGND LOIPP LOIPN DVCC
TXOPP
IFGND IFGND IIPP
AD6122
VIEW
IIPP IIPN
(Not Scale) MODCMREF QIPN QIPP MODOPP MODOPN IFINP IFINN
AD6122 View (Not Scale)
IIPN MODCMREF QIPN QIPP MODOPP
DVCC TXOPP TXOPN TXVCC IFGND
IFGND IFGND MODOPN TXOPN TXVCC IFINN IFINP
CONNECT
ORDERING GUIDE
Model AD6122ARS AD6122ARSRL AD6122ACP AD6122ACPRL
Temperature Range -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C
Package Description Shrink Small Outline Package (SSOP) 28-Lead SSOP Tape-and-Reel Chip Scale Package (LPCC) 32-Leadless LPCC Tape-and-Reel
Package Option RS-28 CP-32
CAUTION (electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although AD6122 features proprietary protection circuitry, permanent damage occur devices subjected high-energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
WARNING!
SENSITIVE DEVICE
REV.
AD6122
FUNCTION DESCRIPTIONS
SSOP
LPCC
Label
Description Power-Down
Function Amplifier Power-Down Control Input; CMOS Compatible; HIGH Entire Powers Down, Amplifiers Modulator Power-Down Control Input; CMOS Compatible; HIGH Modulator Modulator Connects Emitter External Pass Transistor VCC. Connects Base External Pass Transistor. Connects Collector External Pass Transistor. Ground. Ground. Connects Local Oscillator; Coupled. Connects Ground Decoupling Capacitor. Connects Digital Supply. Connects Output Filter; Coupled. Connects Output Filter; Coupled. Connects Output Decoupling Network. Ground. "Negative" Input from Roofing Filter. "Positive" Input from Roofing Filter. Output Modulator Output Roofing Filter. Modulator Output Roofing Filter. Connects "Positive" Output Baseband Connects "Negative" Output Baseband Connects CDMA Baseband Converter Common-Mode Reference Input. Connects "Negative" Output Baseband Connects "Positive" Output Baseband Connects Ground. Connects Decoupled Output Regulator. Provides 1.23 Voltage Reference Output CDMA Baseband Converter REFIN. Accepts 1.23 Reference Input from REFOUT External Reference. Accepts Gain Control Input Voltage from External DAC. Gain Gain
LDOE LDOB LDOC LDOGND DGND LOIPP LOIPN DVCC TXOPP TXOPN TXVCC IFGND IFINN IFINP MODOPN MODOPP QIPP QIPN MODCMREF IIPN IIPP IFGND IFVCC REFOUT REFIN VGAIN
Power-Down Dropout Regulator Pass Transistor Emitter Connection Dropout Regulator Pass Transistor Base Dropout Regulator Pass Transistor Collector Dropout Regulator Ground Digital Ground Local Oscillator "Positive" Input Local Oscillator "Negative" Input Digital Transmit Output "Positive" Transmit Output "Negative" Transmit Output Ground Input "Negative" Input "Positive" Modulator "Negative" Output Modulator "Positive" Output Input "Positive" Input "Negative" Modulator Common-Mode Reference Input "Negative" Input "Positive" Ground Connect Gain Control Reference Output Gain Control Reference Input Gain Control Voltage Input
REV.
AD6122 Test Figures
+15V DATA +15V -15V MODOPP +15V MUST EQUAL LENGTHS MODCMREF DATA +15V -15V LOIPP LOIPN -15V MODOPN 10nF 10nF MOD_OUT -15V MUST EQUAL LENGTHS MODCMREF
IIPP
AD830
AD6122
MODCMREF
IIPN VREG
AD830
QIPP VREG
AD830
MODCMREF
MODCMREF QIPN
AD830
INPUT
Figure Quadrature Modulator's Characterization Input Output Impedance Matches
REV.
AD6122
VREG PULL-UP INDUCTORS CHOSEN PEAK RESPONSE TEST FREQUENCY. SOURCE 10nF IFINN 10nF TXOPN 10nF IFINP TXOPP 10nF SPECTRUM ANALYZER
AD6122
VREG
Figure Amplifier's Characterization Input Output Impedance Matches
NOTE: CABLES PATHS MUST EQUAL LENGTH TEST MOTHERBOARD DATA TEKTRONIX AFG2002 500mVp-p DIFFERENTIAL DATA SMT03 CHANNEL IFTX INPUT MEAS PORT CHANNEL FSEA20/30 SPECTRUM ANALYZER INPUT
SOURCE
SWITCHES
SMT03
HPE3610 POWER SUPPLY
HP34970A DATA ACQUISITION SWITCH CONTROL MEASUREMENTS CONTROL BITS
SOURCE
Figure General Test
REV.
AD6122
VREG PULL-UP INDUCTORS CHOSEN PEAK RESPONSE TEST FREQUENCY. NOISE SOURCE REACTIVE CONJUGATE MATCH 10nF IFINN 10nF TXOPN 10nF IFINP TXOPP 10nF NOISE FILTER METER
AD6122
VREG
Figure Amplifier's Noise Figure Test
HP8116A FUNCTION GEN. kHz, 0.5V 2.5V WAVE
ROHDE SCHWARZ SMT03 100MHz, -30dBm
HP8116A FUNCTION GEN. 4kHz, 2.7V WAVE
ROHDE SCHWARZ SMT03 100kHz, -30dBm
IFIN
TEKTRONIX 744A WITH PROBE
PD1,
IFIN
TEKTRONIX 744A WITH PROBE
IFOUT AD6122 TEST
WITH COAX CABLE
IFOUT AD6122 TEST
WITH COAX CABLE
Response Time from Gain Control Output
Response Time from Control Output
Figure Response Time Setup
REV.
AD6122 -Typical Performance Characteristics
-40dBm 30kHz 100kHz UNIT
UNDESIRED SIDEBAND
-49.18dBm (T1) 130.67458918MHz -33.92dBm -77.32dB 77.46dB
POWER
-100 -110 -120 -130 -140 CENTER 130.38MHz 519kHz/DIV SPAN 5.19MHz
OUTPUT FREQUENCY
Figure Spectral Plot Modulator Outputs: ACPR
Figure Modulator Output Undesired Sideband Output Frequency
MODULATOR OUTPUT REFERRED DIFFERENTIAL LOAD
FREQUENCY
LEAKAGE
-14.0
-12.0
-10.0 -8.0 -6.0 MODULATOR,
-4.0
-2.0
Figure Modulator Leakage Output Frequency
Figure Modulator Gain: Input (dBV) Output (dBm)
OUTPUT DESIRED SIDEBAND LEVEL REFERRED
THIRD HARMONIC
OUTPUT FREQUENCY
OUTPUT FREQUENCY
Figure Modulator Output Desired Sideband Output Frequency Without Roofing Filter
Figure Modulator Third Harmonic
REV.
AD6122
Load
IIP3 Referred
GAIN With
VGAIN
SUPPLY VOLTAGE
Figure Amplifier Response Curve: Gain VGAIN,
Figure Amplifier Input Supply Voltage
GAIN ERROR
ERROR FROM PREDICTED VALVE
-1.0 -2.0 GAIN -3.0 -4.0 -5.0 VGAIN -6.0
IIP3 Referred
GAIN
FREQUENCY
Figure Amplifier Gain Error VGAIN
Figure Amplifier Input Frequency
30.0
IIP3 Referred
NOISE FIGURE
25.0
-5.0
20.0 133MHz 313MHz 15.0 238MHz 10.0
-10.0
-15.0
-20.0
-25.0
VGAIN
-10.0
10.0 20.0 GAIN
30.0
40.0
Figure Amplifier Input VGAIN
Figure Amplifier Noise Figure Gain
REV.
AD6122
VGAIN 2.5V VGAIN 2.0V
GAIN TOTAL CURRENT CONSUMPTION
18.0
16.0
14.0
VGAIN 1.5V
12.0
VGAIN 1.0V VGAIN 0.5V FREQUENCY
10.0
VGAIN
Figure Amplifier Gain Frequency VGAIN
Figure Total Current Consumption VGAIN
-30dBm
POWER
30kHz 300kHz
UNIT
-46.78dBm (T1) 130.38000000MHz -31.93dBm -66.95dB -68.95dB -0.28 (T1) 330.66132265kHz
-100 -110 -120 -130 CENTER 130.38MHz 600kHz/DIV SPAN 6MHz
Figure ACPR Cascaded Modulator, Amplifier: Spectral Plot
-10-
REV.
AD6122
QUADRATURE MODULATOR OUTPUT QUADRATURE MODULATOR INPUT
ATTENUATOR
AMPLIFIER INPUT
AMPLIFIERS LOCAL OSCILLATOR INPUT INPUT COMMON-MODE REFERENCE OUTPUT VPOS DROPOUT REGULATOR VREG TRANSMIT OUTPUT
AD6122
GAIN CONTROL SCALE FACTOR
TEMPERATURE COMPENSATION
POWERDOWN
POWERDOWN
1.23 REFERENCE OUTPUT
GAIN CONTROL REFERENCE VOLTAGE INPUT
GAIN CONTROL VOLTAGE INPUT
Figure Block Diagram
THEORY OPERATION Amplifiers Gain Control
CDMA Transmitter Subsystem (Figure consists modulator with divide-by-two quadrature generator, high dynamic range amplifiers with voltage-controlled gain, dropout regulator power-down control inputs.
Modulator
modulator accepts differential quadrature baseband inputs from CDMA baseband converters. injected twice frequency. divide-by-two quadrature generator followed dual polyphase filters ensures quadrature accuracy (Figure 22). differential input signals, output power modulator will referred when output modulator loaded with differential load. With maximum input conditions stated above, modulator outputs differential current; consequently, output load will greatly affect output power modulator.
INPUT
amplifiers provide linear gain control range. input stage uses differential, continuously variable attenuator based Analog Devices' patented X-AMPtopology. This noise attenuator consists differential R-2R ladder network, linear interpolator fixed gain amplifier. amplifier's input impedance differential. Similar modulator's output, amplifier's output differential current, which will vary depending upon gain control voltage. order achieve specified gain, output amplifiers should loaded with differential load. gain control circuits contain both temperature compensation circuitry choice internal external reference adjusting gain scale factor. gain control input accepts external gain control voltage input from DAC. provides gain control range with nominal dB/V scale factor. external gain control input signal should clean signal. recommended filter this signal order eliminate noise that results from DAC. noisy signal used gain control voltage, VGAIN inband adjacent channel noise peaking occur output AD6122. simple filter employed, care should taken with design. resistor used, large voltage drop occur across resistor, resulting lower gain than expected result lower voltage reaching AD6122). filter with bandwidth, employing resistor appropriate. This results capacitor. resulting circuit shown Figure Note that input resistance VGAIN approximately
FROM BASEBAND CONVERTER 8.2nF
POLYPHASE FILTERS QUADRATURE OUTPUT MODULATOR
Figure Simplified Quadrature Generator Circuit
modulator also provides common mode reference signal MODCMREF pin. This voltage voltage 1.408 when supply used. used bias output that provides inputs modulator.
AD6122
VGAIN 109k
X-AMP trademark Analog Devices, Inc.
Figure Gain Voltage Filtering
REV.
-11-
AD6122
AD6122's overall gain, expressed decibels, linear with respect automatic gain control (AGC) voltage, VGAIN. Either REFOUT external reference voltage connected REFIN used voltage range VGAIN. When internal 1.23 reference, REFOUT, connected REFIN VGAIN will control entire range when typically between Minimum gain occurs minimum voltage VGAIN maximum gain occurs maximum voltage VGAIN. maximum minimum gain will change with change voltage REFIN. Rather, slope gain curve will change result change required range VGAIN. Figure shows piecewise linear approximation gain curve AD6122. control provided control pins, PD2. Table shows operating modes AD6122.
Table Operating Modes
INVALID STATE
Modulator INVALID STATE
Dropout Regulator
MAXIMUM GAIN
MINIMUM GAIN
AD6122 incorporates integrated dropout regulator. regulator accepts inputs from supplies constant reference output LDOC. signal used provide voltages required DVCC, TXVCC IFVCC supplies. order configure dropout regulator, external pass transistor required. bipolar junction transistor with minimum maximum VCESAT -0.4 required. order dropout regulator, configure transistor shown Figure capacitor Figure used decoupling signal. addition dropout regulator, band-gap voltage reference produces 1.23 reference voltage REFOUT. This reference voltage will present whenever signal present LDOC. This 1.23 reference voltage then used provide gain reference signal required REFIN reference voltage transmit DACs baseband converter.
AD6122
GAIN
VGAIN
Figure Piecewise Linear Approximation AD6122 Gain Curve
Because minimum maximum gain from AD6122 constant, approximate VGAIN range given REFIN voltage using Equation
VGAIN (GAIN MinGain) 1.6REFIN REFIN MaxGain MinGain
2.9V 4.2V PASS TRANSISTOR 2.7V 18pF REFOUT 1.23V LDOE
Where MaxGain maximum gain (+34 MinGain minimum gain (-63 REFIN reference input voltage, volts, VGAIN gain control voltage input, volts, GAIN particular gain, would have given REFIN VGAIN. Consequently, REFIN choose, calculate VGAIN range solving Equation VGAIN. example, order determine VGAIN value maximum gain condition, given 1.23 REFIN, solve Equation VGAIN substituting GAIN MaxGain, MinGain 1.23 REFIN. VGAIN then calculated 2.46 approximately minimum gain condition, determine VGAIN value substituting MaxGain, GAIN MinGain 1.23 REFIN. VGAIN then calculated 0.492 approximately
Power-Down Control
LDOB LDOC
Figure Configuring Dropout Regulator
possible bypass dropout regulator AD6122 external regulator instead. order bypass integrated dropout regulator, connect pins LDOE, LDOB LDOC together then connect them external regulator voltage. This configuration shown Figure Even when dropout regulator bypassed, 1.23 reference voltage REFOUT still present.
AD6122 operated with amplifiers quadrature modulator both powered both powered down with amplifiers powered modulator powered down. AD6122 cannot operate with only modulator powered
-12-
REV.
AD6122
AD6122
LDOE FROM EXTERNAL VOLTAGE REGULATOR
attenuator discussed next section entitled Measuring Adjacent Channel Protection Ratio (ACPR). order confirm whether roofing filter been correctly designed, sweep frequency view output amplifier spectrum analyzer. signal should peak frequency inductor value correct. filter should enough that variations parasitic capacitances should negligible.
LDOB
LDOC
REFOUT
1.23V
Figure Configuration Bypassing Dropout Regulator
ROOFING FILTER
value inductor required will function frequency which operating. values inductors used during characterization Analog Devices shown Table Because exact value will also function printed circuit board layout, will have vary value from those Table those required board.
Table Roofing Filter Inductor Values
Because outputs AD6122 modulator open collector, parasitic capacitances seen output modulator, inputs amplifiers, high enough create low-pass filter, which attenuate signal. Consequently, parasitic capacitance must cancelled using external inductors form parallel resonant circuit. external inductors internal parasitic capacitors form what known roofing filter, with resonant frequency given Equation
Frequency (MHz) 50-125 126-200 201-275 276-350
Value Roofing Filter Inductor (nH)
LCPAR
where frequency, Hertz, CPAR total parasitic capacitance Farads, value external inductors, henrys. roofing filter composed pull-up inductors required open collector outputs modulator. This configuration shown Figure capacitors used coupling.
should noted that roofing filter only required when cascading output from modulator input amplifiers. driving into amplifiers directly, roofing filter required, however, pull-up inductors required order voltage open collector modulator outputs.
MEASURING ADJACENT CHANNEL POWER RATIO (ACPR)
AD6122
MODOPP 2CPAR
maximum gain specified input conditions (500 baseband inputs), output modulator greater than (one compression point) amplifiers. This configuration maximizes ratio signal feedthrough also maximizes signal noise ratio. Once these ratios maximized, attenuate noise, signal feedthrough without affecting ratios. Therefore, attenuation required between modulator amplifiers. order determine exactly much attenuation required, must recognize that ACPR function attenuation from modulator outputs amplifier inputs. result, order determine much attenuation required, must first know good ACPR performance desired. much attenuation applied, ACPR will very good, but, amplifier's output power level will low, possibly resulting poor signal noise ratio possibly requiring additional amplification external AD6122. appropriate method that used provide correct amount attenuation between modulator outputs amplifier inputs simple differential voltage divider. topology design equations shown Figure Equations input impedance amplifiers typically result, design resistor much less than neglect effects amplifier's input impedance attenuator.
2CPAR MODOPN
10nF PARALLEL RESONANT CIRCUIT 10nF
IFINN
IFINP 10nF ATTENUATOR
Figure Roofing Filter Configuration
REV.
-13-
AD6122
AD6122
MODOPP IFINP
This circuit very sensitive parasitic capacitances. result, extra care should taken ensure minimum equal printed circuit board transmission lines. should also keep small order minimize effects printed circuit board parasitic capacitance loading output pad. conclusion, have develop system-level ACPR budget radio, from that budget determine much ACPR performance desire from AD6122. then need implement appropriate attenuation network that ACPR performance.
LEVEL DIAGRAM
MODOPN
IFINN
RSHUNT >>R2
Figure Topology
2R1+
where transducer loss loss through pad) desired input resistance ohms. Using these equations, design attenuator circuit provide whatever amount attenuation require.
Figure provided better understand different voltage levels expect different points AD6122. represents voltage power levels expected maximum input condition modulator maximum gain amplifiers. When trying make these measurements, high impedance active probe (for example, P6204, from Tektronix) should used minimize effects loading circuit with probe. order produce these results, attenuator designed have input impedance output amplifiers loaded with roofing filter designed resonate parasitic capacitance frequency.
MODULATORS 500mV DIFFERENTIAL 100mV DIFFERENTIAL 500mV DIFFERENTIAL -21dBm (REFERRED 252.1mV DIFFERENTIAL MODOP -41dBm (REFERRED 25.21mV AMPLIFIERS DIFFERENTIAL IFIN -7dBm (REFERRED 1.263V DIFFERENTIAL TRANSMIT OUTPUT
VGAIN 2.5V GAIN +34dB 20dB ATTENUATOR ZOUT
Figure Level Diagram
-14-
REV.
AD6122
INPUT INTERFACES
AD6122 interfaces CDMA baseband converters providing either baseband outputs. baseband input provided direct connection baseband converter's baseband output baseband input AD6122 (Figure 30). amplifier's gain control provided connection transmit DAC's output baseband converter, through low-pass filter VGAIN AD6122.
TEMPERATURE COMPENSATION GAIN CONTROL SCALE FACTOR
VGAIN REFIN
LDOE LDOB LDOC LDOGND DROPOUT REGULATOR REFOUT IFVCC IFGND IIPP OUTPUT LOIPP LOIPN DVCC QIPN QIPP MODOPP MODOPN IIPN MODCMREF OUTPUT OUTPUT OUTPUT
DGND
AD6122
CDMA BASEBAND
TXOPP TXOPN TXVCC IFGND
IFINP
IFINN
Figure Typical Connections Baseband Using Inputs with SSOP Package
REV.
-15-
AD6122
AD6122 Evaluation Board
AD6122 Evaluation Board consists AD6122, connectors, 20-pin dual header, 2-pin headers four AD830 high speed video difference amplifiers. allows user evaluate AD6122's amplifier modulator together separately. Because AD6122 used from MHz, pads provided LOIPP input, TXOP output, MODOP output IFIP inputs allow user matching networks. board configured frequency 130.38 when shipped. There difference between configuration boards with SSOP LPCC package. AD830s used provide single-ended differential conversion appropriate phase shift data input pins. result, single-ended signal generator used generate these signals. order test power-down modes AD6122, locate headers AD6122 evaluation boards labeled PD2. open-circuiting pins labeled PD1, amplifiers power down. open-circuiting pins labeled PD2, modulator powers down. Note that amplifiers modulator powered down unless pins headers, PD2, short circuited. input port impedance match used during characterization AD6122 Analog Devices follows:
AD6122
SIGNAL GENERATOR IFINN IFINP
output port impedance match used during characterization Analog Devices follows:
AD6122
TXOPP TXOPN SPECTRUM ANALYZER
Figure Output Port Impedance Match Used During Characterization
This broadband lossy output match frequency range. ratio Figure impedance ratio voltage ratio. shipped, board configured follows: open shorted. This enables regulator. external transistor should remain place even when regulator bypassed (the LDOB pulled transistor). X11, X25, shorted X12, X14, opened order connect output modulator input amplifiers. roofing filter components optimized frequency 130.38 MHz. R14, attenuation between modulator outputs amplifier inputs pulled jumpers headers. power down chip, high removing jumpers. order look modulator amplifiers separately, disconnect output modulator from input amplifiers. This accomplished short circuiting X12, X14, open circuiting X11, X18, X26.
Figure Input Port Impedance Match Used During Characterization
This broadband lossy match used characterization over frequency range. references characterization data collected using this match referenced Note that ratio Figure impedance ratio voltage ratio.
-16-
REV.
AD6122
Table describes high frequency signal connectors AD6122 customer sample boards.
Table III. Evaluation Board Signal Connector Description
Table lists connections 20-pin power-supply connector.
Table 20-Pin Power Supply Connection Information
Connector Description Modulator Input. into termination, coupled. level shifting phase splitting done board AD830 amplifiers. Modulator Input. into termination, coupled. level shifting phase splitting done board AD830 amplifiers. Modulator Output. differential-to-single ended conversion performed balun board. Impedance matched 130.38 frequency. Amplifier Input. Single-ended-to-differential conversion performed balun board. Impedance matched 130.38 frequency. Amplifier Output. Differential-to-singleended conversion performed balun board. Impedance matched 130.38 frequency. Local oscillator positive input frequency.
Function VPOS AD6122; using regulator; bypassing regulator. VPOS AD6122; using regulator; bypassing regulator. Ground. Ground. Ground. Regulated Output Input Voltage; Connects AD6122. Ground. Ground. Ground. Ground. Ground. PD1; Power-Down Input. Ground. 1.23 Reference Voltage from AD6122. Ground. VGAIN; Gain Control Voltage Input. Supply AD830 Differential Amplifier. Supply AD830 Differential Amplifier. MODCMREF; common-mode reference output baseband converter common-mode reference input. PD2; Power-Down Input.
MODOP
IFIP
TXOP
LOIPP
schematic diagram evaluation board next pages.
REV.
-17-
AD6122
AD6122
VPOS 2.9V 4.2V FMMT4403CT-ND LDOE LDOB LDOC LDOGND DGND LOIPP 10nF 10nF LOIPP LOIPN DVCC 220nH DVCC TXOPP TXOPN TXVCC 220nH 10nF TXVCC IFGND REFOUT 10nF VREG 18pF IFVCC IFGND IIPP IIPN MODCMREF QIPN QIPP MODOPP MODOPN IFINP IFINN 10nF 10nF 10nF 10nF 27nH IFIP 56nH IIPP VREG IIPN MODCMREF QIPN QIPP 10nF 10nF VREG IFVCC REFOUT VGAIN REFIN 10nF VGAIN
180nH
180nH 100nH MODOP
100nH TXOP
10nF
10nF
Figure Schematic Diagram Evaluation Board
-18-
REV.
AD6122
+15V MODCMREF -15V +15V MODCMREF -15V IIPN MODCMREF -15V +15V SOIC PACKAGE IIPP MODCMREF -15V +15V SOIC PACKAGE QIPP
AD830
AD830
QIPN
AD830
AD830
TXVCC
18pF
0.01
VREG
VPOS
470nH
FROM VPOS 2.9V-4.2V
DVCC
VREG
18pF
0.01 0.01
REFOUT VGAIN +15V
IFVCC
18pF
-15V MODCMREF
NOTES: REGULATOR, SHORT OPEN BYPASS REGULATOR, SHORT OPEN CONNECT OUTPUT MODULATOR INPUT AMP, SHORT TEST MODULATOR SEPARATELY, OPEN INDICATES TRACE.
Figure Schematic Diagram Evaluation Board
REV.
-19-
AD6122
OUTLINE DIMENSIONS
Dimensions shown inches (mm).
28-Lead SSOP (RS-28)
0.407 (10.34) 0.397 (10.08)
0.078 (1.98) 0.068 (1.73)
0.07 (1.79) 0.066 (1.67)
0.008 (0.203) 0.0256 (0.65) 0.002 (0.050)
0.015 (0.38) SEATING 0.009 (0.229) 0.010 (0.25) PLANE 0.005 (0.127)
0.03 (0.762) 0.022 (0.558)
32-Leadless Chip Scale Package (LPCC) (CP-32)
0.205 (5.20) 0.197 (5.00) 0.189 (4.80)
0.128 (3.25) 0.106 (2.70) 0.049 (1.25)
INDICATOR 0.015 (0.38) 0.012 (0.30) 0.009 (0.23)
BOTTOM VIEW
0.138 (3.50) 0.010 (0.25) 0.020 (0.50) 0.039 (1.00) 0.035 (0.90) 0.031 (0.80) 0.002 (0.05) 0.001 (0.02) 0.000 (0.00)
0.018 (0.45) 0.016 (0.40) 0.014 (0.35)
CONTROLLING DIMENSIONS MILLIMETERS DIMENSIONS MEET JEDEC MO-220-VHHD-2
-20-
REV.
PRINTED U.S.A.
C00946a-.5-6/00 (rev.
0.311 (7.9) 0.301 (7.64)
0.212 (5.38) 0.205 (5.21)

CDMA Transmitter Subsystem with Integrated Voltage Regulator AD6122

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