FLASH MEMORY 8/4M MBM29DD640E 10/12 FEATURES Dual
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AE0.7E
FLASH MEMORY
8/4M
MBM29DD640E 10/12
FEATURES
Dual Operation
0.23 Process Technology Simultaneous Read/Write operations (Dual Bank) virtual Banks chosen from combination four physical banks (Refer Table Host system program erase bank, then read immediately simultaneously from other bank with zero latency between read write operations. Read-while-erase Read-while-program Single read, program, erase Minimized system level power requirements Compatible with JEDEC-standard commands same software commands E2PROMs Compatible with JEDEC-standard world-wide pinouts 48-pin TSOP(I) (Package suffix: Normal Bend Type, Reversed Bend Type) 63-ball FBGA (Package suffix: PBT) Minimum 100,000 program/erase cycles High performance maximum access time Sector erase architecture Sixteen word hundred twenty-six word sectors word mode Sixteen byte hundred twenty-six byte sectors byte mode combination sectors concurrently erased. Also supports full chip erase. Hidden (Hi-ROM) region byte Hi-ROM, accessible through "Hi-ROM Enable" command sequence Factory serialized protected provide secure electronic serial number (ESN) WP/ACC input VIL, allows protection "outermost" bytes both ends boot sectors, regardless sector protection/ unprotection status VIH, allows removal boot sector protection VACC, increases program performance Embedded EraseAlgorithms Automatically pre-programs erases chip sector
(Continued)
Embedded Eraseand Embedded Programare trademarks Advanced Micro Devices, Inc.
This document contains information product under development Fujitsu. information intended help evaluate this product. Fujitsu reserves right change this proposed product without notice.
MBM29DD640E 10/12
(Continued) Embedded ProgramAlgorithms Automatically writes verifies data specified address Data Polling Toggle feature detection program erase cycle completion Ready/Busy output (RY/BY) Hardware method detection program erase cycle completion Automatic sleep mode When addresses remain stable, automatically switch themselves power mode. Program Suspend/Resume Suspends program operation allow read another byte Erase Suspend/Resume Suspends erase operation allow read data and/or program another sector within same device Sector group protection Hardware method disables combination sector groups from program erase operations Sector Group Protection function Extended sector group protection command Fast Programming Function Extended Command Temporary sector group unprotection Temporary sector group unprotection RESET pin. accordance with (Common Flash Memory Interface)
PACKAGE
48-pin plastic TSOP
Marking Side
48-pin plastic TSOP
Marking Side
(FPT-48P-M19)
(FPT-48P-M20)
63-ball plastic FBGA
(BGA-63P-M02)
MBM29DD640E 10/12
GENERAL DESCRIPTION
MBM29DD640E 64M-bit, V-only Flash memory organized bytes bits each words bits each. device offered 48-pin TSOP(I) 63-ball FBGA packages. This device designed programmed system with standard system supply. 12.0 required write erase operations. device also reprogrammed standard EPROM programmers. device organized into four physical Banks, Bank Bank Bank Bank which considered four separate memory arrays certain operations concerned. This device same Fujitsu's standard only Flash memories with additional capability allowing normal non-delayed read access from non-busy bank array while embedded write (either program erase) operation simultaneously taking place other bank. device, design concept implemented, called "FlexBank Architecture". Under this concept, device execute simultaneous operation between Bank certain bank chosen from four physical banks, Bank bank made from rest three banks. certain" means that either four banks chosen Bank choice Bank depends system requirement size program data area. standard device offers access times allowing operation high-speed microprocessors without wait state. eliminate contention device separate chip enable (CE), write enable (WE), output enable (OE) controls. device command compatible with JEDEC standard E2PROMs. Commands written command register using standard microprocessor write timings. Register contents serve input internal state-machine which controls erase programming circuitry. Write cycles also internally latch addresses data needed programming erase operations. Reading data device similar reading from 12.0 Flash EPROM devices. device programmed executing program command sequence. This will invoke Embedded Program Algorithm which internal algorithm that automatically times program pulse widths verifies proper cell margin. Typically, each sector programmed verified about seconds. Erase accomplished executing erase command sequence. This will invoke Embedded Erase Algorithm which internal algorithm that automatically preprograms array already programmed before executing erase operation. During erase, device automatically time erase pulse widths verify proper cell margin. sector typically erased verified second. already completely preprogrammed.) device also features sector erase architecture. sector mode allows each sector erased reprogrammed without affecting other sectors. device erased when shipped from factory. device features single power supply operation both read write functions. Internally generated regulated voltages provided program erase operations. detector automatically inhibits write operations loss power. program erase detected Data Polling DQ7, Toggle feature DQ6, RY/BY output pin. Once program erase cycle been completed, device internally resets read mode. device also hardware RESET pin. When this driven low, execution Embedded Program Algorithm Embedded Erase Algorithm terminated. internal state machine then reset read mode. RESET tied system reset circuitry. Therefore, system reset occurs during Embedded Program Algorithm Embedded Erase Algorithm, device automatically reset read mode will have erroneous data stored address locations being programmed erased. These locations need re-writing after Reset. Resetting device enables system's microprocessor read boot-up firmware from Flash memory.
MBM29DD640E 10/12
Fujitsu's Flash technology combines years EPROM E2PROM experience produce highest levels quality, reliability, cost effectiveness. device memory electrically erase entire chip bits within sector simultaneously Fowler-Nordhiem tunneling. bytes/words programmed byte/word time using EPROM programming mechanism electron injection. Table Bank Splits Bank Megabits Combination Memory Bank Sector Sizes Eight byte/ word, fifteen byte/ word Sixteen byte/ word, thirty byte/ word Forty-eight byte/ word Eight byte/ word, sixty-three byte/ word Example Virtual Banks Combination Bank Megabits Combination Memory Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Sector Sizes Eight byte/ word, hundred eleven byte/32K word Ninety-six byte/ word Sixteen byte/ word, seventy-eight byte/32K word Eight byte/ word, sixty-three byte/ word
Mbit
Bank
Mbit
Mbit
Bank Bank
Mbit
Mbit
Bank
Mbit
Mbit
Bank Bank
Mbit
Bank Address 000000h 0FFFFFh byte mode) Bank Address 100000h 3FFFFFh byte mode) Bank Address 400000h 6FFFFFh byte mode) Bank Address 700000h 7FFFFFh byte mode)
MBM29DD640E 10/12
PRODUCT LINE
Part Ordering Part
+0.2 -0.2
MBM29DD640E
Max. Address Access Time (ns) Max. Access Time (ns) Max. Access Time (ns)
BLOCK DIAGRAM
Bank Address
Y-Gating
(A-1)
Cell Matrix (Bank X-Decoder
Cell Matrix (Bank X-Decoder
RESET BYTE WP/ACC
State RY/BY Control Status Command Control Register
Bank Address Bank Address X-Decoder X-Decoder Y-Gating Cell Matrix (Bank Cell Matrix (Bank Y-Gating
Bank Address
Y-Gating
MBM29DD640E 10/12
CONNECTION DIAGRAMS
TSOP(I) RESET WP/ACC RY/BY (Marking Side) BYTE 15/A-1 DQ14 DQ13 DQ12 DQ11 DQ10
MBM29DD640E Standard Pinout
FPT-48P-M19 RY/BY WP/ACC RESET (Marking Side) DQ10 DQ11 DQ12 DQ13 DQ14 DQ15/A-1 BYTE
MBM29DD640E Reverse Pinout
FPT-48P-M20
MBM29DD640E 10/12
(Continued)
FBGA (TOP VIEW) Marking side
N.C. N.C.
N.C. N.C.
N.C. N.C.
BYTE DQ15/
N.C. N.C.
DQ14 DQ13
RESET
DQ12
RY/BY N.C. N.C. N.C.
DQ10 DQ11
N.C. N.C.
N.C. N.C.
(BGA-63P-M02)
MBM29DD640E 10/12
LOGIC SYMBOL
Table
DQ15 RESET BYTE WP/ACC RY/BY
MBM29DD640E Configuration Function Address Inputs Data Inputs/Outputs Chip Enable Output Enable Write Enable Ready/Busy Output Hardware Reset Pin/Temporary Sector Group Unprotection Selects 8-bit 16-bit mode Hardware Write Protection/Program Acceleration Internal Connection Device Ground Device Power Supply
DQ15 RY/BY RESET BYTE WP/ACC N.C.
MBM29DD640E 10/12
Table Sector Address Bank Sector Address Tables (Bank Address Range 000000h 001FFFh 002000h 003FFFh 004000h 005FFFh 006000h 007FFFh 008000h 009FFFh 00A000h 00BFFFh 00C000h 00DFFFh 00E000h 00FFFFh 010000h 01FFFFh 020000h 02FFFFh 030000h 03FFFFh 040000h 04FFFFh 050000h 05FFFFh 060000h 06FFFFh 070000h 07FFFFh 080000h 08FFFFh 090000h 09FFFFh 0A0000h 0AFFFFh 0B0000h 0BFFFFh 0C0000h 0CFFFFh 0D0000h 0DFFFFh 0E0000h 0EFFFFh 0F0000h 0FFFFFh Address Range 000000h 000FFFh 001000h 001FFFh 002000h 002FFFh 003000h 003FFFh 004000h 004FFFh 005000h 005FFFh 006000h 006FFFh 007000h 007FFFh 008000h 00FFFFh 010000h 017FFFh 018000h 01FFFFh 020000h 027FFFh 028000h 02FFFFh 030000h 037FFFh 038000h 03FFFFh 040000h 047FFFh 048000h 04FFFFh 050000h 057FFFh 058000h 06FFFFh 060000h 067FFFh 068000h 06FFFFh 070000h 077FFFh 078000h 07FFFFh
Sector Size Bank Sector Address (Kbytes/ Kwords)
SA10 Bank SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22
64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32
Note: address range A21: byte mode (BYTE VIL). address range A21: word mode (BYTE VIH).
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Table Sector Address Bank Sector Address Tables (Bank Address Range 100000h 10FFFFh 110000h 11FFFFh 120000h 12FFFFh 130000h 13FFFFh 140000h 14FFFFh 150000h 15FFFFh 160000h 16FFFFh 170000h 17FFFFh 180000h 18FFFFh 190000h 19FFFFh 1A0000h 1AFFFFh 1B0000h 1BFFFFh 1C0000h 1CFFFFh 1D0000h 1DFFFFh 1E0000h 1EFFFFh 1F0000h 1FFFFFh 200000h 20FFFFh 210000h 21FFFFh 220000h 22FFFFh 230000h 23FFFFh 240000h 24FFFFh 250000h 25FFFFh 260000h 26FFFFh 270000h 27FFFFh 280000h 28FFFFh 290000h 29FFFFh 2A0000h 2AFFFFh 2B0000h 2BFFFFh 2C0000h 2CFFFFh 2D0000h 2DFFFFh 2E0000h 2EFFFFh 2F0000h 2FFFFFh 300000h 30FFFFh 310000h 31FFFFh 320000h 32FFFFh 330000h 33FFFFh 340000h 34FFFFh 350000h 35FFFFh 360000h 36FFFFh 370000h 37FFFFh Address Range 080000h 087FFFh 088000h 08FFFFh 090000h 097FFFh 098000h 09FFFFh 0A0000h 0A7FFFh 0A8000h 0AFFFFh 0B0000h 0B7FFFh 0B8000h 0BFFFFh 0C0000h 0C7FFFh 0C8000h 0CFFFFh 0D0000h 0D7FFFh 0D8000h 0DFFFFh 0E0000h 0E7FFFh 0E8000h 0EFFFFh 0F0000h 0F7FFFh 0F8000h 0FFFFFh 100000h 107FFFh 108000h 10FFFFh 110000h 117FFFh 118000h 11FFFFh 120000h 127FFFh 128000h 12FFFFh 130000h 137FFFh 138000h 13FFFFh 140000h 147FFFh 148000h 14FFFFh 150000h 157FFFh 158000h 15FFFFh 160000h 167FFFh 168000h 16FFFFh 170000h 177FFFh 178000h 17FFFFh 180000h 187FFFh 188000h 18FFFFh 190000h 197FFFh 198000h 19FFFFh 1A0000h 1A7FFFh 1A8000h 1AFFFFh 1B0000h 1B7FFFh 1B8000h 1BFFFFh
Sector Size Bank Sector Address (Kbytes/ Kwords)
SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 SA39 SA40 SA41 SA42 Bank SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62
64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32
(Continued)
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(Continued)
Bank
Sector Size Bank Sector Address (Kbytes/ Kwords)
Sector Address
Address Range 380000h 38FFFFh 390000h 39FFFFh 3A0000h 3AFFFFh 3B0000h 3BFFFFh 3C0000h 3CFFFFh 3D0000h 3DFFFFh 3E0000h 3EFFFFh 3F0000h 3FFFFFh
Address Range 1C0000h 1C7FFFh 1C8000h 1CFFFFh 1D0000h 1D7FFFh 1D8000h 1DFFFFh 1E0000h 1E7FFFh 1E8000h 1EFFFFh 1F0000h 1F7FFFh 1F8000h 1FFFFFh
SA63 SA64 SA65 SA66 Bank SA67 SA68 SA69 SA70
64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32
Note: address range A21: byte mode (BYTE VIL). address range A21: word mode (BYTE VIH).
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Table Sector Address Bank Sector Address Tables (Bank Address Range 400000h 40FFFFh 410000h 41FFFFh 420000h 42FFFFh 430000h 43FFFFh 440000h 44FFFFh 450000h 45FFFFh 460000h 46FFFFh 470000h 47FFFFh 480000h 48FFFFh 490000h 49FFFFh 4A0000h 4AFFFFh 4B0000h 4BFFFFh 4C0000h 4CFFFFh 4D0000h 4DFFFFh 4E0000h 4EFFFFh 4F0000h 4FFFFFh 500000h 50FFFFh 510000h 51FFFFh 520000h 52FFFFh 530000h 53FFFFh 540000h 54FFFFh 550000h 55FFFFh 560000h 56FFFFh 570000h 57FFFFh 580000h 58FFFFh 590000h 59FFFFh 5A0000h 5AFFFFh 5B0000h 5BFFFFh 5C0000h 5CFFFFh 5D0000h 5DFFFFh 5E0000h 5EFFFFh 5F0000h 5FFFFFh 600000h 60FFFFh 610000h 61FFFFh 620000h 62FFFFh 630000h 63FFFFh 640000h 64FFFFh 650000h 65FFFFh 660000h 66FFFFh 670000h 67FFFFh Address Range 200000h 207FFFh 208000h 20FFFFh 210000h 217FFFh 218000h 21FFFFh 220000h 227FFFh 228000h 22FFFFh 230000h 237FFFh 238000h 23FFFFh 240000h 247FFFh 248000h 24FFFFh 250000h 257FFFh 258000h 25FFFFh 260000h 267FFFh 268000h 26FFFFh 270000h 277FFFh 278000h 27FFFFh 280000h 287FFFh 288000h 28FFFFh 290000h 297FFFh 298000h 29FFFFh 2A0000h 2A7FFFh 2A8000h 2AFFFFh 2B0000h 2B7FFFh 2B8000h 2BFFFFh 2C0000h 2C7FFFh 2C8000h 2CFFFFh 2D0000h 2D7FFFh 2D8000h 2DFFFFh 2E0000h 2EE7FFh 2E8000h 2EFFFFh 2F0000h 2F7FFFh 2F8000h 2FFFFFh 300000h 307FFFh 308000h 30FFFFh 310000h 317FFFh 318000h 31FFFFh 320000h 327FFFh 328000h 32FFFFh 330000h 337FFFh 338000h 33FFFFh
Sector Size Bank Sector Address (Kbytes/ Kwords)
SA71 SA72 SA73 SA74 SA75 SA76 SA77 SA78 SA79 SA80 SA81 SA82 SA83 SA84 SA85 SA86 SA87 SA88 SA89 SA90 Bank SA91 SA92 SA93 SA94 SA95 SA96 SA97 SA98 SA99 SA100 SA101 SA102 SA103 SA104 SA105 SA106 SA107 SA108 SA109 SA110
64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32
(Continued)
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(Continued)
Bank
Sector Size Bank Sector Address (Kbytes/ Kwords)
Sector Address
Address Range 680000h 68FFFFh 690000h 69FFFFh 6A0000h 6AFFFFh 6B0000h 6BFFFFh 6C0000h 6CFFFFh 6D0000h 6DFFFFh 6E0000h 6EFFFFh 6F0000h 6FFFFFh
Address Range 340000h 347FFFh 348000h 34FFFFh 350000h 357FFFh 358000h 35FFFFh 360000h 367FFFh 368000h 36FFFFh 370000h 377FFFh 378000h 37FFFFh
SA111 SA112 SA113 SA114 Bank SA115 SA116 SA117 SA118
64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32
Note: address range A21: byte mode (BYTE VIL). address range A21: word mode (BYTE VIH).
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Table Sector Address Bank Sector Address Tables (Bank Address Range 700000h 70FFFFh 710000h 71FFFFh 720000h 72FFFFh 730000h 73FFFFh 740000h 74FFFFh 750000h 75FFFFh 760000h 76FFFFh 770000h 77FFFFh 780000h 78FFFFh 790000h 79FFFFh 7A0000h 7AFFFFh 7B0000h 7BFFFFh 7C0000h 7CFFFFh 7D0000h 7DFFFFh 7E0000h 7EFFFFh 7F0000h 7F1FFFh 7F2000h 7F3FFFh 7F4000h 7F5FFFh 7F6000h 7F7FFFh 7F8000h 7F9FFFh 7FA000h 7FBFFFh 7FC000h 7FDFFFh 7FE000h 7FFFFFh Address Range 380000h 387FFFh 388000h 38FFFFh 390000h 397FFFh 398000h 39FFFFh 3A0000h 3A7FFFh 3A8000h 3AFFFFh 3B0000h 3B7FFFh 3B8000h 3BFFFFh 3C0000h 3C7FFFh 3C8000h 3CFFFFh 3D0000h 3D7FFFh 3D8000h 3DFFFFh 3E0000h 3E7FFFh 3E8000h 3EFFFFh 3F0000h 3F7FFFh 3F8000h 3F8FFFh 3F9000h 3F9FFFh 3FA000h 3FAFFFh 3FB000h 3FBFFFh 3FC000h 3FCFFFh 3FD000h 3FDFFFh 3FE000h 3FEFFFh 3FF000h 3FFFFFh
Sector Size Bank Sector Address (Kbytes/ Kwords)
SA119 SA120 SA121 SA122 SA123 SA124 SA125 SA126 SA127 SA128 SA129 Bank SA130 SA131 SA132 SA133 SA134 SA135 SA136 SA137 SA138 SA139 SA140 SA141
64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32
Note: address range A21: byte mode (BYTE VIL). address range A21: word mode (BYTE VIH).
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Table Sector Group SGA0 SGA1 SGA2 SGA3 SGA4 SGA5 SGA6 SGA7 SGA8 SGA9 SGA10 SGA11 SGA12 SGA13 SGA14 SGA15 SGA16 SGA17 SGA18 SGA19 SGA20 SGA21 SGA22 SGA23 Sector Group Address Table SA11 SA14 SA15 SA18 SA19 SA22 SA23 SA26 SA27 SA30 SA31 SA34 SA35 SA38 SA39 SA42 SA43 SA46 SA47 SA50 SA51 SA54 SA55 SA58 SA59 SA62 SA63 SA66 SA67 SA70 SA10 Sectors
(Continued)
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Sector Group SGA24 SGA25 SGA26 SGA27 SGA28 SGA29 SGA30 SGA31 SGA32 SGA33 SGA34 SGA35 SGA36 SGA37 SGA38 SGA39 SGA40 SGA41 SGA42 SGA43 SGA44 SGA45 SGA46 SGA47 SA134 SA135 SA136 SA137 SA138 SA139 SA140 SA141 SA131 SA133 Sectors SA71 SA74 SA75 SA78 SA79 SA82 SA83 SA86 SA87 SA90 SA91 SA94 SA95 SA98 SA99 SA102 SA103 SA106 SA107 SA110 SA111 SA114 SA115 SA118 SA119 SA122 SA123 SA126 SA127 SA130
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Table Operation Auto-Select Manufacturer Code Auto-Select Device Code Extended Auto-Select Device Code Read Standby Output Disable Write (Program/Erase) Enable Sector Group Protection (2), Verify Sector Group Protection (2), Temporary Sector Group Unprotection Reset (Hardware)/Standby Boot Block Sector Write Protection MBM29DD640E User Operations (BYTE VIH) DQ15 RESET WP/ACC Code Code Code DOUT HIGH-Z HIGH-Z Code HIGH-Z
Legend: VIL, VIH, VIH,
Pulse input. Characteristics voltage levels.
Notes: Manufacturer device codes also accessed command register write sequence. Table Refer section Sector Group Protection. VIL, initiates write operations. also used extended sector group protection. Protect "outermost" bytes words) both ends boot block sectors.
MBM29DD640E 10/12
Table Operation Auto-Select Manufacturer Code Auto-Select Device Code Extended Auto-Select Device Code Read Standby Output Disable Write (Program/Erase) Enable Sector Group Protection (2), Verify Sector Group Protection (2), Temporary Sector Group Unprotection Reset (Hardware)/ Standby Boot Block Sector Write Protection MBM29DD640E User Operations (BYTE VIL) RESET WP/ACC Code Code Code DOUT HIGH-Z HIGH-Z Code HIGH-Z
DQ15/
Legend: VIL, VIH, VIH,
Pulse input. Characteristics voltage levels.
Notes: Manufacturer device codes also accessed command register write sequence. Table Refer section Sector Group Protection. VIL, initiates write operations. also used extended sector group protection. Protect "outermost" bytes words) both ends boot block sectors.
MBM29DD640E 10/12
FUNCTIONAL DESCRIPTION
Simultaneous Operation
device feature, which capable reading data from bank memory while program erase operation progress other bank memory (simultaneous operation), addition conventional features (read, program, erase, erase-suspend read, erase-suspend program). bank selection selected bank address (A21, A20, A19) with zero latency. simultaneous operation execute multi-function mode same bank. Table shows possible combinations simultaneous operation. (Refer Figure Bank-to-Bank Read/Write Timing Diagram.) Table Case Simultaneous Operation Bank Status Read mode Autoselect mode Program mode Erase mode Read mode Read mode Read mode
Bank Status Read mode Read mode Read mode Read mode Autoselect mode Program mode Erase mode
erase operation also supended read from program sector being erased.
Read Mode
device control functions which must satisfied order obtain data outputs. power control should used device selection. output control should used gate data output pins device selected. Address access time (tACC) equal delay from stable addresses valid output data. chip enable access time (tCE) delay from stable addresses stable valid data output pins. output enable access time delay from falling edge valid data output pins. (Assuming addresses have been stable least tACC-tOE time.) When reading data without changing addresses after power-up, necessary input hardware reset change from "L". RESET must held during rampup insure that device power correctly. (Refer Figure 5.3.)
Standby Mode
There ways implement standby mode device, using both RESET pins; other RESET only. When using both pins, CMOS standby mode achieved with RESET inputs both held Under this condition current consumed less than max. During Embedded Algorithm operation, active current (ICC2) required even "H". device read with standard access time (tCE) from either these standby modes. When using RESET only, CMOS standby mode achieved with RESET input held "L"). Under this condition current consumed less than max. Once RESET taken high, device requires wake time outputs valid read access. standby mode outputs high impedance state, independently input.
MBM29DD640E 10/12
Automatic Sleep Mode
There function called automatic sleep mode restrain power consumption during read-out device data. This mode useful application such handy terminal which requires power consumption. activate this mode, device automatically switches themselves power mode when device addresses remain stable during access time necessary control mode. Under mode, current consumed typically (CMOS Level). During simultaneous operation, active current (ICC2) required. Since data latched during this mode, data read-out continuously. addresses changed, mode canceled automatically, device reads data changed addresses.
Output Disable
With input logic high level (VIH), output from device disabled. This will cause output pins high impedance state.
Autoselect
autoselect mode allows reading binary code from device will identify manufacturer type. This mode intended programming equipment purpose automatically matching device programmed with corresponding programming algorithm. This mode functional over entire temperature range device. activate this mode, programming equipment must force (11.5 12.5 address Three identifier bytes then sequenced from device outputs toggling address from VIH. addresses DON'T CARES except (A-1). (See Tables manufacturer device codes also read command register, instances when device erased programmed system without access high voltage pin. command sequence illustrated Table (Refer Autoselect Command section.) command Autoselect mode, bank addresses A20, A19) must point specific bank during third write cycle Autoselect command. Then Autoselect data will read from that bank while array data read from other bank. read cycle from address (BA)00h returns manufacturer's code (Fujitsu 04h). read cycle from address (BA)01h, (BA)0Eh (BA)0Fh returns device code. (See Tables 8.2.) case applying since both Bank Bank enters Autoselect mode, simultenous operation executed.
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Table Type Manufacture's Code Byte Device Code Word Byte BA*3 Extended Device Code Word Byte BA*3 Word Sector Group Protection Byte mode. Outputs protected sector group addresses outputs unprotected sector group addresses. Bank Address which needed only Command Autoselect mode. Table Type Manufacturer's Code Device Code 227Eh HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z Code Expanded Autoselect Code Table
MBM29DD640E Sector Group Protection Verify Autoselect Codes BA*3 BA*3 Sector Group Addresses 2200h 01h*2 2204h 227Eh A-1*1 Code (HEX)
DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 A-1/0
HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z
Extended Device 2204h Code HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 2200h Sector Group Protection (B): Byte mode (W): Word mode
A-1/0
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Write
Device erasure programming accomplished command register. contents register serve inputs internal state machine. state machine outputs dictate function device. command register itself does occupy addressable memory location. register latch used store commands, along with address data information needed execute command. command register written bringing VIL, while VIH. Addresses latched falling edge whichever happens later; while data latched rising edge whichever happens first. Standard microprocessor write timings used. Refer Write Characteristics Erase/Programming Waveforms specific timing parameters.
Sector Group Protection
device features hardware sector group protection. This feature will disable both program erase operations combination forty eight sector groups memory. (See Table sector group protection feature enabled using programming equipment user's site. device shipped with sector groups unprotected. activate this mode, programming equipment must force address control (suggest 11.5 VIL, VIH. sector group addresses (A21, A20, A19, A18, A17, A16, A15, A14, A13, A12) should sector protected. Tables define sector address each hundred forty-two (142) individual sectors, Table define sector group address each forty eight (48) individual group sectors. Programming protection circuitry begins falling edge pulse terminated with rising edge same. Sector group addresses must held constant during pulse. Figures sector group protection waveforms algorithm. verify programming protection circuitry, programming equipment must force address with VIH. Scanning sector group addresses (A21, A20, A19, A18, A17, A16, A15, A14, A13, A12) while (A6, will produce logical code device output protected sector. Otherwise device will produce unprotected sector. this mode, lower order addresses, except DON'T CARES. Address locations with reserved Autoselect manufacturer device codes. requires apply byte mode. also possible determine sector group protected system writing Autoselect command. Performing read operation address location (BA) XX02h, where higher order addresses (A21, A20, A19, A18, A17, A16, A15, A14, A13, A12) desired sector group address will produce logical protected sector group. Note that bank addresses (A21, A20, A19) must pointing specific bank during third write cycle Autoselect command. Then, Autoselect data read from that bank while array data still read from other bank. read Autoselect data from other bank, must reset read mode then write Autoselect command other bank. Tables Autoselect codes.
Temporary Sector Group Unprotection
This feature allows temporary unprotection previously protected sector groups device order change data. Sector Group Unprotection mode activated setting RESET high voltage (VID). During this mode, formerly protected sector groups programmed erased selecting sector group addresses. Once taken away from RESET pin, previously protected sector groups will protected again. Refer Figures
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Extended Sector Group Protection
addition normal sector group protection, device Extended Sector Group Protection extended function. This function enables protect sector group forcing RESET write command sequence. Unlike conventional procedure, necessary force control timing control pins. only RESET requires sector group protection this mode. extended sector group protection requires RESET pin. With this condition, operation initiated writing set-up command (60h) into command register. Then, sector group addresses pins (A21, A20, A19, A18, A17, A16, A15, A14, A12) (A6, should sector group protected (recommend other addresses pins), write extended sector group protection command (60h). sector group typically protected verify programming protection circuitry, sector group addresses pins (A21, A20, A19, A18, A17, A16, A15, A14, A12) (A6, should write command (40h). Following command write, logical device output will produce protected sector read operation. output logical "0", please repeat write extended sector group protection command (60h) again. terminate operation, necessary RESET VIH. (Refer Figures 28.)
RESET Hardware Reset
device reset driving RESET VIL. RESET pulse requirement kept (VIL) least "tRP" order properly reset internal state machine. operation process being executed will terminated internal state machine will reset read mode "tREADY" after RESET driven low. Furthermore, once RESET goes high, device requires additional "tRH" before will allow read access. When RESET low, device will standby mode duration pulse data output pins will tri-stated. hardware reset occurs during program erase operation, data that particular location will corrupted. Please note that RY/BY output signal should ignored during RESET pulse. Figure timing diagram. Refer Temporary Sector Group Unprotection additional functionality.
Boot Block Sector Protection
Write Protection function provides hardware method protecting certain boot sectors without using VID. This function provided WP/ACC pin. system asserts WP/ACC pin, device disables program erase functions "outermost" byte both ends boot sectors independently whether those sectors protected unprotected using method described "Sector Protection/Unprotection". (MBM29DD640E: SA0, SA1, SA140, SA141) system asserts WP/ACC pin, device reverts whether outermost byte both ends boot sectors were last protected unprotected. That sector protection unprotection these four sectors depends whether they were last protected unprotected using method described "Sector protection/unprotection".
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Accelerated Program Operation
device offers accelerated program operation which enables programming high speed. system asserts VACC WP/ACC pin, device automatically enters acceleration mode time required program operation will reduce about 60%. This function primarily intended allow high speed program, caution needed sector group will temporarily unprotected. system would fast program command sequence when programming during acceleration mode. command fast mode reset command from fast mode necessary. When device enters acceleration mode, device automatically fast mode. Therefore, pressent sequence could used programming detection completion during acceleration mode. Removing VACC from WP/ACC returns device normal operation. remove VACC from while programming. Figure
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Table Command Sequence
Read/Reset Read/Reset Write Cycles Req'd
MBM29DD640E Command Definitions
Fifth Sixth First Second Third Fourth Write Cycle Write Cycle Write Cycle Read/Write Write Cycle Write Cycle Cycle Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data XXXh 2AAh 555h 2AAh AAAh 555h 2AAh 555h 2AAh 555h 2AAh 555h
Word Byte Word Byte Word
555h AAAh (BA) 555h (BA) AAAh 555h AAAh 555h AAAh 555h AAAh 555h AAAh 555h AAAh 555h AAAh
(HRBA)
555h AAAh 555h
Autoselect
Byte Word Byte
Program
Program Suspend Program Resume Chip Erase
Word Byte Word Byte
Sector Erase
Erase Suspend Erase Resume
Extended Sector Group Protection Fast Mode Fast Program Reset from Fast Mode Query Hi-ROM Entry Hi-ROM Program
555h AAAh 555h AAAh 555h AAAh XXXh
2AAh 555h 2AAh 555h
555h AAAh
555h AAAh 555h AAAh
(HRA)
Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word
555h 2AAh AAAh 555h XXXh XXXh XXXh XXXh 555h 2AAh AAAh 555h 555h 2AAh AAAh 555h 555h 2AAh AAAh 555h
XXXh
Hi-ROM Exit
Byte
555h
(HRBA)
AAAh
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Notes: Address bits address commands except Program Address (PA), Sector Address (SA), Bank Address (BA). operations defined Tables Address memory location read Address memory location programmed Addresses latched falling edge write pulse. Address sector erased. combination A21, A20, A19, A18, A17, A16, A15, A14, A13, will uniquely select sector. Bank Address (A21, A20, A19) Data read from location during read operation. Data programmed location Data latched falling edge write pulse. Sector group address protected. sector group address (SGA) (A6, Sector group protection verify data. Output protected sector group addresses output unprotected sector group addresses. Address Hi-ROM area Word Mode: 000000h 000040h Byte Mode: 000000h 000080h HRBA =Bank Address Hi-ROM area (A21 VIL) This command valid while Fast Mode. This command valid while RESET VID. valid addresses This command valid while Hi-ROM mode. data "00h" also acceptable.
system should generate following address patterns: Word Mode: 555h 2AAh addresses Byte Mode: AAAh 555h addresses Both Read/Reset commands functionally equivalent, resetting device read mode.
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COMMAND DEFINITIONS
Device operations selected writing specific address data sequences into command register. Writing incorrect address data values writing them improper sequence will reset device read mode. Some commands require Bank Address (BA) input. When command sequences inputed bank being read, commands have priority over reading. Table defines valid register command sequences. Note that Erase Suspend (B0h) Erase Resume (30h) commands valid only while Sector Erase operation progress. Also Program Suspend (B0h) Program Resume (30h) commands valid only while Program operation progress. Moreover both Read/Reset commands functionally equivalent, resetting device read mode. Please note that commands always written DQ15 bits ignored.
Read/Reset Command
order return from Autoselect mode Exceeded Timing Limits (DQ5 Read/Reset mode, Read/ Reset operation initiated writing Read/Reset command sequence into command register. Microprocessor read cycles retrieve array data from memory. device remains enabled reads until command register contents altered. device will automatically power-up Read/Reset state. this case, command sequence required read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that spurious alteration memory content occurs during power transition. Refer Read Characteristics Waveforms specific timing parameters.
Autoselect Command
Flash memories intended applications where local alters memory contents. such, manufacture device codes must accessible while device resides target system. PROM programmers typically access signature codes raising high voltage. However, multiplexing high voltage onto address lines generally desired system design practice. device contains Autoselect command operation supplement traditional PROM programming methodology. operation initiated writing Autoselect command sequence into command register. Autoselect command sequence initiated firstly writing unlock cycles. This followed third write cycle that contains bank address (BA) Autoselect command. Then manufacture device codes read from bank, actual data memory cell read from another bank. Following command write, read cycle from address (BA)00h retrieves manufacture code 04h. read cycle address (BA)01h returns indicate that this device uses extended device code. successive read cycle from (BA)0Eh (BA)0Fh returns this extended device code this device. (See Tables 8.2.) sector state (protection unprotection) will informed address (BA)02h ((BA)04h Scanning sector group addresses (A21, A20, A19, A18, A17, A16, A15, A14, A13, A12) while (A6, will produce logical device output protected sector group. programming verification should performed verify sector group protection protected sector. (See Tables manufacture device codes allowed reading from selected bank. read manufacture device codes sector protection status from non-selected bank, necessary write Read/Reset command sequence into register then Autoselect command should written into bank read. software (program code) Autoselect command stored into Flash memory, device manufacture codes should read from other bank which doesn't contain software. terminate operation, necessary write Read/Reset command sequence into register. execute Autoselect command during operation, writing Read/Reset command sequence must precede Autoselect command.
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Byte/Word Programming
device programmed byte-by-byte word-by-word) basis. Programming four cycle operation. There "unlock" write cycles. These followed program set-up command data write cycles. Addresses latched falling edge whichever happens later data latched rising edge whichever happens first. rising edge (whichever happens first) begins programming. Upon executing Embedded Program Algorithm command sequence, system required provide further controls timings. device will automatically provide adequate internally generated program pulses verify programmed cell margin. system determine status program operation using (Data Polling), (Toggle Bit), RY/BY. Data Polling Toggle must performed memory location which being programmed. automatic programming operation completed when data equivalent data written this which time device returns read mode addresses longer latched. (See Table Hardware Sequence Flags.) Therefore, device requires that valid address device supplied system this particular instance time. Hence, Data Polling must performed memory location which being programmed. commands written chip during this period will ignored. hardware reset occurs during programming operation, impossible guarantee data being written. Programming allowed sequence across sector boundaries. Beware that data cannot programmed back "1". Attempting either hang device result apparent success according data polling algorithm read from Read/Reset mode will show that data still "0". Only erase operations convert "0"s "1"s. Figure illustrates Embedded ProgramAlgorithm using typical command strings operations.
Program Suspend/Resume
Program Suspend command allows system interrupt program operation that data read from address. Writing Program Suspend command (B0h) during Embedded Program operation immediately suspends programming. Program Suspend command also issued during programming operation while erase suspended. bank addresses sector being programed should when writing Program Suspend command. When Program Suspend command written during programming process, device halts program operation within updates status bits. After program operation been suspended, system read data from address. data program-suspended address valid. Normal read timing command definitions apply. After Program Resume command (30h) written, device reverts programming. bank addresses sector being suspended should when writing Program Resume command. system determine status program operation using status bits, just standard program operation. "Write Operation Status" more information. system also write autoselect command sequence when device Program Suspend mode. device allows reading autoselect codes addresses within programming sectors, since codes stored memory. When device exits autoselect mode, device reverts Program Suspend mode, ready another valid operation. "Autoselect Command Sequence" more information. system must write Program Resume command (address bits "Bank Address") exit Program Suspend mode continue programming operation. Further writes Resume command ignored. Another Program Suspend command written after device resumed programming.
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Chip Erase
Chip erase cycle operation. There "unlock" write cycles. These followed writing "set-up" command. more "unlock" write cycles then followed chip erase command. Chip erase does require user program device prior erase. Upon executing Embedded Erase Algorithm command sequence device will automatically program verify entire memory zero data pattern prior electrical erase (Preprogram function). system required provide controls timings during these operations. system determine status erase operation using (Data Polling), (Toggle Bit), RY/BY. chip erase begins rising edge last whichever happens first command sequence terminates when data (See Write Operation Status section.) which time device returns read mode. Chip Erase Time; Sector Erase Time sectors Chip Program Time (Preprogramming) Figure illustrates Embedded EraseAlgorithm using typical command strings operations.
Sector Erase
Sector erase cycle operation. There "unlock" write cycles. These followed writing "set-up" command. more "unlock" write cycles then followed Sector Erase command. sector address (any address location within desired sector) latched falling edge whichever happens later, while command (Data 30h) latched rising edge which happens first. After time-out "tTOW" from rising edge last sector erase command, sector erase operation will begin. Multiple sectors erased concurrently writing cycle operations Table This sequence followed with writes Sector Erase command addresses other sectors desired concurrently erased. time between writes must less than "tTOW" otherwise that command will accepted erasure will start. recommended that processor interrupts disabled during this time guarantee this condition. interrupts re-enabled after last Sector Erase command written. time-out "tTOW" from rising edge last whichever happens first will initiate execution Sector Erase command(s). another falling edge whichever happens first occurs within "tTOW" time-out window timer reset. (Monitor determine sector erase timer window still open, section DQ3, Sector Erase Timer.) command other than Sector Erase Erase Suspend during this time-out period will reset device read mode, ignoring previous command string. Resetting device once execution begun will corrupt data sector. that case, restart erase those sectors allow them complete. (Refer Write Operation Status section Sector Erase Timer operation.) Loading sector erase buffer done sequence with number sectors 141). Sector erase does require user program device prior erase. device automatically programs memory locations sector(s) erased prior electrical erase (Preprogram function). When erasing sector sectors remaining unselected sectors affected. system required provide controls timings during these operations. system determine status erase operation using (Data Polling), (Toggle Bit), RY/BY. sector erase begins after "tTOW" time from rising edge whichever happens first last sector erase command pulse terminates when data (See Write Operation Status section.) which time device returns read mode. Data polling Toggle must performed address within sectors being erased. Multiple Sector Erase Time; [Sector Erase Time Sector Program Time (Preprogramming)] Number Sector Erase
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case multiple sector erase across bank boundaries, read from bank (read-while-erase) performe. Figure illustrates Embedded EraseAlgorithm using typical command strings operations.
Erase Suspend/Resume
Erase Suspend command allows user interrupt Sector Erase operation then perform data reads from programs sector being erased. This command applicable ONLY during Sector Erase operation which includes time-out period sector erase. Erase Suspend command will ignored written during Chip Erase operation Embedded Program Algorithm. Writting Erase Suspend command (B0h) during Sector Erase time-out results immediate termination time-out period suspension erase operation. Writing Erase Resume command (30h) resumes erase operation. bank addresses sector being erased erase-suspended should when writting Erase Suspend Erase Resume command. When Erase Suspend command written during Sector Erase operation, device will take maximum "tSPD" suspend erase operation. When device entered erase-suspended mode, RY/BY output will Hi-Z will logic "1", will stop toggling. user must address erasing sector reading determine erase operation been suspended. Further writes Erase Suspend command ignored. When erase operation been suspended, device defaults erase-suspend-read mode. Reading data this mode same reading from standard read mode except that data must read from sectors that have been erase-suspended. Successively reading from erase-suspended sector while device erase-suspend-read mode will cause toggle. (See section DQ2.) After entering erase-suspend-read mode, user program device writing appropriate command sequence Program. This program mode known erase-suspend-program mode. Again, programming this mode same programming regular Program mode except that data must programmed sectors that erase-suspended. Successively reading from erase-suspended sector while device erase-suspend-program mode will cause toggle. erase-suspended Program operation detected RY/BY output pin, Data polling Toggle (DQ6) which same regular Program operation. Note that must read from Program address while read from address within bank being erase-suspended. resume operation Sector Erase, Resume command (30h) should written bank being erase suspended. further writes Resume command this point will ignored. Another Erase Suspend command written after chip resumed erasing.
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Extended Command
Fast Mode device Fast Mode function. This mode dispenses with initial unclock cycles required standard program command sequence writing Fast Mode command into command register. this mode, required cycle programming cycles instead four cycles standard program command. write erase command this mode.) read operation also executed after exiting this mode. exit this mode, necessary write Fast Mode Reset command into command register. first cycle must contain bank address. (Refer Figure 29.) active current required even during Fast Mode. Fast Programming During Fast Mode, programming executed with cycles operation. Embedded Program Algorithm executed writing program set-up command (A0h) data write cycles (PA/PD). (Refer Figure 29.) (Common Flash Memory Interface) (Common Flash Memory Interface) specification outlines device host system software interrogation handshake which allows specific vendor-specified software algorithms used entire families devices. This allows device-independent, JEDEC ID-independent, forward-and backwardcompatible software support specified flash device families. Refer specification detail. operation initiated writing query command (98h) into command register. bank address should when writing this command. Then device information read from bank, actual data memory cell read from another bank. Following command write, read cycle from specific address retrives device information. Please note that output data upper byte (DQ15 DQ8) word mode bit) read. Refer code table. terminate operation, necessary write read/ reset command sequence into register. (See Table 12.)
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Hidden (Hi-ROM) Region
Hi-ROM feature provides Flash memory region that system access through command sequence. This primarily intended customers wish Electronic Serial Number (ESN) device with protected against modification. Once Hi-ROM region protected, further modification that region impossible. This ensures security once product shipped field. Hi-ROM region bytes length stored same address "outermost" byte boot sector Bank device occupies address byte mode 000000h 000080h (word mode 000000h 000040h). After system written Enter Hi-ROM command sequence, system read HiROM region using addresses normally occupied boot sectors. That device sends commands that would normally sent boot sectors Hi-ROM region. This mode operation continues until system issues Exit Hi-ROM command sequence, until power removed from device. power-up, following hardware reset, device reverts sending commands boot sectors.
Hidden (Hi-ROM) Entry Command
device Hidden area with Time Protect function. This area enter security code unable change code once set. Program/erase possible this area until protected. However, once protected, impossible unprotect, please this with caution. Hidden area bytes. This area normally "outermost" byte boot block area Bank Therefore, write Hidden entry command sequence enter Hidden area. called Hidden mode when Hidden area appears. Sector other than boot block area could read during Hidden mode. Read/program Hidden area possible during Hidden mode. Write Hidden reset command sequence exit Hidden mode. bank address Hidden should third cycle this reset command sequence. Hidden mode, simultaneous operation cannot execute multi-function mode between Hidden area "outermost" byte (SA0) area Bank
Hidden (Hi-ROM) Program Command
program data Hidden area, write Hidden program command sequence during Hidden mode. This command same program command usual except write command during Hidden mode. Therefore detection completion method same past, using data poling, toggle RY/BY pin. Need attention address programmed. address other than Hidden area selected program, data address will changed.
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Hidden (Hi-ROM) Protect Command
There methods protect Hidden area. write sector group protect setup command(60h), sector address Hidden area (A6, write sector group protect command(60h) during Hidden mode. same command sequence could used because, same extension sector group protect past except that Hidden mode does apply high voltage RESET pin. Please refer "Function Explanation Extentended Sector Group Protection" details extention sector group protect setting. other apply high voltage (VID) sector address Hidden area (A6, apply write pulse during Hidden mode. verify protect circuit, apply high voltage (VID) specify (A6, sector address Hidden area, read. When appears DQ0, protect setting completed. will appear protected. Please apply write pulse agian. same command sequence could used above method because other than Hidden mode, same sector group protect past. Please refer "Function Explanation Secor Group Protection" details sector group protect setting. Other sector group will effected address other than those Hidden area selected sector group address, please carefull. Once protected, protection cancelled, please closest attention.
Write Operation Status
Detailed Table status flags that determine status bank current mode operation. read operation from bank which doesn't operate Embedded Algorithm returns data memory cells. These bits offer method determining whether Embedded Algorithm completed properly. information address sensitive. This means that address from erasing sector consectively read, then will toggle. However, will toggle address from non-erasing sector consectively read. This allows users determine which sectors erase which not. status flag output from bank (non-busy bank) which doesn't execute Embedded Algorithm. example, there bank (busy bank) which executing Embedded Algorithm. When read sequence <busy bank>, <non-busy bank>, <busy bank>, toggling case [3]. case [2], data memory cells outputted. erase-suspend read mode with same read sequence, will toggled [3]. erase suspend read mode, toggled [3]. case [2], data memory cell outputted.
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Table Status Embedded Program Algorithm Embedded Erase Algorithm Program Suspend Read Program (Program Suspended Sector) Suspended Program Suspend Read Mode (Non-Program Suspended Sector) Progress Erase Suspend Read (Erase Suspended Sector) Erase Erase Suspend Read Suspended (Non-Erase Suspended Sector) Mode Erase Suspend Program (Non-Erase Suspended Sector) Embedded Program Algorithm Embedded Erase Algorithm Exceeded Time Limits Erase Erase Suspend Program Suspended (Non-Erase Suspended Sector) Mode Hardware Sequence Flags Data Data Data Toggle Toggle Data Data Data Toggle Toggle Toggle Toggle Toggle (Note Data Data Toggle Data (Note
Data Data Data Data
Data Data
Notes: Successive reads from erasing erase-suspend sector will cause toggle. Reading from non-erase suspend sector address will indicate logic bit. reserve pins future use. Fujitsu internal only.
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Data Polling
device features Data Polling method indicate host that Embedded Algorithms progress completed. During Embedded Program Algorithm attempt read device will produce complement data last written DQ7. Upon completion Embedded Program Algorithm, attempt read device will produce true data last written DQ7. During Embedded Erase Algorithm, attempt read device will produce output. Upon completion Embedded Erase Algorithm attempt read device will produce DQ7. flowchart Data Polling (DQ7) shown Figure programming, Data Polling valid after rising edge fourth write pulse four write pulse sequence. chip erase sector erase, Data Polling valid after rising edge sixth write pulse write pulse sequence. Data Polling must performed sector address sectors being erased, protected sectors. Otherwise, status invalid. program address falls within protected sector, Data Polling active approximately then that bank returns read mode. After erase command sequence written, sectors selected erasing protected, Data Polling active approximately then bank returns read mode. Once Embedded Algorithm operation close being completion, device data pins (DQ7) change asynchronously while output enable (OE) asserted low. This means that device driving status information instant time then that byte's valid data next instant time. Depending when system samples output, read status valid data. Even device completed Embedded Algorithm operation valid data, data outputs still invalid. valid data will read successive read attempts. Data Polling feature active only during Embedded Programming Algorithm, Embedded Erase Algorithm sector erase time-out. (See Table 10.) Figure Data Polling timing specifications diagrams.
Toggle
device also features "Toggle method indicate host system that Embedded Algorithms progress completed. During Embedded Program Erase Algorithm cycle, successive attempts read toggling) data from device will result toggling between zero. Once Embedded Program Erase Algorithm cycle completed, will stop toggling valid data will read next successive attempts. During programming, Toggle valid after rising edge fourth write pulse four write pulse sequence. chip erase sector erase, Toggle valid after rising edge sixth write pulse write pulse sequence. Toggle active during sector time out. programming, sector being written protected, toggle will toggle about then stop toggling with data unchanged. erase, device will erase selected sectors except ones that protected. selected sectors protected, chip will toggle toggle about then drop back into read mode, having data unchanged. Either toggling will cause toggle. addition, Erase Suspend/Resume command will cause toggle.
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system determine whether sector actively erased erase-suspended. When bank actively erased (that Embedded Erase Algorithm progress), toggles. When bank enters Erase Suspend mode, stops toggling. Successive read cycles during erase-suspend-program cause toggle. operate toggle function properly, must high when bank address changed. Figure Toggle timing specifications diagrams.
Exceeded Timing Limits
will indicate program erase time exceeded specified limits (internal pulse count). Under these conditions will produce "1". This failure condition which indicates that program erase cycle successfully completed. Data Polling only operating function device under this condition. circuit will partially power down device under these conditions approximately mA). pins will control output disable functions described Tables failure condition also appear user tries program blank location without pre-erase. this case device locks never completes Embedded Algorithm operation. Hence, system never read valid data never stop toggling. Once device exceeded timing limits, will indicate "1." Please note that this device failure condition since device incorrectly used. this occurs, reset device with command sequence.
Sector Erase Timer
After completion initial sector erase command sequence sector erase time-out will begin. will remain until time-out completed. Data Polling Toggle valid after initial sector erase command sequence. Data Polling Toggle indicates device been written with valid erase command, used determine sector erase timer window still open. high ("1") internally controlled erase cycle begun; attempts write subsequent commands device will ignored until erase operation completed indicated Data Polling Toggle ("0"), device will accept additional sector erase commands. insure command been accepted, system software should check status prior following each subsequent Sector Erase command. were high second status check, command have been accepted. Table Hardware Sequence Flags.
Toggle
This toggle along with DQ6, used determine whether device Embedded Erase Algorithm Erase Suspend. Successive reads from erasing sector will cause toggle during Embedded Erase Algorithm. device erase-suspended-read mode, successive reads from erase-suspended sector will cause toggle. When device erase-suspended-program mode, successive reads from byte address non-erase suspended sector will indicate logic bit. different from that toggles only when standard program Erase, Erase Suspend Program operation progress. behavior these status bits, along with that DQ7, summarized follows:
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example, used together determine erase-suspend-read mode progress. (DQ2 toggles while does not.) also Table Figure Furthermore, also used determine which sector being erased. When device erase mode, toggles this read from erasing sector. operate toggle function properly, must high when bank address changed.
Reading Toggle Bits DQ6/DQ2
Whenever system initially begins reading toggle status, must read least twice determine whether toggle toggling. Typically, system would note store value toggle after first read. After second read, system would compare value toggle with first. toggle toggling, device completed program erase operation. system read array data following read cycle. However, after initial read cycles, system determines that toggle still toggling, system also should note whether value high (see section DQ5). system should then determine again whether toggle toggling, since toggle have stopped toggling just went high. toggle longer toggling, device successfully completed program erase operation. still toggling, device complete operation successfully, system must write reset command return reading array data. remaining scenario that system initially determines that toggle toggling gone high. system continue monitor toggle through successive read cycles, determining status described previous paragraph. Alternatively, choose perform other system tasks. this case, system must start beginning algorithm when returns determine status operation. (Refer Figure 25.) Table Mode Program Erase Erase-Suspend Read (Erase-Suspended Sector) Erase-Suspend Program Toggle Status Toggle Toggle Toggle Toggle (Note) Toggle (Note)
Note: Successive reads from erasing erase-suspend sector will cause toggle. Reading from nonerase suspend sector address will indicate logic bit.
RY/BY Ready/Busy
device provides RY/BY open-drain output indicate host system that Embedded Algorithms either progress been completed. output low, device busy with either program erase operation. output high, device ready accept read/write erase operation. When RY/BY low, device will accept additional program erase commands. device placed Erase Suspend mode, RY/BY output will high.
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During programming, RY/BY driven after rising edge fourth write pulse. During erase operation, RY/BY driven after rising edge sixth write pulse. RY/BY will indicate busy condition during RESET pulse. Refer Figures detailed timing diagram. RY/BY pulled high standby mode. Since this open-drain output, RY/BY pins tied together parallel with pull-up resistor VCC.
Byte/Word Configuration
BYTE selects byte (8-bit) mode word (16-bit) mode device. When this driven high, device operates word (16-bit) mode. Data read programmed DQ15 DQ0. When this driven low, device operates byte (8-bit) mode. Under this mode, 15/A-1 becomes lowest address bit, DQ14 bits tri-stated. However, command cycle always 8-bit operation hence commands written DQ15 bits ignored. Refer Figures timing diagram.
Data Protection
device designed offer protection against accidental erasure programming caused spurious system level signals that exist during power transitions. During power device automatically resets internal state machine Read mode. Also, with control register architecture, alteration memory contents only occurs after successful completion specific multi-bus cycle command sequences. Device also incorporates several features prevent inadvertent write cycles resulting from power-up power-down transitions system noise.
Write Pulse "Glitch" Protection
Noise pulses less than (typical) will initiate write cycle.
Logical Inhibit
Writing inhibited holding VIL, VIH, VIH. initiate write cycle must logical zero while logical one.
Power-Up Write Inhibit
Power-up device with will accept commands rising edge internal state machine automatically reset read mode power-up.
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Table Description Query-unique ASCII string "QRY" Primary Command AMD/FJ standard type Address Primary Extended Table Alternate Command (00h applicable) Address Alternate Extended Table Min. (write/erase) D7-4: volt, D3-0: mvolt Max. (write/erase) D7-4: volt, D3-0: mvolt Min. voltage Max. voltage Typical timeout single byte/word write Typical timeout Min. size buffer write Typical timeout individual block erase Typical timeout full chip erase Max. timeout byte/word write times typical Max. timeout buffer write times typical Max. timeout individual block erase times typical Max. timeout full chip erase times typical Device Size byte Flash Device Interface description Max. number byte multi-byte write Number Erase Block Regions within device Erase Block Region Information Common Flash Memory Interface Code
DQ15
0051h 0052h 0059h 0002h 0000h 0040h 0000h 0000h 0000h 0000h 0000h 0023h 0027h 0000h 0000h 0004h 0000h 000Ah 0000h 0005h 0000h 0004h 0000h 0017h 0002h 0000h 0000h 0000h 0003h 0007h 0000h 0020h 0000h 007Dh 0000h 0000h 0001h 0007h 0000h 0020h 0000h
Description Query-unique ASCII string "PRI" Major version number, ASCII Minor version number, ASCII Address Sensitive Unlock Required Required Erase Suspend Supported Read Only Read Write Sector Protection Supported Number sectors group Sector Temporary Unprotection Supported Supported Sector Protection Algorithm Simultaneous Operation Supported Total number sectors banks except Bank Burst Mode Type Supported Page Mode Type Supported (Acceleration) Supply Minimum Supported, D7-4: volt, D3-0: mvolt (Acceleration) Supply Maximum Supported, D7-4: volt, D3-0: mvolt Boot Type Program Suspend Supported Supported Bank Organization data zero. Number Banks Bank Region Information sectors Bank Bank Region Information sectors Bank Bank Region Information sectors Bank Bank Region Information sectors Bank
DQ15
0050h 0052h 0049h 0031h 0033h 0000h
0002h
0001h
0001h
0004h 0077h
0000h 0000h 0085h
0095h
0001h 0001h
0004h
0017h 0030h 0030h 0017h
Erase Block Region Information
Erase Block Region Information
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ABSOLUTE MAXIMUM RATINGS
Parameter Storage Temperature Ambient Temperature with Power Applied Voltage with Respect Ground pins except RESET (Note Power Supply Voltage (Note RESET (Note WP/ACC (Note Symbol Tstg VIN, VOUT VACC Rating Min. -0.5 -0.5 -0.5 -0.5 Max. +125 VCC+0.5 +4.0 +13.0 +10.5 Unit
WARNING: Semiconductor devices permanently damaged application stress (voltage, current, temperature, etc.) excess absolute maximum ratings. exceed these ratings. Notes: Minimum voltage input pins -0.5 During voltage transitions, inputs negative overshoot -2.0 periods Maximum voltage output pins +0.5 During voltage transitions, outputs positive overshoot +2.0 periods Minimum input voltage RESET pins -0.5 During voltage transitions, RESET pins negative overshoot -2.0 periods Maximum input voltage RESET pins +13.0 which positive overshoot 14.0 periods when applied. Minimum input voltage WP/ACC -0.5 During voltage transitions, WP/ACC negative overshoot -2.0 periods Maximum input voltage WP/ACC +10.5V which positive overshoot +10.5V periods 20ns when applied.
RECOMMENDED OPERATING RANGES
Parameter Ambient Temperature Power Supply Voltage Symbol Part MBM29DD640E 10/12 MBM29DD640E 10/12 Ranges Min. +2.3 Max. +2.7 Unit
Operating ranges define those limits between which functionality device guaranteed. WARNING: recommended operating conditions required order ensure normal operation semiconductor device. device's electrical characteristics warranted when device operated within these ranges. Always semiconductor devices within their recommended operating conditionranges. Operation outside these ranges adversely affect reliability could result device failure. warranty made with respect uses, operating conditions, combinations represented data sheet. Users considering application outside listed conditions advised contact their FUJITSU representatives beforehand.
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MAXIMUM OVERSHOOT
+0.6 -0.5 -2.0
Figure
Maximum Negative Overshoot Waveform
+2.0 +0.5 +2.0
Figure
Maximum Positive Overshoot Waveform
+14.0 +13.0 +0.5
This waveform applied RESET.
Figure
Maximum Positive Overshoot Waveform
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CHARACTERISTICS
Parameter Symbol ILIT Parameter Description Input Leakage Current Output Leakage Current RESET Inputs Leakage Current Test Conditions VCC, Max. VOUT VCC, Max. Max. RESET 12.5 VIL, VIH, ICC1 Active Current (Note VIL, VIH, ICC2 ICC3 ICC4 ICC5 Active Current (Note Current (Standby) Current (Standby, Reset) VIL, Max., RESET Max.,WE/ACC RESET Byte Word Byte Word Min. -1.0 -1.0 -0.5 Max. +1.0 +1.0 VCC+0.3 Unit
Max., Current RESET (Automatic Sleep Mode) (Note Active Current (Note (Read-While-Program) Active Current (Note (Read-While-Erase) Active Current (Erase-Suspend-Program) WP/ACC Accelerated Program Current Input Level Input High Level Voltage WP/ACC Sector Protection/Unprotection Program Acceleration (Note Voltage Autoselect Sector Protection (A9, RESET) (Note Output Voltage Level Output High Voltage Level VIL, VIL, VIL, Max. WP/ACC VACC Max. Byte Word Byte Word
ICC6 ICC7 ICC8 IACC VACC
VOH1 VOH2 Notes:
Min. -2.0 Min. -100
11.5 VCC-0.1
12.5
current listed includes both operating current frequency dependent component. active while Embedded Algorithm (program erase) progress. Automatic sleep mode enables power mode when address remain stable Applicable only applying. Embedded Algorithm (program erase) progress. MHz)
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CHARACTERISTICS
Read Only Operations Characteristics Parameter Symbols JEDEC tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tAXQX Standard tACC tREADY tELFL tELFH Read Cycle Time Address Output Delay Chip Enable Output Delay Output Enable Output Delay Chip Enable Output High-Z Output Enable Output High-Z Output Hold Time From Addresses, Whichever Occurs First RESET Read Mode BYTE Switching High Min. (Note1) (Note2)
Description
Test Setup
Unit
Max. Max. Max. Max. Max. Min. Max. Max.
Note: Test Conditions: Output Load: gate Input rise fall times: Input pulse levels: Timing measurement reference level Input: Output:
Note: Test Conditions: Output Load: gate Input rise fall times: Input pulse levels: Timing measurement reference level Input: Output:
IN3064 Equivalent Device Under Test Diodes IN3064 Equivalent
Figure
Test Conditions
MBM29DD640E 10/12
Write/Erase/Program Operations Parameter Symbols Description JEDEC tAVAV tAVWL tWLAX tDVWH tWHDX tGHWL tGHEL tELWL tWLEL tWHEH tEHWH tWLWH tELEH tWHWL tEHEL tWHWH1 tWHWH2 Standard tASO tAHT tOEH tCEPH tOEPH tGHWL tGHEL tWPH tCPH tWHWH1 tWHWH2 tVCS tVIDR tVACCR tVLHT tWPP Write Cycle Time Address Setup Time Address Setup Time During Toggle Polling Address Hold Time Address Hold Time from High During Toggle Polling Data Setup Time Data Hold Time Output Enable Hold Time Read Toggle Data Polling Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Byte Programming Operation Word Sector Erase Operation (Note Setup Time Rise Time (Note Rise Time VACC (Note Voltage Transition Time (Note Write Pulse Width (Note Typ. Typ. Min. Min. Min. Min. Min. Typ. (Note1) (Note2) Unit
High During Toggle Polling High During Toggle Polling Read Recover Time Before Write Read Recover Time Before Write Setup Time Setup Time Hold Time Hold Time Write Pulse Width Pulse Width Write Pulse Width High Pulse Width High
(Continued)
MBM29DD640E 10/12
(Continued)
Parameter Symbols Description JEDEC Standard tOESP tCSP tFLQZ tFHQV tBUSY tEOE tTOW tSPD Setup Time Active (Note Setup Time Active (Note Recover Time From RY/BY RESET Pulse Width RESET High Level Period Before Read BYTE Switching Output High-Z BYTE Switching High Output Active Program/Erase Valid RY/BY Delay Delay Time from Embedded Output Enable Erase Time-out Time Erase Suspend Transition Time Power Time Min. Min. Min. Min. Min. Max. Max. Max. Max. Min. Max. Max. (Note1) (Note2) Unit
Notes: This does include preprogramming time. This timing Sector Group Protection operation. This timing Accelerated Program operation.
MBM29DD640E 10/12
ERASE PROGRAMMING PERFORMANCE
Limits Parameter Min. Sector Erase Time Word Programming Time Byte Programming Time Chip Programming Time Program/Erase Cycle 100,000 Typ. Max. cycles Excludes programming time prior erasure Excludes system-level overhead Excludes system-level overhead Unit Comments
TSOP(I) CAPACITANCE
Parameter Symbol COUT CIN2 CIN3 Parameter Description Input Capacitance Output Capacitance Control Capacitance WP/ACC Capacitance Test Setup VOUT Typ. T.B.D. T.B.D. T.B.D. T.B.D. Max. T.B.D. T.B.D. T.B.D. T.B.D. Unit
Note: Test conditions 25°C,
FBGA CAPACITANCE
Parameter Symbol COUT CIN2 CIN3 Parameter Description Input Capacitance Output Capacitance Control Capacitance WP/ACC Capacitance Test Setup VOUT Typ. T.B.D. T.B.D. T.B.D. T.B.D. Max. T.B.D. T.B.D. T.B.D. T.B.D. Unit
Note: Test conditions 25°C,
MBM29DD640E 10/12
SWITCHING WAVEFORMS
Switching Waveforms
WAVEFORM
INPUTS Must Steady Change from Change from Change Permitted Does Apply
OUTPUTS Will Steady Will Changing from Will Changing from Changing State Unknown Center Line HighImpedance "Off" State
Addresses
Addresses Stable
Outputs
High-Z
Output Valid
High-Z
Figure
Read Operation Timing Diagram
MBM29DD640E 10/12
Addresses
Addresses Stable
RESET
Outputs
High-Z
Output Valid
Figure
Hardware Reset/Read Operation Timing Diagram
RESET
Address
Valid Data
Data
Valid Data
Figure
Power Timing Diagram
MBM29DD640E 10/12
Cycle Addresses
555h
Data Polling
GHWL WHWH1
Data
Notes:
address memory location programmed. data programmed byte address. output complement data written device. DOUT output data written device. Figure indicates last cycles four cycle sequence. These waveforms mode. (The addresses differ from mode.)
Figure
Alternate Controlled Program Operation Timing Diagram
MBM29DD640E 10/12
Cycle
Data Polling
Addresses
555h
GHEL WHWH1
Data
Notes:
address memory location programmed. data programmed byte address. output complement data written device. DOUT output data written device. Figure indicates last cycles four cycle sequence. These waveforms mode. (The addresses differ from mode.)
Figure
Alternate Controlled Program Operation Timing Diagram
MBM29DD640E 10/12
Addresses
555h
2AAh
555h
555h
2AAh
GHWL
10h/
Data
sector address Sector Erase. Addresses 555h (Word), AAAh (Byte) Chip Erase. These waveforms mode. (The addresses differ from mode.)
Figure
Chip/Sector Erase Operation Timing Diagram
MBM29DD640E 10/12
Data Valid Data
High-Z
WHWH1
Data BUSY
Output Flag
Valid Data
High-Z
RY/BY
Valid Data (The device completed Embedded operation). Figure Data Polling during Embedded Algorithm Operation Timing Diagram
MBM29DD640E 10/12
Address
tAHT tASO tAHT
tCEPH
tOEH
tOEPH tOEH
DQ6/DQ2
Data
tBUSY
Toggle Data
Toggle Data
Toggle Data
Stop
Toggling
Output Valid
RY/BY
stops toggling (The device completed Embedded operation). Figure Toggle during Embedded Algorithm Operation Timing Diagram
MBM29DD640E 10/12
Read
Command
Read
Command
Read
Read
Address
(555h)
tACC
(PA)
tAHT
(PA)
tCEPH
tGHWL tOEH
Valid Output
Valid Intput (A0h)
Valid Output
Valid Intput (PD)
Valid Output
Status
Note: This example Read Bank Embedded Algorithm (program) Bank BA1: Address Bank BA2: Address Bank Figure Bank-to-Bank Read/Write Timing Diagram
Enter Embedded Erasing
Erase Suspend Erase
Enter Erase Suspend Program Erase Suspend Program
Erase Resume Erase Suspend Read Erase Erase Complete
Erase Suspend Read
Toggle with
Note: read from erase-suspended sector. Figure
MBM29DD640E 10/12
rising edge last write pulse
Entire programming erase operations
RY/BY
BUSY
Figure
RY/BY Timing Diagram during Program/Erase Operations
RESET
RY/BY
tREADY
Figure
RESET, RY/BY Timing Diagram
MBM29DD640E 10/12
BYTE
Data Output (DQ7 DQ0) tELFH tFHQV DQ15 Data Output (DQ14 DQ0)
DQ14
DQ15/A-1
Figure
Word Mode Configuration Timing Diagram
BYTE
tELFL
DQ14
Data Output (DQ14 DQ0) tACC
Data Output (DQ7 DQ0)
DQ15/A-1
DQ15 tFLQZ
Figure
Byte Mode Configuration Timing Diagram
falling edge last write signal
BYTE
tSET (tAS)
Input Valid
tHOLD (tAH)
Figure
BYTE Timing Diagram Write Operations
MBM29DD640E 10/12
A21, A20, A19, A17, A16, A15, A13,
SGAX
SGAY
VLHT
VLHT VLHT VLHT
OESP
Data
SGAX Sector Group Address initial sector SGAY Sector Group Address next sector Note: byte mode. Figure Sector Group Protection Timing Diagram
MBM29DD640E 10/12
tVCS RESET
tVIDR tVLHT
tVLHT RY/BY Unprotection period Program Erase Command Sequence tVLHT
Figure
Temporary Sector Group Unprotection Timing Diagram
MBM29DD640E 10/12
tVCS
RESET tVIDR
tVLHT SGAX SGAX SGAY
TIME-OUT
Data
SGAX Sector Group Address protected SGAY Next Sector Group Address protected TIME-OUT Time-Out window (min) Figure Extended Sector Group Protection Timing Diagram
MBM29DD640E 10/12
tVCS VACC WP/ACC
tVACCR tVLHT
tVLHT RY/BY Acceleration period Program Erase Command Sequence tVLHT
Figure
Accelerated Program Timing Diagram
MBM29DD640E 10/12
EMBEDDED ALGORITHMS
Start
Write Program Command Sequence (See below)
Data Polling Embedded Program Algorithm progress
Verify Byte
Increment Address
Last Address
Programming Completed
Program Command Sequence* (Address/Command):
555h/AAh
2AAh/55h
555h/A0h
Program Address/Program Data
sequence applied mode. addresses differ from mode.
Figure
Embedded ProgramAlgorithm
MBM29DD640E 10/12
EMBEDDED ALGORITHMS
Start
Write Erase Command Sequence (See below)
Data Polling Embedded Erase Algorithm progress
Data Erasure Completed
Chip Erase Command Sequence* (Address/Command): 555h/AAh
Individual Sector/Multiple Sector* Erase Command Sequence (Address/Command): 555h/AAh
2AAh/55h
2AAh/55h
555h/80h
555h/80h
555h/AAh
555h/AAh
2AAh/55h
2AAh/55h
555h/10h
Sector Address/30h
Sector Address/30h
Additional sector erase commands optional.
Sector Address/30h
sequence applied mode. addresses differ from mode.
Figure
Embedded EraseAlgorithm
MBM29DD640E 10/12
Start
Read Addr.
Data? Read Addr.
Byte address programming sector addresses within sector being erased during sector erase multiple sector erases operation sector addresses within sector being protected during chip erase
Data? Fail
Pass
Note: rechecked even because change simultaneously with DQ5.
Figure
Data Polling Algorithm
MBM29DD640E 10/12
Start
Read Addr. Read Addr.
Bank address being executed Embedded Algorithm.
(Note
Toggle Toggle?
Read Twice Addr. (Notes
Toggle Toggle? Program/Erase Operation Complete, Write Reset Command
Program/Erase Operation Complete
Notes: Read toggle twice determine whether toggling. Recheck toggle because stop toggling changes "1". Figure Toggle Algorithm
MBM29DD640E 10/12
Start Setup Sector Group Addr. (A21, A20, A19, A18, A17, A16, A15, A14, A13, A12)
PLSCNT
RESET
Activate Pulse
Increment PLSCNT
Time
should remain
Read from Sector Group (Addr. SGA, IL)* PLSCNT Remove from Write Reset Command Data 01h? Protect Another Sector Group Remove from Write Reset Command
Device Failed
Sector Group Protection Completed
byte mode.
Figure
Sector Group Protection Algorithm
MBM29DD640E 10/12
Start
RESET (Note
Perform Erase Program Operations
RESET
Temporary Sector Group Unprotection Completed (Note
Notes: protected sector groups unprotected. previously protected sector groups protected once again.
Figure
Temporary Sector Group Unprotection Algorithm
MBM29DD640E 10/12
Start
RESET
Wait
Device Operating Temporary Sector Group Unprotection Mode
Extended Sector Group Protection Entry? Setup Sector Group Protection Write XXXh/60h
PLSCNT
Sector Group Protection Write SGA/60h
Increment PLSCNT
Time Setup Next Sector Group Address
Verify Sector Group Protection Write SGA/40h Read from Sector Group Address IL)* PLSCNT Remove from RESET Write Reset Command Data 01h?
Protection Other Sector Group
Device Failed
Remove from RESET Write Reset Command
byte mode.
Sector Group Protection Completed
Figure
Extended Sector Group Protection Algorithm
MBM29DD640E 10/12
FAST MODE ALGORITHM
Start
555h/AAh
2AAh/55h
Fast Mode
555h/20h
XXXh/A0h
Program Address/Program Data
Data Polling
Verify Byte?
Fast Program
Increment Address
Last Address Programming Completed
(BA) XXXh/90h Reset Fast Mode XXXh/F0h
sequence applied mode. addresses differ from mode. Figure Embedded ProgramAlgorithm Fast Mode
MBM29DD640E 10/12
ORDERING INFORMATION
Standard Products
Fujitsu standard products available several packages. order number formed combination
MBM29DD640
PACKAGE TYPE 48-Pin Thin Small Outline Package (TSOP) Standard Pinout 48-Pin Thin Small Outline Package (TSOP) Reverse Pinout 63-Ball Fine pitch Ball Grid Array Package (FBGA) SPEED OPTION Product Selector Guide DEVICE REVISION
DEVICE NUMBER/DESCRIPTION MBM29DD640 64Mega-bit 8-Bit 16-Bit) CMOS Flash Memory V-only Read, Program, Erase
Valid Combinations
Valid Combinations Valid Combinations list configurations planned supported volume this device. Consult local Fujitsu sales office confirm availability specific valid combinations check newly released combinations.
MBM29DD640E
MBM29DD640E 10/12
PACKAGE DIMENSION
48-pin plastic TSOP(I) (FPT-48P-M19)
LEAD
Resin Protrusion. (Each Side: 0.15 (.006)Max)
INDEX
Details part 0.15(.006)
0.15(.006)
0.35(.014) 0.25(.010)
20.00±0.20 (.787±.008) 18.40±0.20 (.724±.008)
12.00±0.20 (.472±.008) 11.50REF (.460)
1.10 -0.05 +.004 .043 -.002
(Mounting height)
+0.10
0.10(.004)
0.50(.0197) 0.15±0.05 (.006±.002) 0.20±0.10 (.008±.004)
0.05(0.02)MIN STAND 0.10(.004)
19.00±0.20 (.748±.008)
0.50±0.10 (.020±.004)
1996 FUJITSU LIMITED F48029S-2C-2
Dimensions (inches)
48-pin plastic TSOP(I) (FPT-48P-M20)
LEAD
Resin Protrusion. (Each Side: 0.15 (.006)Max)
INDEX
Details part 0.15(.006)
0.15(.006)
0.35(.014) 0.25(.010)
19.00±0.20 (.748±.008)
0.50±0.10 (.020±.004) 0.15±0.10 (.006±.002) 0.20±0.10 (.008±.004) 0.10(.004)
0.10(.004)
0.50(.0197)
0.05(0.02)MIN STAND
18.40±0.20 (.724±.008) 20.00±0.20 (.787±.008)
11.50(.460)REF 12.00±0.20(.472±.008)
1.10 -0.05 +.004 .043 -.002
(Mounting height)
+0.10
1996 FUJITSU LIMITED F48030S-2C-2
Dimensions (inches)
(Continued)
MBM29DD640E 10/12
(Continued)
63-ball plastic FBGA (BGA-63P-M02)
+0.15 +.006
11.00±0.10(.433±.004)
1.05 -0.10
(8.80(.346)) (7.20(.283)) (5.60(.220)) 0.80(.031)TYP
.041 -.004 (Mounting height) 0.38±0.10 (.015±.004) (Stand off)
10.00±0.10 (.394±.004) (4.00(.157)) (5.60(.220))
INDEX AREA
INDEX BALL
0.08(.003)
0.10(.004)
1999 FUJITSU LIMITED B63002S-1C-1
MBM29DD640E 10/12
FUJITSU LIMITED
further information please contact:
Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-8588, Japan Tel: 81(44) 754-3763 Fax: 81(44) 754-3329
Rights Reserved. contents this document subject change without notice. Customers advised consult with FUJITSU sales representatives before ordering. information circuit diagrams this document presented examples semiconductor device applications, intended incorporated devices actual use. Also, FUJITSU unable assume responsibility infringement patent rights other rights third parties arising from this information circuit diagrams. FUJITSU semiconductor devices intended standard applications (computers, office automation other office equipment, industrial, communications, measurement equipment, personal household devices, etc.). CAUTION: Customers considering products special applications where failure abnormal operation directly affect human lives cause physical injury property damage, where extremely high levels reliability demanded (such aerospace systems, atomic energy controls, floor repeaters, vehicle operating controls, medical devices life support, etc.) requested consult with FUJITSU sales representatives before such use. company will responsible damages arising from such without prior approval. semiconductor devices have inherent chance failure. must protect against injury, damage loss from such failures incorporating safety design measures into your facility equipment such redundancy, fire protection, prevention over-current levels other abnormal operating conditions. products described this document represent goods technologies subject certain restrictions export under Foreign Exchange Foreign Trade Japan, prior authorization Japanese government will required export those products from Japan.
http://www.fujitsu.co.jp/
North South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street Jose, 95134-1804, Tel: (408) 922-9000 Fax: (408) 922-9179 Customer Response Center Mon. Fri.: (PST) Tel: (800) 866-8608 Fax: (408) 922-9179
http://www.fujitsumicro.com/
Europe FUJITSU MICROELECTRONICS EUROPE GmbH Siebenstein 6-10 D-63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122
http://www.fujitsu-ede.com/
Asia Pacific FUJITSU MICROELECTRONICS ASIA #05-08, Lorong Chuan Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220
http://www.fmap.com.sg/
F0104 FUJITSU LIMITED Printed Japan
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