September 2000 Revised March 2002 74LCXH162244 Voltage 16-Bit Buf

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September 2000 Revised March 2002 74LCXH162244 Voltage 16-Bit Buf

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74LCXH162244 Voltage 16-Bit Buffer/Line Driver with Bushold Series Resistors Outputs
September 2000 Revised March 2002
74LCXH162244 Voltage 16-Bit Buffer/Line Driver with Bushold Series Resistors Outputs
LCXH162244 contains sixteen non-inverting buffers with 3-STATE outputs designed employed memory address driver, clock driver, oriented transmitter/receiver. device nibble controlled. Each nibble separate 3-STATE control inputs which shorted together full 16-bit operation. LCXH162244 data inputs include active bushold circuitry, eliminating need external pull-up resistors hold unused floating data inputs valid logic level. addition, outputs include equivalent (nominal) series resistors reduce overshoot undershoot designed sink/source 3.0V. LCXH162244 designed voltage (2.5V 3.3V) applications with capability interfacing signal environment. LCXH162244 fabricated with advanced CMOS technology achieve high speed operation while maintaining CMOS power dissipation.
Features
tolerant control inputs outputs 2.3V-3.6V specifications provided Outputs include equivalent series resistance make external termination resistors unnecessary reduce overshoot undershoot Bushold data inputs eliminates need external pull-up/pull-down resistors (VCC 3.0V), Power down high impedance inputs outputs output drive (VCC 3.0V) Implements patented noise/EMI reduction circuitry Latch-up performance exceeds performance: Human body model 2000V Machine model 200V
Ordering Code:
Order Number 74LCXH162244MEA 74LCXH162244MEX 74LCXH162244MTD 74LCXH162244MTX Package Number MS48A MS48A MTD48 MTD48 Package Description 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide [RAIL] 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide [TAPE REEL] 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide [RAIL] 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide [TAPE REEL]
2002 Fairchild Semiconductor Corporation
DS500249
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74LCXH162244
Connection Diagram
Logic Symbol
Descriptions
Names I0-I15 O0-O15 Description Output Enable Input (Active LOW) Bushold Inputs Outputs
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74LCXH162244
Truth Tables
Inputs I0-I3 Outputs O0-O3 Inputs I8-I11 Outputs O8-O11
Inputs
HIGH Voltage Level Voltage Level
Outputs I4-I7 O4-O7
Inputs I12-I15
Outputs O12-O15
Immaterial High Impedance
Functional Description
LCXH162244 contains sixteen non-inverting buffers with 3-STATE standard outputs. LCXH162244 data inputs include active bushold circuitry eliminating need pull-up resistors hold unused floating data inputs valid logic level. devise also designed with series resistors outputs. This design reduces line noise applications such memory address drivers, clock drivers transceiver/transmitters. device nibble bits) controlled with each nibble functioning identically, independent other. control pins shorted together obtain full 16-bit operation. 3-STATE outputs controlled Output Enable (OEn) input each nibble. When LOW, outputs 2-state mode. When HIGH, outputs high impedance mode, this does interfere with entering data into inputs.
Logic Diagram
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74LCXH162244
Absolute Maximum Ratings(Note
Symbol IGND TSTG Parameter Supply Voltage Input Voltage Output Voltage Input Diode Current Output Diode Current Output Source/Sink Current Supply Current Supply Ground Current Ground Storage Temperature Value Conditions Units Output 3-STATE Output HIGH State (Note
-0.5 +7.0 -0.5 +7.0 -0.5 -0.5 +7.0 -0.5 ±100 ±100 +150
Recommended Operating Conditions (Note
Symbol IOH/IOL Supply Voltage Input Voltage Output Voltage Output Current HIGH State 3-STATE 3.0V 3.6V 2.7V 3.0V 2.3V 2.7V Free-Air Operating Temperature Input Edge Rate, 0.8V-2.0V, 3.0V Parameter Operating Data Retention Units
ns/V
Note Absolute Maximum Ratings those values beyond which safety device cannot guaranteed. device should operated these limits. parametric values defined Electrical Characteristics tables guaranteed Absolute Maximum Ratings. "Recommended Operating Conditions" table will define conditions actual device operation. Note Absolute Maximum Rating must observed. Note Unused control inputs must held HIGH LOW. They float.
Electrical Characteristics
Symbol Parameter HIGH Level Input Voltage Level Input Voltage HIGH Level Output Voltage -100 Level Output Voltage Conditions 0.55 -40°C +85°C Units
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74LCXH162244
Electrical Characteristics
Symbol II(HOLD) Parameter Input Leakage Current Bushold Input Minimum Drive Hold Current Data Control
(Continued)
-300 -450 ±5.0 -40°C +85°C ±5.0 ±5.0
Conditions 0.7V 1.7V 0.8V 2.0V
Units
II(OD)
Bushold Input Over-Drive Current Change State
(Note (Note (Note (Note
IOFF
3-STATE Output Leakage Power-Off Leakage Current Quiescent Supply Current Increase Input
5.5V 5.5V -0.6V
Note external driver must source least specified current switch from LOW-to-HIGH. Note external driver must sink least specified current switch from HIGH-to-LOW.
Electrical Characteristics
-40°C +85°C, Symbol Parameter 3.3V 0.3V tPHL tPLH tPZL tPZH tPLZ tPHZ tOSHL tOSLH Output Output Skew (Note Output Disable Time Propagation Delay Data Output Output Enable Time 2.7V 2.5V 0.2V Units
Note Skew defined absolute value difference between actual propagation delay separate outputs same device. specification applies outputs switching same direction, either HIGH-to-LOW (tOSHL) LOW-to-HIGH (tOSLH). Parameter guaranteed design.
Dynamic Switching Characteristics
Symbol VOLP VOLV Parameter Quiet Output Dynamic Peak Quiet Output Dynamic Valley Conditions 3.3V, 2.5V, 3.3V, 2.5V, 25°C Typical 0.35 0.25 -0.35 -0.25 Units
Capacitance
Symbol COUT Input Capacitance Output Capacitance Power Dissipation Capacitance Parameter Conditions Open, 3.3V, 3.3V, VCC, Typical Units
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74LCXH162244
LOADING WAVEFORMS Generic Family
FIGURE Test Circuit includes probe capacitance) 3.3V, 2.7V 2.5V
Waveform Inverting Non-Inverting Functions
3-STATE Output High Enable Disable Times Logic
Propagation Delay. Pulse Width trec Waveforms
Setup Time, Hold Time Recovery Time Logic
3-STATE Output Enable Disable Times Logic FIGURE Waveforms (Input Characteristics; =1MHz, 3ns) Symbol 3.3V 0.3V 1.5V 1.5V 0.3V 0.3V 1.5V 1.5V 0.3V 0.3V 2.7V
trise tfall
2.5V 0.2V VCC/2 VCC/2 0.15V 0.15V
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74LCXH162244
Schematic Diagram Generic LCXH Family
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74LCXH162244
Physical Dimensions inches (millimeters) unless otherwise noted
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Package Number MS48A
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74LCXH162244 Voltage 16-Bit Buffer/Line Driver with Bushold Series Resistors Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD48 Fairchild does assume responsibility circuitry described, circuit patent licenses implied Fairchild reserves right time without notice change said circuitry specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS AUTHORIZED CRITICAL COMPONENTS LIFE SUPPORT DEVICES SYSTEMS WITHOUT EXPRESS WRITTEN APPROVAL PRESIDENT FAIRCHILD SEMICONDUCTOR CORPORATION. used herein: Life support devices systems devices systems which, intended surgical implant into body, support sustain life, whose failure perform when properly used accordance with instructions provided labeling, reasonably expected result significant injury user. critical component component life support device system whose failure perform reasonably expected cause failure life support device system, affect safety effectiveness. www.fairchildsemi.com
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September 2000 Revised March 2002 74LCXH162244 Voltage 16-Bit Buf

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