September 1999, ver. 1.01 Introduction Altera's APEX20K devi
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Gate Counting Methodology APEX Devices
September 1999, ver. 1.01
Introduction
Altera's APEX20K device family offers innovative combination look-up table (LUT) logic, product-term logic, embedded memory. Ranging from 162,000 2,500,000 maximum system gates, revolutionary APEX architecture offers allowing designers combine functions best suited LUT, product-term logic, memory into device. architecture used implement register-intensive data path arithmetic functions. Product-term logic used high fan-in combinatorial functions high speeds. APEX programmable logic devices (PLDs) first devices combine these architectures provide performance, flexibility, efficiency that designers require. This application note describes gate counting method used APEX device family defines gate counting terminology. shows logic array embedded array gates calculated. APEX gates compared gate array gates, using Logic's LCA300K family standard "sea-of-gates" gate arrays reference.
Gate Count Specifications
Feature
Typical Gates Maximum System Gates Logic Elements (LEs) Embedded System Blocks Maximum Bits Maximum Macrocells Maximum Pins
Tables show features, including gate count specifications, APEX devices.
Table APEX Device Features
EP20K60E
60,000 162,000 2,560 32,768
Note
EP20K100E EP20K100
100,000 263,000 4,160 53,248
EP20K160E
160,000 404,000 6,400 81,920
EP20K200E EP20K200
200,000 526,000 8,320 106,496
EP20K300E
300,000 728,000 11,520 147,456 1,152
Altera Corporation
A-AN-110-01.01
110: Gate Counting Methodology APEX Devices
Table APEX Device Features
Feature
Typical Gates Maximum System Gates Logic Elements Embedded System Blocks Maximum Bits Maximum Macrocells Maximum Pins Note tables:
Note
EP20K600E
600,000 1,537,000 24,320 311,296 2,432
EP20K400E EP20K400
400,000 1,052,000 16,640 212,992 1,664
EP20K1000E
1,000,000 1,770,000 38,400 327,680 2,560
EP20K1500E
1,500,000 2,500,000 54,720 466,944 3,648
designs that require IEEE Std. 1149.1 Joint Test Action Group (JTAG) boundary-scan testing, built-in JTAG circuitry contributes 52,130 additional gates.
Table explains terminology used describe APEX device features.
Table APEX Device Terminology (Part
Designation
Logic Elements
Description
Logic elements basic logic building blocks that make logic array APEX architecture. Each consists four-input LUT, programmable flipflop, dedicated signal paths carry cascade functions. logic array performs same function sea-of-gates gate array; used implement general logic such counters, adders, state machines, multiplexers. Logic array gates total number usable gates available logic array device.
Logic Array
Logic Array Gates
Logic Array Blocks (LABs) logic array consists LABs. Each contains local interconnect. used create medium-sized blocks logic-such 10-bit counters, address decoders, state machines-or combined across LABs create larger logic blocks. Embedded System Blocks Embedded system blocks used create RAM, ROM, first-in first-out (FIFO), (ESBs) dual-port RAM, content-addressable memory (CAM) functions. ESBs also implement complex logic functions such digital signal processing (DSP), microcontroller, wide data-path manipulation, data transformation functions. ESBs implement logic either LUTs product terms. Array Gates Product Term array gates total number gates available embedded array. product term wide gate. These gates combined into macrocells when implements product-term logic.
110: Gate Counting Methodology APEX Devices
Table APEX Device Terminology (Part
Designation
Maximum Macrocells Maximum Bits Typical Gate Count
Description
Maximum macrocells number available macrocells when ESBs used entirely product-term logic. Maximum bits number bits available when ESBs used entirely memory functions. Typical gate count capacity metric indicating gate array size that implemented APEX device. Typical gate count assumes that design uses logic array embedded array. also assumes that portions embedded array used both memory logic functions. Maximum system gate count number gates when 100% ESBs used memory. This measurement approximates gate counting method used field-programmable gate array (FPGA) vendors when determining "system gates".
Maximum System Gate Count
Calculating Logic Array Gates
Before calculating total number logic array gates, must first determine gate count. ways calculate logic array gates compare with standard gate arrays empirical data calculating logic array gates. example, APEX gate range determined using LCA300K Data Book comparing implementation various functions versus LCA300K family standard gate arrays. find gate range, calculate number gates simple complex function. simple function determines lower bound, complex function determines higher bound range. register used implement each function. Table
Table Calculating Gates Using LCA300K Functions
Implementation
Simple LCA300K function
APEX
Two-input gate
APEX Register Total Gates Gates
D-type flipflop D-type flipflop with clear, preset, clock enable signals
Complex LCA300K Four-input function gate
110: Gate Counting Methodology APEX Devices
gate range total number gates used simple functions total number gates used complex functions. this case, eight gates used simple functions gates used complex functions. APEX gate equivalents also calculated with empirical data. Altera compiled over designs targeted towards four-input technology, applying same designs LCA300K gate arrays using Synopsys Design Compiler. comparison between LCA300K gate count usage usage yields average gates device's logic array gate count determined multiplying number gates with count. example, EP20K1000E device 38,400 LEs; gates EP20K1000E device approximately 460,000 logic array gates.
Calculating Embedded Array Gates
embedded array contains ESBs, which extremely efficient creating memory functions that configured on-the-fly. APEX devices implement Kbits memory each ESB. addition, designers combine ESBs achieve higher counts. APEX ESBs have capacity speed implement high-end memory blocks. Because ESBs dedicated architectural elements, they require resource trade-offs. ESBs also used implement logic functions LUTs with product-term logic.
Memory Gate Count
Gate counting schemes memory functions vary depending type RAM, vendor, architecture. Because most memory functions average four gates memory bit, APEX family uses same standard, allowing designers easily compare different gatecounting schemes different devices. array gate count also verified using common LCA300K memory functions. Altera compiled various memory functions using memory compiler determine gate counts compare implementations.
110: Gate Counting Methodology APEX Devices
Table shows number gates used each memory function.
Table Calculating Array Gates Using LCA300K Memory Functions
Memory Function
single-port SRAM single-port SRAM single-port SRAM dual-port SRAM dual-port SRAM
Gates
4,620 7,980 14,700 8,300 14,910
Gates
average number gates Table 3.94, indicating that four gates good metric memory functions. APEX device, maximum number array gates determined multiplying number ESBs device with number bits number gates bit. example, following equation shows calculate maximum embedded system gates used memory implementations EP20K1000E device: ESBs 2,048 bits gates 1,310,720 gates EP20K1000E device approximately 1,300,000 array gates. ESBs implement logic product terms LUTs. When implementing product-term functions, becomes macrocells, each which contain product terms register. also implement logic when preprogrammed with pattern. example, implement ROM, which seven address inputs data outputs. When programmed ROM, implement logic with seven inputs outputs, effectively becoming seven-input LUTs with registered inputs outputs.
110: Gate Counting Methodology APEX Devices
Product-Term Logic Gate Count
range gates implemented product-term mode determined simple complex functions adding number LCA300K gate equivalents each macrocell register. Table
Table Calculating Embedded System Product-Term Gates Using LCA300K Functions
Implementation
Simple LCA300K function
Macrocells
Two-input gate
Gates
Registers
D-type flipflop D-type flipflop
Total Gates
Complex LCA300K 16-input function gates plus twoinput gates
product-term gate range total number gates used simple functions total number gates used complex functions. this case, gates used simple functions gates used complex functions.
Look-Up Table Logic Gate Count
range gates implemented logic determined simple complex functions adding number LUTs register gate equivalents. Table
Table Calculating Embedded System Gates Using LCA300K Functions
Implementation
Simple LCA300K function
7-Input LUTs
Two-input gate
Gates
Registers
D-type flipflop D-type flipflop with clear signal
Total Gates
Complex LCA300K Seven-input function gate
110: Gate Counting Methodology APEX Devices
gate count determined logic gate count product-term logic gate count. APEX implement gates logic, depending function type logic used function. estimating device gate count, able implement gates. APEX device, array gate count determined multiplying number ESBs with number gates ESB. following calculation shows determine number embedded array gates used logic EP20K1000E device: ESBs gates 20,480 gates EP20K1000E device approximately 20,500 embedded array gates when ESBs used logic functions
Calculating System Gates
factor determining gate count amount memory used design. determine maximum system gate count EP20K1000E device, gate count gate count. ESBs being used implement both logic memory, percentage ESBs that implement each function must figure into gate count computation. Table shows system gate calculation method EP20K1000E device which gates implemented memory.
Table Calculating Maximum System Gate Count EP20K1000E Device
Gates
gates gates used memory gates used logic
Gates Percentage
460,800 100% 1,310,720 100% 20,480
Total Gates
460,800 1,310,720
determine maximum system gate count, gate totals added together.
Conclusion
APEX gate counting methodology based comparisons with Logic LCA300K family empirical data. APEX architecture contains embedded array, which implements variety memory complex logic functions, logic array that implements general logic functions. combination embedded system logic arrays provides high performance integrated System-on-aProgrammable-Chip applications.
110: Gate Counting Methodology APEX Devices
Revision History
information contained Application Note (Gate Counting Methodology APEX Devices) version 1.01 supersedes information published previous versions. Version 1.01 contains following changes:
Updated system gate count "Introduction" page Added information EP20K60E EP20K1500E devices Updated Tables Minor textual changes throughout document
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Altera, APEX, APEX 20K, System-on-a-Programmable-Chip, EP20K60E, EP20K100, EP20K100E, EP20K160E, EP20K200, EP20K200E, EP20K300E, EP20K400, EP20K400E, EP20K600E, EP20K1000E, EP20K1500E, FLEX, FLEX 6000, MegaLAB trademarks and/or service marks Altera Corporation United States other countries. Altera acknowledges trademarks other organizations their respective products services mentioned this document, specifically: LCA300K registered trademarks Logic Corporation. Altera products protected under numerous U.S. foreign patents pending applications, maskwork rights, copyrights. Altera warrants performance semiconductor products current specifications accordance with Altera's standard warranty, reserves right make changes products services time without notice. Altera assumes responsibility liability arising application information, product, service described herein except expressly agreed writing Altera Corporation. Altera customers advised obtain latest version device specifications before relying published information before placing orders products services. Copyright 1999 Altera Corporation. rights reserved.
Altera Corporation
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