MODIOSoundComm®* Host Signal Processing Codec AD1821 V.42/42bis D
|
|
|
Top Searches for this datasheet
FEATURES General Compatible with Microsoft® Logo Requirements Supports Applications Written Windows® Windows 3.1, Windows SoundBlaster® Pro, AdLib®/OPL3® Plug Play Compatible Operation from Supply Power Management Modes 100-Lead PQFP Package Modem V.34bis (14.4 kbps 33.6 kbps) Software Upgradable V.32/32bis, V.23, V.22/22bis, V.21, Bell Bell Modem Protocols: Automode
MODIOSoundComm®* Host Signal Processing Codec AD1821
V.42/42bis Data Compression V.43 Error Correction Virtual Port 460.8 kbps 16550 UART Hayes Command Group Class Support V.17 (14.4 kbps), V.29 (9600/7200 bps), V.27/V.27ter Hayes Command TIES Escape Sequence Voice/Telephony AT#V Commands Unimodem TAPI-Compliant Voice/Fax/Modem Distinction Ring Detection
FUNCTIONAL BLOCK DIAGRAM
MIDI_IN DATA MIDI_OUT VOL_DN VOL_UP XIRQ
AD1821
HARDWARE VOLUME CONTROL
MODEM/ LOGICAL DEVICE CONTROL
E2PROM CONTROL
WSS/ REGISTER
MPU-401
GAME PORT
LINE
0dB/ 20dB
MDM_IN/ PHONE_IN
16-BIT CONVERTER
FIFO
FORMAT
SYNTH
PLUG PLAY PARALLEL INTERFACE
SELECTOR
SERIAL PORT
PC_D (7:0) PC_A (15:0) DACK
MUSIC SYNTHESIZER
L_OUT PHONE_OUT MDM_OUT/ R_OUT
PHATSTEREO
FIFO
FORMAT
PHATSTEREO
16-BIT CONVERTER
SERIAL PORT
BCLK LRCLK SDATA BCLK LRCLK SDATA
GAIN ATTENUATE MUTE MASTER VOLUME SERIAL PORT INTERFACE SERIAL PORT
OSCILLATORS
DIGITAL
PCLKO
XTALO
XTALI
*SoundComm registered trademark Analog Devices, Inc. *Phat trademark Analog Devices, Inc. other trademarks property their respective holders.
REV.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices. Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 617/329-4700 World Wide Site: http://www.analog.com Fax: 617/326-8703 Analog Devices, Inc., 1997
SDFS
SCLK
AD1821
On/Off Hook Control Call Progress Monitor DTMF Detection Generation Auto Dial Call Forwarding Conferencing (Voice Detection) ADPCM kpbs Voice Compression) Caller Full-Duplex Speakerphone Handset Record Playback Handset On/Off Detection DSVD Software Upgradeable Audio Stereo Audio 16-Bit Codec V.34 Class Modem Analog Front Full-Duplex Capture Playback Operation Different Sample Rates Internal Circuit-PhatTM* Stereo Phase Expander Integrated OPL3-Compatible Music Synthesizer Software Hardware Volume Control PRODUCT OVERVIEW
AD1821 MODIO(Modem over Audio) SoundComm® (Host Signal Processing) Codec single-chip audio communications subsystem personal computers. AD1821 solution includes AD1821 mixed-signal controller controller MODIOhost signal processing software drivers. AD1821 maintains full legacy compatibility with applications written SoundBlaster AdLib, while servicing Microsoft application requirements. AD1821 includes internal OPL3 compatible music synthesizer, PhatStereo circuitry phase expanding analog stereo output, MPU-401 UART joystick interface with built-in timer, serial port Serial ports. MODIOdrivers utilize resources implement high speed fax, data, voice (with Echo Cancellation) communications maintain audio compatibility. drivers enable simultaneous execution communications audio with data flowing through AD1821, provide graceful degradation modem performance host load changes. AD1821 on-chip Plug Play routine provides configuration services integrated logical devices.
TABLE CONTENTS
FEATURES PRODUCT OVERVIEW SPECIFICATIONS CONFIGURATION FUNCTION DESCRIPTIONS HOST INTERFACE REFERENCES SERIAL INTERFACES INTERFACE AD1821 Chip Registers AD1821 Plug Play Device Configuration Registers Sound System Direct Registers Sound System Indirect Registers Pro; AdLib Registers MIDI MPU-401 Registers Game Port Register APPENDIX AD1821JS AD1821JS-M AD1821JS PLUG PLAY INTERNAL AD1821JS-M PLUG PLAY INTERNAL APPENDIX PLUG PLAY "ALTERNATE KEY" SEQUENCES PROGRAMMING EXTERNAL EEPROMS REFERENCE DESIGNS DEVICE DRIVERS OUTLINE DIMENSIONS
Figures
Functional Block Diagram Figure Read Cycle Figure Write Cycle Figure Read Cycle Figure Write Cycle Figure Codec Transfers Figure Port Timing Figure Serial Port Timing Figure Reset Pulse Width Figure Serial Interface Right-Justified Mode Figure Serial Interface I2S-Justified Mode Figure Serial Interface Left-Justified Mode Figure Serial Interface (Default Frame Rate) Figure Serial Interface (User Programmed Frame Rate) Figure Serial Port Figure Codec Transfers Figure AD1821 Frequency Response Plots
Tables
Table Port Time Slot Table Chip Register Diagram Table III. Logical Devices Compatible Plug Play Device Drivers Table Logical Device Configuration Table Sound System Direct Registers Table Codec Transfers Table VII. Indirect Register Reset/Default States Table VIII. Sound System Indirect Registers Table SoundBlaster Registers Table AdLib Registers Table MIDI Registers Table XII. Game Port Registers
REV.
AD1821
SPECIFICATIONS
STANDARD TEST CONDITIONS UNLESS OTHERWISE NOTED
Temperature Digital Supply (VDD) Analog Supply (VCC) Sample Rate (FS) Input Signal Frequency Audio Output Passband
1008
Test Conditions Attenuation Input Full Scale 16-Bit Linear Mode Output Load Mute Measured Line Output Test Conditions Gain Input Relative Full Scale Line Input Selected 16-Bit Linear Mode
ANALOG INPUT
Parameter Full-Scale Input Voltage (RMS Values Assume Sine Wave Input) PHONE_IN, LINE, SYNTH, VID, MDM_IN with Gain (MGE with Gain (MGE Input Impedance* Input Capacitance*
PROGRAMMABLE GAIN AMPLIFIER-ADC
2.83 0.283 2.83
Units
Parameter Step Size 22.5 (All Steps Tested) Gain Range Span
22.5
Units
LINE, MICROPHONE, MODEM, SYNTHESIZER, VIDEO INPUT ANALOG GAIN/AMPLIFIERS, ATTENUATORS/ MUTE
Parameter LINE, MIC, SYNTH, VID, MDM_IN Step Size: (All Steps Tested) -34.5 Input Gain/Attenuation Range PHONE_IN Step Size (All Steps Tested) Input Gain/Attenuation Range
Units
46.5
REV.
AD1821
DIGITAL DECIMATION INTERPOLATION FILTERS*
Parameter Audio Passband Audio Passband Ripple Audio Transition Band Audio Stopband Audio Stopband Rejection Audio Group Delay Group Delay Variation Over Passband
ANALOG-TO-DIGITAL CONVERTERS
0.09 12/FS
Units
Parameter Resolution Signal-to-Noise Ratio (SNR) (A-Weighted, Referenced Full Scale) Total Harmonic Distortion (THD) (Referenced Full Scale) Audio Dynamic Range (-60 Input THD+N Referenced Full-Scale, A-Weighted) Audio THD+N (Referenced Full-Scale) Signal-to-Intermodulation Distortion* (CCIF Method) Crosstalk* Line Inputs (Input Ground Read Input Ground Read Line (Input LINE, Ground Select MIC, Read ADC) Line SYNTH Line Line Gain Error (Full-Scale Span Relative Nominal Input Voltage) Interchannel Gain Mismatch (Difference Gain Errors) Offset Error
DIGITAL-TO-ANALOG CONVERTERS
0.011
0.015 -76.5
Units Bits
0.019 -74.5
Parameter Resolution Signal-to-Noise Ratio (SNR) (A-Weighted) Total Harmonic Distortion (THD) Audio Dynamic Range (-60 Input THD+N Referenced Full Scale, A-Weighted) Audio THD+N (Referenced Full Scale) Signal-to-Intermodulation Distortion* (CCIF Method) Gain Error (Full-Scale Span Relative Nominal Input Voltage) Interchannel Gain Mismatch (Difference Gain Errors) Crosstalk* (Input Zero Measure R_OUT; Input Zero Measure L_OUT) Total Out-of-Band Energy (Measured from L_OUT R_OUT)* Audible Out-of-Band Energy (Measured from L_OUT R_OUT)*
0.006
0.009 -80.5
Units Bits
0.013
0.017 -75.5
MASTER VOLUME ATTENUATORS (L_OUT R_OUT, PHONE_OUT)
Parameter Master Volume Step Size -43.5 Master Volume Step Size (-43.5 -46.5 Master Volume Output Attenuation Range Span Mute Attenuation Fundamental*
46.5
Units REV.
AD1821
DIGITAL ATTENUATORS*
Parameter Step Size: (0), (1), Music, Digital Attenuation Range Span
ANALOG OUTPUT
1.505 94.8
Units
Parameter Full-Scale Output Voltage L_OUT, R_OUT, PHONE_OUT Output Impedance* External Load Impedance* Output Capacitance* External Load Capacitance VREFX* VREFX Current Drive* VREFX Output Impedance* Mute Click (Muted Analog Mixers), Muted Output Minus Unmuted Output
SYSTEM SPECIFICATIONS*
Units
2.10 2.25 2.40
Parameter System Frequency Response Ripple (Line Line Out) Differential Nonlinearity Phase Linearity Deviation
STATIC DIGITAL SPECIFICATIONS
Units Degrees
Parameter High Level Input Voltage (VIH) XTALI Level Input Voltage (VIL) High Level Output Voltage (VOH), Level Output Voltage (VOL), Input Leakage Current Output Leakage Current
POWER SUPPLY
Units
Parameter Power Supply Range-Analog Power Supply Range-Digital Power Supply Current Power Dissipation Analog Supply Current Digital Supply Current Analog Power Supply Current-Power-Down Digital Power Supply Current-Power-Down Analog Power Supply Current-RESET Digital Power Supply Current-RESET Power Supply Rejection (100 Signal kHz)* Both Analog Digital Supply Pins, Both ADCs DACs)
CLOCK SPECIFICATIONS*
4.75 4.75
5.25 5.25 1105
Units
Parameter Input Clock Frequency Recommended Clock Duty Cycle Power-Up Initialization Time REV.
Units
AD1821
TIMING PARAMETERS (Guaranteed Over Operating Temperature Range)
Parameter IOW/IOR Strobe Width IOW/IOR Rising IOW/IOR Falling Write Data Setup Rising Falling Valid Read Data Setup IOW/IOR Falling Hold from IOW/IOR Rising Setup IOW/IOR Falling Hold from IOW/IOR Rising DACK Rising IOW/IOR Falling Data Hold from Rising Data Hold from Rising Hold from IOW/IOR Falling DACK Hold from IOW/IOR Rising Data [SDI] Input Setup Time SCLK* Data [SDI] Input Hold Time from SCLK* Frame Sync [SDFS] Pulse Width* Clock [SCLK] Frame Sync [SDFS] Propagation Delay* Clock [SCLK] Output Data [SDO] Valid* RESET Pulse Width BCLK Pulse Width BCLK Pulse Width BCLK Period LRCLK Setup SDATA Setup SDATA Hold
Symbol tSTW tBWDN tWDSU tRDDV tAESU tAEHD tADSU tADHD tDKSU tDHD1 tDHD2 tDRHD tDKHD tFSW tRPWL tDBH tDBL tDBP tDLS tDDS tDDH
Units
NOTES *Guaranteed, tested. (All pins MIDI_OUT Refer description individual output drive levels. Specifications subject change without notice.
tDKSU
DACK
tDKHD
DACK
tDKSU
tDKHD
tAESU
tAEHD
tAESU
tAEHD
tSTW
tSTW
tRDDV
PC_D [7:0]
tDHD1
tWDSU tDHD2
tADSU tADHD
PC_A [15:0]
PC_D [7:0]
tADSU tADHD
PC_A [15:0]
Figure Read Cycle
Figure Write Cycle
REV.
AD1821
tDKSU
DACK
tDRHD
tDKHD
SCLK
tFSW
SDFS
tAESU
tAEHD
tSTW
tRDDV
PC_D [7:0]
tDHD1
Figure Port Timing Figure Read Cycle
tDBH
BCLK
tDBP
tDKSU
DACK
tDRHD tDKHD
LRCLK
tDBL tDLS
tAESU
tAEHD
SDATA LEFT-JUSTIFIED MODE
tDDS
MSB-1
tSTW
SDATA S-JUSTIFIED MODE
tDDH tDDS
tWDSU
PC_D [7:0]
tDDS tDDH
tDDS
tDHD2
SDATA RIGHT-JUSTIFIED MODE
tDDH
tDDH
Figure Write Cycle
Figure Serial Port Timing
tBWDN
IOR/
tRPWL
RESET
DATA [7:0]
BYTE
Figure Reset Pulse Width Figure Codec Transfers
REV.
AD1821
ABSOLUTE MAXIMUM RATINGS* ENVIRONMENTAL CONDITIONS
Parameter Power Supplies Digital (VDD) Analog (VCC) Input Current (Except Supply Pins) Analog Input Voltage (Signal Pins) Digital Input Voltage (Signal Pins) Ambient Temperature (Operating) Storage Temperature
-0.3 -0.3 -0.3 -0.3
10.0 +150
Units
Ambient Temperature Rating: TAMB TCASE TCASE Case Temperature Power Dissipation Thermal Resistance (Case-to-Ambient) Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Package PQFP
77°C/W
7°C/W
70°C/W
*Stresses greater than those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only; functional operation device these other conditions above those indicated operational section this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
ORDERING GUIDE
Model AD1821JS AD1821JS-M
Temperature Range +70°C +70°C
Package Description 100-Lead PQFP 100-Lead PQFP
Function Description Audio/Modem Modem
Package Option* S-100 S-100
Plastic Quad Flatpack.
CAUTION (electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although AD1821 features proprietary protection circuitry, permanent damage occur devices subjected high energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality. AD1821 latchup immunity been demonstrated +100 mA/-80 pins when tested Industry Standard/JEDEC methods.
WARNING!
SENSITIVE DEVICE
REV.
AD1821
CONFIGURATION
100-Lead PQFP (S-100)
I2S1_LRCLK/MDM_SEL/IRQ (12)/IRQ (13) SPORT_SDO/LD_DACK/VOL_DN/GND
SPORT_SDI/LD_IRQ/VOL_DN/GND
SPORT_SDFS/LD_DRQ/VOL_UP
SPORT_SCLK/LD_SEL/NC
I2S0_DATA/VOL_UP I2S0_LRCLK/VOL_DN I2S0_BCLK/GND PC_A (15) PC_A (14) PC_A (13) PC_A (12) PC_A (11) PC_A (10)
IDENTIFIER
I2S1_DATA/IRQ (3)/IRQ
(9)/IRQ (14) (10)/IRQ (11)/IRQ (9)/IRQ (15)/IRQ (11) XCTL1/RING/LD_SEL1 XCTL0/PCLKO/PNPRST MIDI_OUT MIDI_IN XTALO XTALI DACK DACK DACK EE_CLK EE_DATA
PC_A PC_A PC_A PC_A PC_A PC_A PC_A PC_A PC_A PC_A
AD1821
VIEW (Not Scale)
RESET RX3D CX3D PHONE_OUT MDM_OUT/R_OUT L_OUT
GNDA VREF
L_FILT
R_FILT
R_AAFILT
L_AAFILT
VREF_X
R_LINE
L_LINE
MDM_IN/PHONE_IN
R_SYNTH
L_VID
L_SYNTH
R_VID
R_CD
L_CD
I2S1_BCLK/MDM_IRQ
PC_D
PC_D
PC_D
PC_D
PC_D
PC_D
PC_D
PC_D
CONNECT
REV.
AD1821
FUNCTION DESCRIPTIONS Analog Signals
Name
PQFP
Description Microphone Input. input either line-level from line-level (the difference being made through software controlled gain block). mono input sent left right channel conversion, gained/ attenuated from -34.5 steps then summed with left right line before Master Volume stage. Left Line-Level Input. left line-level input sent left channel ADC; gained/attenuated from -34.5 steps then summed with left line OUT. Right Line-Level Input. right line-level input sent right channel ADC; gained/attenuated from -34.5 steps then summed with right line OUT. Left Synthesizer Input. left MIDI upgrade line-level input sent left channel ADC; gained/attenuated from -34.5 steps then summed with left line OUT. Right Synthesizer Input. right MIDI upgrade line-level input sent right channel ADC; gained/attenuated from -34.5 steps then summed with right line OUT. Left Line-Level Input. left line-level input sent left channel ADC; gained/attenuated from -34.5 steps then summed with left line OUT. Right Line-Level Input. right line-level input sent right channel ADC; gained/attenuated from -34.5 steps then summed with right line OUT. Left Video Input. left audio track video line-level input sent left channel ADC; gained/attenuated from -34.5 steps then summed with left line OUT. Right Video Input. right audio track video line-level input sent right channel ADC; gained/attenuated from -34.5 steps then summed with right line OUT. Left Output. Left channel line-level post-mixed output. final stage passes through Master Volume block attenuated steps. Modem Output/Right Output. Right channel line-level post-mixed output. final stage passes through Master Volume block attenuated steps. Modem Input/Phone Input. Line-level input from DAA/modem chipset. Phone Output. Line-level output from DAA/modem chipset. PhatTM* Stereo Phase Expander filter network, resistor pin. PhatTM* Stereo Phase Expander filter network, capacitor pin.
L_LINE
R_LINE
L_SYNTH
R_SYNTH
L_CD
R_CD
L_VID
R_VID
L_OUT MDM_OUT/ R_OUT MDM_IN/ PHONE_IN PHONE_OUT RX3D CX3D
-10-
REV.
AD1821
Parallel Interface (All Outputs Drivers)
Name PC_D[7:0] IRQ(x)*
PQFP 85-88, 91-94 75-81,
83-86, 89-92
Description Bidirectional Data, drive. Connects AD1821 byte data bus. Host Interrupt Request, drive. (3)/IRQ (9), IRQ(5), IRQ(7), IRQ(9)/IRQ (14), IRQ(10)/IRQ(4), IRQ(11)/IRQ (9)/IRQ (4), IRQ(12)/ IRQ(13), IRQ(15)/IRQ (11). Active signals indicating pending interrupt. Request, drive. DRQ(0), DRQ(1), DRQ(3). Active signals indicating request operation. Address. Connects AD1821 address lines. Address Enable. signal indicates transfer. Acknowledge. DACK(0), DACK(1), DACK(3). Active signal indicating that operation begin. Read. Active signal indicates read operation. Write. Active signal indicates write operation. Reset. Active
DRQ(x) PC_A[15:0] DACK RESET
Game Port
72-74 4-19 59-61
Name
PQFP
Description Game Port Button Game Port Button Game Port X-Axis. Game Port Y-Axis. Game Port Button Game Port Button Game Port X-Axis. Game Port Y-Axis.
MIDI Interface Signal Drivers)
Name MIDI_IN MIDI_OUT
PQFP
Description MIDI Input. This typically connected game port connector. MIDI Output. This typically connected game port connector.
REV.
-11-
AD1821
Muxed Serial Ports Drivers)
Name I2S(0)_BCLK* I2S(0)_LRCLK* I2S(0)_DATA* I2S(1)_BCLK* I2S(1)_LRCLK* I2S(1)_DATA* SPORT_SDI* SPORT_SCLK* SPORT_SDFS* SPORT_SDO*
Miscellaneous Analog Pins
PQFP
Description Clock. Left/Right Clock. Serial Data Input. Clock. Left/Right Clock. Serial Data Input. Serial Port Digital Serial Input. Serial Port Serial Clock. Serial Port Serial Data Frame Synchronization. Serial Port Serial Data Output.
Name VREF_X
PQFP
Description Voltage Reference. Nominal 2.25 volt reference available dc-coupling level-shifting. VREF_X should used sink source signal current. Voltage Reference Filter. Voltage reference filter point external bypassing only. Left Channel Filter. Requires analog ground proper operation. Right Channel Filter. Requires analog ground proper operation. Left Channel Antialias Filter. This requires capacitor analog ground proper operation. Right Channel Antialias Filter. This requires capacitor analog ground proper operation.
VREF L_FILT R_FILT L_AAFILT R_AAFILT
Crystal
Name XTALO XTALI
PQFP
Description Crystal Output. Crystal present leave XTALO unconnected. Clock. When using crystal clock source, crystal should connected between XTALI XTALO pins. Clock input driven into XTALI place crystal. When using external clock, must rather than specified other digital inputs.
External Logical Devices
Name LD_IRQ* LD_DACK* LD_DRQ* LD_SEL* MDM_SEL* MDM_IRQ* LD_SEL1* PNPRST*
PQFP
Description Logical Device IRQ. Logical Device DACK. Logical Device DRQ. Logical Device Select. Modem Chip Select. Modem Chip IRQ. Logical Device Select. Plug Play Reset.
-12-
REV.
AD1821
Hardware Volume Pins
Name VOL_DN*
PQFP
Description Master Volume Down. Modifies output level pins L_OUT R_OUT. Contains internal pull-up resistor. When asserted decreases Master Volume dB/sec. Must asserted least recognized. When asserted simultaneously with VOL_UP, output muted. Output level modification reflected indirect register Master Volume Modifies output level pins L_OUT R_OUT. Contains internal pull-up resistor. When asserted increases Master Volume dB/sec. Must asserted least recognized. When asserted simultaneously with VOL_UP, output muted. Output level modification reflected indirect register
VOL_UP*
Control Pins
Name XCTL0* PCLKO*
PQFP
Description External Control state this (TTL reflected codec indexed register. This open drain driver. Programmable Clock Output. This programmed generate output clock equal MPEG decoders typically require master clock audio synchronization. External Control state this (TTL reflected codec indexed register. Open drain, active pull-up resistor. Ring Indicator. Used accept ring indicator flag from DAA.
XCTL1* RING*
Power Supplies
Name GNDA
PQFP 99*, 100*
Description Analog Supply Voltage Analog Ground. Digital Supply Voltage Digital Ground.
Optional EEPROM Pins
Name EE_CLK EE_DATA
PQFP
Description EEPROM Clock. EEPROM Data.
*The position this location/function dependent EEPROM data.
REV.
-13-
AD1821
HOST INTERFACE
AD1821 contains necessary interface logic onchip. This logic includes address decoding onboard resources, control signal interpretation, selection control logic, selection control logic, interface configuration logic. AD1821 supports Type request/grant architecture transferring data with through 8-bit interface. AD1821 also supports DACK preemption. Programmed (PIO) mode also supported control register accesses applications lacking control. AD1821 includes dual count registers full-duplex operation enabling simultaneous capture playback separate channels.
Codec Functional Description
completely independent. AD1821 includes variable sample rate converter that lets codec instantaneously change process sample rates from 55.2 with resolution in-band integrated noise distortion artifacts introduced rate conversions below four channels digital data summed together presented stereo conversion. Each digital channel pair contain information encoded different sample rate. example, .wav data received from interface, MPEG audio data received from I2S(0), digital 44.1 data received from I2S(1) internally generated 22.05 music data summed together converted DACs. Digital-to-Analog Datapath internally generated music synthesizer data, data received from interface, data received from I2S(0) port data received from I2S(1) port, serial port passes through attenuation mute stage. attenuator allows independent control over each digital channel, which attenuated from -94.5 steps before being summed together passed DAC, channel muted entirely. Analog Outputs analog output summed with analog input signals. summed analog signal enters Master Volume stage where each channel L_OUT, R_OUT PHONE_OUT attenuated from -46.5 steps muted. Digital Data Types codec process 16-bit twos-complement linear digital data, 8-bit unsigned magnitude linear data 8-bit µ-law A-law companded digital data specified control registers. AD1821 also supports ADPCM encoded Creative SoundBlaster ADPCM formats.
Host-Based Echo Cancellation Support
AD1821's full-duplex stereo codec supports business audio multimedia applications. codec includes stereo audio converters, complete on-chip filtering, Level-2 Level-3 compliant analog mixing, programmable gain attenuation, variable sample rate converter, extensive digital mixing FIFOs buffering Plug Play interface. When using MODIO modem software, PHONE_IN R_OUT channels used support modem telephony features. Analog Inputs codec contains stereo pair analog-to-digital converters (ADC). Inputs selected from following analog signals: mono (PHONE_IN), mono microphone (MIC), stereo line (LINE), external stereo synthesizer (SYNTH), stereo (CD), stereo audio from video source (VID) post-mixed stereo mono line output (OUT). Analog Mixing PHONE_IN, MIC, LINE, SYNTH, mixed analog domain with stereo line from digital-to-analog converters (DAC). Each channel stereo analog inputs independently gained attenuated from -34.5 steps, except PHONE_IN, which range steps. summing path mono inputs (MIC, PHONE_IN line OUT) duplicates mono channel data both left right line OUT, which also gained attenuated from -34.5 steps MIC, -45.5 steps PHONE_IN. left right mono summing signals always identical being equally gained attenuated. Analog-to-Digital Datapath selector sends left right channel information programmable gain amplifier (PGA). following selector allows independent gain each channel entering from 22.5 steps. supporting time correlated echo cancellation, capable sampling microphone data left channel mono summation left right right channel. codec operate either global stereo mode global mono mode with left channel inputs appearing both channels 16-bit converters. Data sampled programmed sampling frequency (from 55.2 with resolution). Digital Mixing Sample Rates audio sample rate audio sample rates
AD1821 supports time correlated data format presenting data left channel mono summation left right right channel. sample rates independent sample rate allowing AD1821 support time correlated data data other sample rate range 55.2 simultaneously.
Telephony Support
AD1821 contains PHONE_IN input PHONE_OUT output. These pins supplied AD1821 connected modem chip set, telephone handset down-line phone.
SoundBlaster Compatibility
Windows Sound System software audio compatibility built into AD1821. SoundBlaster emulation provided through SoundBlaster register internal music synthesizer. SoundBlaster version 2.01 functions supported, including record Creative SoundBlaster ADPCM. Virtually applications developed SoundBlaster, Windows Sound System, AdLib MIDI MPU-401 platforms AD1821 SoundComm® Controller. Follow same development process controller would these other devices. REV.
-14-
AD1821
AD1821 contains SoundBlaster (compatible) Windows Sound System logical devices. find following related development kits useful when developing AD1821 applications. Developer SoundBlaster Series, 1993, Creative Labs, Inc., 1901 McCarthy Blvd., Milpitas, 95035 Microsoft Windows Sound System Driver Development (CD), Version 2.0, 1993, Microsoft Corp., Microsoft Way, Redmond, 98052 following reference texts serve additional sources information developing applications that AD1821. Furia Scacciaferro, MIDI Implementation Book, 1986, Third Earth, Pompton Lake) Petzold, Programming Windows: Microsoft guide writing applications Windows 3.1, 3rd. ed., 1992, Microsoft Press, Redmond) Pohlmann, Principles Digital Audio, 1989, Sams, Indianapolis) Stolz, SoundBlaster Book, 1993, Abacaus, Grand Rapids) Strawn, Digital Audio Engineering, Anthology, 1985, Kaufmann, Altos) Yamamoto, MIDI Guidebook, 4th. ed., 1987, 1989, Roland Corp.)
Multimedia Capabilities
built-in FIFOs: byte receive FIFO byte transmit FIFO. Game Port IBM-compatible game port interface provided chip. game port supports joysticks 15-pin D-sub connector. Joystick registers supporting Microsoft Direct Input standard included part register map. AD1821 programmed automatically sample game port save value Joystick Position Data Register. When enabled, this feature saves MIPS off-loading host from constantly polling joystick port. Volume Control registers that control Master Volume output stage accessible through parallel port. Master Volume output also controlled through 2-pin hardware interface. used increase gain, other attenuates output both pins together entirely mute output. Once muted, further activity these pins will unmute AD1821's output.
Plug Play Configuration
AD1821 MPC-2 MPC-3 compliant. This compliance achieved through AD1821's flexible mixer embedded chip resources. Music Synthesis AD1821 includes embedded music synthesizer that emulates industry standard OPL3 synthesizer chips delivers voice polyphony. internal synthesizer generates digital music data 22.05 summed into DACs digital data stream prior conversion. synthesizer data with output, must programmed 22.05 sample rate. synthesizer hardware implementation Eusynth-1+ code that developed Euphonics, research development company that specializes audio processing electronic music synthesis.
AD1821 fully Plug Play configurable. motherboard applications, built-in Plug Play protocol disabled with software providing back door BIOS configure AD1821's logical devices. information Plug Play mode configuration process, Plug Play Specification Version 1.0a (May 1994). AD1821's logical devices comply with Plug Play resource definitions described specification. AD1821 alternatively configured using optional Plug Play Resource ROM. When EEPROM present, some additional AD1821 muxed-pin features become available. example, pins that control external modem logical device muxed with serial port. Some these option combinations mutually exclusive (see Appendix more information).
REFERENCES
EuSynth-1+
Wavetable MIDI Inputs AD1821 dedicated analog input receiving analog wavetable synthesizer output. Alternatively, wavetable synthesizer's formatted digital output directly connected AD1821's serial ports. Digital wavetable data from AD1821's port summed with other digital data streams being handled AD1821 then sent 16-bit DAC. MIDI primary interface communicating MIDI data from host compatible MPU-401 interface that operates UART mode. MPU-401 interface REV.
AD1821 also complies with following related specifications; they used additional reference AD1821 operations beyond material this data sheet. Plug Play Specification, Version 1.0a, 1993, 1994, Intel Corp. Microsoft Corp., Microsoft Way, Redmond, 98052 Multimedia Level Specification, 1993, Multimedia Marketing Council, 1730 Suite 707, Washington, 20036 MIDI Detailed Specification Standard MIDI Files 1.0, 1994, MIDI Manufacturers Association, 3173 Habra, 90632-3173 Recommendation G.711-Pulse Code Modulation (PCM) Voice Frequencies (µ-Law A-Law Companding), International Telegraph Telephone Consultative Committee Plenary Assembly Blue Book, Volume Fascicle III.4, General Aspects Digital Transmission Systems; Terminal Equipment's, Recommendations G.700 G.795, (Geneva, 1988), ISBN 92-61-03341-5 Digital Audio Doc-Pac (IMA-ADPCM), 1992, Interactive Multimedia Association, Maryland Avenue, Suite 202, Annapolis, 21401-8011
-15-
AD1821
SERIAL INTERFACES Serial Ports
serial ports AD1821 accept serial data following formats: Right-Justified, I2S-Justified Left-Justified. Figure shows right-justified mode. LRCLK left channel right channel. Data valid rising edge BCLK. delayed 16-bit clock periods from LRCLK transition, that when there BCLK periods LRCLK period, data will right-justified next LRCLK transition.
LRCLK BCLK
LEFT CHANNEL
RIGHT CHANNEL
SDATA
Figure Serial Interface Right-Justified Mode
Figure shows I2S-justified mode. LRCLK left channel right channel. Data valid rising edge BCLK. left-justified LRCLK transition, with single BCLK period delay.
LEFT CHANNEL
LRCLK BCLK
RIGHT CHANNEL
SDATA
Figure Serial Interface I2S-Justified Mode
Figure shows left-justified mode. LRCLK left channel right channel. Data valid rising edge BCLK. left-justified LRCLK transition, with delay.
LRCLK BCLK
LEFT CHANNEL
RIGHT CHANNEL
SDATA
Figure Serial Interface Left-Justified Mode
Bidirectional Serial Interface
AD1821 SoundComm® Controller transmits receives both data control/status information through serial interface port (SPORT). AD1821 always master supplies frame sync serial clock. AD1821 four pins assigned SPORT: SDI, SDO, SDFS, SCLK. SPORT operating modes: monitor intercept. SPORT always monitors various data streams being processed AD1821. intercept mode, digital data streams manipulated before reaching final stages. pins handle serial data input output AD1821. Communication AD1821 requires that bits data transmitted after rising edge SCLK sampled falling edge SCLK. SCLK frequency always XTALI). Serial Port Interface time slots mapped shown Table
-16-
REV.
AD1821
Table Port Time Slot
Time Slot
Control Word Input Control Register Data Input SS/SB Right Input ISA) SS/SB Left Input ISA) SS/SB Right Input Codec) SS/SB Left Input Codec) Right Input Codec) Left Input Codec) Right Input Codec) Left Input Codec) Right Input Codec) Left Input Codec)
Status Word Output Control Register Data Output SS/SB Right Output (from Codec) SS/SB Left Output (from Codec) SS/SB Right Output (from ISA) SS/SB Left Output (from ISA) Right Output (from Synth Block) Left Output (from Synth Block) Right Output (from Port [1]) Left Output (from Port [1]) Right Output (from Port [0]) Left Output (from Port [0])
*This data ignored AD1821 unless channel pair intercept mode (see below). Sound System Mode SoundBlaster Mode
start-up (after reset), there exactly time slots frame. frame rate will 57,291 sclk/ bits slots)). Interfacing with Analog Devices 21xx family achieved putting ADSP-21xx slot frame mode, where first second slots ADSP-21xx frame identical. frame rate changed from default write DFS(2:0) bits register Rate choices are: Maximum (57,291 default), capture rate, playback rate, rate, Port rate, Port rate. When frame rate less than 57,261 extra SCLK periods added fill time. number SCLK periods added will vary somewhat from frame frame. control sample data flow each channel through Port, valid input, valid output request bits located control status words. specified channel sample rate equal frame rate, these bits ignored since they will always "1". default, serial port allows only codec sample data monitored. Intercept modes must enabled make substitutions sample data flow from codec. There five bits register which enable intercept mode capture, playback, playback, Port playback Port playback.
Control Word Input (Slot SDI)
FCLR ALIVE SSCVI SSPVI IA[5:0] FMVI IS1VI IS0VI
[5:0] ALIVE IS0VI
Indirect Register Address. Sound System Indirect Register Address defines address indirect registers shown Table Read/Write request. Either read from write indirect register occurs every frame. Setting this initiates indirect register read while clearing this initiates indirect register write. port alive bit. When set, this indicates power-down timer that port active. When cleared, this indicates that port inactive. Port Substitution Data Input Valid Flag. This ignored Intercept mode enabled port channel pair, AD1821 request data from port channel pair previous frame. Otherwise, setting this indicates that slots contain valid right left Port substitution data. When this cleared, data slots ignored. Port Substitution Data Input Valid Flag. This ignored Intercept mode enabled port channel pair AD1821 request data from port channel pair previous frame. Otherwise, setting this indicates that Slots contain valid right left Port substitution data. When this cleared, data slots ignored. Synthesis Substitution Data Input Valid Flag. This ignored Intercept mode enabled synthesis channel pair AD1821 request data from synthesis channel pair previous frame (see FMRQ status word output). Otherwise, setting this indicates that slots contain valid right left synthesis channel substitution data. When this reset data slots ignored. -17-
IS1VI
FMVI
REV.
AD1821
SSPVI SS/SB Playback Substitution Data Input Valid Flag. This ignored Intercept mode enabled SS/SB playback AD1821 request data SS/SB playback previous frame (see SSPRQ Status Word Output). Otherwise, setting this indicates that Slots contain valid right left SS/SB playback substitution data. "capture rate equal playback rate" mode, setting this also indicates that valid capture substitution data being sent AD1821. modem mode, right left channel capture substitution data accepted Slots respectively. modem mode, only mono capture substitution data accepted slots When this cleared, data slots controlled this bit, defined above, ignored. SS/SB Capture Substitution Data Input Valid Flag. This ignored Intercept mode enabled capture AD1821 request data SS/SB capture previous frame (see SSCRQ Status Word Output). Otherwise, setting this indicates that valid SS/SB capture substitution data being sent AD1821. modem mode, port based, right left channel capture data accepted Slots respectively. modem mode, only mono capture substitution data accepted Slot because Slot which mapped right capture channel, being used modem. This mono data will, however, sent both left right SS/SB capture channels. When this cleared, data Slots ignored. Reserved: ensure future compatibility write reserved bits. Port Clear Status Flag. When this set, (write PNPR flag bits status word (Bits slots SDO) cleared. When this cleared, (writing effect PNPR preserves them previous states.
SSCVI
FCLR
Status Word Output (Slot SDO)
PNPR SSCVO SSCRQ SSPVO SSPRQ FMVO FMRQ IS1VO IS1RQ IS0VO IS0RQ
IS0RQ IS1RQ FMRQ SSPRQ SSCRQ
Port Input Request Flag. This intercept mode enabled Port four-word stereo input buffer full. Port Input Request Flag. This intercept mode enabled Port four-word stereo input buffer full. Synthesis Input Request Flag. This intercept mode enabled synthesis four-word stereo input buffer full. SS/SB Capture Input Request Flag. This intercept mode enabled SS/SB playback fourword stereo input buffer full. SS/SB Capture Input Request Flag. This intercept mode enabled SS/SB capture four-word stereo input buffer full. Mailbox Status Flag. This most recent action indirect register (DSP port Mail write, cleared most recent action read. status this also reflected indirect register used handshake facilitate communication between port host bus. Mailbox Status Flag. This most recent action indirect register (DSP port Mail write cleared most recent action read. status this also reflected indirect register used handshake facilitate communication between port host bus. Port Valid Out. This Slots contain valid right left Port data. Port Valid Out. This Slots contain valid right left Port data. Synthesis Valid Out. This Slots contain valid left right synthesis data. SS/SB Playback Valid Out. This Slots contain valid right left SS/SB playback data. SS/SB Capture Valid Out. This valid SS/SB capture data being transmitted. modem mode, Slots will contain valid right left SS/SB capture data. modem mode, only Slot will contain valid left SS/SB capture data Slot right channel used modem.
IS0VO IS1V1 FMVO SSPVO SSCVO
-18-
REV.
AD1821
PNPR Plug Play Reset flag. This AD1821 reset (RESETB asserted LOW) Plug Play reset command. This cleared assertion FCLR control word. While this set, attempts write indirect register port will ignored fail. This ensure that Plug Play resets immediately applied application running DSP, without requiring them continuously poll Plug Play reset status bit. During frame which this cleared asserting FCLR), attempt write indirect register will succeed. FCLR continuously asserted, writes indirect registers port will always enabled. Plug Play reset command will this PNPR HIGH during least frame. Power-Down flag. This AD1821 reset (RESETB asserted LOW), AD1821 powerdown. Before AD1821 power-down sequence shuts down port, least frame will sent with this set. This cleared assertion FCLR (DSP port status clear) control word, providing AD1821 longer power-down.
SDFS used serial interface frame synchronization. frames marked SCLK duration pulse, driven SDFS, serial clock period before frame begins. Upon initializing, there exactly time slots frame bits time slot. frame rate 57,291 SCLK /(16 bits slots). frame rate also changed from default value reprogramming rate registers. frame rate default rate programmed match modem sample rate, capture rate, playback rate, music sample rate, I2S(1) sample rate I2S(0) sample rate. When frame rate equivalent sample rate, Valid Out, Request Valid bits used control sample data flow. When frame rate equivalent sample rate, Valid Request bits ignored.
SAMPLE PERIOD SLOT SLOT
SAMPLE PERIOD SLOT SLOT
SAMPLE PERIOD SLOT SLOT
SCLK
SDFS
Figure Serial Interface (Default Frame Rate)
SAMPLE PERIOD SLOT SLOT
SAMPLE PERIOD SLOT SLOT
SAMPLE PERIOD SLOT SLOT
SCLK
SDFS
Figure Serial Interface (User Programmed Frame Rate)
REV.
-19-
AD1821
Figure illustrates flexibility Serial Port interface. This port monitor intercept digital streams managed AD1821. data stream intercepted port, shipped external ASIC manipulated, returned summing path ADC.
SELECTOR
AUDIO/ MODEM
FORMAT
FIFO PLUG PLAY PARALLEL INTERFACE
MUSIC SYNTHESIZER
FORMAT AUDIO
FIFO
SERIAL PORT
SERIAL PORT
SERIAL PORT INTERFACE
Figure Serial Port
INTERFACE AD1821 Chip Registers
Table Chip Register Diagram, details AD1821 direct register available from Bus. Prior accesses host, addressable ports must configured using Plug Play Resources.
Table Chip Register Diagram
Register Type-Register Name Plug Play ADDRESS WRITE_DATA READ_DATA Sound System Codec CODEC REGISTERS
Register Address 0x279 0xA79 Relocatable Range 0x203 0x3FF 0x(SS Base+0 Base+15) Relocatable Range 0x100 0x3FF Table 0x(SB Base) Relocatable Range 0x010 0x3F0 0x(SB Base+1) 0x(SB Base+2) 0x(SB Base+3) 0x(SB Base+4) 0x(SB Base+5) 0x(SB Base+6 0x(SB Base+8) 0x(SB Base+9) 0x(SB Base+A 0x(SB Base+C 0x(SB Base+E
SoundBlaster Music0: Address (w), Status Music0: Data Music1: Address Music1: Data Mixer Address Mixer Data Reset Music0: Address Music0: Data Input Data Status (r), Output Data Status
-20-
REV.
AD1821
Register Type-Register Name AdLib Music0: Address (w), Status Music0: Data Music1: Address Music1: Data MIDI MPU-401 MIDI Data (r/w) MIDI Status (r), Command Game Port Game Port 0x100 0x3F8
AD1821 Plug Play Device Configuration Registers
Register Address 0x(Adlib Base) Relocatable Range 0x100 0x3F8 0x(Adlib Base+1) 0x(Adlib Base+2) 0x(Adlib Base+3) 0x(MIDI Base) Relocatable Range 0x100 0x3F8 0x(MIDI Base+1) 0x(Game Base Game Base Relocatable Range
AD1821 configured according Intel/Microsoft Plug Play Specification using internal ROM. Alternatively, configuration sequence bypassed using "Alternate Sequence" described Appendix operating system configures/reconfigures AD1821 Plug Play Logical Devices after system boot. There "boot-devices" among Plug Play Logical Devices AD1821. Non-Plug Play BIOS systems configure AD1821's Logical Devices after boot using drivers. Depending BIOS implementations, Plug Play BIOS systems configure AD1821's Logical Devices before POST after Boot. Plug Play Specification Version 1.0a more information configuration control. complete this configuration, system reads resource data from AD1821's on-chip resource from other Plug Play cards system, then arbitrates configuration system resources with heuristic algorithm. algorithm maximizes number active devices acceptability their configurations. system considers Plug Play logical device resource data same time makes conflict-free assignment resources devices. system cannot assign conflict-free resource device, system does configure activate device. configured devices activated. system's Plug Play support selects necessary drivers, starts them maintains list system resources allocated each logical device. option, system resources reassigned runtime with Plug Play Resource Manager. custom setup created using manager saved used automatically subsequent system boots. Plug Play Device (embedded logical device's resource data) provide system with information required find load correct device drivers. custom driver, AD1821 Sound System driver from Analog Devices, required correct operation. other cases (MIDI, Game Port), system generic drivers. Table lists AD1821's Logical Devices compatible Plug Play device drivers.
Table III. Logical Devices Compatible Plug Play Device Drivers
Logical Device Number
Emulated Device Sound System MIDI MPU401 Compatible Game/Joystick Port
Compatible (Device PNPB006 PNPB02F
Device ADS7180 ADS7181 ADS7182
configuration process logical devices AD1821 described Plug Play Specification Version 1.0a (May 1994). specification describes transfer logical devices from their start-up Wait state Config state assign ranges, interrupt channels channels. Appendix example setup program specific Plug Play resource data. Table describes detail Port Address Descriptors, Channels, Interrupts functions required AD1821 Logical Device groups.
REV.
-21-
AD1821
Table Logical Device Configuration
Function Port Address Descriptor (0x60-0x61)
Description SoundBlaster address range from 0x100 0x3F0. typical address 0x220. range bytes long must aligned byte memory boundary. Adlib address range from 0x100 0x3F8. typical address 0x388. range bytes long must aligned byte memory boundary. Codec address range from 0x100 0x3F8. range bytes long must aligned byte memory boundary. This shared between device Codec. These devices require following channels: Typically, this device. This 8-bit channel shared between device Codec playback. These devices require following channels: Typically, channel set. This channel used capturing Codec data. Codec operates single channel mode separate channel capture playback assigned. following channels programmed: Channel indicates single channel mode. MPU-401 compatible device address range 0x100 0x3FE. Typical configurations 0x330. range bytes long must aligned byte memory boundary. MIDI device requires following channels: Game Port address range from 0x100 0x3F8. typical address 0x200. range bytes long must aligned byte memory boundary.
Port Address Descriptor (0x62-0x63)
Port Address Descriptor (0x64-0x65) Interrupt Request Level Select (0x70-0x71)
Playback Channel Select (0x74)
Capture Channel Select (0x75)
Port Address Descriptor (0x60-0x61)
Interrupt Request Level Select (0x70-0x71) Port Address Descriptor (0x60-0x61)
NOTE channel indicates single-channel mode.
Sound System Direct Registers
AD1821 programmable Sound System Direct Registers Indirect Registers. This section describes AD1821 registers gives their address, name initialization state/reset value. Following each register table list ascending order) full register name, usage type: (RO) Read Only, (WO) Write Only, (STKY) Sticky, (RW) Read Write Reserved (res). Table AD1821 direct registers.
Table Sound System Direct Registers
Direct Address SSBASE SSBASE SSBASE SSBASE SSBASE SSBASE SSBASE SSBASE SSBASE SSBASE SSBASE SSBASE SSBASE SSBASE SSBASE SSBASE CRDY INADR[5:0] Indirect Data [7:0] Indirect Data [15:8] [1:0] Playback/Capture [7:0] RESERVED PFMT [1:0] PC/L CFMT [1:0] PC/L RESERVED RESERVED JOYSTICK DATA [7:0] JSEL [1:0] JMSK [3:0] JAXIS [7:0] JAXIS [15:8]
[1:0]
JRDY
JWRP
-22-
REV.
AD1821
[Base+0] Chip/Modem Status/Indirect Address
CRDY INADR[5:0] RESET [0x00]
INADR [5:0] (RW) Indirect Address Sound System (SS). These bits used access Indirect Registers shown Table VIII. registers data must written pairs, byte followed high byte, loading Indirect Data Registers, (Base+2) (Base+3). Volume Button Location. When using EEPROM configure state AD1821, this determines whether PQFP Pins (TQFP Pins 100) used VOL_UP VOL_DN I2S0_DATA I2S0_LRCLK respectively. I2S0_DATA I2S0_LRCLK VOL_UP VOL_DN (RO) AD1821 Ready. AD1821 asserts this when AD1821 accept data. AD1821 ready AD1821 ready
Interrupt Status
RESET [0x00]
CRDY
[Base+1]
(RO) SoundBlaster generated Interrupt. interrupt SoundBlaster interrupt pending (RW) Game Interrupt (Sticky, Write Clear). interrupt interrupt pending Digital Game Port data ready (RW) Ring Interrupt (Sticky, Write Clear). interrupt interrupt pending Hardware Ring being asserted (RW) Interrupt (Sticky, Write Clear). interrupt interrupt pending write indirect register [33] <13> (RW) Volume Interrupt (Sticky, Write Clear). interrupt interrupt pending Hardware Volume Button being pressed (RW) Timer Interrupt. This indicates there interrupt pending from timer count registers. (Sticky, Write Clear). interrupt Interrupt pending from timer count register (RW) Capture Interrupt. This indicates that there interrupt pending from capture count register. (Sticky, Write Clear). interrupt Interrupt pending from capture count register (RW) Playback Interrupt. This indicates that there interrupt pending from playback count register. (Sticky, Write Clear). interrupt Interrupt pending from playback count register
Indirect Data Byte
Indirect Data [7:0] RESET [0xXX]
[Base+2]
[Base+3]
Indirect Data High Byte
Indirect Data [15:8] RESET [0xXX]
Indirect Data [15:0]
Indirect Sound System Data. Data this register written Sound System Indirect Register specified address contained INDAR [5:0], Sound System Direct Register [Base+0]. Data written when Indirect Data High Byte value loaded. -23-
REV.
AD1821
[Base+4] Debug
ORR[1:0] ORL[1:0] RESET [0x00]
bits this register sticky until write that clears bits ORL/ORR (RO) [1:0] Overrange Left/Right detect. These bits record largest output magnitude right left channels cleared after write this register. peak amplitude recorded these bits "sticky," i.e., largest output magnitude recorded these bits will persist until these bits explicitly cleared. They also cleared powering down chip.
ORL/ORR Over/Under Range Detection Less than Underrange Between Underrange Between Overrange Greater than Overrange
(RO)
Capture Over Run. codec sets this when capture data read within sample period after capture FIFO fills. When set, FIFO full codec discards data generated. codec clears this immediately after byte capture sample read. Playback Under Run. codec sets this when playback data written within sample period after playback FIFO empties. codec clears this immediately after byte playback sample written. When set, playback channel "run out" data either plays back mid-scale value repeats last sample.
(RO)
[Base+5]
Status
RESET [0x00]
(RO)
Capture Upper/Lower Sample. This indicates whether capture data ready upper lower byte channel. Lower byte ready Upper byte ready 8-bit mode Capture Left/Right Sample. This indicates whether capture data waiting left channel right channel ADC. Right channel Left channel mono Capture Data Ready. Capture Data register contains data ready reading host. This should used only when direct programmed data transfers desired (FIFO least bytes before full). stale. reread information data fresh. Ready next host data read Capture FIFO Half Full. (FIFO least bytes before full.) Playback Upper/Lower Sample. This indicates whether playback data needed upper lower byte channel. Lower byte needed Upper byte needed 8-bit mode Playback Left/Right Sample. This indicates whether playback data needed left channel right channel DAC. Right channel needed Left channel mono Playback Data Ready. Playback data register ready more data. This should only used when direct programmed data transfers desired (FIFO take least bytes). data still valid. overwrite data stale. Ready next host data write value
Playback FIFO Half Empty. FIFO take least 32-bytes, groups 4-bytes.
(RO)
(RO)
(RO) (RO)
(RO)
(RO)
(RO)
-24-
REV.
AD1821
[Base+6] Dat7 Playback/Capture [7:0] RESET [0x00]
Playback/ Capture [7:0]
Programmed (PIO) Data Registers capture playback mapped same address. Writes send data Playback Register reads will receive data from Capture Register. Reading this register will increment capture byte state machine that following read will from next appropriate byte sample. exact byte determined reading Status Register. Once relevant bytes have been read, state machine will stay pointed last byte sample until sample received. Writing data this register will increment playback byte tracking state machine that following write will correct byte sample. Once bytes have been written, subsequent byte writes will ignored. state machine reset when current sample transferred.
Note: writes FIFO "MUST" contain bytes data. sample 16-bit stereo samples 16-bit mono samples 8-bit stereo (Linear PCM, µ-law PCM, A-Law PCM) samples 8-bit mono (Linear PCM, µ-law PCM, A-Law PCM)
[Base+7] Reserved
RESET [0xXX]
Reserved [7:0]
[Base+8]
Playback Configuration
PFMT [1:0] PC/L RESET [0x00]
(RW)
Playback Enable. This enables disables programmed data playback. Disable Enable Programmed Input/Output. This determines whether playback data transferred PIO. transfers only transfers only Playback Stereo/Mono select. These bits select stereo mono formatting input audio data streams. stereo, Codec alternates samples between channels provide left right channel input. mono, Codec captures samples left channel stereo. Mono Stereo Playback Companded/Linear Select. This selects between linear digital representation audio signal nonlinear companded format output data. type linear type companded format defined PFMT [1:0]. Linear Companded Playback Format. these bits select playback data format output data according Table Figure zero. This forces zero. Repeat last sample Force ZERO Transfer Request Disable. This enables disables Codec transfers during Codec interrupt (indicated Codec Status register's being [1]). This assumes Codec transfers were enabled bits set. Transfer Request Enable Transfer Request Disable
(RW)
(RW)
PC/L
(RW)
PFMT [1:0] (RW) (RW)
(RW)
After setting format bits, sample data into AD1821 must ordered according Figure Table
REV.
-25-
AD1821
tBWDN
IOR/IOW
PC_D [7:0]
BYTE
Figure Codec Transfers
Table Codec Transfers
FMT1 FMT0
Format Mono Linear, 8-Bit Unsigned Stereo Linear, 8-Bit Unsigned Mono µ-Law, 8-Bit Companded Stereo µ-Law, 8-Bit Companded Mono Linear 16-Bit Little Endian Stereo Linear 16-Bit Little Endian Mono A-Law, 8-Bit Companded Stereo A-Law, 8-Bit Companded Reserved Reserved Reserved Reserved Mono Linear, 16-Bit Endian Stereo Linear, 16-Bit Endian Reserved Reserved
Byte Sample Bits Left Channel Sample Bits Right Channel Sample Bits Left Channel Sample Bits Right Channel Sample Upper Bits Left Channel Sample Upper Bits Right Channel Sample Bits Left Channel Sample Bits Right Channel
Byte Sample Bits Left Channel Sample Bits Left Channel Sample Bits Left Channel Sample Bits Left Channel Sample Lower Bits Left Channel Sample Lower Bits Right Channel Sample Bits Left Channel Sample Bits Left Channel
Byte Sample Bits Left Channel Sample Bits Right Channel Sample Bits Left Channel Sample Bits Right Channel Sample Upper Bits Left Channel Sample Upper Bits Left Channel Sample Bits Left Channel Sample Bits Right Channel
Byte Sample Bits Left Channel Sample Bits Left Channel Sample Bits Left Channel Sample Bits Left Channel Sample Lower Bits Left Channel Sample Lower Bits Left Channel Sample Bits Left Channel Sample Bits Left Channel
Sample Lower Bits Left Channel Sample Lower Bits Right+ Channel
Sample Upper Bits Left Channel Sample Upper Bits Left Channel
Sample Lower Bits Left Channel Sample Lower Bits Left Channel
Sample Upper Bits Left Channel Sample Upper Bits Left Channel
-26-
REV.
AD1821
[Base+9] Capture Configuration
CFMT [1:0] CC/L RESET [0x00]
(RW)
Capture Enable. This enables disables data capture. Disable Enable Capture Programmed I/O. This determines whether capture data transferred PIO.
(RW)
(RW) Capture Stereo/Mono Select. This selects stereo mono formatting input audio data streams. stereo, Codec alternates samples between channels provide left right channel input. mono, Codec captures samples left channel. Mono Stereo (RW) Capture Companded/Linear Select. This selects between linear digital representation audio signal nonlinear, companded format output data. type linear type companded format defined CFMT [1:0]. Linear Companded (RW) Capture Format. these bits select format capture data according following Table Figure
Reserved
RESERVED RESET [0xXX]
CC/L
CFMT [1:0]
[Base+10]
[Base+11]
Reserved
RESERVED RESET [0xXX]
[Base+12]
Joystick DATA
Joystick Data [7:0] RESET [0xF0]
Joystick Data (RO)
[Base+13]
JRDY
Joystick Data. Joystick Data (identical 0x201): Writes this register ignored.
JWRP JSEL [1:0] JMSK [3:0] RESET 0xF0
Joystick Control
JMSK [3:0]
(RW)
Joystick Axis Mask. JRDY calculated based axes selected JMSK only.
xxx1 xx1x x1xx 1xxx Enable Enable Enable Enable
JSEL [1:0]
(RW)
Joystick Select. Selects four joystick axis register sets according following table:
Read Bits) from [Base+14] [Base+15] Read Bits) from [Base+14] [Base+15] Read Bits) from [Base+14] [Base+15] Read Bits) from [Base+14] [Base+15]
JWRP
(RW)
Joystick Wrapmode. Continuous Joystick sampling mode-sampling automatically restarted every
JRDY (RO) Joystick Ready. Sampling complete, joystick data ready reading. Note: Sampling must started manually JWRP before sampling cycles run. start sampling after setting JWRP bit, write joystick port [Base+14]. REV. -27-
AD1821
[Base+14] Joystick Position Data Byte
JAXIS [7:0] RESET [0xFF]
JAXIS [7:0] (RO) Joystick Axis Byte. Note: Axis read through this register selected JSEL bits control register. write this register starts sampling cycle.
[Base+15] Joystick Position Data High Byte
JAXIS [15:8] RESET [0xFF]
JAXIS [15:8]
(RO)
Joystick Axis High Byte.
Note: Axis read through this register selected JSEL bits control register. write this register starts sampling cycle.
Sound System Indirect Registers
Writing Indirect Registers Indirect Registers "MUST" written pairs: byte followed high byte. Indirect Address Register [SSBASE+0] holds address register pair, Indirect Data Byte [SSBASE+2] used write data byte Indirect High Data Byte [SSBASE+3] used write high data byte. data byte held temporary register until upper byte written.
Programming Example
"Write Sample Rate Voice Playback 11,000 (0x2AF8)" Write [SSBASE+0] with 0x02 indirect register voice playback sample rate Write [SSBASE+2] with 0xF8 byte 16-bit sample rate register Write [SSBASE+3] with 0x2A high byte 16-bit sample rate register Reading Indirect Registers indirect registers individually read. Sound System Indirect Address Register [SSBASE+0] holds address register pair, Indirect Data Byte [SSBASE+2] used read data byte Indirect High Data Byte [SSBASE+3] used read High data byte.
Programming Example
"Read Sample Rate Voice Playback 11,000 (0x2AF8)" Write [SSBASE+0] with 0x02 indirect register voice playback sample rate Read [SSBASE+2] byte 16-bit sample rate register 0xF8 Read [SSBASE+3] high byte 16-bit sample rate register 0x2A Saves Restores Interrupt Service Routines, ISRs, necessary save restore Indirect Address Byte Temporary Data holding registers inside ISR.
Programming Example
"Save/Restore during ISR" Beginning ISR: Read [SSBASE+0] Write [SSBASE+0] with 0x00; Read [SSBASE+2] Code Write [SSBASE+2] with TMP_LBT Write [SSBASE+0] with TMP_IA Return from Interrupt
save Indirect Address register TMP_IA indirect Register Byte Temporary Data save Byte Temporary data TMP_LBT routine restore Byte Temporary data TMP_LBT restore Indirect Address Register TMP_IA return from
-28-
REV.
AD1821
Table VII. Indirect Register Reset/Default States
Address
Register Name Byte Interrupt Enable External Control Voice Playback Sample Rate Voice Capture Sample Rate Voice Attenuation Attenuation I2S(1) Attenuation I2S(0) Attenuation Playback Base Count Playback Current Count Capture Base Count Capture Current Count Timer Base Count Timer Current Count Master Volume Attenuation Gain/Attenuation Synth Gain/Attenuation Video Gain/Attenuation Line Gain/Attenuation Mic/PHONE-IN Gain/Attenuation Source Select Chip Configuration Configuration Sample Rate I2S(1) Sample Rate I2S(0) Sample Rate Reserved Programmable Clock Rate PhatStereo Control/PHONE_OUT Gain Attenuation Reserved Hardware Volume Button Modifier Mailbox Mailbox Power-Down Timer Control Version Reserved
Reset/ Default State 0xXX 0x0102 0x1F40 0x1F40 0x8080 0x8080 0x8080 0x8080 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x8888 0x8888 0x8888 0x8888 0x8888 0x0000 0x00F0 0x0000 0x5622 0xAC44 0xAC44 0x0000 0xAC44 0x8000 0x0000 0xXX1B 0x0000 0x0000 0x0000 0x0000 0x0000
REV.
-29-
AD1821
Table VIII. Sound System Indirect Registers
ADDRESS (0x00) (0x01) (0x02) (0x03) (0x04) (0x05) (0x06) (0x07) (0x08) (0x09) (0x0A) (0x0B) (0x0C) (0x0D) (0x0E) (0x0F) (0x10) (0x11) (0x12) (0x13) (0x14) (0x20) (0x21) (0x22) (0x23) (0x24) (0x25) (0x26) (0x27) (0x28) (0x29 (0x2A) (0x2B) (0x2C) (0x2D) (0x2E) (High Byte) VPSR [15.8] VCSR [15:8] [5:0] LFMA [5:0] LS1A [5:0] LS0A [5:0] [15:8] [15:8] [15:8] [15:8] [15:8] [15:8] LMVA [4:0] LCDA [4:0] LSYA [4:0] LVDA [4:0] [4:0] [4:0] [2:0] [3:0] FSMR [15:8] S1SR [15:8] S0SR [15:8] [15:8] [3:0] MB0R [15:8] MB1R [15:8] [15:8] VPSR [7:0] VCSR [7:0] RFMM RS1M RS0M [5:0] RFMA [5:0] RS1A [5:0] RS0A [5:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] RMVM RCDM RSYM RVDM RAGC [2:0] [3:0] RMVA [4:0] RCDA [4:0] RSYA [4:0] RVDA [4:0] [4:0] [3:0] [3:0] I2SF1 [1:0] I2SF0 [1:0] [2:0] FMSR [7:0] S1SR [7:0] S0SR [7:0] [7:0] [4:0] [4:0] MB0R [7:0] MB1R [7:0] [7:0] (Low Byte) LBTD [7:0]
LFMM LS1M LS0M
LMVM LCDM LSYM LVDM LAGC
3DDM
PD3D
GPSP
[00] INDIRECT BYTE
LBTD [7:0]
DEFAULT [0xXX]
LBTD [7:0] Byte Temporary Data holding latch register pair writes; Written write [SSBase Read from [SSBase when indirect address 0x00.
[01] INTERRUPT ENABLE EXTERNAL CONTROL DEFAULT [0x0102]
External Control state this reflected XCTL0 pin. This also muxed with PCLKO. must greater than PCLKO disabled, [32]. External Control state this reflected XCTL1 pin. XCTL1 also used Ring-In Interrupt. SoundBlaster Interrupt Enable; SoundBlaster Interrupt disabled SoundBlaster Interrupt enabled Joystick Interrupt Enable; Joystick Interrupt disabled Joystick Interrupt enabled
-30-
REV.
AD1821
Ring Interrupt Enable; Ring Interrupt disabled Ring Interrupt enabled Interrupt Enable; Interrupt disabled Interrupt enabled Volume Interrupt Enable. enabled, software increments/decrements BUTTON MODIFIER interrupt routine pushing buttons only sets VUP, VDN, bits. does change volume. Volume Interrupt disabled Volume Interrupt enabled Timer Interrupt Enable; Timer Interrupt disabled Timer Interrupt enabled Capture Interrupt Enable; Capture Interrupt disabled Capture Interrupt enabled Playback Interrupt Enable; Playback Interrupt disabled Playback Interrupt enabled
VPSR [7:0] DEFAULT [0x1F40]
[02] VOICE PLAYBACK SAMPLE RATE VPSR [15:8]
VPSR [15:0] Voice Playback Sample Rate. sample rate programmed from 55.2 hertz increments. default playback sample rate kHz.
[03] VOICE CAPTURE SAMPLE RATE VCSR [15:8] DEFAULT [0x1F40] VCSR [7:0]
VCSR [15:0] Voice Capture Sample Rate. sample rate programmed from 55.2 hertz increments. Ignored [32] which case VPSR [15:0] controls capture rate. default capture sample rate kHz.
[04] VOICE ATTENUATION [5:0] DEFAULT [0x8080] [5:0]
[5:0] [5:0]
Right Voice Attenuation Playback channel. represents -1.5 000000 range -94.5 Right Voice Mute. Unmuted, Muted. Left Voice Attenuation Playback channel. represents -1.5 000000 range -94.5 Left Voice Mute. Unmuted, Muted.
RFMM
[05] ATTENUATION
LFMM
DEFAULT [0x8080]
RFMA [5:0]
LFMA [5:0]
RFMA [5:0] Right Music Attenuation internal Music Synthesizer. represents -1.5 000000 range -94.5 RFMM Right Music Mute. Unmuted, Muted. LFMA [5:0] Left Music Attenuation internal Music Synthesizer. represents -1.5 000000 range -94.5 LFMM Left Music Mute. Unmuted, Muted.
[06] 2S(1) ATTENUATION LS1M LS1A [5:0] RS1M DEFAULT [0x8080] RS1A [5:0]
RS1A [5:0] REV.
Right I2S(1) Attenuation register. represents -1.5 000000 range -94.5 -31-
AD1821
RS1M LS1A [5:0] LS1M Right I2S(1) Mute. Unmuted, Muted. Left I2S(1) Attenuation register. represents -1.5 000000 range -94.5 Left I2S(1) Mute. Unmuted, Muted.
LS0A [5:0] RS0M DEFAULT [0x8080] RS0A [5:0]
[07] 2S(0) ATTENUATION LS0M
RS0A [5:0] RS0M LS0A [5:0] LS0M
Right I2S(0) Attenuation register. represents -1.5 000000 range -94.5 Right I2S(0) Mute. Unmuted, Muted. Left I2S(0) Attenuation register. represents -1.5 000000 range -94.5 Left I2S(0) Mute. Unmuted, Muted.
DEFAULT [0x0000]
[08] PLAYBACK BASE COUNT [15:8]
[7:0]
[15:0]
Playback Base Count. This register loading Playback Count. Writing value this register also loads same data into Playback Current Count register. must load this register when Playback Enable (PEN) deasserted. When asserted, Playback Current Count decrements once every four bytes transferred cycle. next transfer, after zero reached Playback Current Count, will generate interrupt reload Playback Current Count with value Playback Base Count. Playback Base Count should always programmed Number Bytes divided four, minus ((Number Bytes/4) -1). circular software buffer must divisible four ensure proper operation.
[7:0] DEFAULT [0x0000]
[09] PLAYBACK CURRENT COUNT [15:8]
[15:0]
Playback Current Count register. Contains current Playback Count. Reads Writes must done when deasserted.
[7:0] DEFAULT [0x0000]
[10] CAPTURE BASE COUNT [15:8]
[15:0]
Capture Base Count. This register loading Capture Count. Writing value this register also loads same data into Capture Current Count register. Loading must done when Capture Enable (CEN) deasserted. When asserted, Capture Current Count decrements once every four bytes transferred cycle. next transfer, after zero reached Capture Current Count, will generate interrupt reload Capture Current Count with value Capture Base Count. Capture Base Count should always programmed Number Bytes divided four, minus ((Number Bytes/4) -1). circular software buffer must divisible four ensure proper operation.
[7:0] DEFAULT [0x0000]
[11] CAPTURE CURRENT COUNT [15:8]
[15:0]
Capture Current Count register. Contains current Capture Count. Reading Writing must done when deasserted.
[7:0] DEFAULT [0x0000]
[12] TIMER BASE COUNT [15:8]
[15:0]
Timer Base Count. Register loading Timer Count. Writing value this register also loads same data into Timer Current Count register. Loading must done when Timer Enable (TE) deasserted. When asserted, Timer Current Count register decrements once every specified time period. time period programmed [44]. When asserted, Timer Current Count decrements once every time period. next count, after zero reached Timer Current Count register, will generate interrupt reload Timer Current Count register with value Timer Current Count register.
-32-
REV.
AD1821
[13] TIMER CURRENT COUNT [15:8] [7:0] DEFAULT [0x0000]
[15:0]
Timer Current Count register. Contains current timer count. Reading Writing must done when deasserted.
RMVM
[14] MASTER VOLUME ATTENUATION
LMVM LMVA [4:0]
DEFAULT [0x0000]
RMVA [4:0]
RMVA [4:0] Right Master Volume Attenuation. represents -1.5 00000 range -46.5 This register added with Hardware Volume Button Modifier value produce final Master Volume attenuation level. Hardware Volume Button Modifier Register description more details. RMVM Right Master Volume Mute. Unmuted, Muted. LMVA [4:0] Left Master Volume Attenuation. represents -1.5 00000 range -46.5 This register added with Hardware Volume Button Modifier value produce final Master Volume attenuation level. Hardware Volume Button Modifier Register description more details. LMVM Left Master Volume Mute. Unmuted, Muted.
[15] GAIN/ATTENUATION
LCDM
LCDA [4:0]
RCDM
DEFAULT [0x8888]
RCDA [4:0]
RCDA [4:0] RCDM LCDA [4:0] LCDM
Right Attenuation. represents -1.5 00000 range -34.5 Right Mute. Unmuted, Muted. Left Attenuation. represents -1.5 00000 range -34.5 Left Mute. Unmuted, Muted.
RSYM
[16] SYNTH GAIN/ATTENUATION
LSYM LSYA [4:0]
DEFAULT [0x8888]
RSYA [4:0]
RSYA [4:0] RSYM LSYA [4:0] LSYM
Right SYNTH Attenuation. represents -1.5 00000 range -34.5 Right SYNTH Mute. Unmuted, Muted. Left SYNTH Attenuation. represents -1.5 00000 range -34.5 Left SYNTH Mute. Unmuted, Muted.
LVDA [4:0]
[17] GAIN/ATTENUATION
LVDM
RVDM
DEFAULT [0x8888]
RVDA [4:0]
RVDA [4:0] RVDM LVDA [4:0] LVDM
Right Attenuation. represents -1.5 00000 range -34.5 Right Mute. Unmute, Muted. Left Attenuation. represents -1.5 00000 range -34.5 Left Mute. Unmuted, Muted.
[4:0]
[18] LINE GAIN/ATTENUATION
DEFAULT [0x8888]
[4:0]
[4:0] [4:0]
Right LINE Attenuation. represents -1.5 00000 range -34.5 Right Line Mute. Unmuted, Muted. Left LINE Attenuation. represents -1.5 00000 range -34.5 Left Line Mute. Unmuted, Muted.
REV.
-33-
AD1821
[19] MIC/PHONE_IN GAIN/ATTENUATION
[4:0]
DEFAULT [0x8888]
[3:0]
[3:0] [4:0]
PHONE_IN Attenuation. represents 0000 range PHONE_IN Mute. Microphone Attenuation. represents -1.5 00000 range -34.5 Microphone Gain. M20-bit enables Microphone gain stage. Microphone Mute.
RAGC [2:0] DEFAULT [0x0000] [3:0]
[20] SOURCE SELECT LAGC [2:0] [3:0]
[3:0] RAGC [3:0] LAGC [2:0]
Right Gain Control source select Gain. Gain, represents +1.5 0000 range +22.5 Right Automatic Gain Control (AGC) Enable, Enabled, Disabled. Left Gain Control source select Gain. Gain, represents +1.5 0000 range +22.5 Left Automatic Gain Control (AGC) Enable, Enabled, Disabled. Right Input Source R_LINE R_OUT R_CD R_SYNTH R_VID Mono Reserved Reserved [2:0] Left Input Source L_LINE L_OUT L_CD L_SYNTH L_VID PHONE_IN Reserved
DEFAULT [0x00F0] I2SF0 [1:0]
[32] CHIP CONFIGURATION
[3:0]
I2SF1 [1:0]
I2SF0 [1:0] I2SF1 [1:0]
[3:0]
Port Configuration serial data type. Disabled Right Justified Justified Left Justified Clock Output Frequency. Programmable clock output PCLKO determined using following formula PCLKO PCR/2COF where 0:11 value Programmable Clock Rate Register, [38]. then PCLKO disabled. Capture equal Playback. Capture equals Playback. capture sample rate determined playback sample rate [02]. Capture equal Playback. Enable, when player connected (0). Sound System Enable. SoundBlaster Mode. Sound System Mode under Windows. Note: When SoundBlaster Mode, Codec channels will used solely converting SoundBlaster data.
-34-
REV.
AD1821
[33] CONFIGURATION DEFAULT [0x0000] [2:0]
[2:0]
Frame Sync Source. Sets Port Frame Sync according following source. 000-Maximum Frame Rate 001-I2S(0) Sample Rate 010-I2S(1) Sample Rate 011-Music Synthesizer Sample Rate 100-Sound System Playback Sample Rate 101-Sound System Capture Sample Rate 111-Reserved I2S(0) Data Intercept. Disable, Intercept I2S(0) Data Enabled. I2S(1) Data Intercept. Disable, Intercept I2S(1) Data Enabled. Music Synthesizer Data Intercept. Disable, Intercept Music Data Enabled. Playback Data Intercept. Disable, Intercept Playback Data Enabled. Capture Data Intercept. Disable, Intercept Capture Data Enabled. I2S(0) Takeover Data. Disable, Enabled. I2S(1) Takeover Data. Disable, Enabled. Audio Resync. Writing causes FIFOs port re-initialized. Interrupt. write this causes interrupt asserted. Mailbox Status. last access indicates read, last access indicates write. Mailbox Status. last access indicates read, last access indicates write.
FMSR [7:0] DEFAULT [0x5622]
[34] SAMPLE RATE FMSR [15:8]
FMSR [15:0] Music Sample Rate register. sample rate programmed from 27.6 hertz increments.
[35] 2S(1) SAMPLE RATE S1SR [15:8] DEFAULT [0xAC44] S1SR [7:0]
S1SR [15:0]
I2S(1) Sample Rate register. sample rate programmed from 55.2 hertz increments. Programming this register effect unless I2SF1 [1:0] enabled.
S0SR [7:0] DEFAULT [0xAC44]
[36] 2S(0) SAMPLE RATE S0SR [15:8]
S0SR [15:0]
I2S(0) Sample Rate register. sample rate programmed from 55.2 hertz increments. Programming this register effect unless I2SF0 [1:0] enabled.
DEFAULT [0x0000]
[37] RESERVED
[38] PROGRAMMABLE CLOCK RATE [15:8]
[7:0]
DEFAULT [0xAC44]
[15:0]
Programmable Clock Rate register. clock rate programmed from hertz increments. This register only valid when bits [32] multiplier factor. PCLKO PCR/2COF. [32] determining value COF.
DEFAULT [0x8000] [4:0]
[39] PhatStereo Control PHONE_OUT Attenutation 3DDM [3:0]
[4:0] REV.
PHONE_OUT Attenuation. represents -1.5 0000 range -46.5 -35-
AD1821
[3:0] 3DDM PHONE-OUT Mute. Unmuted, Muted. Depth PhatStereo Enhancement Control. represents 2/3% phase expansion, 0000 range 100%. Depth Mute. Writing this same affect writing [3:0] bits, causes Phat3D Stereo Enhancement turned off. PhatTM* Stereo PhatStereo off.
DEFAULT [0x0000]
[40] RESERVED
[41] HARDWARE VOLUME BUTTON MODIFIER
DEFAULT [0xXX1B] [4:0]
[4:0] Button Modifier Volume Down Volume Volume Mute This register contains Master Volume attenuation offset, which incremented decremented Hardware Volume Pins. This register summed with Master Volume attenuation produce actual Master Volume attenuation. momentary grounding greater than VOL_UP will cause decrement (decrease Attenuation) this register. Holding greater than will cause auto-decrement every This also true momentary grounding VOL_DN pin. momentary grounding both VOL_UP VOL_DN causes mute increment decrement occur. When Muted, unmute possible momentary grounding both VOL_UP VOL_DN pins together, momentary grounding VOL_UP (this also causes volume increase), momentary grounding VOL_DN (this also causes volume decrease) write [BASE+1].
[42] MAILBOX MB0R [15:8] MB0R [7:0] DEFAULT [0x0000]
MB0R [15:0]
This register used send data control information from DSP.
MB1R [7:0] DEFAULT [0x0000]
[43] MAILBOX MB1R [15:8]
MB1R [15:0]
This register used send data control information from DSP.
PD3D GPSP DEFAULT [0x0000]
[44] POWER-DOWN TIMER CONTROL
AD1821 supports timeout mechanism used conjunction with Timer Base Count Timer Current Count registers generate power-down interrupt. This interrupt allows software power down entire chip setting bit. This power-down control feature lets users program time interval from approximately hours increments. Five power-down count reload enable bits used reload Timer Current Count from Timer Base Count when activity seen that particular channel. Programming Example: Generate Interrupt Reads Writes occur within Minutes. Write [SSBASE+0] with 0x0C Write Indirect address TIMER BASE COUNT "register Write [SSBASE+2] with 0x28 Write TIMER BASE COUNT with sec/min 0x2328 mili-Seconds Write [SSBASE+3] with 0x23 Write High byte TIMER BASE COUNT Write [SSBASE+0] with 0x2C Write Indirect address POWER-DOWN TIMER CONTROL register Write [SSBASE+2] with 0x00 Write byte POWER-DOWN TIMER CONTROL register Write [SSBASE+3] with 0x30 Enable bits Write [SSBASE+0] with 0x01 Write Indirect address INTERRUPT CONFIG register Write [SSBASE+2] with 0x82 (Timer Enable) Write [SSBASE+3] with 0x20 (Timer Interrupt Enable)
-36-
REV.
AD1821
GPSP Game Port Speed Select. Selects operating speed game port. Slow Game Port Fast Game Port Power-Down Turns internal PhatStereo circuitry. Analog Mixer Bypass. Allows analog output converters bypass PhatStereo Circuit. Enables ultimate flexibility mixing combination enhanced analog signals non-3D enhanced signals with output. PhatStereo Enabled Output PhatStereo Bypassed Output Power-Down Time Base. timer timer Power-down count reload Port enabled; Reload count Port enabled. Port enabled when Slot Serial Port Input Alive (Bit Power-down count reload Digital Activity; Reload count Digital Activity. Digital Activity defined activity (I2S0, I2S1, PLAYBACK). Power-down count reload Analog Activity; Reload count Analog Activity. Analog Activity defined analog input unmuted (LINE, SYNTH, MIC, MONO) MASTER VOLUME unmuting. Power-down count reload Read; Reload count read. Read defined read from active logical device inside AD1821. Power-down count reload Write; Reload count write. Write defined write active logical device inside AD1821.
PD3D
Chip Power-Down Power-Down; Power-Up Power-up, software should poll [SSBASE+0] before writing reading logical device.
[45] VERSION [15:8] [46] RESERVED [7:0] DEFAULT [0x0000] DEFAULT [0x0000]
Test register. Should never written read under normal operation.
Pro; AdLib Registers
AD1821 contains sets registers (ports) that correspond those used SoundBlaster audio card from Creative Labs AdLib audio card from AdLib Multimedia. Table lists SoundBlaster registers. Table lists AdLib registers. Because AdLib registers subset those SoundBlaster card, find complete information using both these registers Developer SoundBlaster Series, 1993, Creative Labs, Inc., 1901 McCarthy Blvd., Milpitas, 95035.
Table SoundBlaster Registers
Register Name Music0: Address (w), Status Music0: Data Music1: Address Music1: Data Mixer Address Mixer Data Reset Music0: Address Music0: Data Input Data Status (r), Output Data Status REV.
Address 0x(SB Base) Relocatable range 0x010 0x3F0 0x(SB Base+1) 0x(SB Base+2) 0x(SB Base+3) 0x(SB Base+4) 0x(SB Base+5) 0x(SB Base+6) 0x(SB Base+8) 0x(SB Base+9) 0x(SB Base+A) 0x(SB Base+C) 0x(SB Base+E) -37-
AD1821
Table AdLib Registers
Register Name Music0: Address (w), Status Music0: Data Music1: Address Music1: Data
MIDI MPU-401 Registers
Address 0x(Adlib Base) Relocatable range 0x008 0x3F8 0x(Adlib Base+1) 0x(Adlib Base+2) 0x(Adlib Base+3)
AD1821 contains registers (ports) that correspond those used MIDI audio interface cards. Table lists MIDI registers. These registers support commands data transfers described MIDI Detailed Specification Standard MIDI Files 1.0, 1994, MIDI Manufacturers Association, 3173 Habra, 90632-3173.
Table MIDI Registers
Register Name MIDI Data (r/w) MIDI Status (r), Command
Address 0x(MIDI Base) Relocatable range 0x008 0x3F8 0x(MIDI Base+1)
0x(MIDI Base+1) STATE NAME
RESERVED
[7:0]
Data Send Ready. When read, this indicates that cannot write MIDI Data register. (Full Empty Data Receive Ready. When read, this indicates that cannot read from MIDI Data register. (Unreadable Readable MIDI Command. Write MPU-401 commands bits [7:0] this register.
NOTES AD1821 supports only MIDI 0xFF (reset) 0x3F (pass-through mode) commands. controller powers setup intelligent MIDI mode, must pass-through mode. start MIDI operations, send reset command (0xFF) then send pass-through mode command (0x3F). MIDI data register contains acknowledge byte (0xFE) after each command transfer. commands return byte "smart" mode. Status commands (0xAx) return data byte; other commands return ACK. commands except reset (0xFF) ignored UART mode. bytes returned. "Smart" mode data transfers supported.
Game Port Registers
AD1821 contains Game Port Register that corresponds game port described specification.
Table XII. Game Port Registers
Register Name Game Port
Address 0x(Game Port Base+0 Game Port Base+7 Relocatable range 0x100 0x3F8
-38-
REV.
AD1821
APPENDIX AD1821JS AD1821JS-M
Contains internal code AD1821JS. Consult Reference Design Guide external EEPROM Code. AD1821JS PLUG PLAY INTERNAL Note: addresses depicted hexidecimal notation.
Vendor ADS7180 Serial Number: FFFFFFFF Checksum: Version: 1.0, vendor version: ASCII string: Analog Devices Logical Device ADS7180 boot device, implements register(s) Start dependent function, best config IRQ: channel(s) type(s) active-high, edge-triggered DMA: channel(s) Type count-by-byte, nonbus-mastering, 8-bit only DMA: channel(s) Type count-by-byte, nonbus-mastering, 8-bit only I/O: 16-bit decode, range [0220,0240] length I/O: 16-bit decode, range [0388,0388] length I/O: 16-bit decode, range [0500,0560] length Start dependent function, acceptable config IRQ: channel(s) type(s) active-high, edge-triggered DMA: channel(s) Type count-by-byte, nonbus-mastering, 8-bit only DMA: channel(s) Type count-by-byte, nonbus-mastering, 8-bit only I/O: 16-bit decode, range [0220,0240] length I/O: 16-bit decode, range [0388,0388] length I/O: 16-bit decode, range [0500,0560] length Start dependent function, acceptable config IRQ: channel(s) type(s) active-high, edge-triggered DMA: channel(s) Type count-by-byte, nonbus-mastering, 8-bit only DMA: channel(s) Type count-by-byte, nonbus-mastering, 8-bit only
I/O: 16-bit decode, range [0220,02E0] length I/O: 16-bit decode, range [0388,03B8] length I/O: 16-bit decode, range [0500,0560] length Start dependent function, suboptimal config IRQ: channel(s) type(s) active-high, edge-triggered DMA: channel(s) Type count-by-byte, nonbus-mastering, 8-bit only DMA: NULL I/O: 16-bit decode, range [0220,02E0] length I/O: 16-bit decode, range [0388,03B8] length I/O: 16-bit decode, range [0500,0560] length dependent functions Logical Device ADS7181 boot device, implements register(s) Compatible Device PNPB006 Start dependent function, best config IRQ: channel(s) type(s) active-high, edge-triggered I/O: 16-bit decode, range [0300,0330] length Start dependent function, acceptable config IRQ: channel(s) type(s) active-high, edge-triggered I/O: 16-bit decode, range [0300,0420] length dependent functions Logical Device ADS7182 boot device, implements register(s) Compatible Device PNPB02F Start dependent function, best config I/O: 16-bit decode, range [0200,0200] length Start dependent function, acceptable config I/O: 16-bit decode, range [0200,0208] length dependent functions End:
REV.
-39-
AD1821
Contains internal code AD1821JS-M. Consult Reference Design Guide external EEPROM Code.
AD1821JS-M PLUG PLAY INTERNAL
Vendor ADS7181 Serial Number: FFFFFFFF Checksum: Version: 1.0, vendor version: ASCII string: Analog Devices Logical Device ADS7180 boot device, implements register(s) Start dependent function, best config IRQ: channel(s) type(s) active-high, edge-triggered DMA: channel(s) Type count-by-byte, nonbus-mastering, 8-bit only DMA: channel(s) Type count-by-byte, nonbus-mastering, 8-bit only I/O: 16-bit decode, range [0220,0240] length I/O: 16-bit decode, range [0388,0388] length I/O: 16-bit decode, range [0500,0560] length Start dependent function, acceptable config IRQ: channel(s) type(s) active-high, edge-triggered DMA: channel(s) Type count-by-byte, nonbus-mastering, 8-bit only DMA: channel(s) Type count-by-byte, nonbus-mastering, 8-bit only I/O: 16-bit decode, range [0220,0240] length I/O: 16-bit decode, range [0388,0388] length I/O: 16-bit decode, range [0500,0560] length Start dependent function, acceptable config IRQ: channel(s) type(s) active-high, edge-triggered DMA: channel(s) Type count-by-byte, nonbus-mastering, 8-bit only DMA: channel(s) Type count-by-byte, nonbus-mastering, 8-bit only
I/O: 16-bit decode, range [0220,02E0] length I/O: 16-bit decode, range [0388,03B8] length I/O: 16-bit decode, range [0500,0560] length Start dependent function, suboptimal config IRQ: channel(s) type(s) active-high, edge-triggered DMA: channel(s) Type count-by-byte, nonbus-mastering, 8-bit only DMA: NULL I/O: 16-bit decode, range [0220,02E0] length I/O: 16-bit decode, range [0388,03B8] length I/O: 16-bit decode, range [0500,0560] length dependent functions Logical Device ADS7181 boot device, implements register(s) Compatible Device PNPB006 Start dependent function, best config IRQ: channel(s) type(s) active-high, edge-triggered I/O: 16-bit decode, range [0300,0330] length Start dependent function, acceptable config IRQ: channel(s) type(s) active-high, edge-triggered I/O: 16-bit decode, range [0300,0420] length dependent functions Logical Device ADS7182 boot device, implements register(s) Compatible Device PNPB02F Start dependent function, best config I/O: 16-bit decode, range [0200,0200] length Start dependent function, acceptable config I/O: 16-bit decode, range [0200,0208] length dependent functions End:
-40-
REV.
AD1821
APPENDIX PLUG PLAY "ALTERNATE KEY" SEQUENCES
additional feature AD1821 alternate programming method used, example, BIOS wants assume control AD1821 present DEVNODES (rather than having device participate Plug Play enumeration). following technique used. Instead normal byte Plug Play sequence, alternate byte used. After byte key, AD1821 device will transition Plug Play "config" state. then programmed usual using standard Plug Play ports. After programming, AD1821 should sent Plug Play "WFK" (wait key) state. Once AD1821 seen alternate key, will longer parse Plug Play (and therefore never participate Plug Play enumeration). reprogrammed reissuing alternate again. Both Plug Play alternate sequences writes Plug Play address register, 0x279. Below data values both keys. This standard Plug Play sequence:
This longer, 126-byte alternate key. generated function: f[n+1] (f[n] (((f[n] (f[n] 0x01) f[0] 0x01
REV.
-41-
AD1821
PROGRAMMING EXTERNAL EEPROMS EEPROM written only "Alternate State"; this prevents accidental EEPROM erasure when using standard setup. procedure writing EEPROM Enter configuration state fully reset part writing 0x07 register 0x02. This step eliminated part been accessed since power-up, previous full reset assertion RESET signal. Send alternate initiation address port. EEPROM writes disabled standard used. Enter isolation state write enter configuration state. perform isolation reads. Poll register 0x05 until equals 0x01 wait least microseconds (ensures that EEPROM idle). Write second byte your serial identifier register 0x20. Read register 0x04. Wait least microseconds, plus EEPROM's write cycle time Xicor X24C02). Repeat steps through each byte your ROM, starting with third byte serial identifier ending with final checksum byte. must then continue write filler bytes until bytes, minus more than number flag bytes, have been written. Finally, write flag byte(s) (described above) first byte serial identifier. Fully reset part writing 0x07 register 0x02. AD1821 will according contents EEPROM.
NOTES
Programming will work more than part uses same alternate initiation system. 256-byte EEPROM used, necessary wait after writing bytes 511, because EEPROM will ignore them anyway. skip over bytes that don't care write just performing read instead write followed read.
REFERENCE DESIGNS DEVICE DRIVERS
Reference designs device drivers AD1821 available Analog Devices Home Page World Wide http://www.analog.com. Reference designs also obtained contacting your local Analog Devices Sales representative authorized distributor.
-42-
REV.
AD1821
-100 -110
-100 -120 -140 -160 -180 -200
Audio/Modem
Audio/Modem
-0.1 -0.2
-0.1
-0.2
Audio/Modem Passband
Audio/Modem Passband
Figure AD1821 Frequency Response Plots (Full-Scale Line-Level Input, Gain). Plots Reflect Additional Benefits On-Chip Analog Filters. Out-of-Band Images Will Attenuated Additional 31.4 kHz.
REV.
-43-
AD1821
OUTLINE DIMENSIONS
Dimensions shown inches (mm).
100-Lead Plastic Quad Flatpack (S-100)
C3057-12-7/97
0.486 (12.35) 0.555 (14.10) 0.547 (13.90) 0.687 (17.45) 0.667 (16.95) 0.923 (23.45) 0.903 (22.95) 0.791 (20.10) 0.783 (19.90) 0.742 (18.85)
0.096 (2.45) 0.037 (0.95) 0.026 (0.65) SEATING PLANE
VIEW
(PINS DOWN)
0.004 (0.10) 0.010 (0.25) 0.083 (2.10) 0.075 (1.90)
0.029 (0.73) 0.023 (0.57)
0.015 (0.35) 0.009 (0.25)
-44-
REV.
PRINTED U.S.A.
Other recent searches
TPS40060 - TPS40060 TPS40060 Datasheet
TPS40061 - TPS40061 TPS40061 Datasheet
SSOP44K - SSOP44K SSOP44K Datasheet
Si7136DP - Si7136DP Si7136DP Datasheet
PMC-12V035W1AA - PMC-12V035W1AA PMC-12V035W1AA Datasheet
IXF6151 - IXF6151 IXF6151 Datasheet
CDSU400 - CDSU400 CDSU400 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
