Publication Release Date: 2002 Revision Preliminary W987Y6CB

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Publication Release Date: 2002 Revision Preliminary W987Y6CB

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Preliminary W987Y6CB BANKS SDRAM
Publication Release Date: 2002 Revision
Preliminary W987Y6CB
Interleaved Bank Read (Burst Length Latency 3).26 Interleaved Bank Read (Burst Length Latency Autoprecharge) Interleaved Bank Write (Burst Length Interleaved Bank Write (Burst Length Autoprecharge) Page Mode Read (Burst Length Latency Page Mode Read Write (Burst Length Latency Auto Precharge Read (Burst Length Latency 3).32 Auto Precharge Write (Burst Length Auto Refresh Cycle.34 Self Refresh Cycle Burst Read Single Write (Burst Length Latency 3).36 PowerDown Mode Autoprecharge Timing (Read Cycle) Autoprecharge Timing (Write Cycle) Timing Chart Read Write Cycle Timing Chart Write Read Cycle Timing Chart Burst Stop Cycle (Burst Stop Command) Timing Chart Burst Stop Cycle (Precharge Command) CKE/DQM Input Timing (Write Cycle) CKE/DQM Input Timing (Read Cycle) Self Refresh/Power Down Mode Exit Timing.44 PACKAGE DIMENSION REVISION HISTORY.46
Preliminary W987Y6CB
GENERAL DESCRIPTION
W987Y6CB high-speed synchronous dynamic random access memory (SDRAM), organized words banks bits. Using pipelined architecture 0.175 process technology, W987Y6CB delivers data bandwidth 125M words second (-8). different application, W987Y6CB sorted into speed grades: compliant MHz/ specification; compliant MHz/ specification. handheld device application, these parts specially designed with several power saving mechanisms achieve extremely Self Refresh Current. Accesses SDRAM burst oriented. Consecutive memory location page accessed burst length full page when bank selected ACTIVE command. Column addresses automatically generated SDRAM internal counter burst operation. Random column read also possible providing address each clock cycle. multiple bank nature enables interleaving among internal banks hide precharging time. having programmable Mode Register, system change burst length, latency cycle, interleave sequential burst maximize performance. W987Y6CB ideal main memory high performance applications.
FEATURES
Power supply 2.5V ±0.2V VDDQ 2.5V Standard Self Refresh Mode Power Down Mode Latency: Burst Length: full page Refresh Cycles Interface: LVTTL Packaged balls FBGA Operating Temperature Range Commercial Temperature Industrial Temperature (-40°
AVAILABLE PART NUMBER
PART NUMBER W987Y6CBN75 W987Y6CBG75 W987Y6CBN80 W987Y6CBG80 SPEED MHz/ MHz/ MHz/ MHz/ SELF REFRESH CURRENT (MAX.) TEMPERATURE RANGE LEAD-FREE PACKAGE
Publication Release Date: 2002 Revision
Preliminary W987Y6CB
BALL CONFIGRUATION
(TOP VIEW)
DQ15
VSSQ
VDDQ
DQ14
DQ13
VDDQ
VSSQ
DQ12
DQ11
VSSQ
VDDQ
DQ10
VDDQ
VSSQ
LDQM
UDQM
A10/
Package Dimension
Preliminary W987Y6CB
BALL DESCRIPTION
NUMBER BALL NAME FUNCTION Address DESCRIPTION Multiplexed pins column address. address: A11. Column address: Select bank activate during address latch time, bank read/write during address latch time.
BS0,
Bank Select
DQ15
Data Input/ Output
Multiplexed pins data output input.
Chip Select
Disable enable command decoder. When command decoder disabled, command ignored previous operation continues. Command input. When sampled rising edge clock, define operation executed.
Address Strobe
UDQM LDQM
Column Address Strobe Referred Write Enable Input/Output Mask Referred output buffer placed Hi-Z (with latency when sampled high read cycle. write cycle, sampling high will block write operation with zero latency. System clock used sample inputs rising edge clock. controls clock activation deactivation. When low, Power Down mode, Suspend mode Self Refresh mode entered. Power input buffers logic circuit inside DRAM. Ground input buffers logic circuit inside DRAM. Separated power from VCC, used output buffers improve noise.
Clock Inputs
Clock Enable
VDDQ VSSQ
Power Ground Power Buffer
Ground Separated ground from VSS, used output buffers Buffer improve noise. Connection connection
Publication Release Date: 2002 Revision
Preliminary W987Y6CB
BLOCK DIAGRAM
CLOCK BUFFER
CONTROL SIGNAL GENERATOR
COMMAND DECODER COLUMN DECODER
COLUMN DECODER
CELL ARRAY BANK
ADDRESS BUFFER
MODE ISTER
CELL ARRAY BANK
IFIER
IFIER
DATA CONTROL CIRCUIT
REFRESH COUNTER COLUMN COUNTER
BUFFER
DQ15 UDQM LDQM
COLUMN DECODER
COLUMN DECODER
CELL ARRAY BANK
CELL ARRAY BANK
IFIER
IFIER
Note: cell array configuration 4096
Preliminary W987Y6CB
ABSOLUTE MAXIMUM RATINGS
PARAMETER Input/Output Voltage Power Supply Voltage Operating Temperature (Commercial parts) Operating Temperature (Industrial parts) Storage Temperature Soldering Temperature (10s) Power Dissipation Short Circuit Output Current SYMBOL VIN, VOUT VDD, VDDQ TOPR TOPR TSTG TSOLDER IOUT RATING -0.3 +0.3 -0.3 UNIT NOTE
Note: Exposure conditions beyond those listed under Absolute Maximum Ratings adversely affect life reliability device.
ELECTRICAL CHARACTERISTICS OPERATING CONDITIONS
70°C commercial parts, -40°C 85°C Industrial parts)
PARAMETER Supply Voltage Supply Voltage (for Buffer) Input High level Voltage Input level Voltage LVTTL Output Level Voltage (IOUT -0.1 LVTTL Output Level Voltage (IOUT +0.1 Input Leakage Current VDD, other pins under test Output Leakage Current (Output disable VOUT VCCQ)
Note: (max.) VDD/ VDDQ +1.2V pulse width (min.) VSS/ VSSQ -1.2V pulse width
SYM. VDDQ
MIN. 0.8*VDDQ -0.3 VDDQ
TYP.
MAX. VDDQ +0.3 0.2*VDDQ
UNIT
II(L)
IO(L)
Publication Release Date: 2002 Revision
Preliminary W987Y6CB
CAPACITANCE
(VDD 2.5V, MHz,
PARAMETER Input Capacitance
A11, BS0, BS1, DQM, CKE)
SYMBOL
MIN.
MAX.
UNIT
Input Capacitance (CLK) Input/Output Capacitance
Note: These parameters periodically sampled 100% tested.
CCLK
OPERATING CURRENT
(VDD 2.5V ±0.2V, commercial parts, -40° Industrial parts)
PARAMETER Operating Current
min., min. Active precharge command cycling without burst operation
SYM. bank operation ICC1
-75/75I
MAX.
-8/-8I
MAX.
UNIT
NOTES
Standby Current
min, (min.)/ (max.) Bank: Inactive state
(Power Down mode)
ICC2 ICC2P ICC2S ICC2PS ICC3 ICC3P ICC4 ICC5 ICC6 ICC7
0.35
0.35
Standby Current
VIL, (min.)/ (max.) BANK: Inactive state
(Power down mode)
Operating Current
min., (min.)
(Power down mode)
BANK: Active state
banks)
Burst Operating Current
min. Read/ Write command cycling
Auto Refresh Current
min. Auto refresh command cycling
Self Refresh Current
Self Refresh Mode 0.2V
Deep Power Down Mode Current
Preliminary W987Y6CB
CHARACTERISTICS OPERATING CONDITION
(Vcc 2.5V 0.2V, 70°C commercial parts -40°C 85°C Industrial parts; Notes:
PARAMETER Ref/Active Ref/Active Command Period Active precharge Command Period Active Read/Write Command Delay Time Read/Write(a) Read/Write(b)Command Period Precharge Active Command Period Active(a) Active(b) Command Period Write Recovery Time Cycle Time High Level width Level width Access Time from Output Data Hold Time Output Data High Impedance Time Output Data Impedance Time Power Down Mode Entry Time Transition Time (Rise Fall) Data-in Set-up Time Data-in Hold Time Address Set-up Time Address Hold Time Set-up Time Hold Time Command Set-up Time Command Hold Time Refresh Time Mode Register Cycle Time
Latency
SYM. tRAS tRCD tCCD tRRD tCKS tCKH tCMS tCMH tREF tRSC
-75/75I MIN. MAX. MIN. 100000
-8/-8I MAX.
UNIT
100000
Cycle
Publication Release Date: 2002 Revision
Preliminary W987Y6CB
Notes: Operation exceeds "ABSOLUTE MAXIMUM RATING" adversely affect life reliability devices. voltages referenced These parameters depend cycle rate listed values measured cycle rate with minimum values tRC. These parameters depend output loading conditions. specified values obtained with output open. Power sequence further described "Functional Description" section. Testing Conditions Output Reference Level Output Load Input Signal Levels Transition Time (Rise Fall) Input Signal Input Reference Level VDDQ diagram below 0.8* VDDQ 0.2* VDDQ VDDQ
VDDQ
ohms
output
ohms 30pF
TEST LOAD
Transition times measured between VIL. defines time which outputs achieve open circuit condition referenced output level. value that shown table based silicon simulation result. will changed according real product characteristic.
Preliminary W987Y6CB
Operation Mode
Fully synchronous operations performed latch commands positive edges CLK. Table shows truth table operation commands. Table Truth Table (Note (1), (2))
COMMAND Bank Active Bank Precharge Precharge Write Write with Autoprecharge Read Read with Autoprecharge Mode Register Operation Burst Stop Device Deselect Auto Refresh Self Refresh Entry Self Refresh Exit Clock Suspend Entry Power Down Entry Clock Suspend Exit Power Down Exit Deep Power Down Entry Deep Power Down Exit Data write/Output Enable Data write/Output Disable Notes: Valid Don't care Level High Level CKEn signal input level when commands provided. CKEn-1 signal input level clock cycle before command issued. These state bank designated BS0, signals. Device state full page burst operation. Power Down Mode entered burst cycle. When this command asserts burst cycle, device state clock suspend mode. DEVICE STATE Idle Active Active Active Active Idle Active Idle Idle idle (S.R.) Active Idle Active Active (power down) Idle DPDM Active Active CKEn-1 CKEn BS0,
Publication Release Date: 2002 Revision
Preliminary W987Y6CB
FUNCTIONAL DESCRIPTION
Power Sequence
default power state mode register unspecified. following power initialization sequence need followed guarantee device being preconditioned each user specific needs. During power VDDQ pins must ramp simultaneously specified voltage when input signals held "NOP" state. power voltage must exceed +0.3V input pins supplies. After power initial pause required followed precharge banks using precharge command. prevent data contention during power required that pins held high during initial pause period. Once banks have been precharged, Mode Register Command must issued initialize Mode Register. additional eight Auto Refresh cycles (CBR) also required before after programming Mode Register ensure proper subsequent operation.
Command Function
Bank Activate command
"L", "H", ="H", BS0, Bank, Address) Bank Activate command activates bank designated (Bank select) signal. addresses latched when this command issued cell data read sense amplifiers. maximum time that each bank held active state specified tRAS (max). After this command issued, Read Write operation executed.
Bank Precharge command
="L", ="H", ="L", BS0, Bank, ="L", Don't care) Bank Precharge command percharges bank designated precharged bank switched from active state idle state.
Precharge command
="L", ="H", ="L", BS0, Don't care, "H", Don't care) Precharge command precharges banks simultaneously. Then banks switched idle state.
Write command
="H", ="L", ="L", BS0, Bank, ="L", Column Address) write command performs Write operation bank designated write data latched rising edge CLK. length write data (Burst Length) column access sequence (Addressing Mode) must programmed Mode Register power-up prior Write operation.
Preliminary W987Y6CB
Write with Auto Precharge command
="H", ="L", ="L", BS0, Bank, A10="H", Column Address) Write with Auto Precharge command performs Precharge operation automatically after Write operation. This command must interrupted other commands.
Read command
="H", ="L", ="H", BS0, Bank, ="L", Column Address) Read command performs Read operation bank designated length read data (Burst Length), Addressing Mode Latency (access time from command clock cycle) must programmed Mode Register power-up prior Read operation.
Read with Auto Precharge command
="H", ="L", ="H", BS0, Bank, ="H", Column Address) Read with Auto precharge command automatically performs Precharge operation after Read operation. This command must interrupted other command.
Mode Register command
="L", ="L", ="L", ="L", ="L", Register Data) Mode Register command programs values Burst Length, Addressing Mode, latency Write Mode Mode Register. default values Mode Register after power-up undefined, therefore this command must issued during power-up sequence. Also, this command issued while banks idle state. Refer table specific codes.
Extended Mode Register command
="L", ="L", ="L", ="L", ="H", Register data) Extended Mode Register command programs values Driver Strength, Temperature Compensated Self Refresh Partial Array Self Refresh. default value extended mode register Full Driver Strength, degrees banks Refreshed
No-Operation command
="H", ="H", ="H") No-Operation command simply performs operation (same command Device Deselect).
Burst Read stop command
="H", ="H", ="L") Burst stop command used stop burst operation. This command only valid during Burst Read operation.
Publication Release Date: 2002 Revision
Preliminary W987Y6CB
Device Deselect command
="H") Device Deselect command disables command decoder that Address inputs ignored. This command similar No-Operation command.
Auto Refresh command
="L", ="L", ="H", ="H", BS0, BS1, Don't care) Auto Refresh command used refresh address provided internal refresh counter. Refresh operation must performed 4096 times within 64ms. next command issued after from Auto Refresh command. When Auto Refresh command used, banks must idle state.
Self Refresh Entry command
="L", ="L", ="H", CKE="L", BS0, BS1, don't care) Self Refresh Entry command used enter Self Refresh mode. While device Self Refresh mode, input output buffer (except buffer) disabled Refresh operation automatically performed. Self Refresh mode exited taking "high" (the Self Refresh Exit command).
Self Refresh Exit command
(CKE during SDRAM Self Refresh Mode) This command used exit from Self Refresh mode. subsequent commands issued after from this command.
Deep Power Down Mode Entry command
="H", ="H", ="L", ="L", BS0, BS1, don't care) Deep Power Down Mode Entry command used enter Deep Power Down mode. While device Deep Power Down mode, internal circuits (except buffer) disabled order 10uA current consumption.
Deep Power Down Mode Exit command
(CKE= during SDRAM Deep Power Down Mode) This command used exit from Deep Power Down mode. Full initialization required when device exits from Deep Power Down Mode.
Data Write Enable /Disable command
(LDQM, UDQM ="L/H") During Write cycle, LDQM UDQM signal functions Data Mask control every word input data. LDQM signal controls UDQM signal controls DQ15.
Preliminary W987Y6CB
Read Operation
Issuing Bank Activate command idle bank puts into active state. When Read command issued after tRCD from Bank Activate command, data read sequentially. address inputs determine starting column address burst. initial read data becomes available after latency from issuing Read command. latency must Mode Register power-up. When Precharge Operation performed bank during Burst Read operation, Burst operation terminated. When Read with Auto Precharge command issued, Precharge operation performed automatically after Read cycle, then bank switched idle state. This command cannot interrupted other commands. Refer diagrams Read operation.
Write Operation
Issuing Write command after tRCD from bank activate command. address inputs determine starting column address. Data first burst write cycle must applied pins same clock cycle that Write Command issued. remaining data inputs must supplied each subsequent rising clock edge until burst length completed. Data supplied pins after burst finishes will ignored. burst length Write data (Burst Length) Addressing Mode must Mode Register power-up. When Precharge operation performed bank during Burst Write operation, Burst operation terminated. When Write with Auto Precharge command issued, Precharge operation performed automatically after Write cycle, then bank switched idle state, Write with Auto Precharge command cannot interrupted other command entire burst data duration.
Precharge
Precharge Command used precharge close bank that been activated. Precharge Command entered when high rising edge clock. Precharge Command used precharge each bank separately banks simultaneously. Three address bits, A10, BS0, BS1, used define which bank(s) precharged when command issued. After Precharge Command issued, precharged bank must reactivated before read write access executed. delay between Precharge Command Activate Command must greater than equal Precharge time (tRP).
Burst Termination
When Precharge command used bank Burst cycle, Burst operation terminated. When Burst Read cycle interrupted Precharge command, read operation disabled after clock cycle latency) from Precharge command. When Burst Write cycle interrupted Precharge command input circuit reset same clock cycle which precharge command issued. this case, signal must asserted "high" during prevent writing invalided data cell array.
Publication Release Date: 2002 Revision
Preliminary W987Y6CB
When Burst Read Stop command issued bank Burst Read cycle, Burst Read operation terminated. Burst read Stop command supported during write burst operation.
Interruption
Read Interrupted Read
Burst Read interrupted another Read Command. When previous burst interrupted, remaining addresses overridden read address with full burst length. data from first Read Command continues appear outputs until latency from interrupting Read Command satisfied.
Read Interrupted Write
interrupt burst read with Write Command, needed place (output drivers) high impedance state avoid data contention bus. Read Command will issue data first second clocks cycles write operation, needed insure tri-stated. After that point Write Command will have control masking longer needed.
Write Interrupted Write
burst write interrupted before completion burst another Write Command. When previous burst interrupted, remaining addresses overridden address data will written into device until programmed burst length satisfied.
Write Interrupted Read
Read Command will interrupt burst write operation same clock cycle that Read Command activated. must high impedance state least cycle before read data appears outputs avoid data contention. When Read Command activated, residual data from burst write cycle will ignored.
Refresh Operation
types Refresh operation performed device: Auto Refresh Self Refresh. repeating Auto Refresh cycle, each bank turn refreshed automatically. Refresh operation must performed 4096 times (rows) within 64ms. period between Auto Refresh command next command specified tRC. Self Refresh Mode entered issuing Self Refresh Entry Command rising edge clock. banks must idle prior issuing Self Refresh Entry Command. Once command registered, must held keep device Self Refresh mode. When SDRAM entered Self Refresh mode external control signals, except CKE, disabled. clock internally disabled during Self Refresh Operation save power. device will exit Self Refresh operation after returned high. minimum delay time required when device exits Self Refresh Operation before next command issued. This delay equal cycle time plus Self Refresh exit time. during normal operation, AUTO REFRESH cycles issued bursts opposed being evenly distributed), burst 4,096 AUTO REFRESH cycles should completed just prior entering just after exiting self refresh mode.
Preliminary W987Y6CB
Power Down Mode
Power Down mode initiated holding low. receiver circuits except gated reduce power. Power Down mode does perform refresh operations, therefore device remain Power Down mode longer than Refresh period (tREF) device.
Mode Register Operation
mode register programmed Mode Register command (MRS/EMRS) when banks idle state. data Mode Register transferred using Address pins inputs. combination BS0, detains this cycle EMRS.
Mode Register Description
Mode Register designates operation mode read write cycle. register divided into four fields; Burst Length field sets length burst data Addressing Mode selection designate column access sequence Burst cycle Latency field sets access time clock cycle Single Write Mode selection designate write operation burst single write.
Defines cycls (Test Mode) Reserved Write Mode Reserved Latency Addressing Mode Burst Length
BurstA0 Length Sequential Interleave Reserved FullA0 Page Addressing Mode Sequential Interleave Reserved
Latency Reserved Reserved Reserved Single Write Mode Burst read Burst write Burst read single write
Mode Register Definition
Publication Release Date: 2002 Revision
Preliminary W987Y6CB
Address sequence Sequential mode column access performed incrementing column address input device. address varied Burst Length following. Addressing Sequence Sequential Mode DATA Data Data Data Data Data Data Data Data ACCESS ADDRESS words(address bits carried from BURST LENGTH words (address bits carried from words (address carried from
Addressing sequence Interleave mode Column access started from inputted column address performed interleaving address bits sequence shown following. Address Sequence Interleave Mode DATA Data Data Data Data Data Data Data Data ACCESS ADDRESS words words BURST LENGTH words
Preliminary W987Y6CB
Simplified State Diagram
Self Refresh
Mode Register
IDLE
Refresh
Power Down ACTIVE
Active Power Down
Writ arge
arge
Write WRITE
Read READ READ SUSPEND
WRITE SUSPEND
Read
Write
term inat ion)
ion) inat term
WRITEA SUSPEND
WRITEA
READA
READA SUSPEND
POWER
Precharge
Precharge
Automatic sequence Manual input
Notes: Mode Register Refresh Active Precharge WRITEA Write with Auto precharge READA Read with Auto precharge
Publication Release Date: 2002 Revision
Preliminary W987Y6CB
TIMING WAVEFORMS
Command Input Timing
tCMS tCMH tCMH tCMS
tCMS
tCMH
tCMS
tCMH
tCMS
tCMH
A0-A11 BS0,
tCKS
tCKH
tCKS
tCKH
tCKS
tCKH
Preliminary W987Y6CB
Timing Waveforms, continued
Read Timing
Read Latency
A0-A11 BS0,
Valid Data-Out
Read Command
Valid Data-Out
Burst Length
Publication Release Date: 2002 Revision
Preliminary W987Y6CB
Timing Waveforms, continued
Control Timing Input Output Data
Control Timing Input Data
(Word Mask)
tCMH tCMS tCMH tCMS
Valid Data-in
Valid Data-in
Valid Data-in
Valid Data-in
(Clock Mask)
tCKH tCKS tCKH tCKS
Valid Data-in
Valid Data-in
Valid Data-in
Valid Data-in
Control Timing Output Data
(Output Enable)
tCMH tCMS tCMH tCMS
Valid Data-Out
Valid Data-Out
Valid Data-Out
OPEN
(Clock Mask)
tCKH tCKS tCKH tCKS
Valid Data-Out Valid Data-Out
Valid Data-Out
Preliminary W987Y6CB
Timing Waveforms, continued
Mode Register Cycle
tCMH
tCMS tCMH
tCMS tCMH
Register data
A0-A11 BS0,1
Reserved (Test Mode) Reserved Write Mode Latency Addressing Mode Burst Length
next command BurstA0 Length Sequential Interleave Reserved FullA0 Page Addressing Mode Sequential Interleave Reserved
Latency Reserved Reserved Reserved Single Write Mode Burst read Burst write Burst read single write
Publication Release Date: 2002 Revision
Preliminary W987Y6CB
OPERATING TIMING EXAMPLE
Interleaved Bank Read (Burst Length Latency
(CLK MHz)
tRAS tRAS
tRAS tRAS
tRCD tRCD
tRCD
tRCD
A0-A9,
tRRD
tRRD
tRRD
tRRD
Bank Active Bank Bank Idle Bank
Read Active
Precharge Read
Active
Read Precharge Active
Precharge Read
Active
Preliminary W987Y6CB
Operating Timing Example, contined
Interleaved Bank Read (Burst Length Latency Autoprecharge)
(CLK MHz)
tRAS tRAS
tRAS tRAS
tRCD tRCD
tRCD
tRCD
A0-A9,
tRRD
tRRD
tRRD
tRRD
Bank Bank Bank Idle Bank
Active
Read Active
Read
Active
Read Active
Read
Active
internal precharge start timing
Publication Release Date: 2002 Revision
Preliminary W987Y6CB
Operating Timing Example, contined
Interleaved Bank Read (Burst Length Latency
(CLK MHz)
tRAS tRAS tRAS
tRCD tRCD
tRCD
A0-A9,
tRRD
tRRD
Bank Bank Bank
Active
Read Precharge Active Read
Precharge
Active
Read Precharge
Idle Bank
Preliminary W987Y6CB
Operating Timing Example, contined
Interleaved Bank Read (Burst Length Latency Autoprecharge)
(CLK MHz)
tRAS tRAS tRAS
tRCD tRCD
tRCD
A0-A9,
tCAC
tCAC
tCAC
tRRD
tRRD
Bank Bank Bank
Active
Read Active
Read
Active
Read
Idle Bank internal precharge start timing
Publication Release Date: 2002 Revision
Preliminary W987Y6CB
Operating Timing Example, contined
Interleaved Bank Write (Burst Length
(CLK MHz)
tRAS tRAS tRAS
tRCD tRCD tRCD
A0-A9,
tRRD
tRRD
Bank Bank Bank Bank
Active
Write Active Write
Precharge
Active
Write Precharge
Idle
Preliminary W987Y6CB
Operating Timing Example, contined
Interleaved Bank Write (Burst Length Autoprecharge)
(CLK MHz)
tRAS tRAS tRAS
tRCD
tRCD
tRCD
A0-A9,
tRRD
tRRD
Bank Active Bank Bank Idle Bank
Write Active
Write
Active
Write
internal precharge start timing
Publication Release Date: 2002 Revision
Preliminary W987Y6CB
Operating Timing Example, contined
Page Mode Read (Burst Length Latency
(CLK MHz)
tCCD tCCD tCCD
tRAS tRAS
tRCD tRCD
A0-A9,
tRRD
Bank Active Bank Bank Idle Bank
Read Active Read
Read
Read Read
Precharge
internal precharge start timing
Preliminary W987Y6CB
Operating Timing Example, contined
Page Mode Read Write (Burst Length Latency
(CLK MHz)
tRAS
tRCD
A0-A9,
Bank Bank Bank Bank
Active
Read
Write
Precharge
Idle
Publication Release Date: 2002 Revision
Preliminary W987Y6CB
Operating Timing Example, contined
Auto Precharge Read (Burst Length Latency
(CLK MHz)
tRAS tRAS
tRCD tRCD
A0-A9,
Bank Bank Bank
Active
Read
Active
Read
Idle Bank internal precharge start timing
Preliminary W987Y6CB
Operating Timing Example, contined
Auto Precharge Write (Burst Length
(CLK MHz)
tRAS tRAS
tRCD tRCD
A0-A9,
Bank Bank Bank
Active
Write
Active
Write
Active
Idle Bank internal precharge start timing
Publication Release Date: 2002 Revision
Preliminary W987Y6CB
Operating Timing Example, contined
Auto Refresh Cycle
(CLK MHz)
BS0,1
A0-A9,
Banks Prechage
Auto Refresh
Auto Refresh (Arbitrary Cycle)
Preliminary W987Y6CB
Operating Timing Example, contined
Self Refresh Cycle
(CLK MHz)
BS0,1
A0-A9,
tCKS
tCKS
tCKS
Self Refresh Cycle
Operation Cycle
Banks Precharge
Self Refresh Entry
Arbitrary Cycle
Publication Release Date: 2002 Revision
Preliminary W987Y6CB
Operating Timing Example, contined
Burst Read Single Write (Burst Length Latency
(CLK MHz)
tRCD
A0-A9,
Bank Active Bank Bank Bank Idle
Read
Single Write Read
Preliminary W987Y6CB
Operating Timing Example, contined
PowerDown Mode
(CLK MHz)
A0-A9
tCKS tCKS
tCKS
tCKS
Active
Read Active Standby Power Down mode
Precharge
NOPActive Precharge Standby Power Down mode
Note: PowerDown Mode entered asserting "low". Input/Output buffers (except buffers) turned PowerDown mode. When goes high, command input must operation next rising edge.
Publication Release Date: 2002 Revision
Preliminary W987Y6CB
Operating Timing Example, contined
Autoprecharge Timing (Read Cycle)
Latency=2
burst length Command
Read
burst length Command
Read
burst length Command
Read Read
burst length Command
Latency=3
burst length Command
Read
burst length Command
Read
burst length Command
Read Read
burst length Command
Note
Read
represents Read with Auto precharge command. represents start internal precharging. represents Bank Activate command.
When Auto precharge command asserted, period from Bank Activate command start internal precgarging must least (min).
Preliminary W987Y6CB
Operating Timing Example, contined
Autoprecharge Timing (Write Cycle)
Latency=2
burst length Command
Write
burst length Command
Write
burst length Command
Write
burst length Command
Write
Latency=3
burst length Command
Write
burst length Command
Write
burst length Command
Write
burst length Command
Write
Note Write
represents Write with Auto precharge command. represents start internal precharging. represents Bank Activate command.
When Auto precharge command asserted, period from Bank Activate command start internal precgarging must least tRAS (min).
Publication Release Date: 2002 Revision
Preliminary W987Y6CB
Operating Timing Example, contined
Timing Chart Read Write Cycle
case Burst Length
Latency=2
Command
Read Write
Read
Write
Command
Latency=3
Command
Read Write Read Write
Command
Note: Output data must masked avoid conflict
Timing Chart Write Read Cycle
case Burst Length=4
Latency=2
Command Command
Write Read Write Read
Latency=3
Command Command
Write Read Write Read
Preliminary W987Y6CB
Operating Timing Example, contined
Timing Chart Burst Stop Cycle (Burst Stop Command)
Read cycle latency
Command
Read Read
)CAS latency
Command
Write cycle
Command
Write
Note:
represents Burst stop command
Timing Chart Burst Stop Cycle (Precharge Command)
case Burst Lenght
Read cycle
)CAS latency
Command
Read Read
PRCG
PRCG
)CAS latency
Command
Write cycle
latency
Command
Write
PRCG
Write
PRCG
)CAS latency
Command
Publication Release Date: 2002 Revision
Preliminary W987Y6CB
Operating Timing Example, contined
CKE/DQM Input Timing (Write Cycle)
cycle
External Internal
MASK
MASK
cycle
External Internal
MASK
MASK
cycle External Internal
MASK
Preliminary W987Y6CB
Operating Timing Example, contined
CKE/DQM Input Timing (Read Cycle)
cycle
External Internal
Open Open
cycle
External Internal
Open
cycle
External Internal
Publication Release Date: 2002 Revision
Preliminary W987Y6CB
Operating Timing Example, contined
Self Refresh/Power Down Mode Exit Timing
Asynchronous Control Input Buffer turn time Power down mode exit time specified tCKS(min) tCK(min) tCKS(min)+t CK(min)
tCKS(min)+tCK(min)
Command
Command
Input Buffer Enable
tCKS(min) (min)
tCKS(min)+tCK(min)
Command
Command
Input Buffer Enable
Note Input Buffer(Include Buffer) turned Power Down mode Self Refresh mode
Command
Represents No-Operation command Represents command
Preliminary W987Y6CB
PACKAGE DIMENSION
FBGA Balls mm^3, 0.40
Publication Release Date: 2002 Revision
Preliminary W987Y6CB
REVISION HISTORY
VERSION DATE 2002 PAGE Initial Issued DESCRIPTION
Headquarters
Creation III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/
Winbond Electronics Corporation America
2727 North First Street, Jose, 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441798
Winbond Electronics (Shanghai) Ltd.
27F, 2299 Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998
Taipei Office
No.480, Rueiguang Rd., Neihu Chiu, Taipei, 114, Taiwan, R.O.C. TEL: 886-2-8177-7168 FAX: 886-2-8751-3579
Winbond Electronics Corporation Japan
Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800
Winbond Electronics (H.K.) Ltd.
Unit 9-15, 22F, Millennium City, Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064
Please note that data specifications subject change without notice. trade marks products companies mentioned this data sheet belong their respective owners.

Publication Release Date: 2002 Revision Preliminary W987Y6CB

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