C8237 programmable controller megafunction peripheral interface circui

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C8237 programmable controller megafunction peripheral interface circui

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C8237 Programmable Controller
C8237 programmable controller megafunction peripheral interface circuit microprocessor systems. megafunction designed used conjunction with external 8-bit address latch. contains four independent channels expanded number channels cascading additional controller chips. Each channel full address word count capability.
Enable/Disable control individual requests Four independent channels Independent auto-initialization channels Memory-to-Memory transfers Memory block initialization Address increment decrement Directly expandable number channels process input terminating transfers Software requests Independent polarity control DREQ DACK signals C8237 developed synthesizes approximately 6,900 gates depending technology used. Functionality based Intel 8237
C8237
Symbol
RESET AIN[3:0] READY AOUT[7:0] HLDA DREQ[3:0] DBIN[7:0] ADSTB DBOUT[7:0] MEMRN IORNIN MEMWN IORNOUT DBDIR IOWNIN IOWNOUT DACK[3:0] EOPNIN EOPNOUT
CAST, Inc.
December 2000 A1.0
C8237 Controller Data Sheet
Description
Name RESET READY HLDA DREQ[3:0] DBIN[7:0] AIN[3:0] IORNIN IOWNIN EOPNIN DBOUT[7:0] AOUT[7:0] IORNOUT IOWNOUT EOPNOUT DBDIR Type Polarity High High High Programmable High High Description Clock Chip Select Reset Ready Hold Acknowledge Request Data Input Address Input Read Input Control Signal Write Input Control Signal Process Input Data Output Address Output Read Output Control Signal Write Output Control Signal Process Output Data Tri-state Controller EOPN, Address Tri-state Controller Address Enable Address Strobe Memory Read Memory Write
ADSTB MEMRN MEMWN
High High
CAST, Inc.
C8237 Controller Data Sheet
Block Diagram
Decrementor Temp Word Count Timing Control Incrementor/ Decrementor Temp Address
RESET READY IORNIN IOWNIN EOPNIN ADSTB EOPNOUT MEMRN MEMWN IORNOUT IOWNOUT HLDA
AOUT[7:0]
Channel-3
C8237REG
Channel-2 Channel-1 Channel-0
Read/Write State Machine Current Word Count Register Write Base Word Count Register Base Word Address Register Current Word Address Register
DBOUT(7:0)
DREQ(3:0)
DACK(3:0)
Fixed Priority Rotating Priority Logic
Command Register Mask Register Request Register Mode Register Status Register Temporary Register
DBIN(7:0)
AIN[3:0]
Figure C8237 Programmable Controller Block Diagram
Device Utilization Performance
Target Device EPF10K30A EPF10K100B EPF10K30E EP1K30 EP20K60E Speed Grade Utilization 1121 1128 1121 1121 1011 Performance Fmax Availability
CAST, Inc.
C8237 Controller Data Sheet
Applications
C8237 megafunction designed improve system performance allowing external devices directly transfer information from system memory.
This 8-bit register controls operation C8237. programmed microprocessor cleared Reset Master Clear instruction.
Functional Description
C8237 megafunction partitioned into modules shown figure described below:
Bit0: Memory-to-memory disable Memory-to-memory enable Bit1: Channel address hold disable Channel address hold enable bit0 Bit2: Controller enable Controller disable Bit3: Normal timing Compressed timing Bit4: Fixed priority Rotating priority Bit5: Late write Extended write bit3 Bit6: DREQ sense active high
Timing Control
generates internal timing external control signals C8237. timing Control block derives internal timing from clock input. C8237 operates major cycles, idle cycle (Si) Active cycle (S0, S4). Memory-to-memory transfers require readfrom write-to-memory complete each transfer. requires eight states single transfer. first four states (S11, S12, S13, S14) used read-from -memory half last four states (S21, S22, S23, S24) write-to-memory half transfer. Each state composed full clock period.
Fixed Priority Rotating Priority Logic
Fixed Priority fixes channels priority order based upon descending value their number. lowest priority channel highest priority channel With Rotating Priority, last channel service becomes lowest priority channel with others rotating accordingly.
DREQ sense active Bit7: DACK sense active DACK sense active high
C8237 Registers
C8237 contains bits internal memory form registers. must when microprocessor attempting write read internal registers C8237. Command Register Write Command Register Command:
IORN IOWN
CAST, Inc.
C8237 Controller Data Sheet
Mode Register Write Mode Register Command:
IORN IOWN
IORN
IOWN
Each channel 6-bit Mode register. programmed microprocessor.
Bit1 Bit0: Channel Channel Channel Channel Bit3 Bit2: Verify transfer (pseudo transfer) Write transfer (from memory) Read transfer (from memory I/O) Illegal bits
Each channel request associated with 4-bit Request register. These nonmaskable subject prioritization Priority Encoder. Each register reset separately under software control cleared upon generation external EOPN. entire register cleared Reset. order make software request, channel must Block Mode.
Bit1 Bit0: Channel Channel Channel Channel Bit2: Reset request request
Bit4: Auto initialization disable Auto initialization enable Bit5: Address increment select Address decrement select Bit7 Bit6: Demand mode Single mode Block mode Cascade mode Demand Transfer Mode: device will continue making transfers until external EOPN encountered until DREQ goes inactive. Single Transfer Mode: device makes transfer only. DREQ must held active until DACK becomes active order recognized. Block Transfer Mode: device active DREQ software request continue making transfers during service until external EOPN encountered. DREQ need only held active until DACK becomes active. Cascade Transfer Mode: This mode used cascade more than C8237 together simple system expansion. ready input ignored this cascade transfer mode.
Mask Register Each channel mask associated with which disable incoming DREQ. Each mask when associated channel produces EOPN channel programmed Auto initialize. Each 4-bit Mask register also cleared separately under software control. entire register also Reset. This disables requests until clear Mask register instruction allows them occur.
Request Register Write Request Register Command: CAST, Inc.
C8237 Controller Data Sheet
Programming Mask Register Bits: Write Mask Register Bits Command:
IORN IOWN
Bits whenever their corresponding channel requesting.
Bit0: Channel reached
Bit1: Channel reached Bit2: Channel reached Bit3: Channel reached Bit4: Channel request Bit5: Channel request Bit6: Channel request Bit7: Channel request
Bit1 Bit0: Channel Channel Channel Channel Bit2: Clear mask mask
Temporary Register Programming Single Mask Register Bits: Write Single Mask Register Command:
IORN IOWN
Read Temporary Register Command:
IORN IOWN
Bit0: Clear channel mask channel mask Bit1: Clear channel mask channel mask Bit2: Clear channel 2-mask channel mask Bit3: Clear channel 3-mask
This register used hold data during memoryto-memory transfers. Following completion transfers, last word moved read microprocessor. temporary register cleared Reset. Current Address Register Each channel 16-bit Current Address register. This register holds value address used during transfers. address automatically incremented decremented after each transfer intermediate values address stored Current Address register during transfer. This register written read microprocessor. Current Word Register
channel mask Status Register Read Status Register Command:
IORN IOWN
This register available read C8237 microprocessor. contains information about status devices this point. Bits when that channel reaches external EOPN applied. These bits cleared upon Reset each Status Read.
Each channel 16-bit Current Word Count register. This register determines number transfers performed. word count decremented after each transfer. When value register goes from zero FFFFH, will generated. This register loaded read microprocessor Program Condition. Base Address Base Word Count Registers Each channel 16-bit Base Address 16bit Base Word Count register. These registers
CAST, Inc.
C8237 Controller Data Sheet
store original value, which will loaded current registers during Auto initialize. Word Count Address Register Command Codes Write IORN IOWN Read IORN IOWN
Register Base Current Address Base Current Word Count Base Current Address Base Current Word Count Base Current Address Base Current Word Count Base Current Address Base Current Word Count W8-W15 A8-A15 W0-W7 W8-W15 A0-A7 A8-A15 W0-W7 W8-W15 A0-A7 A8-A15 W0-W7 W8-W15 A0-A7 A8-A15 W0-W7 DB0-DB7 A0-A7
registers cleared Mask register set. C8237 will idle cycle.
Clear Mask Register Command:
IORN IOWN
This command clears mask bits four channels, enabling them accept requests.
Temporary Word Count Register Decrementor)
will decrement word count after each transfer. When value register goes from zero FFFFH, Terminal Count (TC) will generated.
Temporary Address Register Incrementor/Decrementor)
Base mode address, address will decremented incremented after each transfer. intermediate values address stored Current Address register during transfer.
Software Commands
These three commands depend specific pattern data bus. Clear First/Last Flip-Flop Command:
IORN IOWN
Verification Methods
C8237 megafunction's functionality verified means proprietary hardware modeler. same stimulus applied hardware model that contained original Intel 8237 chip, results compared with megafunction's simulation outputs.
This command must executed prior writing reading address word count information C8237. Master Clear Command:
IORN IOWN
This command same effect hardware Reset. Command, Status, Request, Temporary, Internal First/Last Flip-Flop CAST, Inc.
C8237 Controller Data Sheet
Deliverables
Encrypted Licenses Post-synthesis AHDL Assignment Configuration Symbol file Include file Vectors testing functionality megafunction Source Licenses VHDL Verilog source code Testbench Example testbench wrapper post-route simulation Vectors testbench Simulation synthesis script Expected results testbench
Related Information
Intel 8237 High Performance Programmable Controller Contact: Intel Corporation P.O. 7641 Prospect, 60056-7641 Phone: 800-548-4725 URL: www.intel.com
CAST, Inc.
Stonewall Court Woodcliff Lake, Jersey 07677 Phone: 845-353-6160 Fax: 845-727-7607 E-Mail: info@cast-inc.com www.cast-inc.com Copyright 2000 CAST, Inc. RIGHTS RESERVED
CAST, Inc.

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