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8K-64K/256-1K OTP/ROM/ROMless, voltage (2.7V-5.5V), power, high speed


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8XC54/58 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA 80C51 8-bit microcontroller family
8K-64K/256-1K OTP/ROM/ROMless, voltage (2.7V-5.5V), power, high speed MHz)
Replaces datasheet 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA 1999
2000
Philips Semiconductors
Philips Semiconductors
80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, voltage (2.7V-5.5V), power, high speed MHz)
8XC54/58 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+
DESCRIPTION
Three different Single-Chip 8-Bit Microcontroller families presented this datasheet:
FEATURES
8XC54/8XC58 80C51FA/8XC51FA/8XC51FB/8XC51FC
applications requiring ROM/EPROM, 8XC51/80C31 8-bit CMOS (low voltage, power, high speed) microcontroller families datasheet. families Single-Chip 8-Bit Microcontrollers manufactured advanced CMOS process derivatives 80C51 microcontroller family. devices have same instruction 80C51. These devices provide architectural enhancements that make them applicable variety applications general control systems. ROM/EPROM Memory Size 80C31/8XC51 0K/4K 8XC54/58 0K/8K/16K/32K Size Programmable Timer Counter (PCA) Hardware Watch Timer
80C51 Central Processing Unit Speed Full static operation Operating voltage range: Security bits:
bits OTP-EPROM bits
Encryption array bytes expandable bytes level priority interrupt interrupt sources, depending device Four 8-bit ports Full-duplex enhanced UART
Framing error detection Automatic address recognition
Power control modes
Clock stopped resumed Idle mode Power down mode
80C51FA/8XC51FA/FB/FC 0K/8K/16K/32K
80C51RA+/8XC51RA+/RB+/RC+ 0K/8K/16K/32K 8XC51RD+ 1024
Programmable clock Second DPTR register Asynchronous port reset (inhibit ALE)
ROMless devices, 80C51FA, 80C51RA+ address external memory. devices have four 8-bit ports, three 16-bit timer/event counters, multi-source, four-priority-level, nested interrupt structure, enhanced UART on-chip oscillator timing circuits. systems that require extra memory capability bytes, each expanded using standard TTL-compatible memories logic. added features make even more powerful microcontroller applications that require pulse width modulation, high-speed up/down counting capabilities such motor control. also more versatile serial channel that facilitates multiprocessor communications.
2000
853-2068 24292
Philips Semiconductors
80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, voltage (2.7V-5.5V), power, high speed MHz)
8XC54/58 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+
BLOCK DIAGRAM
P0.0-P0.7 P2.0-P2.7
PORT DRIVERS ADDR REGISTER PORT LATCH
PORT DRIVERS
PORT LATCH
ROM/EPROM
REGISTER STACK POINTER
TMP2
TMP1
PROGRAM ADDRESS REGISTER
SFRs TIMERS P.C.A. only)
BUFFER
INCREMENTER PROGRAM COUNTER
PSEN ALE/PROG EAVPP TIMING CONTROL
INSTRUCTION REGISTER
DPTR'S MULTIPLE
PORT LATCH
PORT LATCH
OSCILLATOR PORT DRIVERS XTAL1 XTAL2 P1.0-P1.7 PORT DRIVERS
P3.0-P3.7
SU00831B
2000
Philips Semiconductors
80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, voltage (2.7V-5.5V), power, high speed MHz)
8XC54/58 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+
LOGIC SYMBOL
XTAL1 PORT ADDRESS DATA
PLASTIC LEADED CHIP CARRIER FUNCTIONS
XTAL2 T2EX PORT EA/VPP PSEN SECONDARY FUNCTIONS ALE/PROG INT0 INT1
Function NIC* P1.0/T2 P1.1/T2EX P1.2/ECI P1.3/CEX0 P1.4/CEX1 P1.5/CEX2 P1.6/CEX3 P1.7/CEX4 P3.0/RxD NIC* P3.1/TxD P3.2/INT0 P3.3/INT1 Function P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD XTAL2 XTAL1 NIC* P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14
Function P2.7/A15 PSEN ALE/PROG NIC* EA/VPP P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0
PORT
PORT
ADDRESS
SU00830
CONFIGURATIONS DUAL IN-LINE PACKAGE FUNCTIONS
T2/P1.0 T2EX/P1.1 ECI/P1.2 CEX0/P1.3 CEX1/P1.4 CEX2/P1.5 CEX3/P1.6 CEX4/P1.7 RxD/P3.0 TxD/P3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5 WR/P3.6 RD/P3.7 XTAL2 XTAL1 DUAL IN-LINE PACKAGE P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA/VPP ALE/PROG PSEN P2.7/A15 P2.6/A14 P2.5/A13 P2.4/A12 P2.3/A11 P2.2/A10 P2.1/A9 P2.0/A8
INTERNAL CONNECTION
SU00023
PLASTIC QUAD FLAT PACK FUNCTIONS
PQFP
Function P1.5/CEX2 P1.6/CEX3 P1.7/CEX4 P3.0/RxD NIC* P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD XTAL2 XTAL1 Function NIC* P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 PSEN ALE/PROG NIC* EA/VPP P0.7/AD7
Function P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 NIC* P1.0/T2 P1.1/T2EX P1.2/ECI P1.3/CEX0 P1.4/CEX1
SU00021
INTERNAL CONNECTION
SU00024
2000
Philips Semiconductors
80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, voltage (2.7V-5.5V), power, high speed MHz)
8XC54/58 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+
DESCRIPTIONS
NUMBER MNEMONIC P0.0-0.7 39-32 43-36 37-30 TYPE NAME FUNCTION Ground: reference. Power Supply: This power supply voltage normal, idle, power-down operation. Port Port open-drain, bidirectional port. Port pins that have written them float used high-impedance inputs. Port also multiplexed low-order address data during accesses external program data memory. this application, uses strong internal pull-ups when emitting Port also outputs code bytes during program verification received code bytes during EPROM programming. External pull-ups required during program verification. Port Port 8-bit bidirectional port with internal pull-ups. Port pins that have written them pulled high internal pull-ups used inputs. inputs, port pins that externally pulled will source current because internal pull-ups. (See Electrical Characteristics: IIL). Port also receives low-order address byte during program memory verification. Alternate functions 8XC51FX 8XC51RX+ Port include: (P1.0): Timer/Counter external count input/Clockout (see Programmable Clock-Out) T2EX (P1.1): Timer/Counter Reload/Capture/Direction Control (P1.2): External Clock Input CEX0 (P1.3): Capture/Compare External module CEX1 (P1.4): Capture/Compare External module CEX2 (P1.5): Capture/Compare External module CEX3 (P1.6): Capture/Compare External module CEX4 (P1.7): Capture/Compare External module Port Port 8-bit bidirectional port with internal pull-ups. Port pins that have written them pulled high internal pull-ups used inputs. inputs, port pins that externally being pulled will source current because internal pull-ups. (See Electrical Characteristics: IIL). Port emits high-order address byte during fetches from external program memory during accesses external data memory that 16-bit addresses (MOVX @DPTR). this application, uses strong internal pull-ups when emitting During accesses external data memory that 8-bit addresses (MOV @Ri), port emits contents special function register. Some Port pins receive high order address bits during EPROM programming verification. Port Port 8-bit bidirectional port with internal pull-ups. Port pins that have written them pulled high internal pull-ups used inputs. inputs, port pins that externally being pulled will source current because pull-ups. (See Electrical Characteristics: IIL). Port also serves special features 80C51 family, listed below: (P3.0): Serial input port (P3.1): Serial output port INT0 (P3.2): External interrupt INT1 (P3.3): External interrupt (P3.4): Timer external input (P3.5): Timer external input (P3.6): External data memory write strobe (P3.7): External data memory read strobe Reset: high this machine cycles while oscillator running, resets device. internal diffused resistor permits power-on reset using only external capacitor VCC. Address Latch Enable/Program Pulse: Output pulse latching byte address during access external memory. normal operation, emitted constant rate oscillator frequency, used external timing clocking. Note that pulse skipped during each access external data memory. This also program pulse input (PROG) during EPROM programming. disabled setting auxiliary.0. With this set, will active only during MOVX instruction.
P1.0-P1.7
40-44,
P2.0-P2.7 21-28
24-31
18-25
P3.0-P3.7
10-17
13-19
7-13
ALE/PROG
2000
Philips Semiconductors
80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, voltage (2.7V-5.5V), power, high speed MHz)
8XC54/58 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+
DESCRIPTIONS (Continued)
NUMBER MNEMONIC PSEN TYPE NAME FUNCTION Program Store Enable: read strobe external program memory. When executing code from external program memory, PSEN activated twice each machine cycle, except that PSEN activations skipped during each access external data memory. PSEN activated during fetches from internal program memory. External Access Enable/Programming Supply Voltage: must externally held enable device fetch code from external program memory locations starting with 0000H. held high, device executes from internal program memory unless program counter contains address greater than Devices (IFFFH), Devices (3FFFH) Devices (7FFFH). Since Internal Memory, will execute only from internal memory when held high. This also receives 12.75 programming supply voltage (VPP) during EPROM programming. security programmed, will internally latched Reset. Crystal Input inverting oscillator amplifier input internal clock generator circuits. Crystal Output from inverting oscillator amplifier.
EA/VPP
XTAL1 XTAL2
NOTE: avoid "latch-up" effect power-on, voltage time must higher than respectively.
2000
Philips Semiconductors
80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, voltage (2.7V-5.5V), power, high speed MHz)
8XC54/58 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+
8XC54/58 ORDERING INFORMATION
MEMORY SIZE P80C54SBPN P87C54SBPN P80C54SBAA P87C54SBAA P80C54SBBB P87C54SBBB P80C54SFP P87C54SFP P80C54SFA P87C54SFA P80C54SFB P87C54SFB P80C54UBAA P87C54UBAA P80C54UBPN P87C54UBPN P80C54UBBB P87C54UBBB P80C54UFA P87C54UFA P80C54UFPN P87C54UFPN P80C54UFBB P87C54UFBB MEMORY SIZE P80C58SBPN P87C58SBPN P80C58SBAA P87C58SBAA P80C58SBBB P87C58SBBB P80C58SFP P87C58SFP P80C58SFA P87C58SFA P80C58SFB P87C58SFB P80C58UBAA P87C58UBAA P80C58UBPN P87C58UBPN P80C58UBBB P87C58UBBB P80C58UFA P87C58UFA P80C58UFPN P87C58UFPN P80C58UFBB P87C58UFBB TEMPERATURE RANGE PACKAGE Plastic Dual line Package +70, In-line +70, Plastic Leaded Chip Carrier Plastic Quad Flat Pack +70, Plastic Dual line Package +85, In-line +85, Plastic Leaded Chip Carrier Plastic Quad Flat Pack +85, +70, Plastic Leaded Chip Carrier Plastic Dual line Package +70, In-line Plastic Quad Flat Pack +70, +85, Plastic Leaded Chip Carrier +85, Plastic Dual line Package In-line Plastic Quad Flat Pack +85, VOLTAGE RANGE FREQ. (MHz) DWG. SOT129 SOT129-1 SOT187-2 SOT187 SOT307 SOT307-2 SOT129-1 SOT129 SOT187 SOT187-2 SOT307-2 SOT307 SOT187 SOT187-2 SOT129-1 SOT129 SOT307 SOT307-2 SOT187-2 SOT187 SOT129 SOT129-1 SOT307-2 SOT307
Note: Multi Time Programmable devices, P89C51RX+ Flash datasheet.
2000
Philips Semiconductors
2000
8XC51FA/FB/FC 80C51FA ORDERING INFORMATION
MEMORY SIZE P83C51FA-4N P87C51FA-4N P83C51FA-4A P87C51FA-4A P83C51FA-4B P87C51FA-4B P83C51FA-5N P87C51FA-5N P83C51FA-5A P87C51FA-5A P83C51FA-5B P87C51FA-5B P83C51FA-IN P87C51FA-IN P83C51FA-IA P87C51FA-IA P83C51FA-IB P87C51FA-IB P83C51FA-JN P87C51FA-JN P83C51FA-JA P87C51FA-JA P83C51FA-JB P87C51FA-JB MEMORY SIZE P83C51FB-4N P87C51FB-4N P83C51FB-4A P87C51FB-4A P83C51FB-4B P87C51FB-4B P83C51FB-5N P87C51FB-5N P83C51FB-5A P87C51FB-5A P83C51FB-5B P87C51FB-5B P83C51FB-IN P87C51FB-IN P83C51FB-IA P87C51FB-IA P83C51FB-IB P87C51FB-IB P83C51FB-JN P87C51FB-JN P83C51FB-JA P87C51FB-JA P83C51FB-JB P87C51FB-JB MEMORY SIZE P83C51FC-4N P87C51FC-4N P83C51FC-4A P87C51FC-4A P83C51FC-4B P87C51FC-4B P83C51FC-5N P87C51FC-5N P83C51FC-5A P87C51FC-5A P83C51FC-5B P87C51FC-5B P83C51FC-IN P87C51FC-IN P83C51FC-IA P87C51FC-IA P83C51FC-IB P87C51FC-IB P83C51FC-JN P87C51FC-JN P83C51FC-JA P87C51FC-JA P83C51FC-JB P87C51FC-JB ROMless P80C51FA P80C51FA-4N P80C51FA-4A P80C51FA P80C51FA P80C51FA-4B P80C51FA-5N P80C51FA P80C51FA P80C51FA-5A P80C51FA-5B P80C51FA P80C51FA P80C51FA-IN P80C51FA-IA P80C51FA P80C51FA-IB P80C51FA P80C51FA-JN P80C51FA P80C51FA-JA P80C51FA P80C51FA-JB P80C51FA TEMPERATURE RANGE PACKAGE Plastic Dual line +70, 40-Pin In-line Pkg. Plastic Leaded Chip Carrier +70, 44-Pin Plastic Quad Flat Pack +70, 44-Pin +85, 40-Pin Plastic Dual In-line Pkg. line +85, 44-Pin Plastic Leaded Chip Carrier Plastic Quad Flat Pack +85, 44-Pin Plastic Dual line +70, 40-Pin In-line Pkg. Plastic Leaded Chip Carrier +70, 44-Pin Plastic Quad Flat Pack +70, 44-Pin +85, 40-Pin Plastic Dual In-line Pkg. line Plastic Leaded Chip Carrier +85, 44-Pin Plastic Quad Flat Pack +85, 44-Pin VOLTAGE RANGE 5.5V 2.7V 2.7V 5.5V 5.5V 2.7V 2.7V 5.5V 5.5V 2.7V 2.7V 5.5V FREQ. (MHz) DWG. SOT129 SOT129-1 SOT187-2 SOT187 SOT307 SOT307-2 SOT129-1 SOT129 SOT187 SOT187-2 SOT307-2 SOT307 SOT129 SOT129-1 SOT187-2 SOT187 SOT307-2 SOT307 SOT129-1 SOT129 SOT187-2 SOT187 SOT307-2 SOT307
80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, voltage (2.7V-5.5V), power, high speed (33MHz) 8XC54/58 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+
Note: Multi Time Programmable devices, P89C51RX+ Flash datasheet.
Philips Semiconductors
2000
87C51RA+/RB+/RC+/RD+ 80C51RA+ ORDERING INFORMATION
MEMORY SIZE P83C51RA+4N P87C51RA+4N P83C51RA+4A P87C51RA+4A P83C51RA+4B P87C51RA+4B P83C51RA+5N P87C51RA+5N P83C51RA+5A P87C51RA+5A P83C51RA+5B P87C51RA+5B P83C51RA+IN P87C51RA+IN P83C51RA+IA P87C51RA+IA P83C51RA+IB P87C51RA+IB P83C51RA+JN P87C51RA+JN P83C51RA+JA P87C51RA+JA P83C51RA+JB P87C51RA+JB MEMORY SIZE P83C51RB+4N P87C51RB+4N P83C51RB+4A P87C51RB+4A P83C51RB+4B P87C51RB+4B P83C51RB+5N P87C51RB+5N P83C51RB+5A P87C51RB+5A P83C51RB+5B P87C51RB+5B P83C51RB+IN P87C51RB+IN P83C51RB+IA P87C51RB+IA P83C51RB+IB P87C51RB+IB P83C51RB+JN P87C51RB+JN P83C51RB+JA P87C51RB+JA P83C51RB+JB P87C51RB+JB MEMORY SIZE P83C51RC+4N P87C51RC+4N P83C51RC+4A P87C51RC+4A P83C51RC+4B P87C51RC+4B P83C51RC+5N P87C51RC+5N P83C51RC+5A P87C51RC+5A P83C51RC+5B P87C51RC+5B P83C51RC+IN P87C51RC+IN P83C51RC+IA P87C51RC+IA P83C51RC+IB P87C51RC+IB P83C51RC+JN P87C51RC+JN P83C51RC+JA P87C51RC+JA P83C51RC+JB P87C51RC+JB MEMORY SIZE P83C51RD+4N P80C51RA+4N P87C51RD+4N P83C51RD+4A P80C51RA+4A P87C51RD+4A P83C51RD+4B P80C51RA+4B P87C51RD+4B P83C51RD+5N P80C51RA+5N P87C51RD+5N P83C51RD+5A P80C51RA+5A P87C51RD+5A P83C51RD+5B P80C51RA+5B P87C51RD+5B P83C51RD+IN P80C51RA+IN P87C51RD+IN P83C51RD+IA P80C51RA+IA P87C51RD+IA P83C51RD+IB P80C51RA+IB P87C51RD+IB P83C51RD+JN P80C51RA+JN P87C51RD+JN P83C51RD+JA P80C51RA+JA P87C51RD+JA P83C51RD+JB P87C51RD+JB P80C51RA+JB ROMless TEMPERATURE RANGE PACKAGE +70, 40-Pin Plastic Dual In-line Pkg. +70, 44-Pin Plastic Leaded Chip Carrier +70, 44-Pin Plastic Quad Flat Pack +85, 40-Pin Plastic Dual In-line Pkg. +85, 44-Pin Plastic Leaded Chip Carrier +85, 44-Pin Plastic Quad Flat Pack +70, 40-Pin Plastic Dual In-line Pkg. +70, 44-Pin Plastic Leaded Chip Carrier +70, 44-Pin Plastic Quad Flat Pack +85, 40-Pin Plastic Dual In-line Pkg. +85, 44-Pin Plastic Leaded Chip Carrier +85, 44-Pin Plastic Quad Flat Pack VOLTAGE RANGE 2.7V 5.5V FREQ. (MHz) DWG. SOT129-1 SOT129
80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, voltage (2.7V-5.5V), power, high speed (33MHz)
2.7V 5.5V
SOT187-2 SOT187
2.7V 5.5V
SOT307-2 SOT307
2.7V 5.5V
SOT129-1 SOT129
2.7V 5.5V
SOT187-2 SOT187
2.7V 5.5V
SOT307-2 SOT307
SOT129 SOT129-1
SOT187-2 SOT187
SOT307-2 SOT307
SOT129-1 SOT129
8XC54/58 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+
SOT187-2 SOT187
SOT307-2
Note: Multi Time Programmable devices, P89C51RX+ Flash datasheet.
Philips Semiconductors
80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, voltage (2.7V-5.5V), power, high speed (33MHz)
8XC54/58 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+
Table
SYMBOL ACC* AUXR# AUXR1# DPTR: IPH# PCON#1 PSW* RCAP2H# RCAP2L# SADDR# SADEN# SBUF SCON* TCON* T2CON* T2MOD# TH2# TL2#
8XC54/58 Special Function Registers
DESCRIPTION Accumulator Auxiliary Auxiliary register Data Pointer bytes) Data Pointer High Data Pointer Interrupt Enable Interrupt Priority Interrupt Priority High Port Port Port Port Power Control Program Status Word Timer Capture High Timer Capture Slave Address Slave Address Mask Serial Data Buffer Serial Control Stack Pointer Timer Control Timer Control Timer Mode Control Timer High Timer High Timer High Timer Timer Timer DIRECT ADDRESS EXF2 RCLK TCLK EXEN2 C/T2 T2OE CP/RL2 DCEN xxxxxx00B
SM0/FE
ADDRESS, SYMBOL, ALTERNATIVE PORT FUNCTION LPEP3
RESET VALUE xxxxxxx0B xxx0xxx0B
AD14 SMOD0
PT2H AD13
AD12 POF2
PT1H AD11 INT1
PX1H AD10 INT0
PT0H T2EX
PX0H 000000x0B xxxxxxxxB 00xx0000B xx000000B xx000000B 0x000000B
AD15 SMOD1
TMOD Timer Mode GATE SFRs addressable. SFRs modified from added 80C51 SFRs. Reserved bits. Reset value depends reset source. will affected Reset. LPEP Power OTP-EPROM only operation.
GATE
2000
Philips Semiconductors
80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, voltage (2.7V-5.5V), power, high speed (33MHz)
8XC54/58 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+
Table
SYMBOL ACC* AUXR# AUXR1# CCAP0H# CCAP1H# CCAP2H# CCAP3H# CCAP4H# CCAP0L# CCAP1L# CCAP2L# CCAP3L# CCAP4L# CCAPM0# CCAPM1# CCAPM2# CCAPM3# CCAPM4#
8XC51FA/FB/FC, 8XC51RA+/RB+/RC+/RD+ Special Function Registers
DESCRIPTION Accumulator Auxiliary Auxiliary register Module Capture High Module Capture High Module Capture High Module Capture High Module Capture High Module Capture Module Capture Module Capture Module Capture Module Capture Module Mode Module Mode Module Mode Module Mode Module Mode DIRECT ADDRESS ECOM ECOM ECOM ECOM ECOM CAPP CAPP CAPP CAPP CAPP CAPN CAPN CAPN CAPN CAPN CCF4 CCF3 CCF2 CCF1 ECCF ECCF ECCF ECCF ECCF CCF0 00x00000B 00xxx000B PPCH CEX3 AD14 SMOD0 PT2H CEX2 AD13 CEX1 AD12 POF2 PT1H CEX0 AD11 INT1 PX1H AD10 INT0 PT0H T2EX PX0H 00xx0000B x0000000B x0000000B ADDRESS, SYMBOL, ALTERNATIVE PORT FUNCTION LPEP3
EXTRAM (RX+ only)
RESET VALUE xxxxxx00B xxx0xxx0B xxxxxxxxB xxxxxxxxB xxxxxxxxB xxxxxxxxB xxxxxxxxB xxxxxxxxB xxxxxxxxB xxxxxxxxB xxxxxxxxB xxxxxxxxB x0000000B x0000000B x0000000B x0000000B x0000000B
CCON*# CMOD# DPTR: IPH#
Counter Control Counter High Counter Counter Mode Data Pointer bytes) Data Pointer High Data Pointer Interrupt Enable Interrupt Priority Interrupt Priority High
CIDL
WDTE
CPS1
CPS0
Port Port Port Port
CEX4 AD15
PCON#1 Power Control SMOD1 SFRs addressable. SFRs modified from added 80C51 SFRs. Reserved bits. Reset value depends reset source. will affected Reset. LPEP Power OTP-EPROM only operation. 2000
Philips Semiconductors
80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, voltage (2.7V-5.5V), power, high speed (33MHz)
8XC54/58 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+
Table
SYMBOL
8XC51FA/FB/FC, 8XC51RA+/RB+/RC+/RD+ Special Function Registers (Continued)
DESCRIPTION DIRECT ADDRESS EXF2 RCLK TCLK EXEN2 C/T2 T2OE CP/RL2 DCEN xxxxxx00B GATE GATE
SM0/FE
ADDRESS, SYMBOL, ALTERNATIVE PORT FUNCTION
RESET VALUE 000000x0B xxxxxxxxB
PSW* RACAP2H# RACAP2L# SADDR# SADEN# SBUF SCON* TCON*
Program Status Word Timer Capture High Timer Capture Slave Address Slave Address Mask Serial Data Buffer Serial Control Stack Pointer Timer Control
T2CON* T2MOD# TH2# TL2# TMOD WDTRST
Timer Control Timer Mode Control Timer High Timer High Timer High Timer Timer Timer Timer Mode
Watchdog 0A6H Timer Reset (RX+ only) SFRs addressable. SFRs modified from added 80C51 SFRs. Reserved bits.
OSCILLATOR CHARACTERISTICS
XTAL1 XTAL2 input output, respectively, inverting amplifier. pins configured on-chip oscillator. drive device from external clock source, XTAL1 should driven while XTAL2 left unconnected. There requirements duty cycle external clock signal, because input internal clock circuitry through divide-by-two flip-flop. However, minimum maximum high times specified data sheet must observed.
RESET
reset accomplished holding high least machine cycles oscillator periods), while oscillator running. insure good power-on reset, must high long enough allow oscillator time start (normally milliseconds) plus machine cycles. power-on, voltage must come same time proper start-up. Ports will asynchronously driven their reset condition when voltage above VIH1 (min.) applied RESET.
2000
Philips Semiconductors
80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, voltage (2.7V-5.5V), power, high speed (33MHz)
8XC54/58 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+
POWER MODES Stop Clock Mode
static design enables clock speed reduced down (stopped). When oscillator stopped, Special Function Registers retain their values. This mode allows step-by-step utilization permits reduced system power consumption lowering clock frequency down value. lowest power consumption Power Down mode suggested.
POWER FLAG
Power Flag (POF) on-chip circuitry when level 8XC51FX/8XC51RX+ rises from cleared software allowing user determine reset result power-on warm start after powerdown. level must remain above remain unaffected level.
Design Consideration
Idle Mode
idle mode (see Table puts itself sleep while on-chip peripherals stay active. instruction invoke idle mode last instruction executed normal operating mode before idle mode activated. contents, on-chip RAM, special function registers remain intact during this mode. idle mode terminated either enabled interrupt which time process picked interrupt service routine continued), hardware reset which starts processor same manner power-on reset.
When idle mode terminated hardware reset, device
normally resumes program execution, from where left off, machine cycles before internal reset algorithm takes control. On-chip hardware inhibits access internal this event, access port pins inhibited. eliminate possibility unexpected write when Idle terminated reset, instruction following that invokes Idle should that writes port external memory.
ONCEMode
ONCE ("On-Circuit Emulation") Mode facilitates testing debugging systems without device having removed from circuit. ONCE Mode invoked Pull while device reset PSEN high; Hold deactivated. While device ONCE Mode, Port pins into float state, other port pins PSEN weakly pulled high. oscillator circuit remains active. While device this mode, emulator test used drive circuit. Normal operation restored when normal reset applied.
Power-Down Mode
save even more power, Power Down mode (see Table invoked software. this mode, oscillator stopped instruction that invoked Power Down last instruction executed. on-chip Special Function Registers retain their values down 2.0V care must taken return minimum specified operating voltages before Power Down Mode terminated. Either hardware reset external interrupt used exit from Power Down. Reset redefines SFRs does change on-chip RAM. external interrupt allows both SFRs on-chip retain their values. properly terminate Power Down reset external interrupt should executed before restored normal operating level must held active long enough oscillator restart stabilize (normally less than 10ms). With external interrupt, INT0 INT1 must enabled configured level-sensitive. Holding restarts oscillator bringing back high completes exit. Once interrupt serviced, next instruction executed after RETI will following instruction that device into Power Down.
Programmable Clock-Out
duty cycle clock programmed come P1.0. This pin, besides being regular pin, alternate functions. programmed: input external clock Timer/Counter output duty cycle clock ranging from 61Hz 4MHz 16MHz operating frequency. configure Timer/Counter clock generator, C/T2 T2CON) must cleared T20E T2MOD must set. (T2CON.2) also must start timer. Clock-Out frequency depends oscillator frequency reload value Timer capture registers (RCAP2H, RCAP2L) shown this equation: Oscillator Frequency (65536 RCAP2H, RCAP2L)
LPEP
LPEP (AUXR.4), only needs applications operating less than
Where (RCAP2H,RCAP2L) content RCAP2H RCAP2L taken 16-bit unsigned integer. Clock-Out mode Timer roll-overs will generate interrupt. This similar when used baud-rate generator. possible Timer baud-rate generator clock generator simultaneously. Note, however, that baud-rate Clock-Out frequency will same.
Table External Status During Idle Power-Down Mode
MODE Idle Idle Power-down Power-down PROGRAM MEMORY Internal External Internal External PSEN PORT Data Float Data Float PORT Data Data Data Data PORT Data Address Data Data PORT Data Data Data Data
2000
Philips Semiconductors
80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, voltage (2.7V-5.5V), power, high speed (33MHz)
8XC54/58 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+
TIMER OPERATION Timer
Timer 16-bit Timer/Counter which operate either event timer event counter, selected C/T2* special function register T2CON (see Figure Timer three operating modes: Capture, Auto-reload down counting), Baud Rate Generator, which selected bits T2CON shown Table
Figure When reset applied DCEN=0 which means Timer will default counting DCEN set, Timer count down depending value T2EX pin. Figure shows Timer which will count automatically since DCEN=0. this mode there options selected EXEN2 T2CON register. EXEN2=0, then Timer counts 0FFFFH sets (Overflow Flag) upon overflow. This causes Timer registers reloaded with 16-bit value RCAP2L RCAP2H. values RCAP2L RCAP2H preset software means. EXEN2=1, then 16-bit reload triggered either overflow 1-to-0 transition input T2EX. This transition also sets EXF2 bit. Timer interrupt, enabled, generated when either EXF2 Figure DCEN=1, which enables Timer count down. This mode allows T2EX control direction count. When logic applied T2EX Timer will count Timer will overflow 0FFFFH flag, which then generate interrupt, interrupt enabled. This timer overflow also causes 16-bit value RCAP2L RCAP2H reloaded into timer registers TH2. When logic applied T2EX this causes Timer count down. timer will underflow when become equal value stored RCAP2L RCAP2H. Timer underflow sets flag causes 0FFFFH reloaded into timer registers TH2. external flag EXF2 toggles when Timer underflows overflows. This EXF2 used 17th resolution needed. EXF2 flag does generate interrupt this mode operation.
Capture Mode
capture mode there options which selected EXEN2 T2CON. EXEN2=0, then timer 16-bit timer counter selected C/T2* T2CON) which, upon overflowing sets TF2, timer overflow bit. This used generate interrupt enabling Timer interrupt register). EXEN2= Timer operates described above, with added feature that 1-to-0 transition external input T2EX causes current value Timer registers, TH2, captured into registers RCAP2L RCAP2H, respectively. addition, transition T2EX causes EXF2 T2CON set, EXF2 like generate interrupt (which vectors same location Timer overflow interrupt. Timer interrupt service routine interrogate EXF2 determine which event caused interrupt). capture mode illustrated Figure (There reload value this mode. Even when capture event occurs from T2EX, counter keeps counting T2EX transitions osc/12 pulses.)
Auto-Reload Mode Down Counter)
16-bit auto-reload mode, Timer configured either timer counter [C/T2* T2CON]) then programmed count down. counting direction determined DCEN (Down Counter Enable) which located T2MOD register (see
(MSB) Symbol EXF2 Position T2CON.7 T2CON.6 EXF2 RCLK TCLK EXEN2 C/T2
(LSB) CP/RL2
Name Significance Timer overflow flag Timer overflow must cleared software. will when either RCLK TCLK Timer external flag when either capture reload caused negative transition T2EX EXEN2 When Timer interrupt enabled, EXF2 will cause vector Timer interrupt routine. EXF2 must cleared software. EXF2 does cause interrupt up/down counter mode (DCEN Receive clock flag. When set, causes serial port Timer overflow pulses receive clock modes RCLK causes Timer overflow used receive clock. Transmit clock flag. When set, causes serial port Timer overflow pulses transmit clock modes TCLK causes Timer overflows used transmit clock. Timer external enable flag. When set, allows capture reload occur result negative transition T2EX Timer being used clock serial port. EXEN2 causes Timer ignore events T2EX. Start/stop control Timer logic starts timer. Timer counter select. (Timer Internal timer (OSC/12) External event counter (falling edge triggered). Capture/Reload flag. When set, captures will occur negative transitions T2EX EXEN2 When cleared, auto-reloads will occur either with Timer overflows negative transitions T2EX when EXEN2 When either RCLK TCLK this ignored timer forced auto-reload Timer overflow.
SU00728
RCLK TCLK EXEN2
T2CON.5 T2CON.4 T2CON.3
C/T2
T2CON.2 T2CON.1
CP/RL2
T2CON.0
Figure Timer/Counter (T2CON) Control Register 2000
Philips Semiconductors
80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, voltage (2.7V-5.5V), power, high speed (33MHz)
8XC54/58 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+
Table Timer Operating Modes
RCLK TCLK CP/RL2 16-bit Auto-reload 16-bit Capture Baud rate generator (off) MODE
C/T2 (8-bits) C/T2 (8-bits)
Control
Transition Detector
Capture Timer Interrupt RCAP2L RCAP2H
T2EX
EXF2
Control
EXEN2
SU00066
Figure Timer Capture Mode
T2MOD
Address 0C9H Addressable T2OE
Reset Value XXXX XX00B
DCEN
Symbol T2OE DCEN
Function implemented, reserved future use.* Timer Output Enable bit. Down Count Enable bit. When set, this allows Timer configured up/down counter.
User software should write reserved bits. These bits used future 8051 family products invoke features. that case, reset inactive value will active value will value read from reserved indeterminate. Figure Timer Mode (T2MOD) Control Register
SU00729
2000
Philips Semiconductors
80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, voltage (2.7V-5.5V), power, high speed (33MHz)
8XC54/58 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+
C/T2 (8-BITS) C/T2 (8-BITS)
CONTROL
RELOAD
TRANSITION DETECTOR
RCAP2L
RCAP2H TIMER INTERRUPT
T2EX
EXF2
CONTROL
EXEN2
SU00067
Figure Timer Auto-Reload Mode (DCEN
(DOWN COUNTING RELOAD VALUE)
TOGGLE EXF2
C/T2 OVERFLOW INTERRUPT
C/T2 CONTROL COUNT DIRECTION DOWN RCAP2L RCAP2H T2EX
COUNTING RELOAD VALUE)
SU00730
Figure Timer Auto Reload Mode (DCEN
2000
Philips Semiconductors
80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, voltage (2.7V-5.5V), power, high speed (33MHz)
8XC54/58 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+
Timer Overflow
NOTE: OSC. Freq. divided C/T2 (8-bits) C/T2 Control (8-bits)
SMOD RCLK
Reload
Clock
TCLK
Transition Detector
RCAP2L
RCAP2H
Clock
T2EX
EXF2
Timer Interrupt
Control EXEN2 Note availability additional external interrupt.
SU00068
Figure Timer Baud Rate Generator Mode
Table
Timer Generated Commonly Used Baud Rates
Timer Freq 12MHz 12MHz 12MHz 12MHz 12MHz 12MHz 12MHz 6MHz 6MHz RCAP2H RCAP2L
baud rates modes determined Timer overflow rate given below: Modes Baud Rates Timer Overflow Rate timer configured either "timer" "counter" operation. many applications, configured "timer" operation (C/T2*=0). Timer operation different Timer when being used baud rate generator. Usually, timer would increment every machine cycle (i.e., 1/12 oscillator frequency). baud rate generator, increments every state time (i.e., oscillator frequency). Thus baud rate formula follows: Modes Baud Rates Oscillator Frequency [65536 (RCAP2H, RCAP2L)]] Where: (RCAP2H, RCAP2L)= content RCAP2H RCAP2L taken 16-bit unsigned integer. Timer baud rate generator mode shown Figure valid only RCLK and/or TCLK T2CON register. Note that rollover does TF2, will generate interrupt. Thus, Timer interrupt does have disabled when Timer baud rate generator mode. Also EXEN2 external enable flag) set, 1-to-0 transition T2EX (Timer/counter trigger input) will EXF2 external flag) will cause reload from (RCAP2H, RCAP2L) (TH2,TL2). Therefore when Timer baud rate generator, T2EX used additional external interrupt, needed.
Rate Baud 375K 9.6K 2.8K 2.4K 1.2K
Baud Rate Generator Mode
Bits TCLK and/or RCLK T2CON (Table allow serial port transmit receive baud rates derived from either Timer Timer When TCLK= Timer used serial port transmit baud rate generator. When TCLK= Timer used serial port transmit baud rate generator. RCLK same effect serial port receive baud rate. With these bits, serial port have different receive transmit baud rates generated Timer other Timer Figure shows Timer baud rate generation mode. baud rate generation mode like auto-reload mode,in that rollover causes Timer registers reloaded with 16-bit value registers RCAP2H RCAP2L, which preset software.
2000
Philips Semiconductors
80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, voltage (2.7V-5.5V), power, high speed (33MHz)
8XC54/58 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+
When Timer baud rate generator mode, should read write TL2. baud rate generator, Timer incremented every state time (osc/2) asynchronously from under these conditions, read write accurate. RCAP2 registers read, should written because write might overlap reload cause write and/or reload errors. timer should turned (clear TR2) before accessing Timer RCAP2 registers. Table shows commonly used baud rates they obtained from Timer
Timer being clocked internally baud rate Baud Rate [65536 (RCAP2H, RCAP2L)]]
Where fOSC= Oscillator Frequency obtain reload value RCAP2H RCAP2L, above equation rewritten RCAP2H, RCAP2L 65536 Baud Rate
Summary Baud Rate Equations
Timer baud rate generating mode. Timer being clocked through T2(P1.0) baud rate Baud Rate Timer Overflow Rate
Timer/Counter Set-up
Except baud rate generator mode, values given T2CON include setting bit. Therefore, must set, separately, turn timer Table set-up Timer timer. Also Table set-up Timer counter.
Table Timer Timer
T2CON MODE 16-bit Auto-Reload 16-bit Capture Baud rate generator receive transmit same baud rate Receive only Transmit only INTERNAL CONTROL (Note EXTERNAL CONTROL (Note
Table Timer Counter
TMOD MODE 16-bit Auto-Reload INTERNAL CONTROL (Note EXTERNAL CONTROL (Note
NOTES: Capture/reload occurs only timer/counter overflow. Capture/reload occurs timer/counter overflow 1-to-0 transition T2EX (P1.1) except when Timer used baud rate generator mode.
2000
Philips Semiconductors
80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, voltage (2.7V-5.5V), power, high speed (33MHz)
8XC54/58 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+
Enhanced UART
UART operates usual modes that described first section Data Handbook IC20, 80C51-Based 8-Bit Microcontrollers. addition UART perform framing error detect looking missing stop bits, automatic address recognition. UART also fully supports multiprocessor communication does standard 80C51 UART. When used framing error detect UART looks missing stop bits communication. missing will SCON register. shares SCON.7 with function SCON.7 determined PCON.6 (SMOD0) (see Figure SMOD0 then SCON.7 functions SCON.7 functions when SMOD0 cleared. When used SCON.7 only cleared software. Refer Figure Automatic Address Recognition Automatic Address Recognition feature which allows UART recognize certain addresses serial stream using hardware make comparisons. This feature saves great deal software overhead eliminating need software examine every serial address which passes serial port. This feature enabled setting SCON. UART modes, mode mode Receive Interrupt flag (RI) will automatically when received byte contains either "Given" address "Broadcast" address. mode requires that information indicate that received information address data. Automatic address recognition shown Figure mode called Mode this mode flag will enabled information received valid stop following address bits information either Given Broadcast address. Mode Shift Register mode ignored. Using Automatic Address Recognition feature allows master selectively communicate with more slaves invoking Given slave address addresses. slaves contacted using Broadcast address. special Function Registers used define slave's address, SADDR, address mask, SADEN. SADEN used define which bits SADDR used which bits "don't care". SADEN mask logically ANDed with SADDR create "Given" address which master will addressing each slaves. Given address allows multiple slaves recognized while excluding others. following examples will help show versatility this scheme: Slave SADDR SADEN Given 1100 0000 1111 1101 1100 00X0
Slave
SADDR SADEN Given
1100 0000 1111 1110 1100 000X
above example SADDR same SADEN data used differentiate between slaves. Slave requires ignores Slave requires ignored. unique address Slave would 1100 0010 since slave requires unique address slave would 1100 0001 since will exclude slave Both slaves selected same time address which (for slave (for slave Thus, both could addressed with 1100 0000. more complex system following could used select slaves while excluding slave Slave SADDR SADEN Given SADDR SADEN Given SADDR SADEN Given 1100 0000 1111 1001 1100 0XX0 1110 0000 1111 1010 1110 0X0X 1110 0000 1111 1100 1110 00XX
Slave
Slave
above example differentiation among slaves lower address bits. Slave requires that uniquely addressed 1110 0110. Slave requires that uniquely addressed 1110 0101. Slave requires that unique address 1110 0011. select Slaves exclude Slave address 1110 0100, since necessary make exclude slave Broadcast Address each slave created taking logical SADDR SADEN. Zeros this result trended don't-cares. most cases, interpreting don't-cares ones, broadcast address will hexadecimal. Upon reset SADDR (SFR address 0A9H) SADEN (SFR address 0B9H) leaded with This produces given address "don't cares" well Broadcast address "don't cares". This effectively disables Automatic Addressing mode allows microcontroller standard 80C51 type UART drivers which make this feature.
2000
Philips Semiconductors
80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, voltage (2.7V-5.5V), power, high speed (33MHz)
8XC54/58 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+
SCON Address Addressable SM0/FE Bit:
Reset Value 0000 0000B
(SMOD0 0/1)*
Symbol
Function Framing Error bit. This receiver when invalid stop detected. cleared valid frames should cleared software. SMOD0 must enable access bit. Serial Port Mode (SMOD0 must access SM0) Serial Port Mode Mode Description shift register 8-bit UART 9-bit UART 9-bit UART Baud Rate** fOSC/12 variable fOSC/64 fOSC/32 variable
Enables Automatic Address Recognition feature Modes then will unless received data (RB8) indicating address, received byte Given Broadcast Address. Mode then will activated unless valid stop received, received byte Given Broadcast Address. Mode should Enables serial reception. software enable reception. Clear software disable reception. data that will transmitted Modes clear software desired. modes data that received. Mode stop that received. Mode used. Transmit interrupt flag. hardware time Mode beginning stop other modes, serial transmission. Must cleared software. Receive interrupt flag. hardware time Mode halfway through stop time other modes, serial reception (except SM2). Must cleared software.
NOTE: *SMOD0 located PCON6. **fOSC oscillator frequency
SU00043
Figure SCON: Serial Port Control Register
2000
Philips Semiconductors
80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, voltage (2.7V-5.5V), power, high speed (33MHz)
8XC54/58 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+
START
DATA BYTE
ONLY MODE
STOP
STOP (FRAMING ERROR) UART MODE CONTROL
SCON (98H)
SMOD1
SMOD0
PCON (87H)
SCON.7 SCON.7
SU01191
Figure UART Framing Error Detection
SCON (98H)
RECEIVED ADDRESS PROGRAMMED ADDRESS COMPARATOR
UART MODE MODE INTERRUPT REN=1, RB8=1 "RECEIVED ADDRESS" "PROGRAMMED ADDRESS" WHEN ADDRESS RECEIVED, CLEAR RECEIVE DATA BYTES WHEN DATA BYTES HAVE BEEN RECEIVED: WAIT NEXT ADDRESS.
SU00045
Figure UART Multiprocessor Communication, Automatic Address Recognition
2000
Philips Semiconductors
80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, voltage (2.7V-5.5V), power, high speed (33MHz)
8XC54/58 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+
Interrupt Priority Structure
8XC51FA/FB/FC 8XC51RA+/RB+/RC+/RD+ have 7-source four-level interrupt structure (see Table 80C54/58 have 6-source four-level interrupt structure because these devices have PCA. There SFRs associated with four-level interrupt. They IPH. (See Figures 12.) (Interrupt Priority High) register makes four-level interrupt structure possible. located address B7H. structure register description bits shown Figure function simple when combined with determines priority each interrupt. priority each interrupt determined shown following table: PRIORITY BITS IPH.x IP.x INTERRUPT PRIORITY LEVEL Level (lowest priority) Level Level Level (highest priority)
priority scheme servicing interrupts same that 80C51, except there four interrupt levels rather than 80C51. interrupt will serviced long interrupt equal higher priority already being serviced. interrupt equal higher level priority being serviced, interrupt will wait until finished before being serviced. lower priority level interrupt being serviced, will stopped interrupt serviced. When interrupt finished, lower priority level interrupt that stopped will completed.
Table
Interrupt Table
POLLING PRIORITY REQUEST BITS CCFn TF2, EXF2 HARDWARE CLEAR? (L)1 (T)2 VECTOR ADDRESS
SOURCE
NOTES: Level activated Transition activated (0A8H)
Enable enables interrupt. Enable disables IE.7 IE.6 IE.5 IE.4 IE.3 IE.2 IE.1 IE.0 SYMBOL FUNCTION Global disable bit. interrupts disabled. each interrupt individually enabled disabled setting clearing enable bit. interrupt enable only otherwise implemented. Timer interrupt enable bit. Serial Port interrupt enable bit. Timer interrupt enable bit. External interrupt enable bit. Timer interrupt enable bit. External interrupt enable bit.
SU00840
Figure Registers
2000
Philips Semiconductors
80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, voltage (2.7V-5.5V), power, high speed (33MHz)
8XC54/58 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+
(0B8H)
Priority assigns high priority Priority assigns priority IP.7 IP.6 IP.5 IP.4 IP.3 IP.2 IP.1 IP.0 SYMBOL FUNCTION implemented, reserved future use. interrupt priority only, otherwise implemented. Timer interrupt priority bit. Serial Port interrupt priority bit. Timer interrupt priority bit. External interrupt priority bit. Timer interrupt priority bit. External interrupt priority bit. SU00841 Figure Registers
(B7H)
PPCH
PT2H
PT1H
PX1H
PT0H
PX0H
Priority assigns higher priority Priority assigns lower priority IPH.7 IPH.6 IPH.5 IPH.4 IPH.3 IPH.2 IPH.1 IPH.0 SYMBOL PPCH PT2H PT1H PX1H PT0H PX0H FUNCTION implemented, reserved future use. interrupt priority high only, otherwise implemented. Timer interrupt priority high. Serial Port interrupt priority high. Timer interrupt priority high. External interrupt priority high. Timer interrupt priority high. External interrupt priority high. SU00881 Figure Registers
2000
Philips Semiconductors
80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, voltage (2.7V-5.5V), power, high speed (33MHz)
8XC54/58 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+
Reduced Mode
(AUXR.0) AUXR register when disables output.
quickly toggled simply executing DPTR instruction without affecting LPEP bits.
Reduced Mode
AUXR (8EH)
EXTRAM (83H) (82H) BIT0 AUXR1
DPTR1 DPTR0 EXTERNAL DATA MEMORY
AUXR.1 AUXR.0
EXTRAM
(RX+ only) Turns output.
SU00745A
Dual DPTR
dual DPTR structure (see Figure which chip will specify address external data memory location. There 16-bit DPTR registers that address external memory, single called AUXR1/bit0 that allows program code switch between them.
Figure
Register Name: AUXR1# Address: Reset Value: xxxx00x0B
LPEP
DPTR Instructions instructions that refer DPTR refer data pointer that currently selected using AUXR1/bit register. instructions that DPTR follows: DPTR DPTR, #data16 Increments data pointer Loads DPTR with 16-bit constant Move code byte relative DPTR Move external (16-bit address) Move external (16-bit address) Jump indirect relative DPTR
A+DPTR MOVX DPTR MOVX DPTR DPTR
Where: AUXR1/bit0 Switches between DPTR0 DPTR1. Select DPTR0 DPTR1
status should saved software when switching between DPTR0 DPTR1. general purpose user-defined flag. Note that writable always read zero. This allows
data pointer accessed byte-by-byte basis specifying high byte instruction which accesses SFRs. application note AN458 more details.
2000
Philips Semiconductors
80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, voltage (2.7V-5.5V), power, high speed (33MHz)
8XC54/58 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+
(8XC51FX 8XC51RX+ ONLY) Programmable Counter Array (PCA) (8XC51FX 8XC51RX+ only)
Programmable Counter Array available 8XC51FX 8XC51RX+ special 16-bit Timer that five 16-bit capture/compare modules associated with Each modules programmed operate four modes: rising and/or falling edge capture, software timer, high-speed output, pulse width modulator. Each module associated with port Module connected P1.3(CEX0), module P1.4(CEX1), etc. basic configuration shown Figure timer common time base five modules programmed 1/12 oscillator frequency, oscillator frequency, Timer overflow, input (P1.2). timer count source determined from CPS1 CPS0 bits CMOD follows (see Figure 17): CPS1 CPS0 Timer Count Source 1/12 oscillator frequency oscillator frequency Timer overflow External Input CMOD three additional bits associated with PCA. They CIDL which allows stop during idle mode, WDTE which enables disables watchdog function module which when causes interrupt overflow flag CCON SFR) when timer overflows. These functions shown Figure watchdog timer function implemented module (see Figure 24). CCON contains control flags timer (CF) each module (refer Figure 18). (CCON.6) must software. shut clearing this bit. (CCON.7) when counter overflows interrupt will generated CMOD register set, only cleared software. Bits through CCON register flags modules (bit module module etc.) hardware when either match capture occurs. These flags also only cleared software. interrupt system shown Figure Each module special function register associated with These registers are: CCAPM0 module CCAPM1 module etc. (see Figure 19). registers contain bits that control mode that each module will operate ECCF (CCAPMn.0 where n=0, depending module) enables flag CCON generate interrupt when match compare occurs associated module. (CCAPMn.1) enables pulse width modulation mode. (CCAPMn.2) when causes output associated with module toggle when there match between counter module's capture/compare register. match (CCAPMn.3) when will cause CCFn CCON register when there match between counter module's capture/compare register. next bits CAPN (CCAPMn.4) CAPP (CCAPMn.5) determine edge that capture input will active CAPN enables negative edge, CAPP enables positive edge. both bits both edges will enabled capture will occur either transition. last register ECOM (CCAPMn.6) when enables comparator function. Figure shows CCAPMn settings various functions. There additional registers associated with each modules. They CCAPnH CCAPnL these registers that store 16-bit count when capture occurs compare should occur. When module used mode these registers used control duty cycle output.
BITS MODULE P1.3/CEX0
MODULE BITS TIMER/COUNTER TIME BASE MODULES MODULE MODULE FUNCTIONS: 16-BIT CAPTURE 16-BIT TIMER 16-BIT HIGH SPEED OUTPUT 8-BIT WATCHDOG TIMER (MODULE ONLY) MODULE
P1.4/CEX1
P1.5/CEX2
P1.6/CEX3
MODULE
P1.7/CEX4
SU00032
Figure Programmable Counter Array (PCA)
2000
Philips Semiconductors
80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, voltage (2.7V-5.5V), power, high speed (33MHz)
8XC54/58 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+
(8XC51FX 8XC51RX+ ONLY)
MODULES
OSC/12
OSC/4 TIMER OVERFLOW EXTERNAL INPUT (P1.2/ECI)
OVERFLOW INTERRUPT
16-BIT COUNTER
DECODE
IDLE CIDL WDTE CPS1 CPS0 CMOD (D9H)
CCF4
CCF3
CCF2
CCF1
CCF0
CCON (D8H)
SU00033
Figure Timer/Counter
TIMER/COUNTER
CCF4
CCF3
CCF2
CCF1
CCF0
CCON (D8H)
MODULE IE.6 MODULE IE.7 INTERRUPT PRIORITY DECODER
MODULE
MODULE
MODULE
CMOD.0
CCAPMn.0
ECCFn
SU00034
Figure Interrupt System
2000
Philips Semiconductors
80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, voltage (2.7V-5.5V), power, high speed (33MHz)
8XC54/58 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+
(8XC51FX 8XC51RX+ ONLY)
CMOD Address OD9H Reset Value 00XX X000B
CIDL Bit: Symbol CIDL WDTE CPS1 CPS0 Function
WDTE
CPS1
CPS0
Counter Idle control: CIDL programs Counter continue functioning during idle Mode. CIDL programs gated during idle. Watchdog Timer Enable: WDTE disables Watchdog Timer function Module WDTE enables implemented, reserved future use.* Count Pulse Select Count Pulse Select CPS1 CPS0 Selected Input** Internal clock, fOSC Internal clock, fOSC Timer overflow External clock ECI/P1.2 (max. rate fOSC
Enable Counter Overflow interrupt: enables CCON generate interrupt. disables that function
NOTE: User software should write reserved bits. These bits used future 8051 family products invoke features. that case, reset inactive value will active value will value read from reserved indeterminate. fOSC oscillator frequency
SU00035
Figure CMOD: Counter Mode Register
CCON Address OD8H Addressable Bit: Symbol CCF4 CCF3 CCF2 CCF1 CCF0 Function CCF4 CCF3 CCF2 CCF1 CCF0
Reset Value 00X0 0000B
Counter Overflow flag. hardware when counter rolls over. flags interrupt CMOD set. either hardware software only cleared software. Counter control bit. software turn counter Must cleared software turn counter off. implemented, reserved future use*. Module interrupt flag. hardware when match capture occurs. Must cleared software. Module interrupt flag. hardware when match capture occurs. Must cleared software. Module interrupt flag. hardware when match capture occurs. Must cleared software. Module interrupt flag. hardware when match capture occurs. Must cleared software. Module interrupt flag. hardware when match capture occurs. Must cleared software.
NOTE: User software should write reserved bits. These bits used future 8051 family products invoke features. that case, reset inactive value will active value will value read from reserved indeterminate.
SU00036
Figure CCON: Counter Control Register
2000
Philips Semiconductors
80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, voltage (2.7V-5.5V), power, high speed (33MHz)
8XC54/58 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+
(8XC51FX 8XC51RX+ ONLY)
CCAPMn Address CCAPM0 CCAPM1 CCAPM2 CCAPM3 CCAPM4 0DAH 0DBH 0DCH 0DDH 0DEH Reset Value X000 0000B
Addressable Bit: Symbol ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn Function implemented, reserved future use*. Enable Comparator. ECOMn enables comparator function. Capture Positive, CAPPn enables positive edge capture. Capture Negative, CAPNn enables negative edge capture. Match. When MATn match counter with this module's compare/capture register causes CCFn CCON set, flagging interrupt. Toggle. When TOGn match counter with this module's compare/capture register causes CEXn toggle. Pulse Width Modulation Mode. PWMn enables CEXn used pulse width modulated output. Enable interrupt. Enables compare/capture flag CCFn CCON register generate interrupt. ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn
NOTE: *User software should write reserved bits. These bits used future 8051 family products invoke features. that case, reset inactive value will active value will value read from reserved indeterminate. SU00037
Figure CCAPMn: Modules Compare/Capture Registers ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn operation 16-bit capture positive-edge trigger CEXn 16-bit capture negative trigger CEXn 16-bit capture transition CEXn 16-bit Software Timer 16-bit High Speed Output 8-bit Watchdog Timer MODULE FUNCTION
Figure Module Modes (CCAPMn Register) Capture Mode modules capture mode either both CCAPM bits CAPN CAPP that module must set. external input module port sampled transition. When valid transition occurs hardware loads value counter registers into module's capture registers (CCAPnL CCAPnH). CCFn module CCON ECCFn CCAPMn then interrupt will generated. Refer Figure 16-bit Software Timer Mode modules used software timers setting both ECOM bits modules CCAPMn register. timer will compared module's capture registers when match occurs interrupt will occur CCFn (CCON SFR) ECCFn (CCAPMn SFR) bits module both (see Figure 22). High Speed Output Mode this mode output port associated with module will toggle each time match occurs between counter module's capture registers. activate this mode TOG, MAT, ECOM bits module's CCAPMn must (see Figure 23). Pulse Width Modulator Mode modules used outputs. Figure shows function. frequency output depends source timer. modules will have same frequency output because they share timer. duty cycle each module independently variable using module's capture register CCAPLn. When value less than value module's CCAPLn output will low, when equal greater than output will high. When overflows from CCAPLn reloaded with value CCAPHn. allows updating without glitches. ECOM bits module's CCAPMn register must enable mode.
2000
Philips Semiconductors
80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, voltage (2.7V-5.5V), power, high speed (33MHz)
8XC54/58 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+
(8XC51FX 8XC51RX+ ONLY)
CCF4
CCF3
CCF2
CCF1
CCF0
CCON (D8H)
INTERRUPT CCFn) TIMER/COUNTER
CEXn
CAPTURE
CCAPnH
CCAPnL
ECOMn
CAPPn
CAPNn
MATn
TOGn
PWMn
ECCFn
CCAPMn, (DAH DEH)
SU00749
Figure Capture Mode
WRITE CCAPnH RESET
CCF4
CCF3
CCF2
CCF1
CCF0
CCON (D8H)
WRITE CCAPnL ENABLE
CCAPnH
CCAPnL
INTERRUPT CCFn)
16-BIT COMPARATOR
MATCH
TIMER/COUNTER
ECOMn
CAPPn
CAPNn
MATn
TOGn
PWMn
ECCFn
CCAPMn, (DAH DEH)
SU00750
Figure Compare Mode
2000
Philips Semiconductors
80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, voltage (2.7V-5.5V), power, high speed (33MHz)
8XC54/58 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+
(8XC51FX 8XC51RX+ ONLY)
WRITE CCAPnH RESET CCAPnH
CCF4
CCF3
CCF2
CCF1
CCF0
CCON (D8H)
WRITE CCAPnL ENABLE
CCAPnL
INTERRUPT CCFn)
MATCH 16-BIT COMPARATOR
TOGGLE CEXn
TIMER/COUNTER
ECOMn
CAPPn
CAPNn
MATn
TOGn
PWMn
ECCFn
CCAPMn, (DAH DEH)
SU00751
Figure High Speed Output Mode
CCAPnH
CCAPnL CCAPnL ENABLE 8-BIT COMPARATOR CCAPnL OVERFLOW TIMER/COUNTER CEXn
ECOMn
CAPPn
CAPNn
MATn
TOGn
PWMn
ECCFn
CCAPMn, (DAH DEH)
SU00752
Figure Mode
2000
Philips Semiconductors
80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, voltage (2.7V-5.5V), power, high speed (33MHz)
8XC54/58 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+
(8XC51FX 8XC51RX+ ONLY)
CIDL WRITE CCAP4H RESET
WDTE
CPS1
CPS0
CMOD (D9H)
WRITE CCAP4L ENABLE
CCAP4H
CCAP4L
MODULE
MATCH 16-BIT COMPARATOR RESET
TIMER/COUNTER
ECOMn
CAPPn
CAPNn
MATn
TOGn
PWMn
ECCFn
CCAPM4 (DEH)
SU00832
Figure Watchdog Timer m(Module only) Watchdog Timer on-board watchdog timer available with improve reliability system without increasing chip count. Watchdog timers useful systems that susceptible noise, power glitches, electrostatic discharge. Module only module that programmed watchdog. However, this module still used other modes watchdog needed. Figure shows diagram watchdog works. user pre-loads 16-bit value compare registers. Just like other compare modes, this 16-bit value compared timer value. match allowed occur, internal reset will generated. This will cause driven high. order hold reset, user three options: periodically change compare value will never match timer, periodically change timer value will never match compare values, disable watchdog clearing WDTE before match occurs then re-enable first options more reliable because watchdog timer never disabled option program counter ever goes astray, match will eventually occur cause internal reset. second option also recommended other modules being used. Remember, timer time base modules; changing time base other modules would good idea. Thus, most applications first solution best option. Figure shows code initializing watchdog timer. Module configured either compare mode, WDTE CMOD must also set. user's software then must periodically change (CCAP4H,CCAP4L) keep match from occurring with timer (CH,CL). This code given WATCHDOG routine Figure This routine should part interrupt service routine, because program counter goes astray gets stuck infinite loop, interrupts will still serviced watchdog will keep getting reset. Thus, purpose watchdog would defeated. Instead, call this subroutine from main program within count timer.
2000
Philips Semiconductors
80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, voltage (2.7V-5.5V), power, high speed (33MHz)
8XC54/58 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+
(8XC51FX 8XC51RX+ ONLY)
INIT_WATCHDOG: CCAPM4, #4CH CCAP4L, #0FFH CCAP4H, #0FFH
CMOD, #40H
Module compare mode Write byte first Before timer counts FFFF Hex, these compare values must changed WDTE enable watchdog timer without changing other bits CMOD
Main program goes here, CALL WATCHDOG periodically. WATCHDOG: Hold interrupts CCAP4L, Next compare value within CCAP4H, counts current SETB timer value Figure Watchdog Timer Initialization Code
2000
Philips Semiconductors
80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, voltage (2.7V-5.5V), power, high speed (33MHz)
8XC54/58 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+
(8XC51RX+ ONLY) Expanded Data Addressing (8XC51RX+ ONLY)
8XC51RX+ have internal data memory that mapped into four separate segments: lower bytes RAM, upper bytes RAM, bytes Special Function Register (SFR), bytes (768 RD+) expanded (EXTRAM). four segments are: Lower bytes (addresses 7FH) directly indirectly addressable. Upper bytes (addresses FFH) indirectly addressable only. Special Function Registers, SFRs, (addresses FFH) directly addressable only. 256-bytes (768 RD+) expanded ((EXTRAM (256-bytes) 00H-FFH)) ((EXTRAM (768-bytes RD+) 2FFH)) indirectly accessed move external instruction, MOVX, with EXTRAM cleared, Figure Lower bytes accessed either direct indirect addressing. Upper bytes accessed indirect addressing only. Upper bytes occupy same address space SFR. That means they have same address, physically separate from space. When instruction accesses internal location above address 7FH, knows whether access upper bytes data space addressing mode used instruction. Instructions that direct addressing access space. example: 0A0H,#data accesses location 0A0H (which P2). Instructions that indirect addressing access Upper bytes data RAM. AUXR Address Addressable Bit: Symbol Function Disable/Enable Operating Mode emitted constant rate oscillator frequency. active only during MOVX MOVC instruction. Internal/External access using MOVX @Ri/@DPTR EXTRAM Operating Mode Internal ERAM (00H-FFH) (00H-2FFH RD+) access using MOVX @Ri/@DPTR External data memory access. implemented, reserved future use*. EXTRAM example: @R0,#data where contains 0A0H, accesses data byte address 0A0H, rather than (whose address 0A0H). EXTRAM accessed indirect addressing, with EXTRAM cleared MOVX instructions. This part memory physically located on-chip, logically occupies first 256-bytes (768 RD+) external data memory. With EXTRAM EXTRAM indirectly addressed, using MOVX instruction combination with registers selected bank DPTR. access EXTRAM will affect ports P3.6 (WR#) P3.7 (RD#). output during external addressing. example, with EXTRAM MOVX @R0,#data where contains 0A0H, access EXTRAM address 0A0H rather than external memory. access external data memory locations higher than (2FF RD+) (i.e., 0100H FFFFH) will performed with MOVX DPTR instructions same standard 80C51, with data/address bus, P3.6 P3.7 write read timing signals. Refer Figure With EXTRAM MOVX MOVX @DPTR will similar standard 80C51. MOVX will provide 8-bit address multiplexed with data Port output port pins used output higher order address bits. This provide external paging capability. MOVX @DPTR will generate 16-bit address. Port outputs high-order eight address bits (the contents DPH) while Port multiplexes low-order eight address bits (DPL) with data. MOVX MOVX @DPTR will generate either read write signals P3.6 (#WR) P3.7 (#RD). stack pointer (SP) located anywhere bytes (lower upper RAM) internal data memory. stack located EXTRAM. Reset Value xxxx xx00B
EXTRAM
NOTE: *User software should write reserved bits. These bits used future 8051 family products invoke features. that case, reset inactive value will active value will value read from reserved indeterminate.
SU01003
Figure AUXR: Auxiliary Register (RX+ only)
2000
Philips Semiconductors
80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, voltage (2.7V-5.5V), power, high speed (33MHz)
8XC54/58 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+
(8XC51RX+ ONLY)
RD+)
HARDWARE WATCHDOG TIMER (ONE-TIME ENABLED WITH RESET-OUT 89C51RC+/RD+)
intended recovery method situations where subjected software upset. consists 14-bit counter WatchDog Timer reset (WDTRST) SFR. disabled reset. enable WDT, user must write 01EH 0E1H sequence WDTRST, location 0A6H. When enabled, will increment every machine cycle while oscillator running there disable except through reset (either hardware reset overflow reset). When overflows, will drive output reset HIGH pulse RST-pin.
Using
enable WDT, user must write 01EH 0E1H sequence WDTRST, location 0A6H. When enabled, user needs service writing 01EH 0E1H WDTRST avoid overflow. 14-bit counter overflows when reaches 16383 (3FFFH) this will reset device. When using WDT, 1Kohm resistor must inserted between device Power Reset circuitry. When enabled, will increment every machine cycle while oscillator running. This means user must reset least every 16383 machine cycles. reset WDT, user must write 01EH 0E1H WDTRST. WDTRST write only register. counter cannot read written. When overflows, will generate output RESET pulse reset pin. RESET pulse duration TOSC, where TOSC 1/fOSC. make best WDT, should serviced those sections code that will periodically executed within time required prevent reset.
2000
ERAM BYTES
FFFF
UPPER BYTES INTERNAL
SPECIAL FUNCTION REGISTER
EXTERNAL DATA MEMORY
LOWER BYTES INTERNAL (RD+ only) 0100 0000
SU00834
Figure Internal External Data Memory Address Space with EXTRAM applications using Hardware Watchdog Timer P8xC51RD+, series resistor (1KW "20%) needs included between reset external components. Without this resistor watchdog timer will function.
Philips Semiconductors
80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, voltage (2.7V-5.5V), power, high speed (33MHz)
8XC54/58 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+
ABSOLUTE MAXIMUM RATINGS1,
PARAMETER Operating temperature under bias Storage temperature range Voltage EA/VPP Voltage other Maximum RATING +150 +13.0 -0.5 +6.5 UNIT
Power dissipation (based package heat transfer limitations, device power consumption) NOTES: Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only functional operation device these conditions other than those described Electrical Characteristics section this specification implied. This product includes circuitry specifically designed protection internal devices from damaging effects excessive static charge. Nonetheless, suggested that conventional precautions taken avoid applying greater than rated maximum. Parameters valid over operating temperature range unless otherwise specified. voltages with respect unless otherwise noted.
ELECTRICAL CHARACTERISTICS
Tamb +70°C -40°C +85°C CLOCK FREQUENCY RANGE SYMBOL 1/tCLCL FIGURE PARAMETER Oscillator frequency Speed versions 4:5:S (16MHz) I:J:U (33MHz) UNIT
2000
Philips Semiconductors
80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, voltage (2.7V-5.5V), power, high speed (33MHz)
8XC54/58 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+
ELECTRICAL CHARACTERISTICS
Tamb +70°C -40°C +85°C, 2.7V 5.5V, (16MHz devices) SYMBOL PARAMETER TEST CONDITIONS 4.0V 5.5V 2.7V<VCC< 4.0V LIMITS -0.5 -0.5 0.2VCC+0.9 0.7VCC 2.7V 1.6mA2 2.7V 3.2mA2 2.7V -20µA 4.5V -30µA 2.7V -3.2mA 0.4V 2.0V note 0.45 note -650 TYP1 0.2VCC-0.1 VCC+0.5 VCC+0.5 UNIT
VIH1 VOL1
Input voltage Input high voltage (ports Input high voltage, XTAL1, Output voltage, ports Output voltage, port ALE, PSEN8,
Output high voltage, ports voltage
VOH1
Output high voltage (port external mode), ALE9, PSEN3 Logical input current, ports Logical 1-to-0 transition current, ports Input leakage current, port Power supply current (see Figure 36): Active mode 16MHz (all except 8XC51RD+) 87C51RD+ Idle mode 16MHz Power-down mode clock stopped (see Figure conditions) diti Internal reset pull-down resistor capacitance10
Tamb 70°C Tamb -40°C +85°C
RRST
(except NOTES: Typical ratings guaranteed. values listed room temperature, Capacitive loading ports cause spurious noise superimposed VOLs ports noise external capacitance discharging into port port pins when these pins make 1-to-0 transitions during operations. worst cases (capacitive loading 100pF), noise pulse exceed 0.8V. such cases, desirable qualify with Schmitt Trigger, address latch with Schmitt Trigger STROBE input. exceed these conditions provided that single output sinks more than more than outputs exceed test conditions. Capacitive loading ports cause PSEN momentarily fall below VCC-0.7 specification when address bits stabilizing. Pins ports source transition current when they being externally driven from transition current reaches maximum value when approximately Figures through test conditions, Figure Freq. Active mode: (0.9 FREQ. 1.1)mA devices except 8XC51RD+; 8XC51RD+ (0.9 Freq +2.1) Idle mode: (0.18 FREQ. +1.01)mA This value applies Tamb +70°C. Tamb -40°C +85°C, -750µA. Load capacitance port ALE, PSEN 100pF, load capacitance other outputs 80pF. Under steady state (non-transient) conditions, must externally limited follows: Maximum port pin: 15mA (*NOTE: This 85°C specification.) 26mA Maximum 8-bit port: Maximum total outputs: 71mA exceeds test condition, exceed related specification. Pins guaranteed sink current greater than listed test conditions. tested VOH1, except when then voltage specification. capacitance characterized tested. capacitance less than 25pF. capacitance ceramic package less than 15pF (except 25pF).
2000
Philips Semiconductors
80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, voltage (2.7V-5.5V), power, high speed (33MHz)
8XC54/58 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+
ELECTRICAL CHARACTERISTICS
Tamb +70°C -40°C +85°C, 33MHz devices; ±10%; SYMBOL VIH1 VOL1 VOH1 Input voltage Input high voltage (ports Input high voltage, XTAL1, Output voltage, ports Output voltage, port ALE, PSEN Output high voltage, ports Output high voltage (port external mode), ALE9, PSEN3 Logical input current, ports Logical 1-to-0 transition current, ports Input leakage current, port Power supply current (see Figure 36): Active mode (see Note Idle mode (see Note Power-down mode clock stopped (see Figure conditions) diti Internal reset pull-down resistor capacitance10 (except 4.5V 1.6mA2 4.5V 3.2mA2 4.5V -30µA 4.5V -3.2mA 0.4V 2.0V note 0.45 note -650 PARAMETER TEST CONDITIONS 4.5V 5.5V LIMITS -0.5 0.2VCC+0.9 0.7VCC TYP1 UNIT 0.2VCC-0.1 VCC+0.5 VCC+0.5
Tamb 70°C Tamb -40°C +85°C
RRST
NOTES: Typical ratings guaranteed. values listed room temperature, Capacitive loading ports cause spurious noise superimposed VOLs ports noise external capacitance discharging into port port pins when these pins make 1-to-0 transitions during operations. worst cases (capacitive loading 100pF), noise pulse exceed 0.8V. such cases, desirable qualify with Schmitt Trigger, address latch with Schmitt Trigger STROBE input. exceed these conditions provided that single output sinks more than more than outputs exceed test conditions. Capacitive loading ports cause PSEN momentarily fall below VCC-0.7 specification when address bits stabilizing. Pins ports source transition current when they being externally driven from transition current reaches maximum value when approximately Figures through test conditions Figure Freq. Active mode: ICC(MAX) (0.9 FREQ. 1.1)mA. devices except 8XC51RD+; 8XC51RD+ (0.9 Freq +2.1) Idle mode: ICC(MAX) (0.18 FREQ. +1.0)mA This value applies Tamb +70°C. Tamb -40°C +85°C, -750µA. Load capacitance port ALE, PSEN 100pF, load capacitance other outputs 80pF. Under steady state (non-transient) conditions, must externally limited follows: 15mA (*NOTE: This 85°C specification.) Maximum port pin: Maximum 8-bit port: 26mA 71mA Maximum total outputs: exceeds test condition, exceed related specification. Pins guaranteed sink current greater than listed test conditions. tested VOH1, except when then voltage specification. capacitance characterized tested. capacitance less than 25pF. capacitance ceramic package less than 15pF (except 25pF).
2000
Philips Semiconductors
80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, voltage (2.7V-5.5V), power, high speed (33MHz)
8XC54/58 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+
ELECTRICAL CHARACTERISTICS
Tamb +70°C -40°C +85°C, +2.7V +5.5V, 0V1, 16MHz CLOCK SYMBOL 1/tCLCL tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tAVIV
VARIABLE CLOCK UNIT 4tCLCL-100 tCLCL-30 3tCLCL-45 3tCLCL-105 tCLCL-25 5tCLCL-105 6tCLCL-100 6tCLCL-100 5tCLCL-165 2tCLCL-60 8tCLCL-150 9tCLCL-165 3tCLCL-50 4tCLCL-130 tCLCL-50 tCLCL-50 7tCLCL-150 3tCLCL+50 tCLCL-40 tCLCL+40 tCLCL-tCLCX tCLCL-tCHCX 12tCLCL 10tCLCL-133 2tCLCL-117
FIGURE
PARAMETER Oscillator frequency5 Speed versions pulse width Address valid Address hold after valid instruction PSEN PSEN pulse width PSEN valid instruction Input instruction hold after PSEN Input instruction float after PSEN Address valid instruction PSEN address float pulse width pulse width valid data Data hold after Data float after valid data Address valid data Address valid Data valid transition Data hold after Data valid high address float high high High time time Rise time Fall time Serial port clock cycle time Output data setup clock rising edge Output data hold after clock rising edge Input data hold after clock rising edge
2tCLCL-40 tCLCL-40 tCLCL-30
tPLAZ Data Memory tRLRH tWLWH tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tQVWX tWHQX tQVWH tRLAZ tWHLH tCHCX tCLCX tCLCH tCHCL Shift Register tXLXL tQVXH tXHQX tXHDX
External Clock
tXHDV Clock rising edge input data valid 10tCLCL-133 NOTES: Parameters valid over operating temperature range unless otherwise specified. Load capacitance port ALE, PSEN 100pF, load capacitance other outputs 80pF. Interfacing microcontroller devices with float times 45ns permitted. This limited contention will cause damage Port drivers. application note AN457 external memory interface. Parts guaranteed operate down 0Hz. 2000
Philips Semiconductors
80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, voltage (2.7V-5.5V), power, high speed (33MHz)
8XC54/58 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+
ELECTRICAL CHARACTERISTICS
Tamb +70°C -40°C +85°C, ±10%, 0V1, VARIABLE CLOCK4 SYMBOL tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tAVIV tPLAZ Data Memory tRLRH tWLWH tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tQVWX tWHQX tQVWH tRLAZ tWHLH External Clock tCHCX tCLCX tCLCH tCHCL Shift Register tXLXL tQVXH tXHQX tXHDX Serial port clock cycle time Output data setup clock rising edge Output data hold after clock rising edge Input data hold after clock rising edge 12tCLCL 10tCLCL-133 2tCLCL-80 High time time Rise time Fall time 0.38tCLCL 0.38tCLCL tCLCL-tCLCX tCLCL-tCHCX pulse width pulse width valid data Data hold after Data float after valid data Address valid data Address valid Data valid transition Data hold after Data valid high address float high high tCLCL-25 3tCLCL-50 4tCLCL-75 tCLCL-30 tCLCL-25 7tCLCL-130 tCLCL+25 2tCLCL-28 8tCLCL-150 9tCLCL-165 3tCLCL+50 6tCLCL-100 6tCLCL-100 5tCLCL-90 FIGURE PARAMETER pulse width Address valid Address hold after valid instruction PSEN PSEN pulse width PSEN valid instruction Input instruction hold after PSEN Input instruction float after PSEN Address valid instruction PSEN address float tCLCL-25 5tCLCL-80 tCLCL-25 3tCLCL-45 3tCLCL-60 2tCLCL-40 tCLCL-25 tCLCL-25 4tCLCL-65 33MHz CLOCK UNIT
tXHDV Clock rising edge input data valid 10tCLCL-133 NOTES: Parameters valid over operating temperature range unless otherwise specified. Load capacitance port ALE, PSEN 100pF, load capacitance other outputs 80pF. Interfacing microcontroller devices with float times 45ns permitted. This limited contention will cause damage Port drivers. frequencies equal less than 16MHz, 16MHz Electrical Characteristics", page Parts guaranteed operate down 0Hz.
2000
Philips Semiconductors
80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, voltage (2.7V-5.5V), power, high speed (33MHz)
8XC54/58 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+
EXPLANATION SYMBOLS
Each timing symbol five characters. first character always time). other characters, depending their positions, indicate name signal logical status that signal. designations are: Address Clock Input data Logic level high Instruction (program memory contents) Logic level low, PSEN Output data signal Time Valid signal longer valid logic level Float Examples: tAVLL Time address valid low. tLLPL =Time PSEN low.
tLHLL
tAVLL
tLLPL
PSEN
tPLPH tLLIV tPLIV tPLAZ tPXIX
INSTR
tLLAX
tPXIZ
PORT
A0-A7
A0-A7
tAVIV
PORT A0-A15 A8-A15
SU00006
Figure External Program Memory Read Cycle
tWHLH
PSEN
tLLDV tLLWL
tRLRH
tAVLL
PORT
tLLAX tRLAZ
A0-A7 FROM
tRLDV tRHDX
DATA
tRHDZ
A0-A7 FROM
INSTR
tAVWL tAVDV
PORT P2.0-P2.7 A8-A15 FROM A0-A15 FROM
SU00025
Figure External Data Memory Read Cycle
2000
Philips Semiconductors
80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, voltage (2.7V-5.5V), power, high speed (33MHz)
8XC54/58 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+
tWHLH
PSEN
tLLWL
tWLWH
tAVLL
PORT
tLLAX
tQVWX tQVWH
tWHQX
A0-A7 FROM
DATA
A0-A7 FROM
INSTR
tAVWL
PORT
P2.0-P2.7 A8-A15 FROM
A0-A15 FROM
SU00026
Figure External Data Memory Write Cycle
INSTRUCTION
tXLXL
CLOCK
tQVXH
OUTPUT DATA WRITE SBUF
tXHQX
tXHDV
INPUT DATA VALID CLEAR VALID
tXHDX
VALID VALID VALID VALID VALID VALID
SU00027
Figure Shift Register Mode Timing
VCC-0.5 0.45V
0.7VCC 0.2VCC-0.1
tCHCL
tCLCX tCLCL
tCHCX tCLCH
SU00009
Figure External Clock Drive
2000
Philips Semiconductors
80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, voltage (2.7V-5.5V), power, high speed (33MHz)
8XC54/58 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+
VCC-0.5
0.2VCC+0.9 VLOAD 0.2VCC-0.1
VLOAD+0.1V VLOAD-0.1V
TIMING REFERENCE POINTS
VOH-0.1V VOL+0.1V
0.45V
NOTE: inputs during testing driven -0.5 logic 0.45V logic `0'. Timing measurements made logic logic `0'.
NOTE: timing purposes, port longer floating when 100mV change from load voltage occurs, begins float when 100mV change from loaded VOH/VOL level occurs. IOH/IOL ±20mA.
SU00717
SU00718
Figure Testing Input/Output
Figure Float Waveform
ICC(mA) ICCMAX ACTIVE MODE (8XC51RD+) ICCMAX FREQ ACTIVE MODE
ACTIVE MODE (EXCEPT 8XC51RD+) ICCMAX FREQ.
IDLE MODE IDLE MODE
FREQ XTAL1 (MHz)
SU00837A
Figure FREQ Valid only within frequency specifications device under test
2000
Philips Semiconductors
80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, voltage (2.7V-5.5V), power, high speed (33MHz)
8XC54/58 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+
(NC) CLOCK SIGNAL XTAL2 XTAL1 (NC) CLOCK SIGNAL XTAL2 XTAL1
SU00719
SU00720
Figure Test Condition, Active Mode other pins disconnected
Figure Test Condition, Idle Mode other pins disconnected
VCC-0.5 0.45V
0.7VCC 0.2VCC-0.1
tCHCL
tCLCX tCLCL
tCHCX tCLCH
SU00009
Figure Clock Signal Waveform Tests Active Idle Modes tCLCH tCHCL
(NC) XTAL2 XTAL1
SU00016
Figure Test Condition, Power Down Mode other pins disconnected. 5.5V
2000
Philips Semiconductors
80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, voltage (2.7V-5.5V), power, high speed (33MHz)
8XC54/58 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+
EPROM CHARACTERISTICS
these devices programmed using modified Improved Quick-Pulse Programmingalgorithm. differs from older methods value used (programming supply voltage) width number ALE/PROG pulses. family contains signature bytes that read used EPROM programming system identify device. signature bytes identify device being manufactured Philips. Table shows logic levels reading signature byte, programming program memory, encryption table, security bits. circuit configuration waveforms quick-pulse programming shown Figures Figure shows circuit configuration normal program memory verification.
address program memory locations read applied ports shown Figure other pins held `Verify Code Data' levels indicated Table contents address location will emitted port External pull-ups required port this operation. byte encryption table been programmed, data presented port will exclusive program byte with encryption bytes. user will have know encryption table contents order correctly decode verification data. encryption table itself cannot read out. Reading Signature Bytes signature bytes read same procedure normal verification locations 030H 031H, except that P3.6 P3.7 need pulled logic low. values are: (030H) indicates manufactured Philips (031H) indicates 87C54 indicates 87C58 indicates 87C51FA indicates 87C51FB indicates 87C51FC indicates 87C51RA+ indicates 87C51RB+ indicates 87C51RC+ indicates 87C51RD+ (060H)
Quick-Pulse Programming
setup microcontroller quick-pulse programming shown Figure Note that device running with 6MHz oscillator. reason oscillator needs running that device executing internal address program data transfers. address EPROM location programmed applied ports shown Figure code byte programmed into that location applied port RST, PSEN pins ports specified Table held `Program Code Data' levels indicated Table ALE/PROG pulsed times shown Figure program encryption table, repeat pulse programming sequence addresses through 1FH, using `Pgm Encryption Table' levels. forget that after encryption table programmed, verification cycles will produce only encrypted data. program security bits, repeat pulse programming sequence using `Pgm Security Bit' levels. After security programmed, further programming code memory encryption table disabled. However, other security bits still programmed. Note that EA/VPP must allowed above maximum specified level amount time. Even narrow glitch above that voltage cause permanent damage device. source should well regulated free glitches overshoot. Program Verification security bits have been programmed, on-chip program memory read program verification.
Program/Verify Algorithms
algorithm agreement with conditions listed Table which satisfies timing specifications, suitable.
Security Bits
With none security bits programmed code program memory verified. encryption table programmed, code will encrypted when verified. When only security (see Table programmed, MOVC instructions executed from external program memory disabled from fetching code bytes from internal memory, latched Reset further programming EPROM disabled. When security bits programmed, addition above, verify mode disabled. When three security bits programmed, conditions above apply external program memory execution disabled.
Encryption Array
bytes encryption array initially unprogrammed (all 1s).
TMTrademark phrase Intel Corporation. 2000
Philips Semiconductors
80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, voltage (2.7V-5.5V), power, high speed (33MHz)
8XC54/58 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+
Table EPROM Programming Modes
MODE Read signature Program code data Verify code data encryption table security security security PSEN ALE/PROG EA/VPP P2.7 P2.6 P3.7 P3.6
NOTES: Valid that pin, valid high that pin. 12.75V ±0.25V. 5V±10% during programming verification. ALE/PROG receives programming pulses code data (also user array; pulses encryption security bits) while held 12.75V. Each programming pulse 100µs (±10µs) high minimum 10µs.
Table Program Security Bits EPROM Devices
PROGRAM LOCK BITS1, PROTECTION DESCRIPTION Program Security features enabled. (Code verify will still encrypted Encryption Array programmed.) MOVC instructions executed from external program memory disabled from fetching code bytes from internal memory, sampled latched Reset, further programming EPROM disabled. Same also verify disabled. Same external execution disabled.
NOTES: programmed. unprogrammed. other combination security bits defined.
2000
Philips Semiconductors
80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, voltage (2.7V-5.5V), power, high speed (33MHz)
8XC54/58 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+
A0-A7
P3.6 P3.7 XTAL2
DATA +12.75V PULSES GROUND A8-A13 (RD+ ONLY)
EA/VPP ALE/PROG PSEN P2.7 P2.6
4-6MHz XTAL1 A8-A15 programming addresses (not external memory addresses device out)
P2.0-P2.5 P3.4 P3.5
SU00838A
Figure Programming Configuration
PULSES ALE/PROG:
EXPLODED VIEW BELOW tGHGL 10µs tGLGH 100µs±10µs ALE/PROG:
SU00875
Figure PROG Waveform
A0-A7 P3.6 P3.7 XTAL2 4-6MHz XTAL1 A8-A15 programming addresses (not external memory addresses device out) ALE/PROG PSEN P2.7 P2.6 P2.0-P2.5 P3.4 P3.5 DATA ENABLE A8-A13 (RD+ ONLY)
EA/VPP
SU00870
Figure Program Verification
2000
Philips Semiconductors
80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, voltage (2.7V-5.5V), power, high speed (33MHz)
8XC54/58 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+
EPROM PROGRAMMING VERIFICATION CHARACTERISTICS
Tamb 21°C +27°C, 5V±10%, (See Figure SYMBOL 1/tCLCL tAVGL tGHAX tDVGL tGHDX tEHSH tSHGL tGHSL tGLGH tAVQV tELQZ tEHQZ tGHGL NOTE: tested. Programming supply voltage Programming supply current Oscillator frequency Address setup PROG Address hold after PROG Data setup PROG Data hold after PROG P2.7 (ENABLE) high setup PROG hold after PROG PROG width Address data valid ENABLE data valid Data float after ENABLE PROG high PROG 48tCLCL 48tCLCL 48tCLCL 48tCLCL 48tCLCL 48tCLCL 48tCLCL 48tCLCL PARAMETER 12.5 13.0 UNIT
PROGRAMMING* P1.0-P1.7 P2.0-P2.5 P3.4 A14) ADDRESS
VERIFICATION* ADDRESS
tAVQV
DATA DATA
PORT P0.0 P0.7
tDVGL tAVGL
ALE/PROG
tGHDX tGHAX
tGLGH tSHGL
tGHGL tGHSL
LOGIC EA/VPP LOGIC
LOGIC
tEHSH
P2.7
tELQV
tEHQZ
SU00871
NOTES: PROGRAMMING CONFIGURATION FIGURE
VERIFICATION CONDITIONS FIGURE TABLE
Figure EPROM Programming Verification
2000
Philips Semiconductors
80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, voltage (2.7V-5.5V), power, high speed (33MHz)
8XC54/58 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+
MASK DEVICES Security Bits
With none security bits programmed code program memory verified. encryption table programmed, code will encrypted when verified. When only security (see Table programmed, MOVC instructions executed from external program memory disabled from fetching code bytes from internal memory, latched Reset further programming EPROM disabled. When security bits programmed, addition above, verify mode disabled.
Encryption Array
bytes encryption array initially unprogrammed (all 1s).
Table Program Security Bits
PROGRAM LOCK BITS1, PROTECTION DESCRIPTION Program Security features enabled. (Code verify will still encrypted Encryption Array programmed.) MOVC instructions executed from external program memory disabled from fetching code bytes from internal memory, sampled latched Reset, further programming EPROM disabled.
NOTES: programmed. unprogrammed. other combination security bits defined.
CODE SUBMISSION DEVICES (83C51FA, 83C51RA+)
When submitting code devices, following must specified: byte user data byte encryption security bits. ADDRESS 0000H 1FFFH 2000H 203FH 2040H CONTENT DATA BIT(S) COMMENT User Data Encryption encryption Security enable security disable security Security enable security disable security
2040H
Security When programmed, this effects masked parts: External MOVC disabled, latched Reset. Security When programmed, this inhibits Verify User ROM. NOTE: Security cannot enabled unless Security enabled.
Code file does include options, following information must included with code. each following, check appropriate box, send Philips along with code: Security Security Encryption:
Enabled Enabled
Disabled Disabled Yes, must send file.
2000
Philips Semiconductors
80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, voltage (2.7V-5.5V), power, high speed (33MHz)
8XC54/58 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+
CODE SUBMISSION DEVICES (80C54, 83C51FB 83C51RB+)
When submitting code devices, following must specified: byte user data byte encryption security bits. ADDRESS 0000H 3FFFH 4000H 403FH 4040H CONTENT DATA BIT(S) COMMENT User Data Encryption encryption Security enable security disable security Security enable security disable security
4040H
Security When programmed, this effects masked parts: External MOVC disabled, latched Reset. Security When programmed, this inhibits Verify User ROM. NOTE: Security cannot enabled unless Security enabled.
Code file does include options, following information must included with code. each following, check appropriate box, send Philips along with code: Security Security Encryption:
Enabled Enabled
Disabled Disabled Yes, must send file.
2000
Philips Semiconductors
80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, voltage (2.7V-5.5V), power, high speed (33MHz)
8XC54/58 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+
CODE SUBMISSION DEVICES (80C58, 83C51FC, 83C51RC+)
When submitting code devices, following must specified: byte user data byte encryption security bits. ADDRESS 0000H 7FFFH 8000H 803FH 8040H CONTENT DATA BIT(S) COMMENT User Data Encryption encryption Security enable security disable security Security enable security disable security
8040H
Security When programmed, this effects masked parts: External MOVC disabled, latched Reset. Security When programmed, this inhibits Verify User ROM. NOTE: Security cannot enabled unless Security enabled.
Code file does include options, following information must included with code. each following, check appropriate box, send Philips along with code: Security Security Encryption:
Enabled Enabled
Disabled Disabled Yes, must send file.
2000
Philips Semiconductors
80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, voltage (2.7V-5.5V), power, high speed (33MHz)
8XC54/58 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+
CODE SUBMISSION DEVICE (83C51RD+)
When submitting code devices, following must specified: byte user data byte encryption security bits. ADDRESS 0000H FFFFH 10000H 1003FH 10040H CONTENT DATA BIT(S) COMMENT User Data Encryption encryption Security enable security disable security Security enable security disable security
10040H
Security When programmed, this effects masked parts: External MOVC disabled, latched Reset. Security When programmed, this inhibits Verify User ROM. NOTE: Security cannot enabled unless Security enabled.
Code file does include options, following information must included with code. each following, check appropriate box, send Philips along with code: Security Security Encryption:
Enabled Enabled
Disabled Disabled Yes, must send
2000
Philips Semiconductors
80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, voltage (2.7V-5.5V), power, high speed (33MHz)
8XC54/58 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+
QFP44: plastic quad flat package; leads (lead length mm); body 1.75
SOT307-2
2000
Philips Semiconductors
80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, voltage (2.7V-5.5V), power, high speed (33MHz)
8XC54/58 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+
PLCC44: plastic leaded chip carrier; leads
SOT187-2
2000
Philips Semiconductors
80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, voltage (2.7V-5.5V), power, high speed (33MHz)
8XC54/58 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+
DIP40: plastic dual in-line package; leads (600 mil)
SOT129-1
2000
Philips Semiconductors
80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, voltage (2.7V-5.5V), power, high speed (33MHz)
8XC54/58 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+
NOTES
2000
Philips Semiconductors
80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, voltage (2.7V-5.5V), power, high speed (33MHz)
8XC54/58 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+
Data sheet status
Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition This data sheet contains design target goal specifications product development. Specification change manner without notice. This data sheet contains preliminary data, supplementary data will published later date. Philips Semiconductors reserves right make changes time without notice order improve design supply best possible product. This data sheet contains final specifications. Philips Semiconductors reserves right make changes time without notice order improve design supply best possible product.
Production
Please consult most recently issued datasheet before initiating completing design.
Definitions
Short-form specification data short-form specification extracted from full data sheet with same type number title. detailed information relevant data sheet data handbook. Limiting values definition Limiting values given accordance with Absolute Maximum Rating System (IEC 134). Stress above more limiting values cause permanent damage device. These stress ratings only operation device these other conditions above those given Characteristics sections specification implied. Exposure limiting values extended periods affect device reliability. Application information Applications that described herein these products illustrative purposes only. Philips Semiconductors make representation warranty that such applications will suitable specified without further testing modification.
Disclaimers
Life support These products designed life support appliances, devices systems where malfunction these products reasonably expected result personal injury. Philips Semiconductors customers using selling these products such applications their risk agree fully indemnify Philips Semiconductors damages resulting from such application. Right make changes Philips Semiconductors reserves right make changes, without notice, products, including circuits, standard cells, and/or software, described contained herein order improve design and/or performance. Philips Semiconductors assumes responsibility liability these products, conveys license title under patent, copyright, mask work right these products, makes representations warranties that these products free from patent, copyright, mask work right infringement, unless otherwise specified. Philips Semiconductors East Arques Avenue P.O. 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 Copyright Philips Electronics North America Corporation 2000 rights reserved. Printed U.S.A. Date release: 08-00 Document order number: 9397 07405
Philips Semiconductors
2000

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