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SST39SF512 SST39SF010 SST39SF512 0105.0V 512Kb (x8) memories


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Kbit Mbit (x8) Multi-Purpose Flash
SST39SF512 SST39SF010
SST39SF512 0105.0V 512Kb (x8) memories
FEATURES:
Organized 128K Single 4.5-5.5V Read Write Operations Superior Reliability Endurance: 100,000 Cycles (typical) Greater than years Data Retention Power Consumption: Active Current: (typical) Standby Current: (typical) Sector-Erase Capability Uniform KByte sectors Fast Read Access Time: Latched Address Data Fast Erase Byte-Program: Sector-Erase Time: (typical) Chip-Erase Time: (typical) Byte-Program Time: (typical) Chip Rewrite Time: seconds (typical) SST39SF512 seconds (typical) SST39SF010 Automatic Write Timing Internal Generation End-of-Write Detection Toggle Data# Polling Compatibility JEDEC Standard Flash EEPROM Pinouts command sets Packages Available 32-lead PLCC 32-lead TSOP (8mm 14mm) 32-pin PDIP
PRODUCT DESCRIPTION
SST39SF512/010 CMOS Multi-Purpose Flash (MPF) manufactured with SST's proprietary, high performance CMOS SuperFlash technology. split-gate cell design thick oxide tunneling injector attain better reliability manufacturability compared with alternate approaches. SST39SF512/010 devices write (Program Erase) with 4.5-5.5V power supply. SST39SF512/010 device conforms JEDEC standard pinouts memories. Featuring high performance Byte-Program, SST39SF512/010 devices provide maximum Byte-Program time µsec. These devices Toggle Data# Polling indicate completion Program operation. protect against inadvertent write, they have on-chip hardware Software Data Protection schemes. Designed, manufactured, tested wide spectrum applications, these devices offered with guaranteed endurance 10,000 cycles. Data retention rated greater than years. SST39SF512/010 devices suited applications that require convenient economical updating program, configuration, data memory. system applications, they significantly improve performance reliability, while lowering power consumption. They inherently less energy during erase program than alter©2002 Silicon Storage Technology, Inc. S71149-03-000 2/02
native flash technologies. total energy consumed function applied voltage, current, time application. Since given voltage range, SuperFlash technology uses less current program shorter erase time, total energy consumed during Erase Program operation less than alternative flash technologies. These devices also improve flexibility while lowering cost program, data, configuration storage applications. SuperFlash technology provides fixed Erase Program times, independent number Erase/Program cycles that have occurred. Therefore system software hardware does have modified de-rated necessary with alternative flash technologies, whose Erase Program times increase with accumulated Erase/Program cycles. meet high density, surface mount requirements, SST39SF512/010 offered 32-lead PLCC packages, 32-lead TSOP mil, 32-pin PDIP also available. Figures pinouts.
logo SuperFlash registered trademarks Silicon Storage Technology, Inc. Multi-Purpose Flash trademarks Silicon Storage Technology, Inc. These specifications subject change without notice.
Kbit Mbit Multi-Purpose Flash SST39SF512 SST39SF010
Device Operation
Commands used initiate memory operation functions device. Commands written device using standard microprocessor write sequences. command written asserting while keeping low. address latched falling edge CE#, whichever occurs last. data latched rising edge CE#, whichever occurs first.
latched rising edge sixth pulse. internal Erase operation begins after sixth pulse. Erase determined using either Data# Polling Toggle methods. Figure timing waveforms. commands written during SectorErase operation will ignored.
Chip-Erase Operation
SST39SF512/010 provide Chip-Erase operation, which allows user erase entire memory array "1s" state. This useful when entire device must quickly erased. Chip-Erase operation initiated executing sixbyte Software Data Protection command sequence with Chip-Erase command (10H) with address 5555H last byte sequence. Erase operation begins with rising edge sixth CE#, whichever occurs first. During Erase operation, only valid read Toggle Data# Polling. SeeTable command sequence, Figure timing diagram, Figure flowchart. commands written during Chip-Erase operation will ignored.
Read
Read operation SST39SF512/010 controlled OE#, both have system obtain data from outputs. used device selection. When high, chip deselected only standby power consumed. output control used gate data from output pins. data high impedance state when either high. Refer Read cycle timing diagram further details (Figure
Byte-Program Operation
SST39SF512/010 programmed byte-by-byte basis. Before programming, sector where byte exists must fully erased. Program operation accomplished three steps. first step three-byte load sequence Software Data Protection. second step load byte address byte data. During ByteProgram operation, addresses latched falling edge either WE#, whichever occurs last. data latched rising edge either WE#, whichever occurs first. third step internal Program operation which initiated after rising edge fourth CE#, whichever occurs first. Program operation, once initiated, will completed, within Figures controlled Program operation timing diagrams Figure flowcharts. During Program operation, only valid reads Data# Polling Toggle Bit. During internal Program operation, host free perform additional tasks. commands written during internal Program operation will ignored.
Write Operation Status Detection
SST39SF512/010 provide software means detect completion Write (Program Erase) cycle, order optimize system Write cycle time. software detection includes status bits: Data# Polling (DQ7) Toggle (DQ6). End-of-Write detection mode enabled after rising edge WE#, which initiates Program Erase cycle. actual completion nonvolatile write asynchronous with system; therefore, either Data# Polling Toggle read simultaneous with completion Write cycle. this occurs, system possibly erroneous result, i.e., valid data appear conflict with either DQ6. order prevent spurious rejection, erroneous result occurs, software routine should include loop read accessed location additional times. both reads valid, then device completed Write cycle, otherwise rejection valid.
Sector-Erase Operation
Sector-Erase operation allows system erase device sector-by-sector basis. sector architecture based uniform sector size KByte. SectorErase operation initiated executing six-byte command load sequence Software Data Protection with Sector-Erase command (30H) sector address (SA) last cycle. sector address latched falling edge sixth pulse, while command (30H)
©2002 Silicon Storage Technology, Inc.
S71149-03-000 2/02
Kbit Mbit Multi-Purpose Flash SST39SF512 SST39SF010
Data# Polling (DQ7)
When SST39SF512/010 internal Program operation, attempt read will produce complement true data. Once Program operation completed, will produce true data. Note that even thought have valid data immediately following completion internal Write operation, remaining data outputs still invalid: valid data entire data will appear subsequent successive Read cycles after interval During internal Erase operation, attempt read will produce `0'. Once internal Erase operation completed, will produce `1'. Data# Polling valid after rising edge fourth CE#) pulse Program Operation. sector Chip-Erase, Data# Polling valid after rising edge sixth CE#) pulse. Figure Data# Polling timing diagram Figure flowchart.
Software Data Protection (SDP)
SST39SF512/010 provide JEDEC approved Software Data Protection scheme data alteration operations, i.e., Program Erase. Program operation requires inclusion series three byte sequence. three-byte load sequence used initiate Program operation, providing optimal protection from inadvertent Write operations, e.g., during system power-up power-down. Erase operation requires inclusion six-byte load sequence. SST39SF512 device shipped with Software Data Protection permanently enabled. Table specific software command codes. During command sequence, invalid commands will abort device read mode, within TRC.
Product Identification
Product Identification mode identifies device SST39SF512 SST39SF010 manufacturer SST. This mode accessed software operations. Users software Product Identification operation identify part (i.e., using device when using multiple manufacturers same socket. details, Table software operation, Figure software entry read timing diagram Figure entry command sequence flowchart. TABLE PRODUCT IDENTIFICATION
Address Manufacturer's Device SST39SF512 SST39SF010 0001H 0001H
T1.2
Toggle (DQ6)
During internal Program Erase operation, consecutive attempts read will produce alternating i.e., toggling between Toggle will begin with "1". When internal Program Erase operation completed, toggling will stop. device then ready next operation. Toggle valid after rising edge fourth CE#) pulse Program operation. Sector Chip-Erase, Toggle valid after rising edge sixth CE#) pulse. Figure Toggle timing diagram Figure flowchart.
Data
0000H
Data Protection
SST39SF512/010 provide both hardware software features protect nonvolatile data from inadvertent writes.
Hardware Data Protection
Noise/Glitch Protection: pulse less than will initiate Write cycle. Power Up/Down Detection: Write operation inhibited when less than 2.5V. Write Inhibit Mode: Forcing low, high, high will inhibit Write operation. This prevents inadvertent writes during power-up power-down.
Product Identification Mode Exit/Reset
order return standard Read mode, Software Product Identification mode must exited. Exit accomplished issuing Software Exit command sequence, which returns device Read operation. Please note that software reset command ignored during internal Program Erase operation. Table software command codes, Figure timing waveform Figure flowchart.
©2002 Silicon Storage Technology, Inc.
S71149-03-000 2/02
Kbit Mbit Multi-Purpose Flash SST39SF512 SST39SF010
FUNCTIONAL BLOCK DIAGRAM
X-Decoder
SuperFlash Memory
Memory Address
Address Buffers Latches Y-Decoder
B1.1
Control Logic
Buffers Data Latches
SST39SF512 SST39SF010
SST39SF010 SST39SF512
SST39SF512 SST39SF010
SST39SF010 SST39SF512
32-lead PLCC View
F02b.5
FIGURE ASSIGNMENTS 32-LEAD PLCC
©2002 Silicon Storage Technology, Inc.
S71149-03-000 2/02
Kbit Mbit Multi-Purpose Flash SST39SF512 SST39SF010
SST39SF010 SST39SF512
SST39SF512 SST39SF010
Standard Pinout View
F01.2
FIGURE ASSIGNMENTS 32-LEAD TSOP (8MM
14MM)
SST39SF010 SST39SF512
SST39SF512 SST39SF010
32-pin PDIP View
F02a.3
FIGURE ASSIGNMENTS 32-PIN PDIP
©2002 Silicon Storage Technology, Inc.
S71149-03-000 2/02
Kbit Mbit Multi-Purpose Flash SST39SF512 SST39SF010
Data Sheet TABLE DESCRIPTION
Symbol AMS1-A0 DQ7-DQ0 Name Address Inputs Data Input/output Functions provide memory addresses. During Sector-Erase AMS-A12 address lines will select sector. output data during Read cycles receive input data during Write cycles. Data internally latched during Write cycle. outputs tri-state when high. activate device when low. gate data output buffers. control Write operations. provide 4.5-5.5V supply Unconnected pins.
T2.4
Chip Enable Output Enable Write Enable Power Supply Ground Connection
Most significant address SST39SF512 SST39SF010
TABLE OPERATION MODES SELECTION
Mode Read Program Erase Standby Write Inhibit Product Identification Software Mode Table
T3.4
DOUT High High DOUT High DOUT
Address Sector address, Chip-Erase
VIH, other value.
©2002 Silicon Storage Technology, Inc.
S71149-03-000 2/02
Kbit Mbit Multi-Purpose Flash SST39SF512 SST39SF010
Data Sheet TABLE SOFTWARE COMMAND SEQUENCE
Command Sequence Byte-Program Sector-Erase Chip-Erase Software Entry4,5 Software Exit6 Software Exit6 Write Cycle Addr1 5555H 5555H 5555H 5555H 5555H Data 2AAAH 5555H
T4.3
Write Cycle Addr1 2AAAH 2AAAH 2AAAH 2AAAH Data
Write Cycle Addr1 5555H 5555H 5555H 5555H Data
Write Cycle Addr1 5555H 5555H Data Data
Write Cycle Addr1 2AAAH 2AAAH Data
Write Cycle Addr1 SAX3 5555H Data
Address format A14-A0 (Hex), Address VIH, other value, Command sequence SST39SF512. Addresses A15-A16 VIH, other value, Command sequence SST39SF010. Program Byte address Sector-Erase; uses AMS-A12 address lines Most significant address SST39SF512 SST39SF010 device does remain Software Product mode powered down. With AMS-A1 Manufacturer's BFH, read with SST39SF512 Device B4H, read with SST39SF010 Device B5H, read with Both Software Exit operations equivalent
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" cause permanent damage device. This stress rating only functional operation device these conditions conditions greater than those defined operational sections this data sheet implied. Exposure absolute maximum stress rating conditions affect device reliability.) Temperature Under Bias -55°C +125°C Storage Temperature -65°C +150°C Voltage Ground Potential -0.5V VDD+0.5V Transient Voltage (<20 Ground Potential -2.0V VDD+2.0V Voltage Ground Potential -0.5V 14.0V Package Power Dissipation Capability 25°C) 1.0W Through Hold Lead Soldering Temperature Seconds) 300°C Surface Mount Lead Soldering Temperature Seconds) 240°C Output Short Circuit Current1
Outputs shorted more than second. more than output shorted time.
OPERATING RANGE
Range Commercial Industrial Ambient Temp +70°C -40°C +85°C
4.5-5.5V 4.5-5.5V
CONDITIONS
TEST
Input Rise/Fall Time Output Load Output Load Figures
©2002 Silicon Storage Technology, Inc.
S71149-03-000 2/02
Kbit Mbit Multi-Purpose Flash SST39SF512 SST39SF010
Data Sheet TABLE OPERATING CHARACTERISTICS 4.5-5.5V
Limits Symbol Parameter Power Supply Current Read Write ISB1 ISB2 Standby Current (TTL input) Standby Current (CMOS input) Input Leakage Current Output Leakage Current Input Voltage Input High Voltage Output Voltage Output High Voltage Units Test Conditions Address input=VIL/VIH, f=1/TRC VDD=VDD CE#=OE#=VIL, WE#=VIH, I/Os open CE#=WE#=VIL, OE#=VIH CE#=VIH, VDD=VDD CE#=VDD -0.3V, VDD=VDD VIN=GND VDD, VDD=VDD VOUT=GND VDD, VDD=VDD VDD=VDD VDD=VDD IOL=2.1 VDD=VDD IOH=-400 VDD=VDD
T5.4
TABLE RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol TPU-READ1 TPU-WRITE
Parameter Power-up Read Operation Power-up Program/Erase Operation
Minimum
Units
T6.1
This parameter measured only initial qualification after design process change that could affect this parameter.
TABLE CAPACITANCE
Parameter CI/O
25°C, Mhz, other pins open)
Description Capacitance Input Capacitance
Test Condition VI/O
Maximum
T7.0
CIN1
This parameter measured only initial qualification after design process change that could affect this parameter.
TABLE RELIABILITY CHARACTERISTICS
Symbol NEND1 TDR1 ILTH1 Parameter Endurance Data Retention Latch Minimum Specification 10,000 Units Cycles Years Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard
T8.1
This parameter measured only initial qualification after design process change that could affect this parameter.
©2002 Silicon Storage Technology, Inc.
S71149-03-000 2/02
Kbit Mbit Multi-Purpose Flash SST39SF512 SST39SF010
CHARACTERISTICS
TABLE READ CYCLE TIMING PARAMETERS 4.5-5.5V
SST39SF512/010-70 Symbol TCLZ1 TOLZ1 TCHZ1 TOHZ1 TOH1 Parameter Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time Active Output Active Output High High-Z Output High High-Z Output Output Hold from Address Change SST39SF512/010-90 Units
T9.3
This parameter measured only initial qualification after design process change that could affect this parameter.
TABLE PROGRAM/ERASE CYCLE TIMING PARAMETERS
Symbol TOES TOEH TWPH1 TCPH TSCE
Parameter Byte-Program Time Address Setup Time Address Hold Time Setup Time Hold Time High Setup Time High Hold Time Pulse Width Pulse Width Pulse Width High Pulse Width High Data Setup Time Data Hold Time Software Access Exit Time Sector-Erase Chip-Erase
Units
TIDA1
T10.1
This parameter measured only initial qualification after design process change that could affect this parameter.
©2002 Silicon Storage Technology, Inc.
S71149-03-000 2/02
Kbit Mbit Multi-Purpose Flash SST39SF512 SST39SF010
ADDRESS AMS-0
TOLZ
TOHZ TCHZ HIGH-Z DATA VALID
DQ7-0
HIGH-Z
TCLZ
DATA VALID
Note: Most significant address SST39SF512 SST39SF010
F03.1
FIGURE READ CYCLE TIMING DIAGRAM
INTERNAL PROGRAM OPERATION STARTS ADDRESS AMS-0 5555 DQ7-0 DATA BYTE (ADDR/DATA) TWPH 2AAA 5555 ADDR
F04.1
Note: Most significant address SST39SF512 SST39SF010
FIGURE CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
©2002 Silicon Storage Technology, Inc.
S71149-03-000 2/02
Kbit Mbit Multi-Purpose Flash SST39SF512 SST39SF010
INTERNAL PROGRAM OPERATION STARTS ADDRESS AMS-0 5555 DQ7-0 DATA BYTE (ADDR/DATA) TCPH 2AAA 5555 ADDR
F05.1
Note: Most significant address SST39SF512 SST39SF010
FIGURE CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
ADDRESS AMS-0 TOEH TOES
F06.1
Note: Most significant address SST39SF512 SST39SF010
FIGURE DATA# POLLING TIMING DIAGRAM
©2002 Silicon Storage Technology, Inc.
S71149-03-000 2/02
Kbit Mbit Multi-Purpose Flash SST39SF512 SST39SF010
ADDRESS AMS-0 TOEH TOES
Note
Note: Toggle output always high first. Most significant address SST39SF512 SST39SF010
READ CYCLES WITH SAME OUTPUTS F07.1
FIGURE TOGGLE TIMING DIAGRAM
SIX-BYTE CODE SECTOR-ERASE ADDRESS AMS-0 5555 2AAA 5555 5555 2AAA
DQ7-0
F08.2
Note: This device also supports controlled Sector-Erase operation. signals interchageable long minimum timings met. (See Table Sector Address Most significant address SST39SF512 SST39SF010
FIGURE CONTROLLED SECTOR-ERASE TIMING DIAGRAM
©2002 Silicon Storage Technology, Inc.
S71149-03-000 2/02
Kbit Mbit Multi-Purpose Flash SST39SF512 SST39SF010
SIX-BYTE CODE CHIP-ERASE ADDRESS AMS-0 5555 2AAA 5555 5555 2AAA 5555
TSCE
DQ7-0
F17.1
Note: This device also supports controlled Chip-Erase operation. signals interchageable long minimum timings met. (See Table Sector Address Most significant address SST39SF512 SST39SF010
FIGURE CONTROLLED CHIP-ERASE TIMING DIAGRAM
Three-byte sequence Software Entry ADDRESS A14-0 5555 2AAA 5555 0000 0001
TWPH DQ7-0 Device
F09.2
TIDA
Device SST39SF010 SST39SF020
FIGURE SOFTWARE ENTRY
READ
©2002 Silicon Storage Technology, Inc.
S71149-03-000 2/02
Kbit Mbit Multi-Purpose Flash SST39SF512 SST39SF010
THREE-BYTE SEQUENCE SOFTWARE EXIT RESET
ADDRESS A14-0
5555
2AAA
5555
DQ7-0
TIDA
F10.0
FIGURE SOFTWARE EXIT RESET
©2002 Silicon Storage Technology, Inc.
S71149-03-000 2/02
Kbit Mbit Multi-Purpose Flash SST39SF512 SST39SF010
VIHT
INPUT REFERENCE POINTS
OUTPUT
VILT
F11.0
test inputs driven VIHT (2.4V) logic VILT (0.4 logic "0". Measurement reference points inputs outputs (2.0 (0.8 Input rise fall times (10% 90%)
Note: VHIGH Test VLOW Test VIHT VINPUT HIGH Test VILT VINPUT Test
FIGURE INPUT/OUTPUT REFERENCE WAVEFORMS
TEST LOAD EXAMPLE TESTER HIGH
F12.1
FIGURE TEST LOAD EXAMPLE
©2002 Silicon Storage Technology, Inc.
S71149-03-000 2/02
Kbit Mbit Multi-Purpose Flash SST39SF512 SST39SF010
Start
Load data: Address: 5555H
Load data: Address: 2AAAH
Load data: Address: 5555H
Byte Address/Byte Data
Wait Program (TBP' Data# Polling Toggle operation) Program Completed
F13.1
FIGURE BYTE-PROGRAM ALGORITHM
©2002 Silicon Storage Technology, Inc.
S71149-03-000 2/02
Kbit Mbit Multi-Purpose Flash SST39SF512 SST39SF010
Internal Timer Program/Erase Initiated
Toggle Byte-Program/ Sector Erase Initiated
Data# Polling Byte-Program Initiated
Wait TBP, TSCE,
Read byte
Read
Program/Erase Completed
Read same byte
true data?
Does match?
Write Completed
Write Completed
F14.0
FIGURE WAIT OPTIONS
©2002 Silicon Storage Technology, Inc.
S71149-03-000 2/02
Kbit Mbit Multi-Purpose Flash SST39SF512 SST39SF010
Software Product Entry Command Sequence
Software Product Exit Reset Command Sequence
Load data: Address: 5555H
Load data: Address: 5555H
Load data: Address:
Load data: Address: 2AAAH
Load data: Address: 2AAAH
Wait TIDA
Load data: Address: 5555H
Load data: Address: 5555H
Return normal operation
Wait TIDA
Wait TIDA
Read Software
Return normal operation
F15.1
FIGURE SOFTWARE PRODUCT COMMAND FLOWCHARTS
©2002 Silicon Storage Technology, Inc.
S71149-03-000 2/02
Kbit Mbit Multi-Purpose Flash SST39SF512 SST39SF010
Chip-Erase Command Sequence Load data: Address: 5555H
Sector-Erase Command Sequence Load data: Address: 5555H
Load data: Address: 2AAAH
Load data: Address: 2AAAH
Load data: Address: 5555H
Load data: Address: 5555H
Load data: Address: 5555H
Load data: Address: 5555H
Load data: Address: 2AAAH
Load data: Address: 2AAAH
Load data: Address: 5555H
Load data: Address:
Wait TSCE
Wait
Chip-Erase
Sector-Erase
F16.1
FIGURE ERASE COMMAND SEQUENCE
©2002 Silicon Storage Technology, Inc.
S71149-03-000 2/02
Kbit Mbit Multi-Purpose Flash SST39SF512 SST39SF010
PRODUCT ORDERING INFORMATION
Device SST39SFxxx Speed Suffix1 Suffix2 Package Modifier pins leads Package Type PLCC PDIP TSOP (type 14mm) Temperature Range Commercial +70°C Industrial -40°C +85°C Minimum Endurance 10,000 cycles Read Access Speed Device Density Mbit Kbit Voltage 4.5-5.5V
Valid combinations SST39SF512 SST39SF512-70-4C-NH SST39SF512-90-4C-NH SST39SF512-70-4I-NH SST39SF512-90-4I-NH SST39SF512-70-4C-WH SST39SF512-90-4C-WH SST39SF512-70-4I-WH SST39SF512-90-4I-WH SST39SF512-70-4C-PH SST39SF512-90-4C-PH
Valid combinations SST39SF010 SST39SF010-70-4C-NH SST39SF010-90-4C-NH SST39SF010-90-4I-NH
Note:
SST39SF010-70-4C-WH SST39SF010-90-4C-WH SST39SF010-90-4I-WH
SST39SF010-70-4C-PH SST39SF010-90-4C-PH
Valid combinations those products mass production will mass production. Consult your sales representative confirm availability valid combinations determine availability combinations.
©2002 Silicon Storage Technology, Inc.
S71149-03-000 2/02
Kbit Mbit Multi-Purpose Flash SST39SF512 SST39SF010
PACKAGING DIAGRAMS
VIEW
Optional Identifier .048 .042 .495 .485 .453 .447
SIDE VIEW
.112 .106 .020 MAX. .029 .023 .040 .030
BOTTOM VIEW
.042 .048 .595 .553 .585 .547 .032 .026
.021 .013 .400 .530 .490
.050 .015 Min. .050 .095 .075 .140 .125 .032 .026
Note: Complies with JEDEC publication MS-016 dimensions, although some dimensions more stringent. linear dimensions inches (max/min). Dimensions include mold flash. Maximum allowable mold flash .008 inches. Coplanarity: mils.
32-plcc-NH-3
32-LEAD PLASTIC LEAD CHIP CARRIER (PLCC) PACKAGE CODE:
Identifier
1.05 0.95 0.50
8.10 7.90
0.27 0.17
12.50 12.30 DETAIL 1.20 max. 0.70 0.50 14.20 13.80
0.15 0.05
0.70 0.50 Note: Complies with JEDEC publication MO-142 dimensions, although some dimensions more stringent. linear dimensions millimeters (max/min). Coplanarity: Maximum allowable mold flash 0.15 package ends, 0.25 between leads.
32-tsop-WH-7
32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) PACKAGE CODE:
©2002 Silicon Storage Technology, Inc.
14MM
S71149-03-000 2/02
Kbit Mbit Multi-Purpose Flash SST39SF512 SST39SF010
Identifier
.075 .065 Base Plane Seating Plane
1.655 1.645
PLCS. .200 .170
.625 .600 .550 .530
.050 .015 .100 .150 .120
.012 .008 .600
.080 .070
.065 .045
.022 .016
Note: Complies with JEDEC publication MO-015 dimensions, although some dimensions more stringent. linear dimensions inches (max/min). Dimensions include mold flash. Maximum allowable mold flash .010 inches. 32-pdip-PH-3
32-PIN PLASTIC DUAL IN-LINE PINS (PDIP) PACKAGE CODE:
Silicon Storage Technology, Inc. 1171 Sonora Court Sunnyvale, 94086 Telephone 408-735-9110 408-735-9036 www.SuperFlash.com www.sst.com
©2002 Silicon Storage Technology, Inc. S71149-03-000 2/02

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