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SST27SF256 SST27SF512 SST27SF010 SST27SF020 SST27SF256 0205.0V-Re


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Kbit Kbit Mbit Mbit (x8) Many-Time Programmable Flash
SST27SF256 SST27SF512 SST27SF010 SST27SF020
SST27SF256 0205.0V-Read 256Kb 512Kb (x8) flash memories
FEATURES:
Organized 128K 256K 4.5-5.5V Read Operation Superior Reliability Endurance: least 1000 Cycles Greater than years Data Retention Power Consumption Active Current: (typical) Standby Current: (typical) Fast Read Access Time Fast Byte-Program Operation Byte-Program Time: (typical) Chip Program Time: seconds (typical) SST27SF256 seconds (typical) SST27SF512 seconds (typical) SST27SF010 seconds (typical) SST27SF020 Electrical Erase Using Programmer Does require source Chip-Erase Time: (typical) Compatibility JEDEC Standard Byte-wide EPROM Pinouts Packages Available 32-lead PLCC 32-lead TSOP (8mm 14mm) 28-pin PDIP SST27SF256/512 32-pin PDIP SST27SF010/020
PRODUCT DESCRIPTION
SST27SF256/512/010/020 128K 256K CMOS, Many-Time Programmable (MTP) cost flash, manufactured with SST's proprietary, high performance SuperFlash technology. split-gate cell design thick oxide tunneling injector attain better reliability manufacturability compared with alternate approaches. These devices electrically erased programmed least 1000 times using external programmer with volt power supply. They have erased prior programming. These devices conform JEDEC standard pinouts byte-wide memories. Featuring high performance Byte-Program, SST27SF256/512/010/020 provide Byte-Program time Designed, manufactured, tested wide spectrum applications, these devices offered with endurance least 1000 cycles. Data retention rated greater than years. SST27SF256/512/010/020 suited applications that require infrequent writes power nonvolatile storage. These devices will improve flexibility, efficiency, performance while matching cost nonvolatile applications that currently UV-EPROMs, OTPs, mask ROMs. meet surface mount conventional through hole requirements, SST27SF256/512 offered 32-lead PLCC, 32-lead TSOP 28-pin PDIP packages. SST27SF010/020 offered 32-pin PDIP 32-lead PLCC 32-lead TSOP packages. Figures pinouts.
©2002 Silicon Storage Technology, Inc. S71152-02-000 2/02
Device Operation
SST27SF256/512/010/020 cost flash solution that used replace existing UVEPROM, OTP, mask sockets. These devices functionally (read program) compatible with industry standard EPROM products. addition EPROM functionality, these devices also support electrical Erase operation external programmer. They require source erase, therefore packages have window.
Read
Read operation SST27SF256/512/010/020 controlled OE#. Both have system obtain data from outputs. Once address stable, address access time equal delay from output (TCE). Data available output after delay from falling edge OE#, assuming that been addresses have been stable least TCE-TOE. When high, chip deselected typical standby current consumed. output control used gate data from output pins. data high impedance state when either high.
logo SuperFlash registered trademarks Silicon Storage Technology, Inc. Many-Time Programmable trademarks Silicon Storage Technology, Inc. These specifications subject change without notice.
Kbit Kbit Mbit Mbit Many-Time Programmable Flash SST27SF256 SST27SF512 SST27SF010 SST27SF020
Byte-Program Operation
SST27SF256/512/010/020 programmed using external programmer. programming mode SST27SF256/010/020 activated asserting 11.4-12.6V pin, 4.5-5.5V, pin, pin. programming mode SST27SF512 activated asserting 11.4-12.6V OE#/VPP pin, 4.55.5V, pin. These devices programmed byte-by-byte with desired data desired address using single pulse (CE# SST27SF256/512 PGM# SST27SF010/020) Using programming algorithm, Byte-Programming process continues byte-by-byte until entire chip been programmed.
pins "don't care". falling edge (PGM# SST27SF010/020) will start Chip-Erase operation. Once chip been erased, bytes must verified FFH. Refer Figures flowcharts.
Product Identification Mode
Product Identification mode identifies devices SST27SF256, SST27SF512, SST27SF010 SST27SF020 manufacturer SST. This mode accessed hardware method. activate this mode SST27SF256/010/020, programming equipment must force (11.4-12.6V) address with (4.5-5.5V) VSS. activate this mode SST27SF512, programming equipment must force (11.4-12.6V) address with OE#/VPP VIL. identifier bytes then sequenced from device outputs toggling address line details, Tables hardware operation. TABLE PRODUCT IDENTIFICATION
Address Manufacturer's Device SST27SF256 SST27SF512 SST27SF010 SST27SF020 0001H 0001H 0001H 0001H
T1.1
Chip-Erase Operation
only change data from electrical erase that changes every device "1". Unlike traditional EPROMs, which light ChipErase, SST27SF256/512/010/020 uses electrical Chip-Erase operation. This saves significant amount time (about minutes each Erase operation). entire chip erased single pulse (CE# SST27SF256/512 PGM# SST27SF010/020). order activate Erase mode SST27SF256/010/020, 11.4-12.6V applied pins, 4.5-5.5V, pin, pin. order activate Erase mode SST27SF512, 11.4-12.6V applied OE#/VPP pins, 4.5-5.5V, pin. other address data FUNCTIONAL BLOCK DIAGRAM SST27SF256
Data
0000H
X-Decoder
SuperFlash Memory
Address Buffer Y-Decoder
Control Logic
Buffers
B1.1
©2002 Silicon Storage Technology, Inc.
S71152-02-000 2/02
Kbit Kbit Mbit Mbit Many-Time Programmable Flash SST27SF256 SST27SF512 SST27SF010 SST27SF020
FUNCTIONAL BLOCK DIAGRAM
SST27SF512
X-Decoder
SuperFlash Memory
Address Buffer Y-Decoder
OE#/VPP
Control Logic
Buffers
B2.1
FUNCTIONAL BLOCK DIAGRAM SST27SF010/020
X-Decoder
SuperFlash Memory
Address Buffer Y-Decoder
PGM#
Buffers Control Logic
B3.2
SST27SF020, SST27SF010
©2002 Silicon Storage Technology, Inc.
S71152-02-000 2/02
Kbit Kbit Mbit Mbit Many-Time Programmable Flash SST27SF256 SST27SF512 SST27SF010 SST27SF020
SST27SF256 SST27SF512 SST27SF010 SST27SF020
PGM# PGM#
SST27SF020 SST27SF010 SST27SF512 SST27SF256 SST27SF020 SST27SF010 SST27SF512 SST27SF256
SST27SF256 SST27SF512 SST27SF010 SST27SF020 OE#/VPP
F02c.3
32-lead PLCC View
FIGURE ASSIGNMENTS 32-LEAD PLCC
©2002 Silicon Storage Technology, Inc.
S71152-02-000 2/02
Kbit Kbit Mbit Mbit Many-Time Programmable Flash SST27SF256 SST27SF512 SST27SF010 SST27SF020
SST27SF020 SST27SF010 SST27SF512 SST27SF256
PGM# PGM#
SST27SF256
SST27SF512 SST27SF010 SST27SF020
OE#/VPP
Standard Pinout View
F01.1
FIGURE ASSIGNMENTS 32-LEAD TSOP (8MM
14MM)
SST27SF020 SST27SF010 SST27SF512 SST27SF256 SST27SF256
F02a.1
SST27SF010 SST27SF020 32-pin PDIP View PGM#
F02b.1
SST27SF512 OE#/VPP
28-pin PDIP View
PGM#
FIGURE ASSIGNMENTS 28-PIN
32-PIN PDIP
©2002 Silicon Storage Technology, Inc.
S71152-02-000 2/02
Kbit Kbit Mbit Mbit Many-Time Programmable Flash SST27SF256 SST27SF512 SST27SF010 SST27SF020
Data Sheet TABLE DESCRIPTION
Symbol AMS1-A0 DQ7-DQ0 OE#/VPP Name Address Inputs Data Input/output Chip Enable Output Enable Output Enable/VPP Power Supply Program Erase Power Supply Ground Connection Unconnected pins.
T2.4
Functions provide memory addresses output data during Read cycles receive input data during Program cycles outputs tri-state when high. activate device when SST27SF256/010/020, gate data output buffers during Read operation SST27SF512, gate data output buffers during Read operation high voltage during Chip-Erase programming operation SST27SF256/010/020, high voltage during Chip-Erase programming operation 11.4-12.6V provide 5.0V supply (4.5-5.5V)
Most significant address SST27SF256, SST27SF512, SST27SF010, SST27SF020
TABLE OPERATION MODES SELECTION
Mode Read Output Disable Byte-Program Standby Chip-Erase Program/Erase Inhibit Product Identification
SST27SF256
DOUT High High High High Manufacturer's (BFH) Device (A3H) Address A14-A1=VIL, A0=VIL A14-A1=VIL, A0=VIH
T3.2
VPPH VPPH VPPH
VIH, other value. Note: VPPH 11.4-12.6V, 11.4-12.6V
TABLE OPERATION MODES SELECTION
Mode Read Output Disable Program Standby Chip-Erase Program/Erase Inhibit Product Identification
SST27SF512
DOUT High High High High Manufacturer's (BFH) Device (A4H) Address A15-A1=VIL, A0=VIL A15-A1=VIL, A0=VIH
T4.2
OE#/VPP VPPH VPPH VPPH
VIH, other value. Note: VPPH 11.4-12.6V, 11.4-12.6V
©2002 Silicon Storage Technology, Inc.
S71152-02-000 2/02
Kbit Kbit Mbit Mbit Many-Time Programmable Flash SST27SF256 SST27SF512 SST27SF010 SST27SF020
Data Sheet TABLE OPERATION MODES SELECTION
Mode Read Output Disable Program Standby Chip-Erase Program/Erase Inhibit Product Identification PGM#
SST27SF010/020
VPPH VPPH VPPH DOUT High High High High Manufacturer's (BFH) Device Address AMS3 A1=VIL, A0=VIL AMS3 A1=VIL, A0=VIH
T5.2
VIH, other value. Device SST27SF010 SST27SF020 Most significant address SST27SF010 SST27SF020 Note: VPPH 11.4-12.6V, 11.4-12.6V
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" cause permanent damage device. This stress rating only functional operation device these conditions conditions greater than those defined operational sections this data sheet implied. Exposure absolute maximum stress rating conditions affect device reliability.) Temperature Under Bias -55°C +125°C Storage Temperature -65°C +150°C Voltage Ground Potential -0.5V VDD+0.5V Transient Voltage (<20 Ground Potential -2.0V VDD+2.0V Voltage Ground Potential -0.5V 14.0V Package Power Dissipation Capability 25°C) 1.0W Through Hold Lead Soldering Temperature Seconds) 300°C Surface Mount Lead Soldering Temperature Seconds) 240°C Output Short Circuit Current1
Outputs shorted more than second. more than output shorted time.
OPERATING RANGE
Range Commercial Ambient Temp +70°C 4.5-5.5V 11.4-12.6V
CONDITIONS
TEST
Input Rise/Fall Time Output Load Output Load Figures
©2002 Silicon Storage Technology, Inc.
S71152-02-000 2/02
Kbit Kbit Mbit Mbit Many-Time Programmable Flash SST27SF256 SST27SF512 SST27SF010 SST27SF020
Data Sheet TABLE READ MODE OPERATING CHARACTERISTICS SST27SF256/512/010/020 4.5-5.5V, VPP=VDD +70°C (Commercial))
Limits Symbol Parameter Read Current IPPR Read Current ISB1 ISB2 Standby Current (TTL input) Standby Current (CMOS input) Input Leakage Current Output Leakage Current Input Voltage Input High Voltage Output Voltage Output High Voltage Supervoltage Current VDD+0.5 Units Test Conditions Address input=VIL/VIH f=1/TRC VDD=VDD CE#=OE#=VIL, I/Os open Address input=VIL/VIH f=1/TRC VDD=VDD Max, VPP=VDD CE#=OE#=VIL, I/Os open CE#=VIH, VDD=VDD CE#=VDD-0.3 VDD=VDD VIN=GND VDD, VDD=VDD VOUT=GND VDD, VDD=VDD VDD=VDD VDD=VDD IOL=2.1 VDD=VDD IOH=-400 VDD=VDD CE#=OE#=VIL, A9=VH
T6.3
TABLE PROGRAM/ERASE OPERATING CHARACTERISTICS VDD=4.5-5.5V, VPP=VPPH (Ta=25°C±5°C)
Limits Symbol Parameter VPPH Erase Program Current Erase Program Current Input Leakage Current Output Leakage Current Supervoltage Supervoltage Current High Voltage 11.4 11.4 12.6 12.6 Units
SST27SF256
Test Conditions CE#=VIL, OE#=VIH, VPP=11.4-12.6V, VDD=VDD CE#=VIL, OE#=VIH, VPP=11.4-12.6V, VDD=VDD VIN=GND VDD, VDD=VDD VOUT=GND VDD, VDD=VDD CE#=OE#=VIL, CE#=OE#=VIL, A9=VH
T7.3
©2002 Silicon Storage Technology, Inc.
S71152-02-000 2/02
Kbit Kbit Mbit Mbit Many-Time Programmable Flash SST27SF256 SST27SF512 SST27SF010 SST27SF020
Data Sheet TABLE PROGRAM/ERASE OPERATING CHARACTERISTICS VDD=4.5-5.5V, VPP=VPPH (Ta=25°C±5°C)
Limits Symbol Parameter VPPH Erase Program Current Erase Program Current Input Leakage Current Output Leakage Current Supervoltage Supervoltage Current High Voltage OE#/VPP Units Test Conditions 11.4 12.6 11.4 12.6
T8.3
SST27SF512
CE#=VIL, OE#/VPP=11.4-12.6V, VDD=VDD CE#=VIL, OE#/VPP=11.4-12.6V, VDD=VDD VIN=GND VDD, VDD=VDD VOUT=GND VDD, VDD=VDD CE#=OE#/VPP=VIL, CE#=OE#/VPP=VIL, A9=VH
TABLE PROGRAM/ERASE OPERATING CHARACTERISTICS VDD=4.5-5.5V, VPP=VPPH (Ta=25°C±5°C)
Limits Symbol Parameter VPPH Erase Program Current Erase Program Current Input Leakage Current Output Leakage Current Supervoltage Supervoltage Current High Voltage
SST27SF010/020
Units Test Conditions
T9.3
CE#=PGM#=VIL, OE#=VIH, VPP=11.4-12.6V, VDD=VDD CE#=PGM#=VIL, OE#=VIH, VPP=11.4-12.6V, VDD=VDD =GND VDD, VDD=VDD VOUT =GND VDD, VDD=VDD CE#=OE#=VIL, CE#=OE#=VIL, A9=VH
11.4 12.6 11.4 12.6
TABLE RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol TPU-READ1 TPU-WRITE
Parameter Power-up Read Operation Power-up Write Operation
Minimum
Units
T10.1
This parameter measured only initial qualification after design process change that could affect this parameter.
TABLE CAPACITANCE
Parameter CI/O
25°C, Mhz, other pins open)
Description Capacitance Input Capacitance
Test Condition VI/O
Maximum
T11.0
CIN1
This parameter measured only initial qualification after design process change that could affect this parameter.
©2002 Silicon Storage Technology, Inc.
S71152-02-000 2/02
Kbit Kbit Mbit Mbit Many-Time Programmable Flash SST27SF256 SST27SF512 SST27SF010 SST27SF020
Data Sheet TABLE RELIABILITY CHARACTERISTICS
Symbol NEND1 TDR1 ILTH1 Parameter Endurance Data Retention Latch Minimum Specification 1000 Units Cycles Years Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard
T12.2
This parameter measured only initial qualification after design process change that could affect this parameter.
CHARACTERISTICS
TABLE READ CYCLE TIMING PARAMETERS 4.5-5.5V
+70°C (Commercial))
SST27SF256-70 SST27SF512-70 SST27SF010-70 SST27SF020-70 Symbol TCLZ1 TOLZ1 TCHZ1 TOHZ1 TOH1 Parameter Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time Active Output Active Output High High-Z Output High High-Z Output Output Hold from Address Change
SST27SF256-90 SST27SF512-90 SST27SF010-90 SST27SF020-90 Units
T13.2
This parameter measured only initial qualification after design process change that could affect this parameter.
TABLE PROGRAM/ERASE CYCLE TIMING PARAMETERS
Symbol TPRT TVPS TVPH TART TA9S TA9H Parameter Address Setup Time Address Hold Time Pulse Rise Time Setup Time Hold Time Program Pulse Width Erase Pulse Width Data Setup Time Data Hold Time Recovery Time Rise Time during Erase Setup Time during Erase Hold Time during Erase
SST27SF256
Units
T14.0
©2002 Silicon Storage Technology, Inc.
S71152-02-000 2/02
Kbit Kbit Mbit Mbit Many-Time Programmable Flash SST27SF256 SST27SF512 SST27SF010 SST27SF020
Data Sheet TABLE PROGRAM/ERASE CYCLE TIMING PARAMETERS
Symbol TPRT TVPS TVPH TART TA9S TA9H Parameter Address Setup Time Address Hold Time OE#/VPP Pulse Rise Time OE#/VPP Setup Time OE#/VPP Hold Time Program Pulse Width Erase Pulse Width Data Setup Time Data Hold Time OE#/VPP Recovery Time Rise Time during Erase Setup Time during Erase Hold Time during Erase
SST27SF512
Units
T15.0
TABLE PROGRAM/ERASE CYCLE TIMING PARAMETERS
Symbol TCES TCEH TPRT TVPS TVPH TART TA9S TA9H Parameter Setup Time Hold Time Address Setup Time Address Hold Time Pulse Rise Time Setup Time Hold Time PGM# Program Pulse Width PGM# Erase Pulse Width Data Setup Time Data Hold Time Recovery Time Erase Rise Time during Erase Setup Time during Erase Hold Time during Erase
SST27SF010/020
Units
T16.0
©2002 Silicon Storage Technology, Inc.
S71152-02-000 2/02
Kbit Kbit Mbit Mbit Many-Time Programmable Flash SST27SF256 SST27SF512 SST27SF010 SST27SF020
ADDRESS
TOLZ
TOHZ DATA VALID TCHZ DATA VALID
DQ7-0
HIGH-Z TCLZ
F03.0
FIGURE READ CYCLE TIMING DIAGRAM
SST27SF256/512/010/020
ADDRESS (EXCEPT
DQ7-0 VPPH VPPH TART TA9H
F04a.1
TVPS TVPH TPRT
TA9S
FIGURE CHIP-ERASE TIMING DIAGRAM
SST27SF256
©2002 Silicon Storage Technology, Inc.
S71152-02-000 2/02
Kbit Kbit Mbit Mbit Many-Time Programmable Flash SST27SF256 SST27SF512 SST27SF010 SST27SF020
ADDRESS (EXCEPT
DQ7-0
VPPH OE#/VPP VPPH TART TPRT
TVPS TVPH
TA9S
TA9H
F04b.1
FIGURE READ CYCLE TIMING DIAGRAM
SST27SF512
ADDRESS (EXCEPT
TCEH
DQ7-0 VPPH VPPH TART TA9H PGM# TCES
F04c.1
TVPS TVPH TPRT TA9S
FIGURE CHIP-ERASE TIMING DIAGRAM
SST27SF010/020
©2002 Silicon Storage Technology, Inc.
S71152-02-000 2/02
Kbit Kbit Mbit Mbit Many-Time Programmable Flash SST27SF256 SST27SF512 SST27SF010 SST27SF020
ADDRESS
ADDRESS VALID
DQ7-0
HIGH-Z VPPH
DATA VALID
TVPS
TPRT
TVPH
F05a.1
FIGURE BYTE-PROGRAM TIMING DIAGRAM
SST27SF256
ADDRESS
ADDRESS VALID
DQ7-0
HIGH-Z
DATA VALID
VPPH OE#/VPP
TPRT
TVPS
TVPH
F05b.2
FIGURE BYTE-PROGRAM TIMING DIAGRAM
SST27SF512
©2002 Silicon Storage Technology, Inc.
S71152-02-000 2/02
Kbit Kbit Mbit Mbit Many-Time Programmable Flash SST27SF256 SST27SF512 SST27SF010 SST27SF020
ADDRESS
ADDRESS VALID
TCEH
DQ7-0
HIGH-Z VPPH
DATA VALID
TVPS
PGM#
TPRT
TVPH
TCES
F05c.1
FIGURE BYTE-PROGRAM TIMING DIAGRAM
SST27SF010/020
©2002 Silicon Storage Technology, Inc.
S71152-02-000 2/02
Kbit Kbit Mbit Mbit Many-Time Programmable Flash SST27SF256 SST27SF512 SST27SF010 SST27SF020
VIHT
INPUT REFERENCE POINTS
OUTPUT
VILT
F06.0
test inputs driven VIHT (2.4 logic VILT (0.4 logic "0". Measurement reference points inputs outputs (2.0 (0.8 Input rise fall times (10% 90%)
Note: VHIGHTest VLOW Test VIHT VINPUT HIGH Test VILT VINPUT Test
FIGURE INPUT/OUTPUT REFERENCE WAVEFORMS
TESTER HIGH
F07.1
FIGURE TEST LOAD EXAMPLE
©2002 Silicon Storage Technology, Inc.
S71152-02-000 2/02
Kbit Kbit Mbit Mbit Many-Time Programmable Flash SST27SF256 SST27SF512 SST27SF010 SST27SF020
Start
VPPH,
Erase 100ms pulse (CE# VIL)
Wait Recovery Time
Read Device (CE# VIL)
Compare bytes
Device Passed
Device Failed
F08a.2
FIGURE CHIP-ERASE ALGORITHM
SST27SF256
©2002 Silicon Storage Technology, Inc.
S71152-02-000 2/02
Kbit Kbit Mbit Mbit Many-Time Programmable Flash SST27SF256 SST27SF512 SST27SF010 SST27SF020
Start
OE#/VPP VPPH
Erase 100ms pulse (CE# VIL)
OE#/VPP
Wait OE#/VPP Recovery Time Read Device (CE# VIL)
Compare bytes
Device Passed
Device Failed
F08b.2
FIGURE CHIP-ERASE ALGORITHM
SST27SF512
©2002 Silicon Storage Technology, Inc.
S71152-02-000 2/02
Kbit Kbit Mbit Mbit Many-Time Programmable Flash SST27SF256 SST27SF512 SST27SF010 SST27SF020
Start
VPPH
VIL, Erase 100ms pulse (PGM# VIL)
PGM#
Wait Recovery Time
Read Device
Compare bytes
Device Passed
Device Failed
F08c.1
FIGURE CHIP-ERASE ALGORITHM
SST27SF010/020
©2002 Silicon Storage Technology, Inc.
S71152-02-000 2/02
Kbit Kbit Mbit Mbit Many-Time Programmable Flash SST27SF256 SST27SF512 SST27SF010 SST27SF020
Start
Erase*
VPPH
Address First Location
Program 20µs pulse (CE# VIL)
Increment Address
Last Address?
Wait RecoveryTime Read Device (CE# VIL)
Compare bytes original data
Device Passed
Device Failed
F09a.3
Figure
FIGURE BYTE-PROGRAM ALGORITHM
SST27SF256
©2002 Silicon Storage Technology, Inc.
S71152-02-000 2/02
Kbit Kbit Mbit Mbit Many-Time Programmable Flash SST27SF256 SST27SF512 SST27SF010 SST27SF020
Start
Erase*
OE#/VPP VPPH
Address First Location
Program 20µs pulse (CE# VIL)
Increment Address
Last Address?
OE#/VPP
Wait OE#/VPP RecoveryTime Read Device (CE# VIL)
Compare bytes original data
Device Passed
Device Failed
F09b.2
Figure
FIGURE BYTE-PROGRAM ALGORITHM
SST27SF512
©2002 Silicon Storage Technology, Inc.
S71152-02-000 2/02
Kbit Kbit Mbit Mbit Many-Time Programmable Flash SST27SF256 SST27SF512 SST27SF010 SST27SF020
Start
Erase*
VPPH
Address First Location
VIL,
Program 20µs pulse (PGM# VIL)
Increment Address
Last Address?
Read Device
Compare bytes original data
Device Passed
Device Failed
F09c.1
Figure
FIGURE BYTE-PROGRAM ALGORITHM
SST27SF010/020.
©2002 Silicon Storage Technology, Inc.
S71152-02-000 2/02
Kbit Kbit Mbit Mbit Many-Time Programmable Flash SST27SF256 SST27SF512 SST27SF010 SST27SF020
PRODUCT ORDERING INFORMATION
Device SST27SFxxx Speed Suffix1 Suffix2 Package Modifier pins pins leads Package Type PLCC PDIP TSOP (type 14mm) Temperature Range Commercial +70°C Minimum Endurance 1,000 cycles Read Access Speed Device Density Organization Mbit Mbit Kbit Kbit Function Chip-Erase Byte-Program Voltage Range 4.5-5.5V
©2002 Silicon Storage Technology, Inc.
S71152-02-000 2/02
Kbit Kbit Mbit Mbit Many-Time Programmable Flash SST27SF256 SST27SF512 SST27SF010 SST27SF020
Data Sheet Valid combinations SST27SF256 SST27SF256-70-3C-NH SST27SF256-90-3C-NH SST27SF256-70-3C-WH SST27SF256-90-3C-WH SST27SF256-70-3C-PG SST27SF256-90-3C-PG
Valid combinations SST27SF512 SST27SF512-70-3C-NH SST27SF512-90-3C-NH SST27SF512-70-3C-WH SST27SF512-90-3C-WH SST27SF512-70-3C-PG SST27SF512-90-3C-PG
Valid combinations SST27SF010 SST27SF010-70-3C-NH SST27SF010-90-3C-NH SST27SF010-70-3C-WH SST27SF010-90-3C-WH SST27SF010-70-3C-PH SST27SF010-90-3C-PH
Valid combinations SST27SF020 SST27SF020-70-3C-NH SST27SF020-90-3C-NH
Note:
SST27SF020-70-3C-WH SST27SF020-90-3C-WH
SST27SF020-70-3C-PH SST27SF020-90-3C-PH
Valid combinations those products mass production will mass production. Consult your sales representative confirm availability valid combinations determine availability combinations.
©2002 Silicon Storage Technology, Inc.
S71152-02-000 2/02
Kbit Kbit Mbit Mbit Many-Time Programmable Flash SST27SF256 SST27SF512 SST27SF010 SST27SF020
PACKAGING DIAGRAMS
VIEW
Optional Identifier .048 .042 .495 .485 .453 .447
SIDE VIEW
.112 .106 .020 MAX. .029 .023 .040 .030
BOTTOM VIEW
.042 .048 .595 .553 .585 .547 .032 .026
.021 .013 .400 .530 .490
.050 .015 Min. .050 .095 .075 .140 .125 .032 .026
Note: Complies with JEDEC publication MS-016 dimensions, although some dimensions more stringent. linear dimensions inches (max/min). Dimensions include mold flash. Maximum allowable mold flash .008 inches. Coplanarity: mils.
32-plcc-NH-3
32-LEAD PLASTIC LEAD CHIP CARRIER (PLCC) PACKAGE CODE:
Identifier
1.05 0.95 0.50
8.10 7.90
0.27 0.17
12.50 12.30 DETAIL 1.20 max. 0.70 0.50 14.20 13.80
0.15 0.05
0.70 0.50 Note: Complies with JEDEC publication MO-142 dimensions, although some dimensions more stringent. linear dimensions millimeters (max/min). Coplanarity: Maximum allowable mold flash 0.15 package ends, 0.25 between leads.
32-tsop-WH-7
32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) PACKAGE CODE:
©2002 Silicon Storage Technology, Inc.
14MM
S71152-02-000 2/02
Kbit Kbit Mbit Mbit Many-Time Programmable Flash SST27SF256 SST27SF512 SST27SF010 SST27SF020
Identifier
.075 .065 Base Plane Seating Plane
1.455 1.445
PLCS. .200 .170
.625 .600 .550 .530
.050 .015 .100 .150 .120
.012 .008 .600
.080 .070
.065 .045
.022 .016
Note: Complies with JEDEC publication MO-015 dimensions, although some dimensions more stringent. linear dimensions inches (max/min). Dimensions include mold flash. Maximum allowable mold flash .010 inches. 28-pdip-PG-3
28-PIN PLASTIC DUAL IN-LINE PINS (PDIP) PACKAGE CODE:
Identifier
.075 .065 Base Plane Seating Plane
1.655 1.645
PLCS. .200 .170
.625 .600 .550 .530
.050 .015 .100 .150 .120
.012 .008 .600
.080 .070
.065 .045
.022 .016
Note: Complies with JEDEC publication MO-015 dimensions, although some dimensions more stringent. linear dimensions inches (max/min). Dimensions include mold flash. Maximum allowable mold flash .010 inches. 32-pdip-PH-3
32-PIN PLASTIC DUAL IN-LINE PINS (PDIP) PACKAGE CODE:
Silicon Storage Technology, Inc. 1171 Sonora Court Sunnyvale, 94086 Telephone 408-735-9110 408-735-9036 www.SuperFlash.com www.sst.com
©2002 Silicon Storage Technology, Inc. S71152-02-000 2/02

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