SARA-LiteSAR Type with Traffic, Frame Relay LANE Support INTRODUCTION

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PRODUCT SUMMARY SARA-LiteAAAL0/5 Segmentation Reassembly Product TXC-05551/L
SARA-LiteSAR Type with Traffic, Frame Relay LANE Support INTRODUCTION
TranSwitch SARA-Liteproduct provides ultra high-performance ASegmentation Reassembly (SAR) processing with programmable flexibility. consists separate hardware software parts, namely SARA-2 ACell Processing Integrated Circuit (IC) Device SARA-Lite Microcode. This microcode loaded into instruction memory SARA-2's integral RISC processor enables perform specific Type functions SARA-Lite with CBR, traffic, well providing support implementation frame relay emulation services software. Product documentation applications support available OEMs wish undertake design systems incorporating SARA-Lite. SARA-2 ACell Processing includes integrated RISC engine OC-3 SONET/SDH framer. contains several functional blocks that provide optimal cell processing rates Mbit/s careful hardwired logic programmable microcode. subsystem, SARA-2 ACommunications Processor (ACP), RISC processor with additional specialized instructions cell processing. This engine, along with powerful on-chip memory controllers, hardware hash table lookup mechanism, high-performance cell/line interface functions, enables SARA-Lite support various data networking applications. Furthermore, other functions added future microcode changes standards system requirements evolve. This document describes operation SARA-Lite AAAL0/5 Segmentation Reassembly solution following sections: Page SARA-Lite System Overview Segmentation Reassembly Packets into/from ACells SARA-Lite Traffic Scheduling Hash Mechanisms AAL0 Cells Support Frame Relay Service/AInterworking Emulation (LANE) Service Related Documents
Please refer TranSwitch documents listed Section 7.1, which complete description SARA-Lite product.
Copyright 1998 TranSwitch Corporation TranSwitch, SARA registered trademarks TranSwitch Corporation SARA-Lite trademark TranSwitch Corporation. Microsoft, Windows Windows either trademarks registered trademarks Microsoft Corporation. Other brand, product company names mentioned herein property their respective owners.
Document Number: TXC-05551-SCDA-PS1 January 1998
TranSwitch Corporation
Enterprise Drive Shelton, 06484 Tel: 203-929-8810 Fax: 203-926-9453 www.transwitch.com
SARA-LiteTXC-05551/L SARA-Lite SYSTEM OVERVIEW
SARA-Lite combines versatility programmable RISC architecture with optimized hardware platform perform ASAR functions. SARA-2 ACell Processing Device core hardware platform used conjunction with RISC microcode implement functionality. Figure graphically depicts concept SARA-2 programmable architecture together with SARA-Lite microcode implement following functions: Implementation Common Part Convergence Sublayer (CPCS) Type which includes: Support message mode: fixed variable length 65,535 bytes) CPCS-SDU support Non-assured operation: event corrupted CPCS-SDU, re-transmission supported Preservation sequence integrity connection Preservation information byte) 48-byte alignment CPCS-PDU trailer Insertion bytes CPCS-PDU Insertion length field trailer CRC-32 field calculation trailer Implementation Sublayer Type including: Segmentation variable length CPCS-PDUs into 48-byte PDUs Reassembly 48-byte PDUs into variable length CPCS PDUs Creation 53-byte Acells adding header Exception conditions include: Error cell syntax: header CRC, payload Error received packet: end-of-frame received before beginning packet error conditions error conditions
SARA-2 ACell Processing Part Number TXC-05551-ACBG
SARA-Lite Microcode Part Number TXC-05551-SCDA
SARA-LiteProduct TXC-05551/L
AAL0/5 CBR, Traffic Frame Relay Support Emulation Support
Figure SARA-Lite Product Overview
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AAL0 Cells support 64-byte 48-byte AAL0 supported When 64-byte mode selected, complete 64-byte cell buffer copied into/from external host buffer, rather than 48-byte cell payload Frame Relay Service (FRS) support Interworking Function support Discard Eligibility (DE) mapping FECN EFCI mapping Emulation (LANE) support LECID receive filtering DATA STRUCTURES SARA-Lite
SARA-Lite requires several data structures operation, which control data flow, packet transfers from/to host memory, traffic management, maintenance functions. specific contents each data structures will covered following sections. However, overview each intervening structures will given this section. Figure shows typical environment which SARA-Lite operates with three distinct interfaces: connection host processor, (ii) local control memory, (iii) cell interface. control SARA-Lite performed interface from host processor, which typically will part station with number slots. However, possible implement single PCB. control memory used SARA-Lite store data control temporary buffering incoming and/or outgoing cells.The cell interface transmits receives Acells either UTOPIA SONET/SDH framer. Regarding data structures, actual usage SARA-Lite context sensitive. meaning information these data structures interaction with host controller will understood when specific operation SARA-Lite addressed later this document. this time, summary data structures provided, with brief explanation their function overall operation. More detailed information provided Data Sheet SARA-2 ACell Processing Device, document number TXC-05551MB. RISC Controller Structures SARA-Lite RISC core requires various stacks stack pointers, some local variables, configuration information, dynamic memory allocation heap. These automatically initialized external RISC core upon power-up. Reassembly Hash Table Reassembly Hash Table consists linear array 24-bit pointers chains Reassembly structures. hash table logic performs hash VPI/VCI fields each received Acell header derive table index entry Reassembly Hash Table. hash index computation controlled three registers which provide 16-bit masks 4-bit shift value. programming different binary patterns into mask registers using different shift values, different hash functions generated.
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Host Buffers
SARA-Lite
Reg. Reassembly, Hashing LinkI Queue
Service
Cell FIFO LinkI LinkO UTOPIA/ Framer Cell Interface
DMAI
RISC
DMAO
Segmentation, Traffic shaping
Free Cell Buffer pointer queue
Memory Controller Control Memory
Indicate Pool Free Cell Buffer Pool Pool
Rate Control Table (RCT)
Reassembly Hash Table
Reassembly Buffer Pool
Segmentation structures
Allocated Cell Buffer
Reassembly structures
Figure SARA-Lite Operating Environment Rate Control Table (RCT) SARA-Lite uses Rate Control Table provide precise control over granularity rates requested virtual circuit also provide flexibility multiplexing different virtual circuits. also used determine burst size sustainable cell rate (SCR) allocated each virtual circuit. traffic shaping hardware device traverses Rate Control Table schedule cell transmissions. Rate Control Table linear array 32-bit entries. Each entry points segmentation structure entry. During segmentation, Rate Control Table traversed sequentially each entry provided service according control bits. Each entry table corresponds virtual circuit. When entry Rate Control Table serviced, more Acells (based burst size Segmentation structure) sent from that virtual circuit. Rate Control Table entry also specify null entry idle cell sent) skip entry (that entry skipped). virtual circuit serviced when virtual circuit pointed Rate Control Table does have cell send, when Rate Control Table entry specifies null cell. virtual circuits maintained circular linked list, resulting round-robin servicing virtual circuits.
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Virtual Circuit Structures Data structures associated with both Segmentation Reassembly referred Segmentation structures Reassembly structures, respectively. These structures used SARA-Lite control segmentation reassembly cells into appropriate VCs. segmentation structure contains information relating each virtual connection segmentation. separate structure present each virtual circuit, whether CBR/VBR UBR. When virtual connection established, contents entry corresponding virtual circuit initialized software. structure indicates type associated with virtual circuit contains other control status information specific virtual circuit. additional field structure provides pointer active Buffer Descriptors. reassembly structure contains information relating each virtual circuit reassembly. When virtual circuit established, contents structure corresponding virtual circuit initialized software. structure indicates type associated with virtual circuit contains various control status information related virtual circuit. additional field entry provides pointer active Buffer Descriptors. Buffer Descriptors (BD) SARA-Lite segments reassembles packets using host buffer memory. Buffer Descriptors 16-byte structures that describe parameters blocks data free buffers. Each entry contains parameters segmenting packets location buffer packet memory. When packet segmentation, available Buffer Descriptor initialized with packet parameters. Similarly, free Buffer Descriptors used reassemble cells into packets. Buffer descriptors chained together linked list support sophisticated scatter gather algorithms support efficient packet memory management. Host Request Indicate Ring Structures host software interacts with SARA-2 service interface consisting request indicate message rings host memory. Both high priority rings maintained waiting messages with high priority will served before message priority. host sends request message, such connection set-up packet segmentation, SARA-2 request rings. SARA-2 sends response notification indicate message, such packet reassembly completion cell receive notification, host indicate rings. SARA-Lite host interface logic implements associated request ring indicate ring logic which facilitates exchange messages between host software (e.g., device drivers) on-chip RISC microcode with very overhead either interrupt-driven polled manner. message rings have hardware support minimizing message interrupt overhead also setting bounds interrupt overhead. request indicate message structure similar Buffer Descriptor (i.e., 16-byte entries). Message Pool Message Pool linked list free 16-byte message descriptors. messages from request rings host memory transferred into these descriptors. message packet segmentation, this descriptor then linked associated segmentation structure. host buffer allocated packet reassembly, linked either Reassembly Buffer Pool, specific Reassembly structure. Reassembly Buffer Pool Reassembly Buffer Pool linked list free host buffer descriptors. used SARA-2 queue Buffer Descriptors host buffers that available packet reassembly. When SARA-2 receives first cell packet, fetches descriptor from this queue starts reassembly host buffer pointed descriptor. Indicate Pool Indicate Message Pool used SARA-2 queue response notification messages host before these messages forwarded indicate rings.
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Cell Buffers (CB) cell buffers 64-byte memory segments local control memory used temporary storage cells segmentation reassembly. These buffers allow lossless reassembly even under large latency restrictions. INITIALIZATION PROCEDURES
These procedures perform following functions: Initialize registers SARA-2, such control registers. service interface rings (indicate request rings). Download microcode. host buffers transmit receive data operations.
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SARA-LiteTXC-05551/L SEGMENTATION REASSEMBLY PACKETS INTO/FROM ACELLS
AADAPTATION LAYER
SARA-Lite been designed support segmentation reassembly functions required achieve packet transmission across Anetwork SMDS network). this following section, these functions, defined ANSI draft standards B-ISDN, briefly reviewed. Figure illustrates protocol model variable rate (i.e., packet based) AAdaptation Layer (AAL) Type defined ANSI draft standards1,2. split into three sublayers. service specific convergence sublayer (SSCS) used additional service features such assured transfer (error correction retransmission). null sublayer unassured transfer (error detection correction). Common Part Convergence Sublayer (CPCS) performs error detection control functions frame level. Segmentation Reassembly Sublayer (SAR) performs functions necessary segment frames into Acells reassemble multiplexed stream Acells back into their original frames. SARA-Lite supports functions CPCS sublayers AAL5 common part, some functions Alayer.
User Layer Service-Specific Convergence Sublayer (SSCS) Common Part Convergence Sublayer (CPCS) Segmentation Reassembly Sublayer (SAR) ALayer Physical Layer
AAdaptation Layer (AAL)
AAL5 Common Part
Figure Protocol Model Variable Rate Type 2.1.1 Type
structure CPCS-PDU Type shown Figure CPCS payload variable length field containing 65,535 bytes CPCS-user information. field used align CPCS-PDU 48-byte boundary. field octet-aligned range from bytes. CPCS-UU field contains byte user-user information take value. field reserved supporting future functions. length field indicates length bytes payload field.
T1S1.5/92-003R2 "Broadband ISDN-AAdaptation Layer Common Part Functionality Specification" 1992. T1S1.5/92-010 "Broadband ISDN-AAdaptation Layer Common Part Functionality Specification" 1992.
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CRC-32 field contains result CRC-32 calculation performed over entire CPCS-PDU specified ANSI standard. CPCS-PDU
CPCS Payload Bytes: 0-65535
0-47
CPCS-UU Length CRC-32
CPCS Trailer Figure Structure Type CPCS-PDU1 segmentation process AAL5 illustrated Figure
CPCS-User_PDU
Common part convergence sublayer
CPCS Payload
Trailer
CPCS-PDU
Segmentation Reassembly Sublayer
Payload
Payload
Payload
SAR_PDU
ALayer
Cell Payload
Cell Payload
Cell Payload
Acell header with user-to-user indication Acell header with user-to-user indication
Figure Segmentation Process Type
CPCS-PDU segmented into 48-byte segments, with each segment forming SAR_PDU. SAR_PDUs partially filled, since CPCS-PDU aligned byte boundary. There header trailer SAR_PDU. Each SAR_PDU forms 48-byte payload Acell. Each Acell five-byte cell header. ATM-user-to-user indication available payload type field Acell header. AAL5 uses Auser-to-user indication indicate last SAR_PDU CPCS-PDU. other SAR_PDUs carried Acells with Auser-to-user indication `0'.
T1S1.5/92-010 "Broadband ISDN-AAdaptation Layer Common Part Functionality Specification" 1992.
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2.1.2 SARA-2 AAL5 Service
transmit direction, CPCS-PDU AAL5 illustrated Figure with specific fields calculated inserted. SARA-2 supports: Calculation size insertion Insertion CPCS trailer provided host Service Interface request primitive "Send Segment End". Calculation insertion CRC-32 field. CPCS-PDU CPCS trailer Payload Bytes 65535 CPCS-UU Length CRC-32
Provided host inserted SARA-2
Calculated inserted SARA-2 Figure Construction CPCS-PDU AAL5 Transmit Direction reassembly direction, received CPCS-PDU AAL5 illustrated Figure SARA-2 delivers whole CPCS-PDU host supports: Reassembly full CPCS-PDU into host memory Notification CPCS-UU, Length fields host Service Interface primitive "RcvSDUcomplete" CRC-32 checking. CPCS-PDU CPCS trailer Payload Bytes 65535 CPCS-UU Length CRC-32
Provided host Service Interface Figure Disposition CPCS-PDU AAL5 Reassembly Direction
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ALAYER
format Acell user network interface (UNI) Anetwork, defined CCITT broadband ISDN1, shown Figure generic flow control (GFC) field used ensure fair efficient access between multiple devices sharing single UNI. label space bits provided, divided into fields: eight-bit virtual path identifier (VPI), 16-bit virtual channel identifier (VCI)2. allows group virtual connections, called virtual path, identified identifies individual virtual connections within each virtual path. payload type (PT) field used distinguish user information network information. user information cells, payload type field carries single Auser-to-user identification. cell loss priority (CLP) permits priorities cell defined that network discard priority cells under congestion conditions. header error check (HEC) field provides eight-bit cyclic redundancy check contents cell header.
ACell Header
Bits
Payload
bytes
Figure Structure ACell User Network Interface ASEGMENTATION SARA-Lite
segmentation packets performed SARA-Lite requires series steps, shown Figure order properly connection initiate segmentation packets, there must interaction between host processor SARA-Lite bus. service interface defines low-level control operation SARA-Lite messages that passed between host memory SARA-Lite hardware. Allocate Host Buffer Data Packet Link Host Buffer structure (See Figure Packet Segmentation (See Figure
Recycle Host Buffer (See Figure Figure Steps Segmentation AAL5 Packet
CCITT Recommendations I.150, I.361 (Geneva, June 1992). Note that CCITT since been re-named ITU-T. Within telecommunications industry, terms "virtual connection", "virtual channel", "virtual circuit" tend used synonyms. this document more general term "virtual circuit" been adopted.
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order segment packet into Acells several steps must fulfilled which shown Figure Several simplifications have been applied this flowchart. First assumed that structures SARA- Lite have been properly initialized appropriate parameters each programmed into Control Memory. Some these parameters include bandwidth allocation each VBR/CBR circuit, setup number VCs.
Host buffers
Request/ Indicate Rings
Segmentation Interface Traffic Shaping RISC
UTOPIA Interface
Output Cell Control FIFO Reassembly
SONET/ Framer Interface
Hashing
Serial EPROM Interface
Memory Controller
SARA-Lite
Host Memory
Cell Buffers
Buffer Descriptors
Segmentation structures
Rate Control Table
Control Memory
Figure Segmentation Flow SARA- Lite following numbered list describes individual arcs shown Figure Segmentation Flow. host writes packets (CPCS-PDU payloads) that segmented buffers host memory. CPCS-PDU scattered among several host buffers. host buffers filled with data, host software generates series service interface request messages (one host buffer). Each request message specifies buffer size host memory address. message also specifies type whether host buffer associated with last fragment CPCS-PDU. SARA-2 processes request messages adds resulting buffer descriptors linked list pointed segmentation structure. This linked list enables multiple host buffers same segmentation. When traffic scheduler services Rate Control Table (RCT), Segmentation structures retrieved. CURR_BUFF_DESCR Segmentation structure NULL, then data exists Otherwise, there host buffers active segmentation, CURR_BUFF_DESCR provides pointer linked list buffer descriptors. Each buffer descriptor provides address access data host memory. controller makes request bus. Once request granted, SARA-2 becomes master bus. controller also fetches free cell buffer from free cell buffer pool SARA-2 control memory. controller fills free cell buffer with data from memory, decrementing size incrementing address fields buffer descriptor. data belongs last cell PDU, controller writes specified number padding bytes into cell buffer then copies CPCS-PDU trailer.
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segmentation processing logic processes Specific Fields Segmentation structure flags from buffer descriptor generate SAR-PDU header trailer fields. SARA-2 writes back control memory partial CRC, data address data size fields, updates flags cell count. When output cell FIFO accept cell, output control logic retrieves cell from cell buffer prepare transmission. cell buffer released free cell buffer pool. UTOPIA mode, external interface ready accept cell, cell sent out. framer mode, cell mapped into payload SONET/SDH frame framer adds SONET/SDH overhead bytes. When CPCS-PDU completely segmented, SARA-2 sends service interface indicate message, with without interrupt, releasing buffers associated with CPCS-PDU re-use host. 2.3.1 Link Host Buffer Structure
linking packet corresponding structure starts when host writes message into Request Ring, shown Figure format message specified SARA-Lite Service Interface Technical Manual (document number TXC-05551-TM1) repeated Table reader's convenience. message written host 16-byte message containing information number link packet well other parameters such type connection (VBR, CBR, UBR) request send packet. detailed explanation message format, meaning, usage found same Technical Manual. Host
Write Request Ring (RR), host buffer Update Tail registers SARA-2
Format:
Mtype Mflags Word1 Word2 VCID
SARA-Lite
queue empty: Read from process Mtype Mflags; copy Free buffer (h/w) Update head register (h/w) Update head pointer Free Buffer queue
Word3
SARA-Lite
Load pointer (physical address buffer) with proper request code service queue (h/w) TypeCode(4) ReqCode(4) BDptr(24)
SARA-Lite
RISC processes TypeCode ReqCode: RISC links this buffer structure buffer contains information packet segmentation. structure Buffer Descriptor (BD) updated.
Figure Host Buffer Linking Structure SARA-Lite
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Mtype
Mflags Word Word Word
VCID
Table 16-Byte Structure Request Ring Messages After writing message into Request Ring, host updates Request Ring tail pointers. This action will prompt SARA-Lite read message Request Ring start process link packet into structure. these actions performed internally SARA-2 transparent user. Request Ring head tail registers part Communications Registers SARA-2 host will have write tail register order additional message queue which will serviced SARA-2 RISC. important notice that minimum number Service Interface messages that host needs write Request Ring transmit CPCS-PDU two. first message used "Send Segment" over interface SARA-Lite control memory, second used "Send Segment End" signal that more buffers need linked that particular that CPCS-PDU. 2.3.2 Packet Segmentation
segmentation packet will take place conditions fulfilled, namely that there data transferred particular that candidate transmission. first condition soon linkage packet finalized. second condition required order fulfill negotiated rate that which determined programming Rate Control Table. Also, important distinguish between different types traffic such CBR/VBR UBR. traffic managed means Rate Control Table mechanism. Rate Control Table traversed that candidates examined determine data that ready transferred. Rate Control Table linear array 32-bit long descriptors that have appropriately programmed allocate bandwidth each connections. Figure shows flowchart events required segmentation packet AAL5. rate control tables displayed: CBR/VBR VCs, (ii) VCs.
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traverse (CBR/VBR)
Traversal Unit sequentially scans through RCT; Traversal Unit looks segmentation candidate Send CBR/VBR cells, cells idle cells DMAO obtains free cell buffer pointer from free cell buffer pointer queue structure
DMAO writes Aheader (read from structure) into cell buffer; copies bytes from host buffer cell buffer Calculates CRC-32; updates table table
CBR/VBR traffic
traverse
structure
DMAO forwards cell buffer pointer DMAO-LinkO queue Link controller outgoing channel reads data from cell buffers; forms 52-byte Acell into cell FIFO Link controller writes cell buffer pointer free cell buffer pointer queue
traffic
Figure Packet Segmentation SARA-Lite CBR/VBR circuits, once data available that particular candidate send cells, SARA-Lite will transfer cells from host memory into Control memory. cells will forwarded from Control memory either UTOPIA SONET/SDH Framer cell interface transmission onto physical link. absence CBR/VBR candidates, absence CBR/VBR data transfer, SARA-Lite will look candidates transfer data.
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2.3.3 Host Buffer Recycling
After segmentation, necessary recycle some data structures used process. Some structures automatically recycled SARA-Lite transparently user. However, host needs recycle buffers allocated host memory packet. host start recovering these packet buffers soon SARA-Lite notifies host that information buffers been transferred SARA-Lite Control memory. Figure describes processing Buffer Descriptor SARA-2. "NOTIFY" Descriptor Mode `1', RISC will forward message contained host indicate rings.
last cell
Continue Segmentation
RISC processes Buffer Descriptor after packet segmented.
Notify=1?
RISC releases back Pool. Update head pointer pool.
RISC links indicate pool. Update tail pointer Indicate pool.
DMAI copies Indicate Indicate Ring. DMAI updates head pointer indicate pool. DMAI releases pool updating head pointer pool.
Figure SARA-2 Segmentation Processing Buffer Descriptor
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summary host buffer recycling shown Figure path begins host allocating buffers memory notifying SARA-Lite existence packet waiting segmentation. Internally SARA-Lite will allocate Buffer Descriptor each memory segments required packet awaiting segmentation. Host SARA-Lite Pool Request Ring RISC Indicate Ring Indicate Logic Indicate Pool Figure Host Buffer Recycling SARA-Lite Once packets transferred Control memory, entry internal service queue added. With every Buffer Descriptor being used, SARA-Lite will recycle buffer re-utilization. last Buffer Descriptor packet, SARA-Lite notifies host indicating logic placing message Indicate Ring. message written Indicate Ring similar shown Table REASSEMBLY AAL5 PACKETS Buffer Descriptor
Cells received either UTOPIA SONET/SDH frames. either case, cells received forwarded link queue block which turn will managing transfer cell buffers control memory finally packet memory host memory.
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reassembly steps shown Figure flow detailed Figure Three main blocks represented Figure SARA-Lite with internal structures, (ii) Control Memory used SARA-Lite store data structures, (iii) Host Memory both packet memory service interface messages.
Receive Cell Cell Control Block
Perform Hashing incoming VP/VC Connection Supported
Search Connection find pointer Reassembly Structure
Cell Discarded
Notify Host Write Cell Free Cell Buffer
Transfer Cell Host Memory Packets Figure Steps Reassembly AAL5 Packet
Host buffers
Segmentation Traffic Shaping RISC UTOPIA Interface
Output Cell Control FIFO Reassembly
Request/ Indicate Rings
Interface
SONET/ Framer Interface
Hashing Serial EPROM Interface
Memory Controller
SARA-Lite
Host Memory
Cell Buffers Buffer Descriptors
Reassembly structures
Hash Table
Reassembly Buffer Descriptor Pool
Control Memory
Figure Reassembly Flow SARA-Lite
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cell coming from either SONET/SDH framer UTOPIA interface processed reassembled into host memory. Before actual reassembly occurs, several intermediate steps must fulfilled. flow chart detailing these steps shown Figure Aheader cell that arrives SONET/SDH framer UTOPIA interface used perform hashing algorithm determine valid connection not. pointer obtained from hashing search appropriate connection performed. cell corresponds valid connection transferred cell buffer Control memory where will wait final transfer appropriate host memory buffer. After cell been transferred, some intervening data structures need recycled. AAL5 CPCS-PDU Reassembly following numbered list describes individual arcs shown Figure internal framer mode used, SARA-2 delineates cells after framing transmission format. UTOPIA mode used, SARA-2 receives complete 53-byte Acells. hash control logic processes Acell header received cell provide hash table index. hash table entry provides pointer Reassembly structure corresponding Acell. SARA-2 fetches free cell buffer writes cell control memory. This allows adequate system throughput even under delayed access (due usage other devices). Reassembly structure fields read determine type obtain reassembly flags. fields incoming cell also processed. AAL-specific functions performed reassembly structure fields updated. controller gets buffer descriptor pointer. reassembly host buffers allocated structure points available buffer descriptor, that used. Otherwise, SARA-2 fetches buffer descriptor from reassembly buffer pool. this first cell CPCS-PDU, SARA-2 reads partial information from Reassembly structure well. interface makes request bus. When request granted, controller transfers 48-byte AAL5 payload from cell buffer host buffer, computing AAL5 data transferred. host buffer filled, current descriptor appended linked list descriptors already used this CPCS-PDU. SARA-2 fetches descriptor from reassembly buffer pool continues with transfer. partial then written Reassembly structure. cell buffer then released free cell buffer pool. When cell been transferred, size host buffer address buffer descriptor updated. When last cell CPCS-PDU transferred, AAL5 length fields verified errors, any, flagged. When reassembly CPCS-PDU complete, SARA-2 sends indicate message each used buffer, with without interrupt, releasing buffer(s) associated with CPCSPDU. used buffer descriptors copied indicate ring host processing. buffer descriptors released reuse.
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2.4.1 Host Buffering Recycling Reassembly Process
Host buffers must available SARA-Lite order reassemble received cells into packets. request host free buffers made Service Interface. Figure shows processing Buffer Descriptor SARA-2 after host buffer filled.
RISC processes Buffer Descriptor after host buffer filled.
SARA-2 moves filled Indicate pool. Update Indicate tail pointer.
DMAI copies contents Indicate Descriptor Indicate Ring (IR). Update Indicate pool head pointer. Update tail register. Release Indicate descriptor pool; update head register pool.
Host processes message Update head register.
Host assigns message buffer Reassembly buffer pool from pool. Update head Reassembly buffer pool. Update head pool.
Figure SARA-2 Reassembly Processing Buffer Descriptor
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host provides free buffers SARA-Lite buffer pool, which used send cells into host memory. After cells reassembled host memory, SARA-Lite notifies host (via indicate ring) that those buffers needed reassembly data manipulated form required. Figure shows summary host buffer recycling process.
Reassembly Buffer Pool
Buffer Descriptor
Request Ring
Pool
RISC
Indicate Pool Indicate Ring Figure Host Buffer Recycling SARA-Lite
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SARA-LiteTXC-05551/L SARA-Lite TRAFFIC SCHEDULING HASH MECHANISMS
TRAFFIC SCHEDULING SARA-2 incorporates traffic scheduler which schedules transmission CBR, cell streams per-virtual-circuit basis. SARA-Lite uses table-based scheduler provide precise control over granularity rates requested CBR/VBR virtual circuit. table-based approach provides adequate flexibility multiplexing different virtual circuits while achieving desired burst size sustainable cell rate allocated each virtual circuit. traffic shaping hardware device traverses Rate Control Table schedule cell transmissions. Rate Control Table linear array 32-bit entries, illustrated Figure Each entry points either segmentation structure entry NULL entry. During segmentation, Rate Control Table traversed sequentially each entry provided service according control bits. Each entry table corresponds virtual circuit. When entry Rate Control Table serviced, more Acells (based burst size Segmentation structure) sent from that virtual circuit. single virtual circuit occupy from zero table's slots. When more than entry Rate Control Table point same Segmentation structure entry, multiple bursts cells sent that virtual circuit single traversal Rate Control Table. hardware cycles through Rate Control Table entries endlessly, slot more cell times, transmitting more cells virtual circuit named slot. 3-bit control field entry determines action taken, which following: send more) cells from particular virtual circuit (identified bits 0-23 entry) jump another location transmit null cell. Pointer Segmentation structure Entry Pointer Segmentation structure Entry NULL Pointer Segmentation structure Entry Jump Beginning Table
Command
Reserved
Figure SARA-Lite Rate Control Table Circular Linked List CBR/VBR Virtual Circuits SARA-Lite maintains separate doubly-linked list active virtual circuits shown Figure traffic scheduler traverses Rate Control Table circular list order select candidate virtual circuits segmentation. Rate Control Table used schedule traffic, while circular list used schedule traffic. Note that circular list simple linked list active that have cells transmit.
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Linked List
Figure Circular Linked List Virtual Circuits During segmentation, traversed sequentially. each cell slot time accessed operation identified entry (that scheduler pointing that time) performed. next cell slot time contents next entry investigated. Note that jump operations require cell slot time complete, considered take place instantly. Since traversed cyclic fashion, granularity each virtual circuit equal total line rate (say Mbit/s) divided total number cells (including burst size) allocated entries table (NCELLTOT). Note that number entries programmable have maximum 64,000 (thereby yielding granularity approximately kbit/s, less present). same token, amount bandwidth allocated specific equal total line rate divided NCELLTOT, then multiplied number entries associated burst sizes that have been assigned that Hence, case connections, number entries size shaped according traffic parameter. "gap" between entries allocated certain with made equal more complex case. Here PCR, should taken into consideration. entries allocated according MBS, they spaced equal i.e. then entries filled RCT, between entries (where 1/T). Also bursts have separated leaving where 1/Ts. Note also, that case bursty traffic, there exists field specified Segmentation structure called "Burst Size" that allows certain number cells transmitted back back. This avoids allocating separate entries reproduce bursts, thereby simplifying set-up. virtual circuit serviced when virtual circuit pointed Rate Control Table does have cells send. virtual circuit also served NULL entry encountered Rate Control Table. hardware traffic scheduler continuously scans linked list virtual circuits identify virtual circuit that data ready segmentation.
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HASH MECHANISM hashing algorithm used locate state information required reassembly received cells. does this indexing entries Reassembly Hash Table control memory. Such entries contain pointers chains Reassembly structure entries. Figure shows Reassembly Hash Table.
Pointer first Reassembly Structure Entry Hash Bucket Chain Pointer first Reassembly Structure Entry Hash Bucket Chain Pointer first Reassembly Structure Entry Hash Bucket Chain Pointer first Reassembly Structure Entry Hash Bucket Chain (n-1) Pointer first Reassembly Structure Entry Hash Bucket Chain Figure Reassembly Hash Table Consider easier case, whereby every entry Hash Control Table points single Reassembly structure entry. Reassembly structure contains information relevant particular such information needed whenever cell received, order perform appropriate functions, place cell appropriate host memory location, etc. soon Acell received header isolated passed through Hash Computation Logic. Here fields examined order determine index Hash Control Table which contains pointer structure associated with that cell. However, several Reassembly structures "grouped" linked (hash bucket) chain, that they accessed single entry Hash Control Table. This mechanism enables memory space search time trade-off. hashing computation logic customized implement this feature, modification HLMASK1 HLMASK2 fields. index generated hashing logic used read Hash Control Table entry, which points chain Reassembly structure entries. This chain traversed until match found between VP/VC field received Acell that contained Reassembly structure entry. Figure describes Hash Index computation logic.
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VPI(7:0)
HLCSR VCI(15:0) shift
HLMASK2
VCI(15:0)
HLMASK1
Exclusive-OR gates HLIMASK Hash Index
Note:
indicates two-input gates operating corresponding bits registers gates immediately above below with 16-bit result passed downwards.
Figure Hash Index Computation Logic
TXC-05551-SCDA-PS1 January 1998
SARA-LiteTXC-05551/L AAL0 CELLS SUPPORT
SARA-2 supports both 48-byte 64-byte mode AAL0 traffic. transmitting side: traffic AAL0, segmentation structure set, then entire cell buffer copied from host buffer space. "0", 48-byte cell payload copied from external host buffer. cell buffer format shown Figure
Reserved bits) Unused bits) Unused bits) Aheader bits) Payload bytes Payload bytes Payload bytes 45-47
Figure Cell Buffer Format
receiving side: complete 64-byte cell buffer transferred host memory buffer reassembly structure set. Otherwise, 48-byte cell payload transferred host buffer.
TXC-05551-SCDA-PS1 January 1998
SARA-LiteTXC-05551/L FRAME RELAY SERVICE/AINTERWORKING
Frame Relay Service (FRS) widespread technology virtual networking. However, most backbone network migrating towards ATM-based transport structure operating Mbit/s higher over SONET/SDH systems. cell-based technology with fixed length 53-bytes cell which permits optimized switch architecture. This optimization allows switching cells much higher speed than variable length packet switching schemes. Also, Aprovides possibility mixing different types traffic such voice, data, video into single network. However, presently installed base Frame Relay networks, possible take advantage that infrastructure providing interworking solutions between Frame Relay networks Anetworks. Network Network
FR-CPE
FR-CPE
B-ISDN
Frame Relay Network
FR-CPE
ANetwork
ANetwork
Frame Relay Network
FR-CPE
B-CPE
B-ISDN
B-ISDN
B-CPE
Figure Frame Relay/AInterworking Configurations Frame Relay Forum FRF.5 specifies interworking scenario between ATM. Figure depicts generic diagram various scenarios connecting networks B-ISDN/CPE B-ISDN networks. ITU-Recommendation I.555 specifies distinct scenarios: Connection networks/CPE using B-ISDN Connection network/CPE with B-ISDN/CPE using B-ISDN. these scenarios, interworking function (IWF) between Frame Relay Aclouds will device segment reassemble frames to/from cells.
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NETWORK INTERWORKING FUNCTIONS
Frame Relay Service connection-oriented data transport service that provides bidirectional transfer variable length packets interconnection terminal-host applications. Frame Relay Service requires initial establishment end-to-end connections, either through provisioning call setup procedures. interworking function (IWF) required when packets need traverse Anetwork. Please refer AForum B-ICI document different network interworking scenarios functionality IWF. This section discusses functional mapping between functions Afunctions.
A
user
FR-SSCS upper layers Q.922 core Q.922 core CPCS APHY APHY FR-SSCS CPCS APHY Q.922 core
user
upper layers Q.922 core
Figure Mapping between networks Using ANetwork shown Figure part function service specific convergence layer into Acells. features supported are: Variable length formatting delimiting Error detection Connection multiplexing Loss priority indication Congestion indication (forward backward) status management
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5.1.1 Frame Formatting Delimiting
FR/AIWF shall FR-SSCS structure specified I.365.1. Several structure formats supported with octet header format being mandatory. octet header structure depicted Figure Three four octet header format supported optionally.
Upper DLCI Lower DLCI FECN BECN
Information
Figure FR-SSCS Format FR-SSCS must first mapped into AAL5-CPCS PDUs which then segmented into Acells using function. Figure shows mapping FR-SSCS PDU. FR-SSCS
CPCS-SDU
CPCS-UU
Length
Figure Frame Relay CPCS-PDU Mapping mapping FR-SSCS-PDU into CPCS-SDU straightforward sense that single CPCSSDU required single FR-SSCS-PDU. layer structure required FR/AIWF detailed Figure FR-SSCS Q.922 core CPCS APHY
Figure FR/AIWF Internal Architecture
However, main issue mapping individual fields FR-SSCS Acell header fields.
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5.1.2 Error Detection
error detection capabilities provided Type CPCS CRC-32. 5.1.3 Connection Multiplexing
mapping Data Link Connection Identifier (DLCI) Aconnection identifier dependent method multiplexing used Aconversion. multiple logical connections multiplexed into single Avirtual channel connection, multiplexing accomplished FR-SSCS sublayer using DLCIs. one-to-one mapping used, each frame relay connection mapped single Avirtual channel connection. Multiplexing performed Alayer using VPI/VCIs. mandatory that supports one-to-one multiplexing which single logical connection mapped single AVCC. 5.1.4 Discard Eligibility (DE) mapping
network provider select between modes operation loss priority mapping Adirection. Mode from Q.922 core FR-SSCS from Q.922 core Mode FR-SSCS fixed connection setup fixed connection setup
Table DE/CLP Mapping ADirection SARA-Lite supports both modes shown Table SARA-Lite allows bits cells based descriptor mode bits. This enables cells from each frame have different values. Mode easily supported, with host software setting CLP_EN Buffer Descriptor packets FR-SSCS frames. Mode very much simplified programming CLP_EN value connection does have modified every frame. network provider select between modes operation loss priority mapping direction, shown Table Mode more cells packet from FR-SSCS Q.922 core Mode from FR-SSCS Q.922 core
Table CLP/DE Mapping Direction
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Mode SARA-Lite microcode keeps sticky cells received packet. more cells packet, message created when packet reassembled indicating status sticky bit. This enables host software Q.922 core frame appropriately. Mode much simpler SARA-Lite does have anything this case. host software looks FR-SSCS sets Q.922 core. 5.1.5 Congestion Indication (Forward): FECN EFCI
Aprotocol uses 3-bit field (numbered Explicit Forward Congestion Indication (EFCI). Forward congestion indication supported frame level with Forward Explicit Congestion Notification (FECN). Frame Relay Aforward direction, EFCI field Acells always shown Table FECN from Q.922 core FECN FR-SSCS Table FECN EFCI Mapping ADirection This mapping straightforward. host software would Buffer Descriptor every buffer associated with connection Frame Relay forward direction, EFCI field last Acell segmented frame received then shall FECN Q.922 core frame, shown Table EFCI (PT(1)) last cell packet FECN FR-SSCS Table FECN EFCI Mapping Direction this direction SARA-Lite provides PT(1) last cell packet. This will used host software addition FECN SSCS-PDU FECN field Q.922 core. 5.1.6 Congestion Indication (Backward) FECN Q.922 core EFCI (PT(1))
Backward congestion indication supported only frame level Backward Congestion Notification (BECN) field. SARA-Lite does need involved this function. STATUS MANAGEMENT
management FR-SSCS layer Alayer operate independently. status from Alayer shall used FR-SSCS layer when determining status PVCs.
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OPERATIONS MAINTENANCE
Errors that occur: Invalid CPI. Must equal Length violation. CPCS-PDU length differs from Length field CSCP-PDU trailer. Oversized received data unit. violation required count occurrences previously listed errors also required count occurrences buffer overflowing.
EMULATION (LANE) SERVICE
Another promising area connectivity legacy LANs ATM. now-common ethernet switching, switches interconnected through support large number ethernet ports. AForum specifies Emulation over Adocument implementation agreement Emulation Service. order interconnect legacy LANs over Anetworks, several characteristic networks must emulated: Connectionless Services: legacy LANs establish connection prior sending data. This basic departure from connection-oriented scheme Anetworks. Therefore, transparency must provided emulated environment. Multicast Services: legacy LANs support broadcast/multicast communications. There possibilities provide this capability using ATM-based networks: intercept multicast/broadcast messages forward message appropriate station(s), (ii) send message stations stations perform filtering. Driver Interface AStations Emulated LANs: this requirement comes from need connecting independent LANs into single network. Therefore, Anetwork acts super-LAN which several segments attached. Interconnection with Existing LANs: provides connectivity from Astations stations stations stations across Abackbones. According AForum LANE document, emulation used different configurations: Intermediate Systems (routers, bridges) which enable communications legacy LANs over Abackbones, (ii) Stations (hosts PCs) which enable communications between Astations stations. order provide these emulation capabilities, high performance with emulation features required. EMULATION FRAME FORMATS
Emulation Client (LEC) conforming LANE must frame formats: Based 8802.3/CSMA-CD (IEEE 802.3) format Based 8802.5 (IEEE 802.5, Token Ring) format
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6.1.1 Ethernet (IEEE 802.3) Frame Format
Emulation Client frame format Ethernet frames given Figure
Byte/Bit
HEADER Destination Address Source Address Source Address Information Information
Destination Address
Type/Length
Figure Data Frame Format Ethernet Header: Contains value 0000H. Valid range Header from 0000H FEFFH. frame received with Header outside this range (except value FF00H),or equal LECID, must discarded LEC. 6.1.2 Token Ring (IEEE 802.5) Frame Format
Emulation Client frame format Token Ring frames given Figure
Byte/Bit 10H-2EH
Destination Address
HEADER Destination Address
Source Address Source Address
Routing Information Field Information Figure Data Frame Format Token Ring
SARA-Lite Filtering
SARA-Lite will validate LECID received data frame. LECID equal LECID that host configured card LECID equal FF00H range 0000H-FEFFH, then SARA-Lite will discard data frame.
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SARA-LiteTXC-05551/L RELATED DOCUMENTS
TRANSWITCH DOCUMENTS THAT COMPLETE DESCRIPTION SARA-Lite
TranSwitch Data Sheet SARA-2 ACell Processing Device, document number TXC-05551-MB TranSwitch Technical Manual SARA-Lite Service Interface, document number TXC-05551-TM1 OTHER DOCUMENTS
Traffic Management Specification, Version 4.0, AForum, af-tm-0056.000, April 1996 Source Behavior AUBR Traffic Management: Explanation, Jain al., IEEE Communications Magazine, November 1996, 50-55 References Frame Relay: B-ICI specification version ITU-T Rec. I.555, I.365.1 AForum af-lane-0021.00, LANE 1.0, 8802.3, 8802.5 T1S1.5/92-003R2 "Broadband ISDN-AAdaptation Layer Common Part Functionality Specification" 1992. T1S1.5/92-010 "Broadband ISDN-AAdaptation Layer Common Part Functionality Specification" 1992.
TranSwitch reserves right make changes product(s) circuit(s) described herein without notice. liability assumed result their application. TranSwitch assumes liability TranSwitch applications assistance, customer product design, software performance, infringement patents services described herein. does TranSwitch warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right TranSwitch covering relating combination, machine, process which such semiconductor products services might used.
TXC-05551-SCDA-PS1 January 1998
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TranSwitch Corporation
Enterprise Drive
Shelton, 06484
Tel: 203-929-8810
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SARA-LiteSAR Type with Traffic, Frame Relay LANE Support INTRODUCTION

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