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Static MARKETING PART CY7C150 DEVICE DESCRIPTION
PRODUCT DESCRIPTION (for qualification)
Information provided this document intended generic qualification technically describes Cypress part supplied: Marketing Part Device Description: Cypress Division: Size (stepping) CY7C150 Static RAM, Separate I/O, Memory Reset Cypress Semiconductor Coporation 7C150A 10/1990 mils mils What markings Die:
Overall Mask) Level (pre-requisite qualification): Cypress Qualification completion/Marketing Availability Dates (Current REV):
TECHNOLOGY/FAB PROCESS DESCRIPTION
Number Metal Layers: Passivation Type Materials: Free Phosphorus contents glass layer(%): Coating(s), used: Gate Oxide Material/Thickness (MOS): Name/Location (prime) Facility: Line ID/Wafer Process CMOS, Double Poly, Single Metal 0.8µm SiO2 195A Cypress Semiconductor, Round Rock, Generic Process Technology/Design Rule (µ-drawn): Metal Composition: None 1%SiAl, 4,000A 15,000A Oxynitride
PLASTIC PACKAGE/ASSEMBLY DESCRIPTION
Package Outline, Type, Name: Package edge clearance: Mold Compound Name/Manufacturer: Lead Frame material: Lead Finish, composition: Attach Area Plating: Attach Method: Wire Bond Method: Assembly Line Process Name/Location Assembly (prime) facility: Paste Thermocompression Copper Solder Dipped, 63%Sn, 37%Pb Silver Attach Dim: Attach Material: Wire Material/Size: Cypress Semiconductor mils mils Silver Epoxy Gold 24-lead, 300-mil Plastic mils side Sumitomo EME-6300H(R)
Cypress Semiconductor, Jose,
CYPRESS SEMICONDUCTOR PAGE
PLASTIC PACKAGE/ASSEMBLY DESCRIPTION
Package Outline, Type, Name: Package edge clearance: Mold Compound Name/Manufacturer: Lead Frame material: Lead Finish, composition: Attach Area Plating: Attach Method: Wire Bond Method: Assembly Line Process Name/Location Assembly (prime) facility: Paste Thermocompression Copper Solder Plate 80%Sn, 20%Pb Silver Attach Dim: Attach Material: Wire Material/Size: Cypress Semiconductor mils mils Silver Epoxy Gold 24-lead, 300-mil Plastic SOIC mils side Sumitomo EME-6300H(R)
Cypress Semiconductor, Jose,
HERMETIC PACKAGE/ASSEMBLY DESCRIPTION
Package Outline, Type, Name: Package edge clearance: Mold Compound Name/Manufacturer: Lead Frame material: Lead Finish, composition: Attach Area Plating: Attach Method: Wire Bond Method: Name/Location Assembly (prime) facility: Assembly Line Process Paste Ultrasonic Alloy Solder Dipped, 63%Sn, 37%Pb Silver Attach Dim: Attach Material: Wire Material/Size: Cypress Semiconductor mils mils Silver Glass Aluminum 1.25 24-lead, 300-mil CerDIP mils side
Cypress Semiconductor, Jose,
HERMETIC PACKAGE/ASSEMBLY DESCRIPTION
Package Outline, Type, Name: Package edge clearance: Mold Compound Name/Manufacturer: Lead Frame material: Lead Finish, composition: Attach Area Plating: Attach Method: Wire Bond Method: Name/Location Assembly (prime) facility: Assembly Line Process Paste Ultrasonic None Solder Dipped, 63%Sn, 37%Pb None Attach Dim: Attach Material: Wire Material/Size: Cypress Semiconductor mils mils Silver Glass Aluminum 1.25 24-pin, rectangular LCC, gold mils side
Cypress Semiconductor, Jose,
CYPRESS SEMICONDUCTOR PAGE
OTHER INFORMATION
approval similarity, identify other devices using same basic with bonding metal mask options test selections explain: None Cypress planning changes near future, identify change (Qtr/Yr) Design Rev./Shrink/Date: Fab/Assembly site change/Date: Other Packages qualified this device: Voltage Rating (per STD-008, Method 3018): Flammability Classification (UL-94V): Alternate Fab/Assembly Locations: UL-94V0 Cypress Semiconductor Corp., Jose, (Fab Assembly Omedata, Indonesia Other Devices qualified this technology: None 1992 Process Change/Date: Cross Licensee/Licensor/Date: CY7C123 CerDIP, LCC, SOIC, >2,000V None None
Please attach following Qualification Reliability data revision Package type, assembly sites identified above (mark included): (130°C/85%RH) Temperature Cycles (-65°C 150°C) Data Retention Bake, Plastic (185°C) Data Retention Bake, Hermetic (250°C) Autoclave (PCT, 121°C, 100%RH, 15psig) Tests (MIL-STD 883, method 3015) Operating Life (temp): Latchup Testing Other: Other: Other: Other: 150°C
CYPRESS SEMICONDUCTOR PAGE
PRODUCT INFORMATION QUALIFICATION SIMILARITY
Product Family: Division: Static Cypress Semiconductor Size/ Type Revision Size (stepping) Design Rule Fabrication Passivation Mold Assembly Volt Type Compound Line Rating Location Availability (mm/yy)
Supplier's Part Number Rated Speed
Process Line CY7C150(commercial) xxPC xxDC xxLC xxSC CY7C150(military) xxLMB 12ns 35ns 10ns 35ns 24.3 PDIP 24.3 CDIP 24.3 SOIC 7C150A 0.8µ CMOS Oxynitride Sumitomo Jose, >2000
W4.3 CDIP 7C150A
0.8µ
CMOS
Oxynitride
Sumitomo
Jose,
>2000
NOTE: "xx" replaces speed options which are: 10ns, 12ns, 15ns, 25ns, 35ns. Military devices range from 12ns 35ns only. Jose California, Qualified Process Device 1986, number 86171 DIP/LCC packages qualified 1984. packages qualified 1987/1989, QTPs 87041, 89048, 89343
CYPRESS SEMICONDUCTOR PAGE
DEVICE RELIABILITY SUMMARY
Marketing Part Description: CY7C150 24-pin, 300-mil Plastic Wafer Fab: Assembly: Round Rock, Jose, Cypress
High Temperature Dynamic Operating Life (HTOL, 5.75V, 150°C) Early Failure Rate Device 7C150 Lot# 2018616 Hours 0/2000 Cumulative 0/2000
High Temperature Dynamic Operating Life (HTOL, 5.75V, 150°C) Latent Failure Rate Device 7C150 Lot# 2018616 Hours 1/341 Hours 0/340 Failure Cumulative 1/341
Temperature Cycle (-65°C 150°C, Condition Device 7C150 Lot# 2018616 Cycles 0/76 Cycles 0/75 Cumulative 0/76
Autoclave (Unbiased, 121°C, 100% 15psig) Device 7C150 Lot# 2018616 Hours 0/75 Hours 0/75 Cumulative 0/75
High Accelerated Saturation Test (HAST, Unbiased, 130°C, 85%RH) Device 7C150 Lot# 2018616 Hours 0/76 Cumulative 0/76
CYPRESS SEMICONDUCTOR PAGE
Device Reliability Summary
Static CY7C150 Electrostatic Discharge Human Body Model Circuit 883, Method 3015 >+2,000V Unit >-2,000V >+2,000V Unit >-2,000V >+2,000V Unit >-2,000V (Highest passing voltage, +10% Guard-banded)
Latchup Testing Cypress Internal Latch-up Procedure Tests: Current Injection 200mA Trigger Socket Oscillation 7.5V 1MHz Temp 150°C
CYPRESS SEMICONDUCTOR PAGE
CYPRESS PREVIOUS QUALIFICATION
Device Status: 7C150A Production Prod. Family: Results: Static Passed Mask Complete Date: 7C150A 1986
Process
Technology:
CMOS
Process Loc:
Jose,
Package:
PDIP, SOIC (Plastic) CDIP, (Ceramic) Silver Epoxy (Plastic) Silver Glass (Ceramic)
Mold Compound:
Sumitomo (Plastic Only)
Lead Frame:
PDIP/SO: Copper CDIP: Alloy Jose,
Attach Mat:
Package Loc:
Jose, PDIP: Omedata, Indonesia
Test Loc:
Cypress Test
Stress/Test
Reference Method Temp/Bias
Actual Conditions Hrs/Cyc 1000 1000 1000 SS/Fail 5013/1 1660/0 205/0 80/0 110/0 448/5 320/0 256/0 310/0
Status
Qualification Data Reference
Test Result Pass Fail
HTOL HTOL HTOL Steady State Life High Temp Storage Group
150°/5.75V 150°/5.75V 150°/5.75V 150°/5.75V 150°/None 150°/6.5V
121°/100%RH
86171 86171 86171 86171 86171 86171 86171 86171 86171 86171
HTSSL Static Life Steam Test/Autoclave/PCT Temp/Humidity Bias (5.5V)
85°/85%RH Cond.
Temperature Cycle Accelerated Soft Error Rate Mechanical Sequence X-Ray ESD-HBM Latch-up
Flammability Oxygen Index
Corner Pins 200mA
Internal Pins
-5/0 86171
Moisture Resistance Internal Water Vapor Solvent Resistance Internal Visual Physical Dimensions Solderability Lead Integrity Bond Strength Shear Strength Torque
Interim, Complete

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