Versus Core Programming Model Differences July 1999 Microcontroll

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Versus Core Programming Model Differences July 1999 Microcontroll

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PowerPC Application Note
Versus Core Programming Model Differences
July 1999 Microcontroller Applications Microelectronics Research Triangle Park, ppcsupp@us.ibm.com Version:
This document will help programmers understand what code changes necessary when porting code between PowerPC* core-based products PowerPC core-based products. PowerPC 403GA, 403GB, 403GC, 403GCX Embedded Controllers standard products which include PowerPC core. PowerPC embedded microprocessor core available Blue Logic* Core Library will basis family standard products custom devices. first device feature core PowerPC 405GP Embedded Processor. Timebase Differences 403, timebase consists following four registers. These registers accessed using mtspr mfspr instructions. Mnemonic TBHI TBHU TBLO TBLU Register Name Time Base High Time Base High User Mode Time Base Time Base User-mode SPRN 0x3DC 0x3CC 0x3DD 0x1BE Access Read/Write Read Only Read/Write Read Only Mode Privileged User Privileged User
core changed timebase same PowerPC 6xx/7xx family. These registers also mtspr instruction writing, mftb instruction reading. timebase registers are: Mnemonic Alignment Support core hardware support misaligned half-word (16-bit) word (32-bit) sized loads stores. These misaligned accesses cause alignment exception 403. Register Name Time Base Time Base High SPRN 0x10C 0x11C 0x10D 0x11D Access Read Only Write Only Read Only Write Only Mode User Privileged User Privileged
Little-Endian Support support "PowerPC Little-Endian Mode" which controlled settings MSR[ILE] (bit MSR[LE] (bit bits. This legacy support previous 6xx/7xx systems, true storage Little-Endian support really desired programmers. Therefore, storage little endian support that specified given memory region either using SLER register (when addressing memory real-mode) through entry's field when address translation enabled (virtual-mode). legacy PowerPC Little-Endian mode been dropped 405. MSR[15] MSR[31] reserved fields. Debug Support Changes Instruction Address Compare registers (IACs), Data Address Compare registers (DACs), First Events Counter, level debug event sequencing. removed First Events Counter debug event sequencing. Instead additional IACs total four, well Data Value Compare registers (DVCs). There range compare capability using IACs DACs such that different ranges, range enabled simultaneously. support these changes DBCR DBSR registers have changed significantly IAC3, IAC4, DVC1, DVC2 registers have been added. DBCR (SPR 0x3F2) been removed. Instead control registers DBCR0 (SPR 0x3F2) DBCR1 (SPR 0x3BD) addition, added debug-wait mode that allows core enter JTAG-stopped state which retains ability respond interrupts. response will take core JTAG-stopped state until interrupt handler code completed execution. This mode controlled value MSR[DWE] (bit 21). used optional debug when using JTAG connected debugger such IBM's RISCWatch. MSR[21] reserved 403. Auxiliary Port Unit (APU) Interface added interface system-on-a-chip designers opcodes instruction stream. This feature does exist 403. controlled using MSR[AP] (bit MSR[APE] (bit bits. These bits reserved 403. Floating Point Unit (FPU) Support supports addition floating-point unit attachment interface core. support enabled MSR[FP] (bit MSR[FE0] (bit 405. These bits reserved 403. Multiply-Accumulate (MAC) Unit multiply-accumulate unit. This unit exists within core supports fast execution multiply multiply-accumulate instructions. example, unit execute 16bit multiply followed 32-bit addition with cycle latency. There multiply-accumulate operations three multiply operations total twenty-four related instruction types. instruction opcodes part space. unit based using registers source destination locations. instructions are:
macchw, macchwu, macchws, macchwsu, machhw, machhws, machhws, machhwsu, maclhw, maclhwu, maclhws, maclhwsu, mulchu, mulchwu, mulhhw, mulhhwu, mullhw, mullhwu, nmacchw, nmacchws, nmacchhw, nmachhws, nmaclhw, nmaclhws. does have unit instruction space generates program exception. Protection Bound Registers Protection Bound Registers that were used implement basic memory protection scheme when real-mode addressing have been removed from architecture favor more granular protection provided MMU. These registers PBL1 (SPR 0x3FC), PBL2 (SPR 0x3FE), PBU1 (SPR 0x3FD), PBU2 (SPR 0x3FF). These registers exist 405. Data Cache Write-Through Mode 403GC, 403GCX, have data cache write-through register DCWR. 403, programming cache write-through mode would cause alignment exceptions because caches support write-through mode, only supported write-back cache policy. supports both writeback write-through mode will cause alignment exception when using write-through mode. Instead will update both cache main memory stores when write-through mode. Cache Control Register cache debug control register assist cache read instructions CDBCR (SPR 0x3D7). This information been moved Core Configuration Register CCR0 (SPR 0x3B3). 405's CCR0 register contains more information than CDBCR including load store allocation instruction cache prefetching control. Exception Syndrome Register Changes Exception Syndrome Register, (SPR 0x3D4), changes that reflect difference between 405. 403's ESR[IMCN, IMCB, IMCT] (bits 1:3) reserved 405. ESR[0], which used bank protection machine checks 403, used instruction machine-check 405. addition, definitions bits ESR[14:16] handle exceptions from FPU, APU, field, respectively. Processor Version Register base value 0x00200000. 0x40110000. General Special Purpose Registers defines four SPGR registers, SPGR0 SPGR3. These four registers accessed privileged mode only have read/write access. these four registers adds four more, with separate numbers read-only write-only access. Note access mode required different operations. four SPRG registers are:
Mnemonic SPRG4 SPRG5 SPRG6 SPRG7
Register Name Special Purpose Register General Special Purpose Register General Special Purpose Register General Special Purpose Register General
SPRN 0x104 0x114 0x105 0x115 0x106 0x116 0x107 0x117
Access Read Only Write Only Read Only Write Only Read Only Write Only Read Only Write Only
Mode User Privileged User Privileged User Privileged User Privileged
Note: None SPRG registers used processor. They scratch registers which used example, storage space operating system pointer variables (anchors) working registers things like miss handler. Storage Attribute Changes: User-defined Storage Region Storage Little Endian share following storage attributes controlling registers: Storage Attribute Write-through policy Caching Speculative loads/stores Real-mode access (MMU Off) DCWR DCCR/ICCR field (MMU
defines following additional storage attributes associated registers: Endianness User-Defined SLER SU0R
example usage user-defined storage attribute would define code regions utilizing CodePack compression technology. addition these storage attributes means that tblre tlbwe instruction changed support reading writing these attributes. code usable both 405, 405's fields should incorporates data-side shadow TLB. transparent programming model changes code required. However, timings hits misses will different between with being faster certain situations. Cache Instruction Changes instruction data cache line widths have changed. 403, both instruction data caches line lengths four words. changed instruction data cache lines eight words. This change will affect code which line-length dependent, such cache invalidate cache flush code. changed operation iccci instruction. 403, this instruction would invalidate congruency class instruction cache. 405, this instruction will invalidate entire instruction cache. This allows invalidation entire instruction cache single instruction cycle with
side effect that legacy code which executes iccci repeatedly invalidate entire cache) will function without change longer necessary. icbt instruction, which privileged 403, user-mode instruction 405. added cache instruction dcba, pre-load block memory into data cache. does contain this instruction. Note: dcba continued future cores; programmers encouraged dcbz instruction pre-allocate memory into data cache.
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Versus Core Programming Model Differences July 1999 Microcontroll

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