Internal External Voltage Reference Out-of-Range Detection Voltage Ref
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Single-Chip, DSP-Based High Performance Motor Controller ADMC401
Internal External Voltage Reference Out-of-Range Detection Voltage Reference Internal 2.0% Voltage Reference Three-Phase 16-Bit Generation Unit Programmable Switching Frequency, Dead Time Minimum Pulsewidth Edge Resolution 38.5 Updates Switching Period Hardware Polarity Control Individual Enable/Disable Each Output High Frequency Chopping Mode Dedicated Shutdown (PWMTRIP) Additional Shutdown Pins System High Output Sink Source Capability Incremental Encoder Interface Unit Quadrature Rates 17.3 Programmable Filtering Encoder Inputs Alternative Frequency Direction Mode Registration Inputs Latch Count Value Optional Hardware Reset Counter Single North Marker Mode Count Error Monitor Function Dedicated 16-Bit Loop Timer (Periodic Interrupts) Companion Encoder Event (1/T) Timer
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FEATURES MIPS Fixed-Point Core Single Cycle Instruction Execution (38.5 ADSP-21xx Family Code Compatible 16-Bit Arithmetic Logic Unit (ALU) Single Cycle 16-Bit 16-Bit Multiply Accumulate Into 40-Bit Accumulator (MAC) 32-Bit Shifter (Logical Arithmetic) Multifunction Instructions Single Cycle Context Switch Zero Overhead Looping Conditional Instruction Execution Independent Data Address Generators Memory Configuration 24-Bit Internal Program Memory 24-Bit Internal Program Memory 16-Bit Internal Data Memory 14-Bit Address 24-Bit Data External Memory Expansion High Resolution Multichannel 12-Bit Pipeline Flash Analog-to-Digital Converter Eight Dedicated Analog Inputs Simultaneous Sampling Capability Eight Inputs Converted Input Voltage Range Synchronized External Convert Start
FUNCTIONAL BLOCK DIAGRAM
MIPS CORE DATA ADDRESS GENERATOR
MEMORY WATCHDOG TIMER POWERON RESET
MOTOR CONTROL PERIPHERALS INTERRUPT CONTROLLER ENCODER INTERFACE EVENT CAPTURE UNIT DIGITAL UNIT
PROGRAM SEQUENCER
EXTERNAL ADDRESS EXTERNAL DATA
PROGRAM MEMORY ADDRESS DATA MEMORY ADDRESS PROGRAM MEMORY DATA DATA MEMORY DATA
ARITHMETIC UNITS SHIFTER
SERIAL PORTS SPORT SPORT
INTERVAL TIMER
CHANNEL AUXILIARY
CHANNEL 12-BIT
PRECISION VOLTAGE REFERENCE
16-BIT GENERATION
REV.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices. Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Site: http://www.analog.com Fax: 781/326-8703 Analog Devices, Inc., 1999
ADMC401-SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
Parameter AVDD TAMB Digital Supply Voltage Analog Supply Voltage Ambient Operating Temperature
(VDD AVDD AGND TAMB CLKIN MHz, unless otherwise noted)
Grade 4.75 4.75 5.25 5.25 Unit
ELECTRICAL CHARACTERISTICS
Parameter IOZH IOZL HI-Level Input Voltage LO-Level Input Voltage1, HI-Level Output Voltage1, LO-Level Output Voltage1, HI-Level Output Voltage5 LO-Level Output Voltage5 HI-Level Input Current7 HI-Level Input Current8 HI-Level Input Current9 LO-Level Input Current7 LO-Level Input Current8 LO-Level Input Current9 HI-Level Three-State Leakage Current10 LO-Level Three-State Leakage Current10 Digital Supply Current (Idle)11 Digital Supply Current (Dynamic)12 Analog Supply Current Input Capacitance13 Output Capacitance13,
Test Conditions min, -1.0 min, -0.1 min, min, -10.0 min, 10.0 max, max, max, max, max, max, max, max, AVDD MHz, TAMB +25°C MHz, TAMB +25°C
Unit
NOTES Bidirectional pins: D0-D23, RFS0, RFS1, TFS0, TFS1, SCLK0 SCLK1, PIO0-PIO11. Input only pins: PWMTRIP, PWMPOL, PWMSR, RESET, EIA, EIB, EIZ, EIS, ETU0, ETU1, DR1A, DR1B, DR0, CLKIN, CONVST, MMAP, BMODE, PWD. Programmable Pins (PIO0-PIO11). Output pins: PWMSYNC, AUX0, AUX1, CLKOUT, DT0, DT1, BGH, PMS, DMS, BMS, PWDACK A0-A13. Output pins: Although specified outputs, ADMC401 outputs CMOS-compatible will drive DD-0.3 GND+0.3 assuming loads. Input only pins RESET, EIA, EIB, EIZ, EIS, ETU0, ETU1, DR1A, DR1B, DR0, CLKIN, CONVST, MMAP, BMODE, PWD. Input pins with internal pull-down PIO0-PIO11 PWMTRIP. Input pins with internal pull-up, PWMPOL PWMSR. Three-statable pins: A0-A13, D0-D23, PMS, DMS, BMS, DT0, DT1, RFS0, RFS1, TFS0, TFS1, SCLK0, SCLK1. Idle refers execution IDLE instruction. Deasserted pins driven GND. Current reflects device operation with CLKOUT disabled. Current reflects device operating with output loads. Guaranteed tested. Output Capacitance capacitive load three-state output pin. Specifications subject change without notice.
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ADMC401 ANALOG-TO-DIGITAL CONVERTER
Parameter SPECIFICATIONS Signal Noise Ratio SNRD Signal Noise Distortion Total Harmonic Distortion CTLK Channel-Channel Crosstalk CMRR Common-Mode Rejection Ratio PSRR Power Supply Rejection Ratio ACCURACY Integral Nonlinearity Differential Nonlinearity Missing Codes Zero Error Gain Error1 TEMPERATURE DRIFT Zero Error Gain Error1 INPUT VOLTAGE Voltage Span Input Capacitance2 CONVERSION TIME tCONV Total Conversion Time
NOTES Excludes Internal Voltage Reference Error. Analog Input Pins VIN0 VIN7. Typical values neither tested guaranteed. Specifications subject change without notice.
(VDD AVDD AGND TAMB CLKIN MHz, VIN0 VIN7 p-p, VREF unless otherwise noted)
Test Conditions 0.025 0.025 0.025 Channels 1.88 Unit Bits Guaranteed
0.25
VOLTAGE REFERENCE
Parameter VREF
(VDD AVDD AGND TAMB CLKIN MHz, VIN0 VIN7 p-p, VREF unless otherwise noted)
Test Conditions 1.96 2.04 Unit
Output Voltage Reference Output Voltage Tolerance1 Output Current Load Regulation Power Supply Rejection Ratio Reference Input Resistance
SENSE REFCOM SENSE REFCOM Load Current
NOTES Relative tolerance temperature change, MAX. Specifications subject change without notice.
POWER-ON RESET (GND AGND
Parameter VRST VHYST Reset Threshold Voltage Hysteresis Voltage
CLKIN MHz, unless otherwise noted)
Test Conditions 3.25 Unit
Specifications subject change without notice.
REV.
ADMC401
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage -0.3 Input Voltage -0.3 Output Voltage Swing -0.3 Operating Temperature Range (Ambient) -40°C +85°C Storage Temperature Range -65°C +150°C Lead Temperature sec) +280°C
*Stresses above those listed under absolute maximum ratings cause permanent damage device. These stresses only; functional operation device these other conditions above those indicated operational section this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
ORDERING GUIDE
Model ADMC401BST
Temperature Range -40°C +85°C
Instruction Rate
Package Description 144-Lead Plastic Thin Quad Flatpack (LQFP)
Package Option ST-144
CAUTION (electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although ADMC401 features proprietary protection circuitry, permanent damage occur devices subjected high energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
WARNING!
SENSITIVE DEVICE
Timing Parameters
GENERAL NOTES MEMORY REQUIREMENTS
exact timing information given. attempt derive parameters from addition subtraction others. While addition subtraction would yield meaningful results individual device, values given this data sheet reflect statistical variations worst cases. Consequently, cannot meaningfully parameters derive longer times.
TIMING NOTES
This chart links common memory device specification names ADMC401 timing parameters your convenience. Common
Parameter Name tASW tWRA tRDD Function A0-A13, DMS, Setup before A0-A13, DMS, before Deasserted A0-A13, DMS, Hold after Deasserted Data Setup before High Data Hold after High Data Valid A0-A13, DMS, PMS, Data Valid Memory Device Specification Name Address Setup Write Start Address Setup Write Address Hold Time Data Setup Time Data Hold Time Data Valid Address Access Time
Switching characteristics specify processor changes signals. have control over this timing; dependent internal design. Timing requirements apply signals that controlled outside processor, such data input read operation. Timing requirements guarantee that processor operates correctly with another device. Switching characteristics tell what device will under given circumstance. Also, switching characteristics ensure timing requirement device connected processor (such memory) satisfied.
REV.
ADMC401
Parameter Clock Signals defined 0.5tCKI. ADMC401 uses input clock with frequency equal half instruction rate; clock (which equivalent 76.9 yields 38.5 processor cycle (equivalent MHz). values within range 0.5tCKI period should substituted relevant timing parameters obtain specification value. Example: tCKH 0.5tCK (38.5 9.25 Timing Requirements: tCKI tCKIL tCKIH tCKL tCKH tCKOH Control Signals Timing Requirement: tRSP RESET Width 5tCK1 Shutdown Signals Timing Requirements: tPWMTPW tPIOPWM Signals Timing Requirements: tCSI tCSE Internal Convert Start Width High External Convert Start Width High 2tCK 2tCK PWMTRIP Width Width 2tCK CLKIN Period CLKIN Width CLKIN Width High CLKOUT Width CLKOUT Width High CLKIN High CLKOUT High 76.9 0.5tCK 0.5tCK Unit
Switching Characteristics:
NOTE 1Applies after power-up sequence complete. Internal phase lock loop requires more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal oscillator start-up time).
CKIH
CLKIN
CKIL
CKOH
CLKOUT
Figure Clock Signals
REV.
ADMC401
Parameter Interrupts Flags Timing Requirements: tIFS tIFH tFOH tFOD IRQx Setup before CLKOUT Low1, IRQx Hold after CLKOUT High1, Flag Output Hold after CLKOUT Low4 Flag Output Delay from CLKOUT Low4 0.25tCK 0.25tCK 0.5tCK 0.5tCK Unit
Switching Characteristics:
NOTES IRQx inputs meet setup/hold requirements, they will recognized during current clock cycle; otherwise signals will recognized following cycle. (Refer "Interrupt Controller Operation" Program Control chapter ADSP-2100 Family User's Manual, Third Edition further information interrupt servicing.) Edge-sensitive interrupts require pulsewidths greater than level-sensitive interrupts must held until serviced. IRQx IRQ0 IRQ1. Flag Output
CLKOUT
FLAG OUTPUTS
IRQx
Figure Interrupts Flags
REV.
ADMC401
Parameter Request/Grant Timing Requirements: tSDB tSEC tSDBH tSEH Hold after CLKOUT High1 Setup before CLKOUT Low1 CLKOUT High DMS, PMS, BMS, Disable DMS, PMS, BMS, Disable High DMS, PMS, BMS, Enable DMS, PMS, BMS, Enable CLKOUT High DMS, PMS, BMS, Disable Low2 High DMS, PMS, BMS, Enable2 0.25tCK 0.25tCK 0.25tCK 0.25tCK Unit
Switching Characteristics:
NOTES asynchronous signal. meets setup/hold requirements, will recognized during current clock cycle; otherwise signal will recognized following cycle. Refer ADSP-2100 Family User's Manual, Third Edition BR/BG cycle relationships. asserted when granted processor requires control continue.
CLKOUT
CLKOUT PMS, BMS,
SDBH
Figure Request-Bus Grant
REV.
ADMC401
Parameter Memory Read Timing Requirements: tRDD tRDH tCRD tASR tRDA tRWR
wait states tCK.
Unit
Data Valid A0-A13, PMS, DMS, Data Valid Data Hold from High Pulsewidth CLKOUT High A0-A13, PMS, DMS, Setup before A0-A13, PMS, DMS, Hold after Deasserted High
0.5tCK 0.75tCK 0.5tCK 0.25tCK 0.25tCK 0.25tCK 0.5tCK
Switching Characteristics: 0.25tCK
CLKOUT
A0-A13
DMS,
Figure Memory Read
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ADMC401
Parameter Memory Write Switching Characteristics: tWDE tASW tDDR tCWR tWRA tWWR
wait states tCK.
Unit
Data Setup before High Data Hold after High Pulsewidth Data Enabled A0-A13, DMS, Setup before Data Disable before CLKOUT High A0-A13, DMS, PMS, Setup before Deasserted A0-A13, DMS, Hold after Deasserted High
0.5tCK 0.25tCK 0.5tCK 0.25tCK 0.25tCK 0.25tCK 0.75tCK 0.25tCK 0.5tCK
0.25tCK
CLKOUT
A0-A13
DMS,
Figure Memory Write
REV.
ADMC401
Parameter Serial Ports Timing Requirements: tSCK tSCS tSCH tSCP tSCDE tSCDV tSCDH tTDE tTDV tSCDD tRDV SCLK Period DR/TFS/RFS Setup before SCLK DR/TFS/RFS Hold after SCLK SCLKIN Width CLKOUT High SCLKOUT SCLK High Enable SCLK High Valid TFS/RFSOUT Hold after SCLK High TFS/RFSOUT Delay from SCLK High Hold after SCLK High TFS(Alt) Enable TFS(Alt) Valid SCLK High Disable (Multichannel, Frame Delay Zero) Valid 0.25tCK 0.25tCK Unit
Switching Characteristics:
CLKOUT
SCLK
RFSIN TFSIN
RFSOUT TFSOUT
SCDV SCDE
SCDD SCDH
alternate frame mode
multichannel mode, frame delay (MFD
Figure Serial Ports
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REV.
ADMC401
POWER DISSIPATION
determine total power dissipation specific application, following equation should applied each output: VDD2 load capacitance, output switching frequency.
Example:
INPUT
3.0V 1.5V 0.0V 2.0V 1.5V 0.3V
OUTPUT
application where external data memory used other outputs active, power dissipation calculated follows: Assumptions: External data memory accessed every cycle with address pins switching. External data memory writes occur every other cycle with data pins switching. Each address data total load pin. application operates 38.5 Total Power Dissipation VDD2 PINT (IDD Digital Analog) VDD2 calculated each output:
Pins Address, Data Output, CLKOUT 52.00 29.25 3.25 6.50 91.00
Figure Voltage Reference Levels Measurements (Except Output Enable/Disable)
Output Enable Time
Output pins considered enabled when that have made transition from high-impedance state when they start driving. output enable time (tENA) interval from when reference signal reaches high voltage level when output reached specified high trip point, shown Output Enable/Disable diagram. multiple pins (such data bus) enabled, measurement value that first start driving.
REFERENCE SIGNAL
tMEASURED
(MEASURED) OUTPUT (MEASURED)
tENA
(MEASURED) (MEASURED) 0.5V (MEASURED) +0.5V 2.0V 1.0V (MEASURED) OUTPUT STARTS DRIVING
tDIS
tDECAY
OUTPUT STOPS DRIVING
HIGH-IMPEDANCE STATE. TEST CONDITIONS CAUSE THIS VOLTAGE LEVEL APPROXIMATELY 1.5V.
Total power dissipation this example PINT
TEST CONDITIONS Output Disable Time
Figure Output Enable/Disable
Output pins considered disabled when they have stopped driving started transition from measured output high voltage high impedance state. output disable time (tDIS) difference tMEASURED tDECAY, shown Output Enable/Disable diagram. time interval from when reference signal reaches high voltage level when output voltages have changed from measured output high voltage. decay time, tDECAY, dependent capacitative load, current load, output pin. approximated following equation: DECAY from which MEASURED DECAY calculated. multiple pins (such data bus) disabled, measurement value that last stop driving.
OUTPUT
+1.5V 50pF
Figure Equivalent Device Loading Measurements (Including Fixtures)
REV.
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ADMC401
FUNCTION DESCRIPTION
Name PWDACK BMODE MMAP PWMSR RESET PWMPOL CLKIN XTAL CLKOUT DR1A/FI DRIB/FI DT1/FO
Name RFS1/IRQ0/SROM TFS1/IRQ1 SCLK1 RFS0 TFS0 SCLK0 PWMTRIP PWMSYNC
Name AUX1 AUX0 ETU1 ETU0
Name CONVST AVDD AVSS VIN7 VREF VIN6 REFCOM VIN5 CAPT VIN4 BSHAN ASHAN VIN0 CAPB VIN1 VIN2 GAIN VIN3 SENSE AVSS AVDD
These pins must left unconnected
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ADMC401
CONFIGURATION
AUX0
AUX1
ETU0
ETU1
CONVST AVDD AVSS VIN7 VREF VIN6 REFCOM VIN5 CAPT VIN4 BSHAN ASHAN VIN0 CAPB VIN1 VIN2 GAIN VIN3 SENSE AVSS AVDD MMAP PWMSR RESET PWMPOL CLKIN XTAL CLKOUT DR1A/F1 PWDACK DR1B/FI DT1/FO BMODE
IDENTIFIER
PWMSYNC PWMTRIP SCLK0 TFS0 RFS0 SCLK1 TFS1/IRQ1 RFS1/IRQ0/SROM
ADMC401
VIEW (Not Scale)
CONNECT
REV.
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ADMC401
(Continued from Page
Programmable Digital (PIO) Port 12-Pin Configurable Digital Port Flexible Interrupt Generation Four Dedicated Interrupt Vectors Each Line Configurable Shutdown 8-Bit Auxiliary Outputs Programmable Switching Frequency Independent Offset Modes Two-Channel Event Timer (Capture) Unit Configurable Event Definition Single-Shot Free-Running Modes Peripheral Interrupt Controller Manages Peripheral Interrupts 16-Bit Watchdog Timer Internal Power-On Reset System Programmable 16-Bit Interval Timer with Prescaler Double Buffered Synchronous Serial Ports Boot Load Protocols SPORT1: Synchronous PROM/SROM Booting UART Boot Loader with Autobaud Synchronous Master Slave Boot Loader Debugger Interface SPORT1: UART Interface with Autobaud Synchronous Master Slave Interface Full Debugger Program Development Industrial Temperature Range Operating Voltage Package: 144-Lead LQFP GENERAL DESCRIPTION
data address generators program sequencer. computational units comprise ALU, multiplier/accumulator (MAC) barrel shifter. core also adds instructions manipulation, squaring (x2), biased rounding global interrupt masking. addition, flexible double-buffered, bidirectional synchronous serial ports included ADMC401. ADMC401 provides 24-bit internal program memory RAM, 24-bit internal program memory 16-bit internal data memory RAM. program data memory boot loaded through serial port from either serial E2PROM, through UART connection (either from external host microprocessor from Motion Control Debugger) synchronous serial interface from host microprocessor. Alternatively, internal program data memory booted from external device across address data buses. program memory includes monitor that adds software debugging features through serial port. Additionally, ADMC401 device adds significant external memory peripheral expansion capabilities making available full address data core. This feature permits expansion both external program data memory means that core address bits external program memory bits external data memory. ADMC401 contains number special purpose, motor control peripherals. first high performance, 8-channel, 12-bit system with dual channel simultaneous sampling ability across pair inputs. internal precision voltage reference also available part system. addition, three-phase, 16-bit, center-based generation unit used produce high-accuracy signals with minimal processor overhead. ADMC401 also contains flexible incremental encoder interface unit position sensor feedback; adjustable-frequency auxiliary outputs, lines digital I/O; 2-channel event capture system; 16-bit watchdog timer; 16-bit interval timers (one which linked encoder interface unit) interrupt controller that manages peripheral interrupts. Finally, ADMC401 contains integrated power-on-reset (POR) circuit that used generate required reset signal device power-on.
ADMC401 single-chip DSP-based controller, suitable high performance control induction motors (ACIM), permanent magnet synchronous motors (PMSM), brushless motors (BDCM) switched reluctance (SR) motors industrial applications. ADMC401 integrates MIPS, fixedpoint core with complete motor control peripherals that permits fast motor control highly integrated environment. core ADMC401 ADSP-2171 which completely code compatible with ADSP-21xx family well other members integrated motor controllers ADMC3xx family) combines three computational units,
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ADMC401
INSTRUCTION REGISTER DATA ADDRESS GENERATOR DATA ADDRESS GENERATOR BOOT ADDRESS GENERATOR POWER DOWN CONTROL LOGIC
PROGRAM SEQUENCER
EXTERNAL ADDRESS
EXCHANGE
EXTERNAL DATA
INPUT REGS OUTPUT REGS
INPUT REGS OUTPUT REGS
INPUT REGS SHIFTER OUTPUT REGS
CONTROL LOGIC
COMPANDING CIRCUITRY TRANSMIT RECEIVE SERIAL PORT
TIMER
TRANSMIT RECEIVE SERIAL PORT
Figure Core Block Diagram
ARCHITECTURE OVERVIEW
Figure functional block diagram core ADMC401. core based fixed-point ADSP2171 core that member fixed-point ADSP-21xx family general purpose DSPs from Analog Devices Inc. ADSP-2171 flexible architecture comprehensive instruction allow processor perform multiple operations parallel. processor cycle (38.5 with crystal) core can: Generate next program address. Fetch next instruction. Perform data moves. Update data address pointers. Perform computational operation. Receive transmit through serial ports. Decrement interval timers. Generate signals. Convert input signals. Operate encoder interface unit. Operate other peripherals including auxiliary event timer subsystem.
processor contains three independent computational units: arithmetic logic unit (ALU), multiplier/accumulator (MAC) shifter. computational units process 16-bit data directly have provisions support multiprecision computations. performs standard arithmetic logic operations; division primitives also supported. performs single-cycle multiply, multiply/add, multiply/ subtract operations with bits accumulation. shifter performs logical arithmetic shifts, normalization, denormalization derive exponent operations. shifter used implement numeric format control efficiently, including floating-point representations. internal result directly connects computational units that output unit input unit next cycle. powerful program sequencer dedicated data address generators ensure efficient delivery operands these computational units. sequencer supports conditional jumps, subroutine calls returns single cycle. With internal loop counters loop stacks, ADMC401 executes looping code with zero overhead; explicit jump instructions required maintain loop.
This takes place while ADMC401 continues
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ADMC401
data address generators (DAGs) provide addresses simultaneous dual operand fetches from data memory program memory. Each maintains updates four address pointers registers). Whenever pointer used access data (indirect addressing), post-modified value four modify registers. length value associated with each pointer registers) implement automatic modulo addressing circular buffers. circular buffering feature also used serial ports automatic data transfers from on-chip memory. DAG1 generates only data memory addresses provides optional bit-reversal capability. DAG2 generate either program data memory addresses, bit-reversal capability. Efficient data transfer achieved with five internal buses: Program Memory Address (PMA) Bus. Program Memory Data (PMD) Bus. Data Memory Address (DMA) Bus. Data Memory Data (DMD) Bus. Result Bus. register. When value counter reaches zero, interrupt generated count register reloaded from 16bit period register (TPERIOD). ADMC401 instruction provides flexible data moves multifunction (one data moves with computation) instructions. Each instruction executed single 38.5 processor cycle (for crystal). ADMC401 assembly language uses algebraic syntax ease coding readability. comprehensive development tools supports program development.
Serial Ports
ADMC401 incorporates complete synchronous serial ports (SPORT0 SPORT1) serial communications multiprocessor communication. following brief list capabilities ADMC401 SPORTs. Refer ADSP2100 Family User's Manual, Third Edition further details. SPORTs bidirectional have separate, doublebuffered transmit receive section. SPORTs external serial clock generate their serial clock internally. SPORTs have independent framing receive transmit sections. Sections frameless mode with frame synchronization signals internally externally generated. Frame synchronization signals active high inverted, with either pulsewidths timings. SPORTs support serial data word lengths from bits bits provide optional A-law µ-law companding. SPORT receive transmit sections generate unique interrupts completing data word transfer. SPORTs receive transmit entire circular buffer data with only overhead cycle data word. interrupt generated after data buffer transfer. SPORT0 multichannel interface selectively receive transmit 24-word 32-word, time-division multiplexed, serial bitstream. SPORT1 configured have external interrupts (IRQ0 IRQ1), Flag Flag signals. internally generated serial clock still used this configuration. following additional capabilities ADMC401 SPORTs that part ADSP-21xx products: SPORT1 input single program data memory boot loading. RFS1 configured internally ADMC401 SROM/E2PROM reset signal. SPORT1 data receive pins (DR1A DR1B). DR1A intended only synchronous data receive from external E2PROM. DR1B used data receive general purpose SPORT after booting data receive other boot load modes UART/debugger interface. DR1A DR1B pins internally multiplexed onto data receive SPORT. particular data receive selected determined MODECTRL register.
Program memory store both instructions data, permitting ADMC401 fetch operands single cycle, from internal program memory from internal data memory. ADMC401 fetch operand from on-chip program memory next instruction same cycle. ADMC401 writes data from 16-bit registers 24bit program memory using register provide lower eight bits. When reads data (not instructions) from 24-bit program memory 16-bit data register, lower eight bits placed register. ADMC401 respond number distinct core peripheral interrupts. core interrupts include serial port receive transmit interrupts, timer interrupts, software interrupts external interrupts. addition, there master RESET signal. motor control peripherals also produce interrupts core. serial ports (SPORTs) provide complete synchronous serial interface with optional companding hardware wide variety framed unframed data transmit receive modes operation. Each SPORT generate internal programmable serial clock accept external serial clock. Boot loading both program data memory ADMC401 through serial port SPORT1. Alternatively ADMC401 boot loaded from external bytewide memory connected external address data buses. After reset, seven wait states automatically generated. This permits, example, 38.5 ADMC401 external EPROM boot memory. internal boot address generator provides addresses booting from external byte-wide memory. programmable interval counter also included core used generate periodic interrupts. 16-bit count register (TCOUNT) decremented every processor cycles, where scaling value stored 8-bit TSCALE
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ADMC401
FUNCTION DESCRIPTION INTERRUPT OVERVIEW
ADMC401 available 144-lead TQFP package. Table contains descriptions.
Table List
Group Name A13-A0 D23-D0 PMS, DMS, MMAP RESET CLKOUT CLKIN, XTAL BMODE PWD, PWDACK SPORT0 SPORT1 Input/ Pins Output Function Address Lines Data Lines External Memory Select Lines External Memory Read/Write Enable Memory Select Internal Power Reset Output Processor Reset Input Processor Clock Output External Clock Quartz Crystal Input Request Grant Hang Control Boot Mode Select Power-Down Power-Down Acknowledge Serial Port Pins (TFS0, RFS0, DT0, DR0, SCLK0) Serial Port (TFS1/IRQ1, RFS1/ IRQ0/SROM, DT1/FO, DR1A/FI, DR1B/FI, SCLK1) Analog Inputs Inverting Inputs Sample Hold Amplifiers Analog Input Gain Calibration Reference Voltage Input/Output Reference Common Common-Mode Level (Midsupply) Noise Reduction Pins Voltage Reference Select External Convert Start Outputs Shutdown Signal Polarity Control Synchronization Output Switched Reluctance Mode Control Digital Port Event Timer Inputs Auxiliary Outputs Encoder Interface Inputs External Registration Inputs Connect Analog Power Supply Analog Ground Digital Power Supply Digital Ground
ADMC401 respond different interrupt sources, some which internal core interrupts others from motor control peripherals. core interrupts include Power RESET) interrupt. peripheral IRQ2) interrupt. SPORT0 receive SPORT0 transmit interrupt. SPORT1 receive IRQ0) SPORT1 transmit IRQ1) interrupt. software interrupts. interval timer timeout interrupt. power-down interrupt. addition, motor control peripherals other interrupts that include: PWMSYNC interrupt. conversion interrupt. encoder loop timer timeout interrupt. Five peripheral input/output (PIO) interrupts. event timer interrupt. encoder count error interrupt. trip interrupt.
interrupts internally prioritized individually maskable except nonmaskable power-down interrupt.
Memory
VIN0-VIN7 ASHAN, BSHAN GAIN VREF REFCOM CAPT, CAPB SENSE CONVST AH-CL PWMTRIP PWMPOL PWMSYNC PWMSR PIO0-PIO11 ETU0, ETU1 AUX0-AUX1 EIA, EIB, EIZ, AVDD AVSS
ADMC401 distinct memory types; program memory data memory addition external boot memory). general, program memory contains user code coefficients, while data memory used store variables data during program execution. Both program memory provided internally ADMC401. program memory ADMC401 altered depending state MMAP BMODE pins. various program memory maps illustrated Figure permissible settings MMAP BMODE. state these pins also impact which internal memory ADMC401 booted, described later. There internal ADMC401. Setting ROMENABLE Data Memory Wait State Control Register address (0x3FFE)) enables ROM. When ROMENABLE addressing program memory range will access on-chip ROM. When ROMENABLE zero, addressing program memory this range will access external program memory. ROMENABLE initialized zero after reset unless MMAP BMODE When MMAP BMODE ADMC401 provides bits internal program memory starting address 0x0000 that booted from byte-wide interface address data buses. Following boot loading, program execution starts address 0x0000. this mode, remainder program memory space, 24-bit block starting address 0x1000, assigned external memory. When MMAP BMODE program memory identical previous case, ROMENABLE defaults reset, execution starts from internal program memory located address 0x0800. This permits internal (and external desired) memory boot loaded across various serial interfaces SPORT1.
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ADMC401
0x0000 INTERNAL (BOOTED FROM BYTE-WIDE EPROM) 0x07FF 0x0800 INTERNAL (ROMENABLE EXTERNAL (ROMENABLE 0x07FF 0x0800 0x0000 EXTERNAL MEMORY INTERNAL (ROMENABLE EXTERNAL (ROMENABLE 0x07FF 0x0800 0x0000 INTERNAL (BOOTED SPORT1) INTERNAL (ROMENABLE DEFAULTS DURING RESET) 0x0FFF 0x1000
0x0FFF 0x1000
0x0FFF 0x1000
EXTERNAL MEMORY
EXTERNAL MEMORY
EXTERNAL MEMORY
0x3800 INTERNAL 0x3FFF MMAP BMODE 0x3FFF MMAP BMODE 0x3FFF MMAP BMODE
Figure Program Memory ADMC401
When MMAP BMODE internal program memory mapped program memory space (starting address 0x3800) boot loading occurs. Program execution starts from external program memory address 0x0000. Only with ROMENABLE internal monitor debugger features ADMC401 available program development. Additionally, certain spaces memory have predefined functions illustrated Figure where seen that address space 0x0000 0x005F reserved interrupt vector table.
0x000 0x05F 0x060 0x7FF 0x800 VECTOR TABLE USER PROGRAM SPACE MONITOR 0xFEF 0xFF0 0xFFF 0x1000
DWAIT3 DWAIT4 fields Data Memory Wait State Register (MEMWAIT) illustrated Figure Following reset, DWAIT0 DWAIT1 DWAIT2 DWAIT DWAIT4 However, standalone mode with MMAP BMODE internal monitor code writes these five fields. correct operation DWAIT2 must always configuration MEMWAIT register shown data sheet.
0x0000 EXTERNAL MEMORY 0x1FFF 0x2000 0x23FF 0x2400 0x0000 0x03FF 0x0400 0x07FF 0x0800 DWAIT0 DWAIT1 DWAIT2
PERIPHERAL REGISTERS EXTERNAL MEMORY
0x2FFF 0x3000 0x3400
DWAIT3 DWAIT4
0x37FF 0x3800 0x3B5F 0x3B60 0x3BFF 0x3C00 0x3FFF
0x3800 INTERNAL USER RESERVED MONITOR CORE REGISTERS/ RESERVED WAIT STATES
RESERVED
EXTERNAL MEMORY
0x3FFF
Figure Detailed View Program Memory with MMAP BMODE
Figure Data Memory ADMC401
program memory interface generate wait states external memory devices. program memory wait state field (PWAIT) System Control Register controls number inserted wait states defaults structure System Control Register shown data sheet. data memory ADMC401 shown Figure internal data memory ADMC401 arranged single 16-bit block starting address 0x3800. addition, there blocks reserved data memory space; block starting address 0x2000 that reserved peripheral registers starting address 0x3C00 that reserved internal core registers. Data memory wait states controlled DWAIT0, DWAIT1, DWAIT2,
24-bit block internal program memory starting address 0x800 contains monitor function that used download execute user programs serial port. addition, monitor function supports interactive mode which commands received processed from host that configured UART device. example such host Windows-based Motion Control Debugger that part software development system ADMC401. interactive mode, host access both internal peripheral motor control registers ADMC401, read write both program data memory, implement breakpoints perform single-step operation part program debugging cycle. Again, this debugging feature only available when ROMENABLE
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ADMC401
SYSTEM INTERFACE
CLOCK SIGNALS
ADMC401 uses input clock with frequency equal half instruction rate; input clock yields 38.5 processor cycle (which equivalent MHz). Normally instructions executed single processor cycle. device timing relative internal instruction rate, which indicated CLKOUT signal (when enabled). Throughout this data sheet, period CLKIN signal denoted tCKI. instruction period (the period CLKOUT signal), tCKI. MIPS operation, CLKIN signal used, corresponding tCKI 76.9 38.5 Additionally, fundamental time increment motor control peripherals. Therefore, unless otherwise specified, motor control peripherals clocked rate equal CLKOUT. ADMC401 clocked either crystal external clock source. CLKIN input cannot halted, changed frequency, operated below specified minimum frequency during normal operation. external clock source used, should TTL-compatible signal running half instruction rate. signal connected CLKIN ADMC401. this mode, with external clock signal, XTAL must left unconnected. Because ADMC401 includes on-chip oscillator circuit, external crystal used instead clock source. crystal should connected across CLKIN XTAL pins. parallel-resonant, fundamental frequency, microprocessorgrade crystal should used. frequency value selected crystal should equal half desired instruction rate processor. Figure shows crystal properly connected yield processor rate. CLKOUT output enabled disabled CLKODIS SPORT0 Autobuffer Control Register, (0x3FF3). However, extreme care must exercised when using this (and thus discouraged) since disabling CLKOUT effectively disables motor control peripherals, except watchdog timer.
RESET POWER RESET (POR) CIRCUIT
voltage, VRST level. soon threshold voltage attained, power reset circuit enables 17-bit counter that clocked CLKOUT rate. While counter counting held low. When counter overflows, after time: 38.5 10-9 2.52 brought high RESET pins connected, device brought reset. internal power-on reset circuit also acts power supply monitor puts level detects voltage less than VRST-VHYST, where VHYST hysteresis voltage built into circuit. supply voltage must then exceed VRST initiate another power-on reset sequence.
VRST
VRST VHYST
Figure Operation Power-On Reset (POR) Circuit ADMC401
master reset (RESET causes Full System Reset, which sets internal stack pointers empty stack condition, masks interrupts, clears MSTAT register, restores program counter initial value performs full reset motor control peripherals including watchdog timer. Following power-up, possible initiate Full System Reset simply pulling RESET low. these resets, there need wait stabilization RESET signal must meet minimum pulsewidth specification, tRSP generate external RESET signal, recommended either circuit with Schmitt trigger commercially available reset Separate from Full System Reset, software controlled Peripheral Reset (excluding watchdog timer) achieved toggling flag with following code segment: PRESET: FL2; TOGGLE FL2; TOGGLE FL2; RTS;
RESET initiates complete hardware reset ADMC401 when pulled low. RESET signal must asserted when device powered assure proper initialization. ADMC401 contains integrated power-on reset (POR) circuit that provides output reset signal, POR, from ADMC401 power power supply voltage falls below threshold level. ADMC401 reset from external source using RESET signal alternatively internal power-on reset circuit used connecting RESET pin. During power-up RESET line must activated long enough allow core's internal clock stabilize. power-up sequence defined total time required crystal oscillator stabilize after valid applied processor internal phase locked loop (PLL) lock onto specific crystal frequency. minimum 2000tCKI cycles will ensure that locked (this does include crystal oscillator start-up time). operation internal power-on reset circuit illustrated Figure power-up, circuit maintains until detects that line attained threshold
full peripheral reset (except watchdog timer itself) will occur automatically watchdog trip.
EXTERNAL MEMORY INTERFACE
ADMC401 address bits external program memory bits external data memory. ADMC401 provides address 14-bit address (A13-A0). Instructions data transferred across 24-bit data (D23-D0) during program memory accesses. During data memory accesses, data transferred most significant bits (D23-D8) data bus. dual off-chip fetch, data from program memory read first, then data from data memory. program memory select pin, PMS, activated during external program memory accesses used chip select signal external program memory devices. Similarly, external data memory accesses, activated.
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control lines indicate direction transfer. Memory read, active low, signaling read from external memory memory write; active low, signaling write external memory. Typically, line connected (chip enable) external program memory line connected line external data memory. line connected (output enable) line connected (write enable) both memories. On-chip accesses internal program memory ROM) drive external signals. PMS, lines remain high (deasserted) address data buses three-stated during these internal accesses. Similarly, internal accesses data memory (including internal peripheral core memory mapped registers) drive external signals DMS, lines remain high (deasserted) address data buses also three-stated. External peripherals also connected externally memory mapped external memory space ADMC401. MSBs external data connected internally bits internal data memory bus. Therefore, data lines D23-D8 should used 16-bit peripherals.
BOOT LOADING Standalone Mode (MMAP BMODE
ADMC401
CLKOUT XTAL 13MHz MMAP BMODE CLKIN DR1A SCLK1 RESET RFS1/ SROM DATA RESET SERIAL E2PROM 20pF 20pF
Figure Basic System Configuration Standalone Mode
boot loading from SROM E2PROM unsuccessful, monitor code reconfigures SPORT1 UART (setting both MODECTRL register) attempts receive commands from external device this serial port using DR1B pin. monitor waits bytes information. These bytes received asynchronously that clock needed. first byte autobaud byte used calculate baud rate which data being received. This known autobaud feature. ADMC401 will automatically lock onto baud rate external device sent byte 0x70. maximum baud rate that ADMC401 will lock onto kb/s CLKOUT. second byte information received header byte that uniquely identifies monitor which type interface connected There different interfaces supported ADMC401. These includes: UART boot loader such from Motorola 68HC11 communicating over Serial Communications Interface (SCI) port. synchronous slave boot loader (the clock external). synchronous master boot loader (the ADMC401 provides clock). UART debugger interface such Motion Control Debugger from Analog Devices. monitor then processes commands received from debugger over UART interface. synchronous master debugger interface. synchronous slave debugger interface. Detailed information these software interfaces found "UART Boot Loader Protocol" "UART Debugger Protocol" appendices ADMC401 Developer's Reference Manual.
Byte-Wide EPROM Boot Mode (MMAP BMODE
Boot loading ADMC401 occur number different ways determined state both MMAP BMODE pins. both MMAP BMODE tied (HI), ADMC401 placed so-called standalone mode execution starts from internal program memory address 0x0800 following power-on reset. This starts execution internal monitor function that first performs some initialization functions (including writing three data memory wait state fields) copies default interrupt vector table addresses 0x0000-0x005F program memory RAM. monitor program next clears MODECTRL register connect DR1A internal data receive port (DR1) SPORT1. addition, MODECTRL register set. This connects port core RFS1/SROM reset serial memory device. monitor next attempts boot load from external Serial (SROM) Serial E2PROM SPORT1 using three wire connection Figure This SROM E2PROM should programmed with protocol MAKEPROM utility provided with Motion Control Debugger. monitor program first toggles RFS1/SROM ADMC401 reset serial memory device with following code segment: SROMRESET: FL1; TOGGLE FL1; TOGGLE FL1; RTS;
properly programmed SROM E2PROM connected SPORT1, data clocked synchronously into ADMC401 rate Mb/s. Both internal external program data memory loaded from SROM/E2PROM, available capacity serial memory device. After entire boot load complete, program execution begins address 0x0060. This where first instruction user code should placed.
both MMAP BMODE pins tied GND, ADMC401 operates so-called EPROM Boot mode. this mode entire internal program memory, portion loaded from external source using boot sequence over memory interface. allow boot loading from inexpensive 8-bit wide EPROM devices, processor loads data byte time. boot sequence also initiated after reset software. Boot memory organized into eight pages, each which bytes long. Every fourth byte page empty byte except first one, which contains page length. Each three bytes between successive empty bytes contains 24-bit instruction loaded into internal DSP. REV.
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page length read first then bytes loaded from page downwards. This causes shorter booting times shorter pages. length boot page given page length (number 24-bit words/8) That page length causes boot address generator generate byte addresses eight words that reside sequential EPROM locations. PROM splitter utility (SPL21), part Motion Control Debugger tool set, calculates proper page length your program orders bytes your program according proper protocol. More detailed information about this PROM splitter utility found "Booting from External EPROM with MMAP BMODE chapter ADMC401's Developer's Reference Manual. Following reset, both MMAP BMODE boot sequence always boot loads page After reset, boot loading occur under program control from eight different boot pages. boot page select field (BPAGE) memory mapped System Control Register specifies which boot page loaded. boot from specific boot page, first BPAGE bits desired value boot force (BFORCE) System Control Register initiate boot sequence. ADMC401 boot internal program memory from single byte-wide CMOS EPROM such 27C64 27C512. cost commodity-grade EPROM with industry-standard access time used. number wait states boot memory access selected BWAIT field System Control Register. This field value from number wait states. default value BWAIT field that seven wait states inserted into reset-initiated boot loading sequence. Timing boot memory access identical that external program memory external data memory accesses, except that active strobe rather than DMS. address eight pages bytes each, address lines needed. least significant bits output 14-bit address (A13 while most significant bits output MSBs data (D23 D22) during boot memory accesses. data read from middle eight bits data (D15 D8). development tools ADMC401 support creation EPROM target files capable boot loading both internal external program data memory.
External Memory Mode (BMODE MMAP REQUEST/GRANT
ADMC401 relinquish control external data address buses external device. external device requests asserting (low) request signal asynchronous input ADMC401 performing external access, responds active input following processor cycle Three-stating data address buses PMS, DMS, BMS, output drivers. Asserting grant (BG) signal, Halting program execution (unless Mode enabled). Mode enabled, (using G-MODE instruction) ADMC401 continues execute instructions from internal memory. will halt program execution until encounters instruction that requires external access, which includes access motor control peripheral register. Mode enabled, ADMC401 always halts before granting bus. processor's internal state affected granting bus, serial ports remain active during grant, whether processor core halts. ADMC401 performing external access when signal asserted, will grant buses until cycle after access completes. entire instruction does need completed when granted. single instruction requires external accesses, will granted between accesses. second access performed after removed. When input released, ADMC401 releases signal, re-enables output drivers continues program execution from point where stopped. always deasserted same cycle that removal recognized. request feature operates times, including when ADMC401 booting when RESET active. During RESET, asserted same cycle that recognized. During booting, granted after completion loading current byte (including wait states). Using request during booting bring booting operation under control host computer. ADMC401 additional output, Grant Hang, BGH, which lets operate multiprocessor system with minimum number wasted cycles. asserts when ADMC401 ready execute instruction stopped because external granted another device. other device release deasserting request. Once released, ADMC401 deasserts executes external access.
POWER-DOWN MODES
this mode, with BMODE tied MMAP tied VDD, ADMC401 placed external memory mode there boot loading. effect this mode that internal bank program memory relocated from bottom memory (starting address 0x0000) program memory space address 0x3800). this mode, program execution starts external memory address 0x0000, which point first instruction must placed. mode which BMODE MMAP allowed ADMC401 illegal state. operation ADMC401 neither guaranteed defined with BMODE MMAP
ADMC401 includes power-down feature that allows device enter very power dormant state through hardware software control. power-down mode: Internal clocks disabled Processor registers memory contents maintained Ability recover from power-down less than 100tCKI cycles Interrupt support housekeeping code before entering power-down after recovering from power-down User selectable power-up context
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ADMC401
Entering Power-Down
power-down sequence initiated applying high-to-low transition setting power-down force control (PDFORCE) SPORT1 autobuffer/powerdown control register. core then vectors nonmaskable power-down interrupt vector address 0x002C. Care must taken ensure that multiple power-down interrupts occur else stack overflow result. interrupt service routine address 0x002C used execute number housekeeping instructions prior processor entering power-down mode. Typically, this used configure power-down state, disable on-chip peripherals clear pending interrupts. subsequently enters power-down mode when executes IDLE instruction (while asserted). processor take either cycles power down, depending internal clock states during execution IDLE instruction. register memory contents maintained power-down. Also, active outputs held whatever state they before going into power-down. instruction executed before IDLE instruction, processor returns from power-down interrupt power-down sequence aborted.
Exiting Power-Down
exiting power-down with RESET, XTALDELAY control ignored.
Startup Time After Power-Down
time required exit power-down state depends method used exit power-down. Unlike standard ADSP21xx products, XTALDIS Power-Down Register effect ADMC401 that possible avoid power drain caused XTAL toggling. When processor comes power-down either RESET pins, will begin executing after maximum startup time CLKIN cycles long clock oscillator stable same frequency before power-down. external clock unstable when ADMC401 exits power-down, XTALDELAY control used insert additional 4096 cycle delay into startup time. This delay only inserted when ADMC401 brought power-down pin. processor taken power-down RESET line, clock stable same frequency before power-down, RESET need only held five cycles.
PWDACK
power-down mode exited with with RESET pin. There also several user-selectable modes startup from power-down which specify startup delay well specify program flow after startup. This allows program resume from where left before power-down, program context cleared. Applying low-to-high transition will take processor power-down. amount time takes processor come power-down controllable with delay startup from power-down control (XTALDELAY, Power-Down Control Register SPORT1 Autobuffer Control Register). this cleared, additional delay over quick startup (100 cycles) introduced. this set, delay 4096 cycles introduced. context exiting power-down (PUCR) Power-Down Control Register. this cleared, after exiting power-down processor will continue execute instructions following IDLE instruction after low-to-high transition pin. When instruction encountered interrupt service routine power-down, operation returned main routine. PUCR set, "clear context", processor resumes operation from power-down clearing STATUS, LOOP CNTR registers. IMASK ASTAT registers cleared SSTAT goes 0x55. processor starts execution address 0x0000. Active output pins retain their states during power-down. addition, interrupts latched serviced ADMC401 exits power-down with PUCR possible clock data into serial ports during power-down supplying external serial clock. Data clocked into ADMC401 will remain registers. These activities cause additional power consumption. RESET activated while ADMC401 powerdown mode, power down exited, normal Full System Reset Sequence initiated, (which depends upon settings MMAP BMODE boot method usual). When
PWDACK output that indicates when ADMC401 power-down mode. This driven high processor when powered down. driven after processor completed power-up sequence. level PWDACK also indicates that there valid CLKOUT signal that instruction execution begun. When power-down terminated with RESET startup delay selected, level PWDACK only indicates start oscillations CLKOUT pin. will necessarily indicate start instruction execution. state PWDACK also CLKOUT signal undefined during first cycles initial reset.
Using Power-Down Nonmaskable Interrupt
power-down interrupt never masked. possible this interrupt other purposes, desired. ADMC401 does into power-down until IDLE instruction executed. executed instead, before IDLE instruction, processor returns from power-down interrupt service outline power-down sequence aborted.
ANALOG-TO-DIGITAL CONVERSION SYSTEM
OVERVIEW SYSTEM
ADMC401 contains fast, high accuracy, multiple-input analog-to-digital conversion system with simultaneous sampling capabilities. This conversion system permits fast, accurate conversion currents, voltages other signals needed high performance motor control systems. functional block diagram entire system shown Figure system permits eight dedicated analog inputs converted under MHz) through single 12bit pipeline flash ADC. entire system (including multiplexing sample hold amplifiers) operates clock rate equal quarter instruction rate. Analog input voltages converted. input signals divided into banks four signals each, with VIN0 VIN3 making bank VIN4 VIN7 making second bank. There also dedicated inputs (ASHAN REV.
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BSHAN) inverting terminal sample hold amplifiers (SHA) that external signals correctly biased about nominal operating range ADC. conversion sequence initiated either internally (synchronized generation) from external event CONVST pin. default Simultaneous Sampling mode operation, internal control logic simultaneously samples first pair input signals (VIN0 VIN4) following convert start command. Subsequently, these inputs multiplexed into 12-bit analog-to-digital converter. After delay clock cycles, second pair analog inputs (VIN1 VIN5) sampled simultaneously then multiplexed into ADC. This process continues until four pairs analog inputs have been sampled converted. conversion given analog input channel completed, corresponding digital number written dedicated 16-bit, twos complement, left-aligned register that memory mapped data memory space core. data register ADC0 stores conversion result signal VIN0, etc. Following conversion each pair analog inputs, dedicated ADCSTAT register. result this highly efficient pipelined structure that eight data registers will contain valid conversion results less than MHz) after convert start command. this point dedicated interrupt will generated. Alternatively, data required sooner, ADCSTAT register polled detect when given pair analog inputs have been successfully converted, except Sequential Sampling mode. Once conversion sequence been completed eight data registers have been updated, entire structure automatically reverts Single Channel mode continuously converts analog input VIN0 pin. results this conversion placed additional ADCXTRA register updated once every clock cycle. This feature could used continuously monitor single analog input VIN0 pin. There additional modes operation system that used offset gain calibration entire system. Offset Calibration mode, analog inputs (VIN0 VIN7, GAIN, ASHAN BSHAN) disconnected from inputs sample hold amplifiers. Instead, both terminals each sample hold amplifiers connected together voltage reference. Following conversion sequence, data data register taken measure offset sample hold amplifiers ADC. Additionally, Gain Calibration mode, dedicated analog input GAIN applied noninverting terminal both sample hold amplifiers. number precise external voltages applied this measure correct gain errors, required. Along with each data output from converter, Out-ofRange (OTR) signal exceeds permissible input voltage span. normal conversion, eight bits eight analog inputs stored ADCOTR register, with each analog input. ADCXTRA register stored ADCSTAT register. either internally generated precision reference voltage externally supplied reference voltage level VREF pin. operating mode selected connection SENSE pin.
ASHAN VIN0 VIN1 VIN2 VIN3 ADC0(15.0) ADC1(15.0) ADC2(15.0) DATA ADC3(15.0) ADC4(15.0) ADC5(15.0) ADC6(15.0) ADC7(15.0) ADCXTRA(15.0) ADCOTR(7.0) ADCSTAT(4.0) ADCCTRL(4.0)
GAIN
12-BIT PIPELINE FLASH
VIN4 VIN5 VIN6 VIN7 BSHAN PWMSYNC CONVST CLKOUT
CONVERSION
RANGE
CONTROL SIGNALS
MULTIPLEXER, CONTROL
PWMSYNC (FROM PERIPHERAL) CAPT CAPB VREF REFCOM SENSE
VOLTAGE REFERENCE GENERATION CONTROL
INTERNAL REFERENCE SIGNALS
Figure Functional Block Diagram System ADMC401
basic architecture system consists fourstage pipeline architecture (the core) with wideband input sample hold amplifiers. Excluding last stage, each stage pipeline consists resolution flash connected switched capacitor interstage residue amplifier (MDAC). reside amplifier amplifies difference between reconstructed output flash input next stage pipeline. last stage pipeline simply consists flash A/D. pipeline architecture allows greater throughput rate expense pipeline delay latency. This means that while converter capable capturing input sample every clock cycle, actually takes clock cycles conversion process input fully processed appear output. operate basic conversion modes, Simultaneous Sampling Sequential Sampling. operating mode selected dedicated bits ADCCTRL register. Simultaneous Sampling mode, analog inputs (one from each bank) sampled simultaneously that VIN0 VIN4, VIN1 VIN5, VIN2 VIN6, VIN3 VIN7 represent four pairs simultaneously sampled inputs. alternative sequential operating mode, there simultaneous sampling, analog inputs sampled converted after other (i.e., VIN0 followed VIN1 followed VIN2, etc.). this mode, successive analog inputs sampled clock period four clock cycles) apart.
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ADMC401
CONVERT START COMMAND
+VREF VIN0 VCORE CORE ASHAN -VREF
analog-to-digital conversion process ADMC401 started either internal external command. ADCCTRL register determines whether internal external convert start mode enabled. ADCCTRL register cleared, internal convert start mode selected, conversion process started rising edge PWMSYNC signal. This results conversion sequence switching period start each period) when generation unit operates single update mode. double update operating mode, there conversion sequences switching period (one start middle each period). internal convert start mode, order ensure correct synchronization jitter-free operation, essential that value written PWMregister multiple four. other words, LSBs value written PWMregister must both ADCCTRL register set, external convert start mode selected. this mode, conversion process started occurrence rising edge CONVST pin. Additionally, start conversion placed under software control externally connecting programmable input/ output (PIO) lines CONVST generating rising edge writing appropriate PIODATA register. default, following reset, ADCCTRL register cleared that internal convert start mode selected.
CLOCK SIGNALS
Figure Equivalent Functional Input Circuit System
consists pipeline flash architecture clocked quarter instruction rate. timing system (including control multiplexers sample hold amplifiers) regulated this clock signal determines total conversion time channels well delay between sampling successive pairs analog inputs. clock rate internally fixed changed. period clock, tCKADC related CLKOUT period tCKADC rate corresponds tCKADC approximately
ANALOG INPUT CONFIGURATION OVERVIEW
voltage VREF sets common-mode voltage converter ADMC401. example, when using internal reference, input level will also centered about inputs ADMC401 configured single ended operation, where inverting terminals (ASHAN BSHAN) connected directly reference voltage level, analog inputs (VIN0 VIN7) driven analog signals with range. VIN0 VIN7 inputs unipolar that when operating from internal reference, these signals range from recommended single-ended input configuration single analog input channel ADMC401 shown Figure input converter must driven operational amplifier with sufficient drive strength that performance degraded. Sufficient drive strength ability drive load static switched from ground (capacitive) settle within within Figure operational amplifier shown configured simple noninverting input buffer. course, operational amplifier stage could also used implement necessary level shifting and/or filtering input signal.
VIN0
ADMC401
ASHAN VREF
SENSE
Figure Typical Single-Ended Input Configuration ADMC401
Figure simplified model input structure channel (VIN0) system ADMC401. This model applies eight input channels. internal multiplexers used switch various analog inputs converter. analog inputs VIN0 VIN3, there single common terminal (ASHAN) that inverting input internal differential sample hold amplifier. input signals, VIN4 VIN7, equivalent input BSHAN. value VREF (internally generated voltage reference externally applied voltage reference VREF pin) defines maximum input voltage core. minimum input voltage core automatically defined -VREF.
From Figure clear that input core simply given VCORE ASHAN which must satisfy condition: -VREF VCORE VREF where VREF voltage ADMC401 (either internally generated externally supplied). There additional limit placed valid operating range VIN0 ASHAN inputs that bounded power supply ADMC401: AVSS AVDD AVSS ASHAN AVDD
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Table Digital Data Format
VIN0 VREF VREF VREF VREF VREF VREF
ASHAN VREF VREF VREF VREF VREF VREF VREF VREF VREF
VCORE +VREF VREF VREF -VREF -VREF <-VREF
Digital Data (Hex) 0x7FF0 0x7FF0 0x7FE0 0x0010 0x0000 0xFFF0 0x8010 0x8000 0x8000
Digital Data (Binary) 0111 1111 1111 0000 0111 1111 1111 0000 0111 1111 1110 0000 0000 0000 0001 0000 0000 0000 0000 0000 1111 1111 1111 0000 1000 0000 0001 0000 1000 0000 0000 0000 1000 0000 0000 0000
where AVSS nominally AVDD nominally course, identical input constraints requirements apply other analog inputs VIN1 VIN7 well BSHAN GAIN inputs.
DATA FORMAT OUT-OF-RANGE DETECTION
Simultaneous Sampling Mode
digital data from core that stored dedicated, memory mapped registers (ADC0 ADC7 well ADCXTRA) stored left-aligned, twos complement data. output data format normal operation singleended configuration Figure given Table analog input (VIN0 ASHAN). Naturally, identical conditions apply other analog inputs. well 12-bit data word, core produces outof-range that when analog input core exceeds allowable range (-VREF +VREF). There dedicated 8-bit ADCOTR register that stores eight bits conversions signals VIN0 VIN7 inputs. There single each analog input; ADCOTR register set, VIN0 input exceeded permissible input range. Therefore, following complete conversion cycle, this register zero, signal exceeded input range. given analog input set, possible determine signal overranged (less than VREF) underranged (less than monitoring data word bit, outlined Table III.
Table III. Out-of-Range Truth Table
This operating mode selected clearing both Bits ADCCTRL register. this mode, eight analog inputs sampled four pairs simultaneously sampled inputs with VIN0 VIN4 being first pair sampled inputs, followed VIN1 VIN5, followed VIN2 VIN6, followed VIN3 VIN7. Following rising edge convert start command (either internally externally derived), internal control logic simultaneously samples VIN0 VIN4 analog inputs using dual internal sample hold amplifiers. internal control logic subsequently multiplexes these signals into core ADMC401. conversion each signal requires clock cycles. Following hold operation, VIN0 input applied first stage pipeline during next clock cycle. next clock cycle, VIN0 signal applied second stage pipeline VIN4 input applied first stage this pipeline. this clock cycle, second pair inputs also simultaneously sampled. This process continues feed signals into core until eight channels have been converted. timing this conversion sequence shown Figure
tCKADC
CLOCK CONVERT START VIN0 VIN4
Condition Range: VREF VIN0 VREF Range: VIN0 VREF Overrange: VIN0 VREF Underrange: VIN0
CONVERT VIN0 CONVERT VIN4 CONVERT VIN1 VIN1 VIN5 CONVERT VIN5 CONVERT VIN2 CONVERT VIN6
VIN2 VIN6
OPERATING MODES
conversion system ADMC401 configured operate four basic modes that selected Bits ADCCTRL register. Following reset, default setting that both these bits cleared Simultaneous Sampling mode selected. Simultaneous Sampling Mode (ADCCTRL(4 Sequential Sampling Mode (ADCCTRL(4 Offset Calibration Mode (ADCCTRL(4 Gain Calibration Mode (ADCCTRL(4 REV.
VIN3 VIN7
CONVERT VIN3 CONVERT VIN7
Figure Timing Simultaneous Sampling Operating Mode
this operating mode, there unique status ADCSTAT register that soon data available each pair simultaneously sampled signals. ADCSTAT soon data both ADC0 ADC4 registers valid, soon data ADC1 ADC5 valid, soon data ADC2 -25-
ADMC401
ADC6 valid when data ADC3 ADC7 valid. start next conversion sequence, bits ADCSTAT register cleared. Additionally, complete conversion sequence (when data ADC7 register valid), dedicated interrupt generated. This interrupt masked controlled block. Depending initial synchronization delays, worst case total conversion time (defined duration from rising edge convert start command generation interrupt) eight channels CONV which corresponds 1.88 instruction rate MHz. Additionally, this operating mode, time delay between sampling successive pairs analog inputs 8tCK MHz).
Sequential Sampling Mode
entire input voltage span system. Gain Calibration mode, selected setting both Bits ADCCTRL register, designed offer significant user flexibility determining amount gain compensation that required. this mode dedicated GAIN input internally connected directly noninverting input each sample hold amplifier. user apply different precise analog voltages across input voltage span this measure gain errors over operating range. complete conversion sequence each different GAIN input must initiated. Following conversion, data ADC0 ADC3 registers used calculate four separate measurements gain error first sample hold amplifier. Similarly, data ADC4 ADC7 registers used calculate gain associated with second sample hold amplifier. These data values could averaged obtain gain error values each sample hold amplifier that could stored used compensate future measurements. conversion status bits updated interrupt generated manner identical Simultaneous Sampling mode.
ADCXTRA REGISTER
This operating mode selected setting clearing ADCCTRL register. this operating mode, simultaneous sampling abandoned conversion sequence samples each analog input sequentially. Therefore, first clock period, VIN0 sampled held first sample hold amplifier. second clock period, held sample VIN0 applied first stage pipeline VIN1 signal sampled. This process continues until each analog inputs been sequentially sampled converted (i.e., VIN0 followed VIN1 followed VIN2, etc.). this operating mode, total conversion time same Simultaneous Sampling mode. However, successive channels sampled 4tCK MHz) intervals. this mode, Bits ADCSTAT register together when eight conversions complete. interrupt generated, before, when data ADC7 register valid.
Offset Calibration Mode
order maintain high accuracy system ADMC401, necessary measure compensate intrinsic offset and/or gain errors conversion system. Offset Calibration mode, which selected setting clearing ADCCTRL register, intended used measuring offsets sample hold amplifiers. When this mode selected, analog inputs (VIN0 VIN7, ASHAN BSHAN) disconnected from inputs sample hold amplifiers, inputs internally connected together reference voltage VREF pin). Since these connections effect only during conversion sequence, complete conversion sequence must initiated. Following conversion, data ADC0 ADC3 registers taken four separate measurements offset first sample hold amplifier. Similarly, data ADC4 ADC7 registers taken measurements offset associated with second sample hold amplifier. These data values could averaged obtain offset value each sample hold amplifier that could stored used compensate future measurements. conversion status bits updated interrupt generated manner identical Simultaneous Sampling mode.
Gain Calibration Mode
Following conversion sequence four operating modes, system reverts Single Channel mode. this configuration, multiplexers such that VIN0 input continuously sampled converted. results these conversions placed dedicated ADCXTRA register that updated with results conversion every clock period MHz). This feature permits continuous tracking single analog input, required. these conversions placed ADCSTAT register. interrupt generated following these conversions other status bits generated. ADCXTRA register updated during conversion sequence four operating modes.
VOLTAGE REFERENCE OPERATION
ADMC401 contains onboard bandgap reference that used provide precise output system externally VREF biasing level- shifting functions. Additionally, ADMC401 configured operate with external reference applied VREF pin. SENSE used select between internal external references. actual reference voltages used internal circuitry ADMC401 appear CAPT CAPB pins. correct operation internal voltage reference generation circuitry, either with internal external reference, necessary capacitor network between these pins, shown Figure tantalum capacitor parallel with ceramic recommended well capacitors analog ground. internal bias circuitry take after power-up settle. conversions performed prior this accurate possible. start-up time evaluated measuring long takes voltage difference between CAPT CAPB settle VREF. Additionally, ceramic capacitor must connected between analog ground. Finally, VREF should decoupled analog ground tantalum capacitor parallel with ceramic capacitor. REV.
desirable measure compensate gain errors associated with conversion process across
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SENSE controls whether system operates with internal external reference. operation with internal reference, SENSE should tied REFCOM pin. this mode, internally derived voltage reference appears VREF pin. operate with external voltage reference, SENSE should tied AVDD external voltage reference applied VREF pin.
CAPT CAPB
CONTROLLER
OVERVIEW
ADMC401
VREF REFCOM SENSE
generator block ADMC401 flexible, programmable, three-phase waveform generator that programmed generate required switching patterns drive three-phase voltage source inverter induction (ACIM) permanent magnet synchronous (PMSM) motor control. addition, block contains special functions that considerably simplify generation required switching patterns control electronically commutated motor (ECM) brushless motor (BDCM). special mode switched reluctance motors (SRM) exists well, enabled dedicated pin. generator produces three pairs signals output pins (AH, CL). output signals consist three high side drive signals (AH, three side drive signals (AL, CL). polarity generated signals programmed PWMPOL pin, that either active active patterns produced ADMC401. switching frequency, dead time minimum pulsewidths generated patterns programmable using respectively, PWMTM, PWMDT PWMPD registers. addition, three duty-cycle control registers (PWMCHA, PWMCHB PWMCHC) directly control duty cycles three pairs signals. Each output signals enabled disabled separate output enable bits PWMSEG register. addition, three control bits PWMSEG register permit crossover signals pair easy control BDCM. crossover mode, signal destined high side switch diverted complementary lowside output signal destined side switch diverted corresponding high side output signal. addition ease controller BDCM, this crossover mode also used transition signals into overmodulation range with relative ease. many applications, there need provide isolation barrier gate-drive circuits that turn power devices inverter. general, there common isolation techniques, optical isolation using opto-isolators transformer isolation using pulse transformers. controller ADMC401 permits mixing output signals with high-frequency chopping signal permit easy interface such pulse transformers. features this gate-drive chopping mode controlled PWMGATE register. There 8-bit value within PWMGATE register that directly controls chopping frequency. addition, high frequency chopping independently enabled high side side outputs using separate control bits PWMGATE register. Also, outputs have sufficient sink source capability directly drive most opto-isolators. generator capable operating distinct modes, single update mode double update mode. single update mode duty cycle values programmable only once period, that resultant patterns symmetrical about midpoint period. double update mode, second updating registers implemented midpoint period. this mode, possible produce asymmetrical patterns that produce
Figure Recommended Capacitor Decoupling Networks ADMC401
OPTIMIZING PERFORMANCE
optimum noise linearity performance achieved with largest input signal voltage span (i.e., input span) with matching impedance series with each analog inputs (VIN0 VIN7, ASHAN BSHAN). Additionally, operational amplifier must exhibit source impedance that both resistive, beyond sampling frequency. When capacitive load switched onto output operational amplifier, output will momentarily drop, effective output impedance. output recovers, ringing occur. remedy this situation, series resistor inserted between output input shown Figure 18). Recommended configurations include using OP27 amplifiers with Alternative recommended amps AD8051 AD8054. Figure shows ASHAN driven internally generated reference voltage VREF. When driving ASHAN with internally generated VREF, better performance will result driving impedance ASHAN matches driving impedance other analog inputs. This implemented with addition second amplifier Figure between VREF ASHAN, match amplifier VIN0. noise sensitive applications, also beneficial some shunt capacitance between inputs (VIN0 ASHAN Figure analog ground. Since this additional capacitance combines with equivalent input capacitance analog inputs, lower series resistance possible. input combination also provides some antialiasing filtering analog inputs. optimize performance when noise primary consideration, increase shunt capacitance much transient response input signal will allow. Increasing capacitance much adversely affect amp's settling time, frequency response distortion performance.
REGISTERS
configuration structure registers described this data sheet. REV.
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ADMC401
lower harmonic distortion three-phase inverters. This technique also permits closed loop controllers change average voltage applied machine windings faster rate permits faster closed loop bandwidths achieved. operating mode block (single double update mode) selected control MODECTRL register. generator ADMC401 also provides output pulse PWMSYNC pin, which synchronized switching frequency. single update mode PWMSYNC pulse produced start each period. double update mode, additional PWMSYNC pulse produced midpoint each period. width PWMSYNC pulse programmable through PWMSYNCWT register. signals produced ADMC401 shut number different ways. First, there dedicated asynchronous shutdown pin, PWMTRIP, that, when brought instantaneously places outputs state determined state PWMPOL pin). addition, each lines ADMC401 (PIO0 PIO11) configured additional shutdown. setting appropriate PIOPWM register, corresponding line acts asynchronous shutdown source manner identical PWMTRIP pin. These hardware shutdown mechanisms asynchronous that associated disable circuitry does through clocked logic, thereby ensuring correct shutdown even event loss clock. addition hardware shutdown features, system shut down software writing PWMSWT register. Status information about system ADMC401 available user SYSSTAT register. particular, state PWMTRIP PWMPOL pins available, well status bits that indicates whether operation first half second half period. functional block diagram controller shown Figure generation output signals pins controlled four important blocks: Three-Phase Timing Unit, which core controller, generates three pairs complemented dead time adjusted center based signals. Output Control Unit allows redirection outputs Three-Phase Timing Unit each channel either high side side output. addition, Output Control Unit allows individual enabling/disabling each output signals. Gate Drive Unit provides correct polarity output signals based state PWMPOL pin. Gate Drive Unit also permits generation highfrequency chopping frequency subsequent mixing with signals. Shutdown Controller takes care various shutdown modes (via PWMTRIP pin, lines PWMSWT register) generates correct RESET signal Timing Unit. controller driven clock same frequency instruction rate, capable generating interrupts core. interrupt generated occurrence rising edge PWMSYNC pulse other generated occurrence shutdown action.
CONFIGURATION REGISTERS PWM(15.0) PWMDT (9.0) PWMPD(9.0) PWMSYNCWT(7.0) MODECTRL DUTY CYCLE REGISTERS PWMCHA (15.0) PWMCHB (15.0) PWMCHC (15.0)
PWMSEG (8.0)
PWMGATE (9.0)
THREE-PHASE TIMING UNIT SYNC RESET OUTPUT CONTROL UNIT SYNC GATE DRIVE UNIT PWMSR CLKOUT PWMSYNC INTERRUPT CONTROLLER PWMTRIP DETECT PWMSWT PIOPWM (11.0) PWMSYNC PWMPOL PWMTRIP PIO0 PIO11
SHUTDOWN CONTROLLER
Figure Overview ADMC401 Controller
THREE-PHASE TIMING UNIT
16-bit three-phase timing unit core controller produces three pairs pulsewidth modulated signals with high resolution minimal processor overhead. outputs this timing unit active such that level interpreted command turn associated power device. There four main configuration registers (PWMTM, PWMDT, PWMPD PWMSYNCWT) that determine fundamental characteristics outputs. addition, operating mode (single double update mode) selected MODECTRL register. These registers, conjunction with three 16-bit duty cycle registers (PWMCHA, PWMCHB PWMCHC), control output three-phase timing unit.
Switching Frequency, PWMRegister
switching frequency controlled 16-bit period register, PWMTM. fundamental timing unit controller (DSP instruction rate). Therefore, CLKOUT, fundamental time increment 38.5 value written PWMregister effectively number clock increments half period. required PWMvalue function desired switching frequency (fPWM) given PWM= fCLKOUT fCLKIN
Therefore, switching period, written
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REV.
ADMC401
example, CLKOUT desired switching frequency µs), correct value load into PWMregister PWM= 1300 duty cycles signals updated only once period start each cycle. result that patterns that symmetrical about midpoint switching period produced. double update mode, additional PWMSYNC pulse produced midpoint each period. rising edge this PWMSYNC pulse again used latch values configuration registers, duty cycle registers PWMSEG register. result possible alter characteristics (switching frequency, dead time, minimum pulsewidth PWMSYNC pulsewidth) well output duty cycles midpoint each cycle. Consequently, possible with double update mode produce switching patterns that symmetrical about midpoint period (asymmetrical patterns). double update mode, necessary know whether operation point time either first half second half cycle. This information provided SYSSTAT register, which cleared during operation first half each period (between rising edge original PWMSYNC pulse rising edge PWMSYNC pulse introduced double update mode). SYSSTAT register during operation second half each period. This status allows user make determination particular half-cycle during implementation PWMSYNC interrupt service routine, required. advantage double update mode that lower harmonic voltages produced process faster control bandwidths possible. However, given switching frequency, PWMSYNC pulses occur twice rate double update mode. Since duty cycle values must computed each PWMSYNC interrupt service routine, there larger computational burden double update mode. Alternatively, same update rate maintained half switching frequency give lower switching losses.
Width PWMSYNC Pulse, PWMSYNCWT Register
largest value that written 16-bit PWMregister 0xFFFF 65,535, which corresponds minimum switching frequency PWM, 65,535
Switching Dead Time, PWMDT Register
second important parameter that must initial configuration block switching dead time. This short delay time introduced between turning signal (say turning complementary signal, This short time delay introduced permit power switch being turned this case) completely recover blocking capability before complementary switch turned This time delay prevents potentially destructive short-circuit condition from developing across link capacitor typical voltage source inverter. dead time controlled 10-bit PWMDT register. There dead time register that controls dead time inserted into three pairs output signals. dead time, related value PWMDT register PWMDT Therefore, CLKOUT, PWMDT value 0x00A introduces delay between turn-off signal (say turn-on complementary signal (AL). amount dead time therefore programmed increments 2tCK CLKOUT). PWMDT register 10-bit register that maximum value 0x3FF 1023) corresponding maximum programmed dead time
1023 1023 38.5 10-9 78.8
CLKOUT rate MHz. Obviously, dead time programmed zero writing PWMDT register.
Operating Mode, MODECTRL SYSSTAT Registers
controller ADMC401 operate distinct modes; single update mode double update mode. operating mode controller determined state MODECTRL register. this cleared, operates single update mode. Setting places double update mode. default, following reset, MODECTRL register cleared that default operating mode single update mode. single update mode, single PWMSYNC pulse produced each period. rising edge this signal marks start cycle used latch values from configuration registers (PWMTM, PWMDT, PWMPD PWMSYNCWT) duty cycle registers (PWMCHA, PWMCHB PWMCHC) into three-phase timing unit. addition, PWMSEG register also latched into output control unit rising edge PWMSYNC pulse. effect, this means that characteristics resultant REV.
controller ADMC401 produces output synchronization pulse rate equal switching frequency single update mode twice frequency double update mode. This pulse available external PWMSYNC pin. width this PWMSYNC pulse programmable 8-bit read/write PWMSYNCWT register. width PWMSYNC pulse, TPWMSYNC, given TPWMSYNC PWMSYNCWT
that width pulse programmable from (corresponding 38.5 9.85 CLKOUT rate MHz). Following reset, PWMSYNCWT register contains 0x27 that default PWMSYNC width 1.54 again CLKOUT.
Duty Cycles, PWMCHA, PWMCHB, PWMCHC Registers
duty cycles output signals Pins controlled three 16-bit read/write duty cycle registers, PWMCHA, PWMCHB PWMCHC. integer value register PWMCHA controls duty cycle signals PWMCHB controls duty cycle signals PWMCHC controls duty
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ADMC401
cycle signals duty cycle registers programmed integer counts fundamental time unit, tCK, define desired on-time high side signal produced three-phase timing unit over half period. switching signals produced three-phase timing unit also adjusted incorporate programmed dead time value PWMDT register. three-phase timing unit produces active signals that level corresponds command turn associated power device. typical pair outputs this case from timing unit shown Figure operation single update mode. illustrated time values indicate integer value associated register converted time simply multiplying fundamental time increment, tCK. First, noted that switching patterns symmetrical about midpoint switching period this single update mode since same values PWMCHA, PWMand PWMDT used define signals both half cycles period. seen programmed duty cycles adjusted incorporate desired dead time into resultant pair signals. Clearly, dead time incorporated moving switching instants both signals away from instant PWMCHA register. Both switching edges moved equal amount (PWMDT tCK) preserve symmetrical output patterns. Also shown PWMSYNC pulse whose width PWMSYNCWT register SYSSTAT register, which indicates whether operation first second half cycle period.
PWMCHA PWMCHA
Obviously negative values permitted minimum permissible value zero, corresponding duty cycle. similar fashion, maximum value corresponding 100% duty cycle. output signals from timing unit operation double update mode shown Figure This illustrates completely general case where switching frequency, dead time duty cycle changed second half period. course, same value these quantities could used both halves cycle. However, seen that there guarantee that symmetrical signals will produced timing unit this double update mode. Additionally, seen that dead time inserted into signals same single update mode.
PWMCHA1 PWMCHA2
PWMDT1 PWMDT2
PWMSYNC
PWMSYNCWT1
PWMSYNCWT2
SYSSTAT
PWMTM1
PWMTM2
Figure Typical Outputs Three-Phase Timing Unit Double Update Mode (Active Waveforms)
general on-times signals over full period double update mode defined
PWMDT
PWMDT
PWMCHA1 PWMCHA2 PWMDT1 PWMDT2 PWMTM1 PWMTM2 PWMCHA1 PWMCHA2 PWMDT1 PWMDT2
PWMSYNC
PWMSYNCWT
where subscript refers value that register during first half cycle subscript refers value during second half cycle. corresponding duty cycles are:
PWMCHA1 PWMCHA2 PWMDT1 PWMDT2 PWMTM1 PWMTM2
SYSSTAT
PWM
PWM
Figure Typical Outputs Three-Phase Timing Unit Single Update Mode (Active Waveforms)
PWMTM1 PWMTM2 PWMCHA1 PWMCHA2 PWMDT1 PWMDT2 PWMTM1 PWMTM2
resultant on-times signals over full period (two half periods) produced timing unit, illustrated Figure written PWMCHA PWMDT PWM- PWMCHA PWMDT corresponding duty cycles are: PWMCHA PWMDT PWM
since completely general case double update mode, switching period given
PWMTM1 PWMTM2
Again, values constrained between zero Similar signals those illustrated Figure Figure produced outputs programming PWMCHB PWMCHC registers manner identical that described PWMCHA.
Special Consideration Operation Overmodulation
PWM- PWMCHA PWMDT PWM
Timing Unit capable producing signals with variable duty cycle values output pins. extremities modulation process, both 100% modulation possible. These modes termed full full respectively. between, other duty cycle values, operation termed normal modulation. -30- REV.
ADMC401
Full pair signals said operate FULL when desired side output three-phase Timing Unit state (LO) between successive PWMSYNC pulses. This state entered virtue commanded duty cycle values conjunction with PWMDT register) virtue correct operation pulse deletion circuit. Full OFF: pair signals said operate FULL when desired side output three-phase Timing Unit state (HI) between successive PWMSYNC pulses. This state entered virtue commanded duty cycle values conjunction with PWMDT register) virtue correct operation pulse deletion circuit. Normal Modulation: pair signals said operate normal modulation when desired output duty cycle other than 100% between successive PWMSYNC pulses. There certain situations when transitioning either into either full full where necessary insert additional dead time delays prevent potential shoot through conditions inverter. particular situation also depends whether operation single double update mode. double update mode, also necessary consider whether unit transitioning from first half cycle second half cycle vice versa. These transitions detected automatically ADMC401 and, appropriate, dead time inserted. insertion additional dead time into signals given pair during these transitions only needed otherwise both signals would required toggle PWMSYNC boundary. additional dead time delay inserted into signal that toggling into state. effect turn this signal delayed amount PWMDT from rising edge PWMSYNC. After this delay, signal allowed turn provided desired output still state after dead time delay. Figure illustrates examples such transitions where Figure 24(a) when transitioning from normal modulation full half cycle boundary double update mode, special action needed. However, Figure 24(b) when transitioning into full same boundary, seen that additional dead time necessary.
PWMCHA1 FULL FULL PWMDT PWMDT
Minimum Pulsewidth, PWMPD Register
many power converter switching applications, desirable eliminate switching signals below certain width. takes certain finite time both turn turn power semiconductor devices. Therefore, width signals goes below some minimum value, desirable completely eliminate switching that particular cycle. allowable minimum pulsewidth outputs that produced controller programmed using 10-bit PWMPD register. minimum pulsewidth, TMIN, programmed increments TMIN PWMPD that PWMPD value 0x00A defines permissible minimum time 0.39 CLKOUT. operation minimum pulsewidth control ensures that time from turning turning alternatively from turning turning signal never less than TMIN value specified PWMPD register. controller detects that time between turning turning signal (say less than MIN, pulse deleted signal remains completely over period. complementary signal, this case, then turned completely
Effective Resolution
single update mode, same values PWMCHA, PWMCHB PWMCHC used define on-times both half cycles period. result, effective resolution generation process 2tCK CLKOUT), since incrementing duty cycle registers changes resultant on-time associated signals each half period 2tCK full period). double update mode, improved resolution possible since different values duty cycles registers used define on-times both first second halves period. result, possible adjust on-time over whole period increments tCK. This corresponds effective resolution double update mode 38.5 CLKOUT). achievable switching frequency given resolution tabulated Table
Table Achievable Resolution Single Double Update Modes (CLKOUT MHz) Resolution (Bits) Single Update Mode Frequency (kHz) 50.8 25.4 12.7 6.35 3.17 Double Update Mode Frequency (kHz) 50.8 25.4 12.7 6.35
OUTPUT CONTROL UNIT, PWMSEG REGISTER
DEAD TIME INSERTED PWMPWM
operation Output Control Unit controlled 9-bit read/write PWMSEG register which controls distinct features that directly useful control BDCM.
Crossover Feature
Figure Examples transitioning form normal modulation into either Full Full where necessary insert additional dead times.
PWMSEG register contains three crossover bits; each pair outputs. Setting PWMSEG register enables crossover mode AH/AL pair -31-
REV.
ADMC401
signals, setting enables crossover BH/BL pair signals setting enables crossover CH/CL pair signals. crossover mode enabled pair signals, high side signal from timing unit say) diverted associated side output Output Control Unit that signal will ultimately appear pin. course, corresponding side output Timing Unit also diverted complementary high side output Output Control Unit that signal appears pin. Following reset, three crossover bits cleared that crossover mode disabled three pairs signals.
Output Enable Function
PWMCHA PWMCHB PWMCHA PWMCHB
PWMDT
PWMDT
PWMSEG register also contains bits (Bits that used individually enable disable each outputs. signal enabled setting PWMSEG register while controls controls controls controls controls output. associated PWMSEG register set, corresponding output disabled irrespective value corresponding duty cycle register. This output signal will remain state long corresponding enable/disable PWMSEG register set. This output enable function implemented after crossover function. Following reset, enable bits PWMSEG register cleared that outputs enabled default. manner identical duty cycle registers, PWMSEG latched rising edge PWMSYNC signal that changes this register only become effective start each cycle single update mode. double update mode, PWMSEG register also updated midpoint cycle.
Brushless Motor (Electronically Commutated Motor) Control
PWM
PWM
Figure Example active signals suitable control, PWMCHA PWMCHB, crossover BH/BL pair disable outputs. Operation single update mode.
GATE DRIVE UNIT, PWMGATE REGISTER High Frequency Chopping
Gate Drive Unit controller adds features that simplify design isolated gate drive circuits inverters. transformer-coupled power device gate drive amplifier used, active signal must chopped high frequency. 10-bit PWMGATE register allows programming this high frequency chopping mode. chopped active signals required high-side drivers only, side drivers only both high side side switches. Therefore, independent control this mode both high side switches included with separate control bits PWMGATE register. Typical output signals with high frequency chopping enabled both high side side signals shown Figure Chopping high side outputs (AH, enabled setting PWMGATE register. Chopping side outputs (AL, enabled setting PWMGATE register. high frequency chopping frequency controlled 8-bit word (GDCLK) placed Bits PWMGATE register. period this high frequency carrier TCHOP GDCLK chopping frequency therefore integral subdivision CLKOUT frequency: fCHOP
control only inverter legs switched time often high side device must switched same time side driver second leg. Therefore, programming identical duty cycle values channels (i.e., PWMCHA PWMCHB) setting PWMSEG register crossover BH/BL pair signals, possible turn high side switch Phase side switch phase same time. control ECM, usual that third inverter (Phase this example) disabled number cycles. This function implemented disabling both outputs setting Bits PWMSEG register. This situation illustrated Figure where seen that both signals identical, since PWMCHA PWMCHB crossover Phase set. addition, other four signals (AL, have been disabled setting appropriate enable/disable bits PWMSEG register. situation illustrated Figure appropriate value PWMSEG register 0x00A7. normal operation, each inverter disabled certain periods time, that PWMSEG register changed based position rotor shaft (motor commutation).
(GDCLK +1)]
fCLKOUT
GDCLK value range from 255, corresponding programmable chopping frequency rate from 25.4 CLKOUT rate. gate drive features must programmed before operation controller typically changed during normal operation controller. Following reset, bits PWMGATE register cleared that high frequency chopping disabled, default.
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REV.
ADMC401
PWMCHA
PWMCHA
PWMCHA1
PWMCHA2
PWMDT
PWMDT
PWM
(GDCLK+1)]
PWM
PWMCHB1
PWMCHB2
Figure Typical active signals with high frequency gate chopping enabled both high side side switches.
Polarity Control, PWMPOL
PWMCHC1 PWMCHC2
polarity signals produced output pins selected hardware PWMPOL pin. Connecting PWMPOL DGND selects active outputs, such that level interpreted command turn associated power device. Conversely, connecting PWMPOL selects active associated power devices turned level outputs. There internal pull-up PWMPOL pin, that this becomes disconnected connected), active will produced. level PWMPOL read from SYSSTAT register, where zero indicates measured level PWMPOL pin.
SWITCHED RELUCTANCE MODE
PWMPWM
Figure Active signals Mode (PWMPOL PWMSR DGND) ADMC401 double update mode.
SHUTDOWN
block ADMC401 contains switched reluctance (SR) mode that controlled PWMSR pin. switched reluctance mode enabled connecting PWMSR DGND. this mode, side signals from three-phase timing unit assume permanently states, independent value written duty-cycle registers. duty cycles high side signals from timing unit still determined three duty cycle registers. Using crossover feature output control unit, possible divert permanently signals either high-side low-side outputs. This mode necessary because typical power converter configuration switched variable reluctance motors, motor winding connected between power switches given inverter leg. Therefore, order build current motor winding, necessary turn both switches same time. Typical active signals during operation mode shown Figure operation double update mode. clear that three low-side signals (AL, permanently three high side signals modulated usual manner that corresponding high side power switches switched between states. mode only enabled connecting PWMSR GND. There software means which this mode enabled. There internal pull-up resistor PWMSR that this left unconnected becomes disconnected mode disabled. course, mode disabled when PWMSR tied
event external fault conditions, essential that system instantaneously shutdown safe fashion. level PWMTRIP provides instantaneous, asynchronous (independent clock) shutdown controller. outputs placed state defined PWMPOL pin). addition, PWMSYNC pulse disabled associated interrupt stopped. PWMTRIP internal pull-down resistor that becomes unconnected will disabled. state PWMTRIP read from SYSSTAT register. lines ADMC401 also configured operate shutdown pins using PIOPWM register. 12-bit PIOPWM control each line (Bit controls PIO0, etc.). Setting control enables corresponding line shutdown pin. falling edge line will then generate instantaneous, asynchronous shutdown system, manner identical PWMTRIP pin. Also like PWMTRIP, lines have internal pull-down resistors, that becomes unconnected configured shutdown pin, will disabled. Following reset, lines configured inputs, have pull-downs programmed shut down pins (PIOPWM 0x0FFF) that shutdown. Correct operation possible without first correctly configuring system. addition, possible initiate shutdown software writing 1-bit PWMSWT register. writing this register generates shutdown command manner identical PWMTRIP pins. hardware trip effect PWMSWT register. does matter which value written PWMSWT register. However, following shutdown, possible read PWMSWT register determine shutdown generated hardware software. shutdown caused PWMSWT register, will read back from PWMSWT register. Reading PWMSWT register automatically clears contents.
REV.
-33-
ADMC401
Table Fundamental Characteristics Generation Unit ADMC401 (CLKOUT MHz)
Parameter Counter Resolution Edge Resolution Programmable Dead Time Dead Time Increments Programmable Minimum Pulsewidth Minimum Pulsewidth Increments Switching Frequency Switching Frequency1 PWMSYNC Pulsewidth PWMSYNC Pulsewidth Increments Gate Drive Chopping Frequency
Test Conditions Double Update Mode
38.5
Unit Bits
TMIN fPWM fPWM TPWMSYNC fCHOP
77.0 38.5 16-Bit Resolution 8-Bit Resolution 38.5 38.5 25.4
78.8 39.4
9850 6500
NOTE: Higher switching frequencies possible reduced resolutions (i.e., 202.8 bits, 405.6 bits, etc.)
occurrence shutdown command (either from PWMTRIP pin, lines PWMSWT register), PWMTRIP interrupt will generated. addition, PWMSYNC pulse longer appears output pin. However, internal operation timer continues. Following shutdown, only re-enabled PWMTRIP interrupt service routine, example) writing PWMTM, PWMCHA, PWMCHB PWMCHC registers. Provided external fault been cleared PWMTRIP appropriate lines have returned level, controller will restart.
REGISTERS
with encoder signals frequencies 4.33 MHz, corresponding maximum quadrature frequency 17.3 (assuming ideal quadrature relationship between input signals).
ENCODER EVENT TIMER BLOCK CLOCK DIVIDER EIUSCALE (7.0) EIUTIMER (15.0) EIUPERIOD (15.0) TIMEOUT ENCODER EVENT TIMER PULSE DECIMATOR EETDIV(15.0) EETSTAT(0) EETT(15.0) EETDELTAT(15.0) EETN(7.0)
ENCODER LOOP TIMER
registers described this data sheet. parameters block operation tabulated Table
DIRECTION ENCODER INTERFACE BLOCK
QUADRATURE SIGNAL
ENCODER INTERFACE UNIT
OVERVIEW ENCODER INTERFACE UNIT
PROGRAMMABLE NOISE FILTERS
ADMC401 incorporates powerful encoder interface incremental shaft encoders, that often used position feedback high performance motion control systems. functional block diagram entire encoder interface system ADMC401 shown Figure encoder interface unit (EIU) includes 16-bit quadrature up/down counter, programmable input noise filtering encoder input signals zero markers, four dedicated pins ADMC401. quadrature encoder signals alternatively, frequency direction inputs) applied pins. addition, zero marker/strobe inputs provided pins EIS. These inputs used latch contents encoder quadrature counter into dedicated registers, EIZLATCH EISLATCH, occurrence external events pins. These events programmed either rising edge only (latch event) rising edge encoder moving forward direction falling edge encoder moving reverse direction (software latched zero marker functionality). encoder interface unit incorporates programmable noise filtering four encoder inputs prevent spurious noise pulses from adversely affecting operation quadrature counter. encoder interface unit operates clock frequency equal instruction rate. encoder interface unit operates correctly
16-BIT QUADRATURE UP/DOWN COUNTER ENCODER COUNTER CONTROL
EETCNT(15.0) EIUCNT(15.0) EIUMAXCNT(15.0) EIUCTRL(8.0) EIUSTAT(7.0) EISLATCH(15.0) EIZLATCH(15.0) EIUFILTER(5.0)
Figure Configuration Encoder Interface System ADMC401
programmed zero marker reset quadrature encoder hardware, required. Alternatively, zero marker ignored encoder quadrature counter reset according contents maximum count register, EIUMAXCNT. There also "single north marker" mode available which encoder quadrature counter reset only first zero marker pulse. Both modes enabled dedicated control bits control register, EIUCTRL. status EIUSTAT register first occurrence zero marker. encoder interface unit also made implement some error checking functions. error checking mode enabled, upon occurrence zero pulse, contents encoder counter register compared with expected value EIUMAXCNT depending direction rotation). encoder count error detected, status EIUSTAT REV.
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ADMC401
register count error interrupt generated. additional status provided EIUSTAT register that indicates initialization state EIU. Until EIUMAXCNT register written initialized. Four status EIUSTAT register provide state four inputs, EIA, EIB, EIS. encoder interface unit ADMC401 contains 16-bit loop timer that behaves manner similar programmable interval timer core. loop timer consist timer register, period register scale register that programmed timeout reload appropriate intervals. control EIUCTRL register used enable/disable this loop timer. When this loop timer times out, loop timer timeout interrupt generated. This interrupt could used control timing speed position control loops high performance drives. encoder interface unit also includes high performance encoder event timer (EET) block that permits accurate timing successive events encoder inputs. programmed time duration between encoder pulses used enhance velocity estimation, particularly speeds rotation. information from registers block latched ways. mode, contents quadrature count register, EIUCNT relevant registers (EETT EETDELTAT) latched when loop timer times out. second mode, reading EIUCNT register also simultaneously latches registers. data latching mode selected control EIUCTRL register.
ENCODER LOOP TIMER
written encoder interface unit initialized EIUSTAT register set. contents EIUMAXCNT register used certain operating modes reset quadrature counter. contents EIUMAXCNT register also used error checking EIU. Operation encoder interface controlled EIUCTRL register.
Programmable Input Noise Filtering Encoder Signals
functional block diagram input stages encoder interface shown Figure four encoder input signals (EIA, EIB, EIS) first synchronized input synchronization buffers. This eliminates asynchronous nature real world encoder signals prior encoder interface unit logic. Subsequently, four synchronized signals (EIAS, EIBS, EIZS EISS) applied programmable noise filtering circuits that programmed reject pulses that shorter than some suitable value. outputs filter stage applied quadrature counter stage.
INPUT SYNCHRONIZATION STAGE EIAS EIBS EIZS EISS THREE STAGE DIGITAL FILTER
CLKOUT
CLOCK DIVIDE
EIUFILTER(5.0)
Figure Functional Block Diagram Input Stage Encoder Interface
contains 16-bit loop timer that structured manner similar interval timer core (TCOUNT, TPERIOD TSCALE registers). corresponding registers encoder loop timer 16-bit EIUTIMER EIUPERIOD registers 8-bit EIUSCALE register. loop timer clocked CLKOUT rate, tCK. loop timer used generate periodic interrupts based multiples cycle time. loop timer enabled setting EIUCTRL register. When enabled, 16-bit timer register (EIUTIMER) decremented every cycles, where scaling value stored 8-bit EIUSCALE register. When value EIUTIMER register reaches zero, loop timer timeout interrupt generated EIUTIMER register reloaded with 16-bit value EIUPERIOD register. scaling feature this timer, provided EIUSCALE register, allows 16-bit timer generate periodic interrupts over wide range periods. CLKOUT rate (38.5 period), timer generate interrupts with periods 38.5 2.52 with zero scale value (EIUSCALE When scaling used, time periods range 0.645 sec. loop timer timeout interrupt masked PICMASK register.
ENCODER INTERFACE STRUCTURE OPERATION Introduction
Each four synchronized input signals (EIAS, EIBS, EIZS EISS) applied three clock cycle delay filter such that filtered output signals permitted change until stable value been registered three successive clock cycles. While encoder signals changing, filter maintains previous output value. clock frequency used filter circuits programmed Bits EIUFILTER register. 6-bit quantity written Bits EIUFILTER register used divide CLKOUT frequency provide clock source encoder noise filters. value written Bits EIUFILTER register period clock source used encoder filters tCK. This filter structure guarantees that encoder pulses less width than will always rejected filter stage. Additionally, pulses greater than will always through filter stage passed internal quadrature counter. Encoder pulses widths between (N+1) either pass through rejected encoder filter. Whether such pulses pass through filter depends exact nature synchronization between external asynchronous pulses internal clock impossible predict. example, writing value EIUFILTER register, means that clock frequency used encoder filters (for CLKOUT rate MHz). order register stable value, encoder input signals must stable three these cycles ns). Consequently, smallest period that will registered synchronized encoder inputs corresponding maximum encoder
encoder interface section consists 16-bit quadrature up/down counter 16-bit EIUCNT register that allows up/down counter read DSP. There also 16-bit EIUMAXCNT register that must written initialize encoder system. Until EIUMAXCNT register been REV.
-35-
ADMC401
rate 1.08 MHz. general, maximum encoder rate that consistently recognized given ENCMAX fCLKOUT each edge. This signal leads signal) defined forward direction motion. Setting EIUCTRL register causes signal input quadrature counter signal becomes input quadrature counter. Therefore, signal signal pins ADMC401, input quadrature counter will input. This will recognized rotation reverse direction counter will decremented each quadrature pulse. Following reset, cleared. encoder signals used derive quadrature signal that used, conjunction with direction bit, increment decrement encoder counter also encoder event timer. status direction signal indicated EIUSTAT register. While encoder counter incrementing, set. Alternatively, when encoder counter decrementing, EIUSTAT register cleared.
Alternative Frequency Direction Inputs
EIAS
Operation both input synchronization logic noise filters shown Figure default case where EIUFILTER(5::0) 0x00 noise filters clocked CLKOUT.
3tCK
CLKOUT
NOISE PULSE
EIBS
3tCK
3tCK
Figure Operation input synchronization noise filters encoder interface with EIUFILTER(5:0) 0x00 such that filters operated CLKOUT.
default value EIUFILTER(5::0) following power reset 0x00 that filters clocked CLKOUT rate minimal filtering applied. There direct trade-off between amount filtering applied encoder inputs maximum possible encoder signal rate. effect, larger value EIUFILTER(5::0), more filtering that applied encoder signals, that, given number encoder lines, maximum speed rotation lower. influence encoder filter zero marker signals (EIZ EIS) somewhat different that signals, depending exact nature encoder. common incremental encoders, width zero marker equal quarter, half full period quadrature signals (say EIA). Applying three-stage delay filter zero marker whose width either equal half full quadrature pulse period does change achievable maximum encoder rate. However, maximum possible encoder rate changed three-stage filter applied case where width zero marker equal quarter period. this case influence threestage delay filter effectively half maximum encoder signal rate that described above 2.15 CLKOUT rate).
Encoder Counter Direction
Instead quadrature encoder inputs, encoder interface unit also accept alternative Frequency Direction Inputs. This mode enabled setting EIUCTRL register. this so-called Mode, input accepts frequency signal accepts direction signal. signal these pins subject same synchronization filtering logic described previously. However, this mode quadrature counter incremented decremented both falling rising edges signal pin. forward operation assumed counter incremented each edge frequency signal input. other hand, reverse rotation assumed quadrature counter decremented each edge signal pin. power-up reset, EIUCTRL register cleared that this mode disabled default.
Encoder Counter Reset
direction quadrature counting determined (REV) EIUCTRL register. cleared, signal input quadrature counter input. Thus, EIAencoder signal leads EIB-signal (and therefore signal leads signal), quadrature counter incremented
ZERO (Bit EIUCTRL register determines encoder zero marker used hardware reset up/down counter encoder interface. When EIUCTRL register set, zero marker signal used reset up/down counter zero moving forward direction) value EIUMAXCNT register moving reverse direction). reset operation takes place next quadrature pulse after zero marker been recognize
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